FEATURES
FUNCTIONAL BLOCK DIAGRAM
AUX1 AUX2
REFIN
REFOUT REFGND
ADM1166
MUX
Complete supervisory and sequencing solution for up to
10 supplies
16 event deep black box nonvolatile fault recording
10 supply fault detectors enable supervision of supplies to
DPLIMx
In addition, the DAC output buffer is three-stated if DNLIMx >
DPLIMx. By programming the limit registers this way, the user
can make it very difficult for the DAC output buffers to be
turned on during normal system operation. The limit registers
are among the registers downloaded from EEPROM at startup.
Rev. A | Page 24 of 33
Data Sheet
ADM1166
APPLICATIONS DIAGRAM
12V IN
12V OUT
5V IN
5V OUT
3V IN
3V OUT
IN
DC-TO-DC1
5V OUT
3V OUT
3.3V OUT
2.5V OUT
1.8V OUT
1.2V OUT
0.9V OUT
POWRON
EN
OUT
VP1
VP2
VP3
VP4
VX1
VX2
VX3
PDO1
PDO2
VX4
PDO6
IN
DC-TO-DC2
PDO3
PDO4
PDO5
PDO7
RESET
VX5
PDO8
EN
SIGNAL VALID
DC-TO-DC3
EN
OUT
1.8V OUT
3.3V OUT
DAC1*
IN
REFIN VCCP VDDCAP GND
10µF
2.5V OUT
IN
SYSTEM RESET
PDO9
REFOUT
OUT
PWRGD
PDO10
10µF
3.3V OUT
ADM1166
LDO
EN
10µF
OUT
0.9V OUT
3.3V OUT
*ONLY ONE MARGINING CIRCUIT
SHOWN FOR CLARITY. DAC1 TO DAC6
ALLOW MARGINING FOR UP TO SIX
VOLTAGE RAILS.
IN
EN
OUT
DC-TO-DC4
Figure 34. Applications Diagram
Rev. A | Page 25 of 33
1.2V OUT
TRIM
09332-068
VH
ADM1166
Data Sheet
COMMUNICATING WITH THE ADM1166
CONFIGURATION DOWNLOAD AT POWER-UP
Option 1
The configuration of the ADM1166 (undervoltage/overvoltage
thresholds, glitch filter timeouts, and PDO configurations) is
dictated by the contents of the RAM. The RAM comprises digital
latches that are local to each function on the device. The latches are
double buffered and have two identical latches, Latch A and Latch B.
Therefore, when an update to a function occurs, the contents of
Latch A are updated first, and then the contents of Latch B are
updated with identical data. The advantages of this architecture are
explained in detail in the Updating the Configuration section.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the EEPROM
(nonvolatile memory) to the local latches. This download occurs in
steps, as follows:
1. With no power applied to the device, the PDOs are all high
impedance.
2. When 1.2 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPx), the PDOs are all weakly
pulled to GND with a 20 kΩ resistor.
3. When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
4. The EEPROM downloads its contents to all Latch As.
5. When the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
6. At 0.5 ms after the configuration download completes, the first
state definition is downloaded from the EEPROM into the SE.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1166 to issue
a no acknowledge (NACK).
Update the configuration in real time. The user writes to the RAM
across the SMBus, and the configuration is updated immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1166 remains unchanged
and continues to operate in the original setup until the instruction
is given to update the Latch Bs.
Option 3
Change the EEPROM register contents without changing the RAM
contents, and then download the revised EEPROM contents to
the RAM registers. With this method, the configuration of the
ADM1166 remains unchanged and continues to operate in the
original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents if
revisions to the configuration are unsatisfactory. For example, if
the user needs to alter an overvoltage threshold, the RAM register
can be updated as described in the Option 1 section. However,
if the user is not satisfied with the change and wants to revert to
the original programmed value, the device controller can issue a
command to download the EEPROM contents to the RAM again,
as described in the Option 3 section, restoring the ADM1166 to
its original configuration.
The topology of the ADM1166 makes this type of operation
possible. The local, volatile registers (RAM) are all doublebuffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves
the double-buffered latches open at all times. If Bit 0 is set to 0
when a RAM write occurs across the SMBus, only the first side
of the double-buffered latch is written to. The user must then
write a 1 to Bit 1 of the UPDCFG register. This generates a pulse
to update all the second latches at once. EEPROM writes occur
in a similar way.
The final bit in this register can enable or disable EEPROM page
erasure. If this bit is set high, the contents of an EEPROM page can
all be set to 1. If this bit is set low, the contents of a page cannot be
erased, even if the command code for page erasure is programmed
across the SMBus. The bit map for the UPDCFG register is shown
in the AN-698 Application Note. A flow diagram for download at
power-up and subsequent configuration updates is shown in
Figure 35.
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
the EEPROM into the RAM registers, the user may need to alter
the configuration of functions on the ADM1166, such as changing
the undervoltage or overvoltage limit of an SFD, changing the fault
output of an SFD, or adjusting the rise time delay of one of the PDOs.
The ADM1166 provides several options that allow the user to
update the configuration over the SMBus interface. The following
three options are controlled in the UPDCFG register.
SMBus
E
E
P
R
O
M
L
D
DEVICE
CONTROLLER
R
A
M
L
D
D
A
T
A
U
P
D
LATCH A
LATCH B
EEPROM
Figure 35. Configuration Update Flow Diagram
Rev. A | Page 26 of 33
FUNCTION
(OV THRESHOLD
ON VP1)
09332-035
POWER-UP
(VCC > 2.5V)
Data Sheet
ADM1166
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same
way as regular configuration latches. The SE has its own dedicated
512-byte nonvolatile, electrically erasable, programmable, readonly memory (EEPROM) for storing state definitions, providing
63 individual states each with a 64-bit word (one state is reserved).
At power-up, the first state is loaded from the SE EEPROM into
the engine itself. When the conditions of this state are met, the
next state is loaded from the EEPROM into the engine, and so
on. The loading of each new state takes approximately 10 μs.
To alter a state, the required changes must be made directly to
the EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to the EEPROM.
INTERNAL REGISTERS
The ADM1166 contains a large number of data registers. The
principal registers are the address pointer register and the
configuration registers.
Address Pointer Register
The address pointer register contains the address that selects
one of the other internal registers. When writing to the ADM1166,
the first byte of data is always a register address that is written to
the address pointer register.
Configuration Registers
The configuration registers provide control and configuration
for various operating parameters of the ADM1166.
EEPROM
The ADM1166 has two 512-byte cells of nonvolatile EEPROM
from Address 0xF800 to Address 0xFBFF. The EEPROM is used
for permanent storage of data that is not lost when the ADM1166 is
powered down. One EEPROM cell, 0xF800 to 0xF9FF, contains the
configuration data, user information and, if enabled, any fault
records of the device; the other section, 0xFA00 to 0xFBFF, contains
the state definitions for the SE. Although referred to as read-only
memory, the EEPROM can be written to, as well as read from,
using the serial bus in exactly the same way as the other registers.
The major differences between the EEPROM and other
registers are as follows:
Page 8 to Page 11 are available for customer use to store any
information that may be required by the customer in their
application. Customers can store information on Page 12 to
Page 15, or these pages can store the fault records written by the
sequencing engine if users have decided to enable writing of the
fault records for different states.
Data can be downloaded from the EEPROM to the RAM in one
of the following ways:
At power-up, when Page 0 to Page 4 are downloaded.
By setting Bit 0 of the UDOWNLD register (0xD8), which
performs a user download of Page 0 to Page 4.
When the sequence engine is enabled, it is not possible to access
the section of EEPROM from Address 0xFA00 to Address 0xFBFF.
The sequence engine must be halted before it is possible to read
or write to this range. Attempting to read or write to this range if
the sequence engine is not halted will generate a no acknowledge,
or NACK.
Read/write access to the configuration and user EEPROM ranges
from Address 0xF800 to Address 0xF89F and Address 0xF900
to Address 0xF9FF depends on whether the black box fault
recorder is enabled. If the fault recorder is enabled and one or
more states have been set as fault record trigger states, then it is
not possible to access any EEPROM location in this range
without first halting the black box. Attempts to read or write
this EEPROM range while the fault recorder is operating are
acknowledged by the device but do not return any useful data
or modify the EEPROM in any way.
If none of the states are set as fault record trigger states, then the
black box is considered disabled, and read/write access is allowed
without having to halt the black box fault recorder.
SERIAL BUS INTERFACE
The ADM1166 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device under
the control of a master device. It takes approximately 1 ms after
power-up for the ADM1166 to download from its EEPROM.
Therefore, access to the ADM1166 is restricted until the
download is complete.
Identifying the ADM1166 on the SMBus
An EEPROM location must be blank before it can be
written to. If it contains data, the data must first be erased.
Writing to the EEPROM is slower than writing to the RAM.
Writing to the EEPROM should be restricted because it has
a limited write/cycle life of typically 10,000 write operations
due to the usual EEPROM wear-out mechanisms.
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes each.
Page 0 to Page 3, from Address 0xF800 to Address 0xF89F, hold
the configuration data for the applications on the ADM1166
(such as the SFDs and PDOs). These EEPROM addresses are
the same as the RAM register addresses, prefixed by F8. Page 5
to Page 7, from Address 0xF8A0 to Address 0xF8FF, are reserved.
The ADM1166 has a 7-bit serial bus slave address (see Table 11).
The device is powered up with a default serial bus address. The
five MSBs of the address are set to 01101; the two LSBs are
determined by the logical states of Pin A1 and Pin A0. This
allows the connection of four ADM1166 devices to one SMBus.
Table 11. Serial Bus Slave Address
A1 Pin
Low
Low
High
High
1
A0 Pin
Low
High
Low
High
Hex Address
0x68
0x6A
0x6C
0x6E
7-Bit Address1
0110100x
0110101x
0110110x
0110111x
x = Read/write bit. The address is shown only as the first seven MSBs.
Rev. A | Page 27 of 33
ADM1166
Data Sheet
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 12 lists these registers
with their values and functions.
Table 12. Identification Register Values and Functions
Name
MANID
Address
0xF4
Value
0x41
REVID
MARK1
MARK2
0xF5
0xF6
0xF7
0x02
0x00
0x00
All other devices on the bus remain idle while the selected
device waits for data to be read from or written to it. If the
R/W bit is a 0, the master writes to the slave device. If the
R/W bit is a 1, the master reads from the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period because a low-to-high
transition when the clock is high could be interpreted as a
stop signal. If the operation is a write operation, the first
data byte after the slave address is a command byte. This
command byte tells the slave device what to expect next. It
may be an instruction telling the slave device to expect a
block write, or it may be a register address that tells the
slave where subsequent data is to be written. Because data
can flow in only one direction, as defined by the R/W bit,
sending a command to a slave device during a read operation
is not possible. Before a read operation, it may be necessary
to perform a write operation to tell the slave what sort of
read operation to expect and/or the address from which
data is to be read.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device releases the SDA line during the
low period before the ninth clock pulse, but the slave device
does not pull it low. This is known as a no acknowledge. The
master then takes the data line low during the low period
before the 10th clock pulse and then high during the 10th clock
pulse to assert a stop condition.
2.
Function
Manufacturer ID for Analog
Devices
Silicon revision
Software brand
Software brand
General SMBus Timing
Figure 36, Figure 37, and Figure 38 are timing diagrams for
general read and write operations using the SMBus. The
SMBus specification defines specific conditions for different
types of read and write operations, which are discussed in the
Write Operations and the Read Operations sections.
The general SMBus protocol operates in the following three steps.
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA, while the serial clock line SCL remains high.
This indicates that a data stream follows. All slave peripherals
connected to the serial bus respond to the start condition
and shift in the next eight bits, consisting of a 7-bit slave
address (MSB first) plus an R/W bit. This bit determines
the direction of the data transfer, that is, whether data is
written to or read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and by holding it low during the high period
of this clock pulse.
1
9
3.
1
9
SCL
0
SDA
1
1
0
1
A1
A0
D7
R/W
D6
D5
SDA
(CONTINUED)
D3
D2
D1
FRAME 2
COMMAND CODE
1
D7
9
D6
D5
D4
D3
D0
ACK. BY
SLAVE
FRAME 1
SLAVE ADDRESS
SCL
(CONTINUED)
D4
ACK. BY
SLAVE
START BY
MASTER
D2
FRAME 3
DATA BYTE
D1
D0
1
D7
ACK. BY
SLAVE
9
D6
D5
D4
D2
FRAME N
DATA BYTE
Figure 36. General SMBus Write Timing Diagram
Rev. A | Page 28 of 33
D3
D1
D0
ACK. BY
SLAVE
STOP
BY
MASTER
09332-036
1.
Data Sheet
ADM1166
1
9
1
9
SCL
1
1
0
1
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
1
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
FRAME 1
SLAVE ADDRESS
D6
D5
D4
D3
9
D2
D1
D0
FRAME 2
DATA BYTE
1
D7
D6
D5
ACK. BY
MASTER
FRAME 3
DATA BYTE
D0
ACK. BY
MASTER
D4
9
D3
D2
FRAME N
DATA BYTE
D1
D0
STOP
BY
MASTER
NO ACK.
09332-037
0
SDA
Figure 37. General SMBus Read Timing Diagram
tR
tF
t HD; S TA
t LO W
t HI G H
t HD; S TA
t HD; D AT
t SU; S TA
t SU; S TO
t SU; D AT
SDA
t BUF
P
S
S
P
09332-038
SCL
Figure 38. Serial Bus Timing Diagram
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1166 contains volatile registers (RAM) and nonvolatile
registers (EEPROM). User RAM occupies Address 0x00 to
Address 0xDF, and the EEPROM occupies Address 0xF800 to
Address 0xFBFF.
Data can be written to and read from both the RAM and the
EEPROM as single data bytes. Data can be written only to
unprogrammed EEPROM locations. To write new data to a
programmed location, the location contents must first be erased.
EEPROM erasure cannot be done at the byte level. The EEPROM
is arranged as 32 pages of 32 bytes each, and an entire page
must be erased.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
Rev. A | Page 29 of 33
ADM1166
Data Sheet
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 39 to Figure 47:
S = Start
P = Stop
R = Read
W = Write
A = Acknowledge
A = No acknowledge
1
S
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
4.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an acknowledge (ACK)
on SDA.
The master sends a command code.
The slave asserts an ACK on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
In the ADM1166, the send byte protocol is used for the
following two purposes:
To write a register address to the RAM for a subsequent
single byte read from the same address, or for a block read
or block write starting at that address, as shown in Figure 39.
1
2
S
SLAVE
ADDRESS
W
3
4
5
6
A
RAM
ADDRESS
(0x00 TO 0xDF)
A
P
09332-039
Figure 39. Setting a RAM Address for Subsequent Read
W
4
5
6
A
COMMAND
BYTE
(0xFE)
A
P
As soon as the ADM1166 receives the command byte,
page erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
erasure takes approximately 20 ms. If the ADM1166 is
accessed before erasure is complete, it responds with a
no acknowledge (NACK).
Send Byte
3.
SLAVE
ADDRESS
3
Figure 40. EEPROM Page Erasure
The ADM1166 uses the following SMBus write protocols.
1.
2.
2
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
programmed, the page(s) containing those locations must
first be erased. EEPROM memory is erased by writing a
command byte.
Write Byte/Word
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device,
as follows:
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code.
5. The slave asserts an ACK on SDA.
6. The master sends a data byte.
7. The slave asserts an ACK on SDA.
8. The master sends a data byte or asserts a stop condition.
9. The slave asserts an ACK on SDA.
10. The master asserts a stop condition on SDA to end the
transaction.
1.
2.
In the ADM1166, the write byte/word protocol is used for three
purposes:
To write a single byte of data to the RAM. In this case, the
command byte is RAM Address 0x00 to RAM Address 0xDF,
and the only data byte is the actual data, as shown in Figure 41.
1
2
3
SLAVE
S ADDRESS W A
4
5
6
7 8
RAM
ADDRESS
A DATA A P
(0x00 TO 0xDF)
09332-041
09332-040
The master sends a command code telling the slave device
to erase the page. The ADM1166 command code for a page
erasure is 0xFE (1111 1110). Note that for a page erasure to
take place, the page address must be given in the previous
write word transaction (see the Write Byte/Word section). In
addition, Bit 2 in the UPDCFG register (Address 0x90)
must be set to 1.
WRITE OPERATIONS
Figure 41. Single Byte Write to the RAM
Rev. A | Page 30 of 33
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case, the
command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The only data byte is the low
byte of the EEPROM address, as shown in Figure 42.
Data Sheet
4
5
6
7 8
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
S ADDRESS W A
A
A P
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
Figure 42. Setting an EEPROM Address
Because a page consists of 32 bytes, only the three MSBs of
the address low byte are important for page erasure. The
lower five bits of the EEPROM address low byte specify the
addresses within a page and are ignored during an erase
operation.
To write a single byte of data to the EEPROM. In this case,
the command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The first data byte is the low
byte of the EEPROM address, and the second data byte is
the actual data, as shown in Figure 43.
1
S
2
3
SLAVE W A
ADDRESS
4
5
6
7
8
Note that the ADM1166 features a clock extend function for writes
to the EEPROM. Programming an EEPROM byte takes approximately 250 μs, which limits the SMBus clock for repeated or block
write operations. The ADM1166 pulls SCL low and extends the
clock pulse when it cannot accept any more data.
READ OPERATIONS
9 10
EEPROM
EEPROM
ADDRESS
ADDRESS
A
A DATA A P
LOW BYTE
HIGH BYTE
(0x00 TO 0xFF)
(0xF8 TO 0xFB)
The ADM1166 uses the following SMBus read protocols.
09332-043
Receive Byte
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
Figure 43. Single Byte Write to the EEPROM
Block Write
1.
2.
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1166, a send byte operation sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code that tells the slave
device to expect a block write. The ADM1166 command
code for a block write is 0xFC (1111 1100).
5. The slave asserts an ACK on SDA.
6. The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
7. The slave asserts an ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts an ACK on SDA after each data byte.
10. The master asserts a stop condition on SDA to end the
transaction.
2
3
4
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts an ACK on SDA.
The master receives a data byte.
The master asserts a NACK on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
3.
4.
5.
6.
1.
2.
1
There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF) to avoid writing to
invalid addresses.
An address crosses a page boundary. In this case, both
pages must be erased before programming.
In the ADM1166, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 44.
1
2
S
SLAVE
ADDRESS
R
3
4
5
6
A
DATA
A
P
09332-045
3
Figure 44. Single Byte Read from the EEPROM or RAM
5
6
7
8
9
10
SLAVE
COMMAND 0xFC
BYTE
DATA
DATA
DATA
A
A
A P
S ADDRESS W A (BLOCK WRITE) A COUNT A
1
2
N
Figure 45. Block Write to the EEPROM or RAM
Rev. A | Page 31 of 33
09332-044
2
09332-042
1
ADM1166
ADM1166
Data Sheet
Block Read
Error Correction
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1166, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as follows:
The ADM1166 provides the option of issuing a packet error correction (PEC) byte after a write to the RAM, a write to the EEPROM,
a block write to the RAM/EEPROM, or a block read from the
RAM/EEPROM. This option enables the user to verify that the data
received by or sent from the ADM1166 is correct. The PEC byte
is an optional byte sent after the last data byte has been written
to or read from the ADM1166. The protocol is the same as a
block read for Step 1 to Step 12 and then proceeds as follows:
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an ACK on SDA.
The master sends a command code that tells the slave
device to expect a block read. The ADM1166 command
code for a block read is 0xFD (1111 1101).
The slave asserts an ACK on SDA.
The master asserts a repeat start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The slave asserts an ACK on SDA.
The ADM1166 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1166
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.
The master asserts an ACK on SDA.
The master receives 32 data bytes.
The master asserts an ACK on SDA after each data byte.
The master asserts a stop condition on SDA to end the
transaction.
13. The ADM1166 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read, if the
PEC byte is incorrect.
14. A NACK is generated after the PEC byte to signal the end
of the read.
15. The master asserts a stop condition on SDA to end the
transaction.
5.
6.
7.
8.
9.
10.
11.
12.
13.
1
S
2
3
4
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
C(x) = x8 + x2 + x1 + 1
See the SMBus Version 1.1 specification for details. An example
of a block read with the optional PEC byte is shown in Figure 47.
5 6
7
8
9
10
11
12
SLAVE
W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A
ADDRESS
(BLOCK READ)
ADDRESS
COUNT
1
13
DATA
A
32
P
09332-046
3.
4.
Figure 46. Block Read from the EEPROM or RAM
1
S
2
3
4
5 6
7
8
9
10
11
12
SLAVE
W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A
ADDRESS
(BLOCK READ)
ADDRESS
COUNT
1
13 14 15
DATA
32
A PEC A P
Figure 47. Block Read from the EEPROM or RAM with PEC
Rev. A | Page 32 of 33
09332-047
1.
2.
Data Sheet
ADM1166
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
31
1
0.50
BSC
TOP VIEW
0.80
0.75
0.70
4.60 SQ
4.50
10
11
20
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*4.70
EXPOSED
PAD
21
0.45
0.40
0.35
PIN 1
INDICATOR
40
30
02-02-2010-A
PIN 1
INDICATOR
0.30
0.25
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 48. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-7)
Dimensions shown in millimeters
0.75
0.60
0.45
1.20
MAX
9.00
BSC SQ
37
36
48
1
PIN 1
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
7.00
BSC SQ
TOP VIEW
0° MIN
(PINS DOWN)
12
13
25
24
VIEW A
VIEW A
0.50
0.27
BSC
0.22
LEAD PITCH
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABC
Figure 49. 48-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADM1166ACPZ
ADM1166ACPZ-REEL
ADM1166ASUZ
ADM1166ASUZ-REEL7
EVAL-ADM1166TQEBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
48-Lead Thin Plastic Quad Flat Package [TQFP]
48-Lead Thin Plastic Quad Flat Package [TQFP]
Evaluation Kit [TQFP]
Z = RoHS Compliant Part.
©2010–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09332-0-3/15(A)
Rev. A | Page 33 of 33
Package Option
CP-40-7
CP-40-7
SU-48
SU-48
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