Digital Power Monitor
with Clear Pin and ALERT Output
ADM1192
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Powered from 3.15 V to 26 V
Precision current sense amplifier
Precision voltage input
12-bit ADC for current and voltage readback
ALERT output allows basic P-channel FET hot swap up to 26 V
SETV input for setting overcurrent alert threshold
Programmable overcurrent filtering via TIMER pin
CLRB input pin
I2C fast mode-compliant interface (400 kHz maximum)
10-lead MSOP
ADM1192
SDA
V
VCC
0
12-BIT
ADC
I
I2C
SCL
1
A
SENSE
ADR
MUX
CURRENT
SENSE
AMPLIFIER
ALERT
ALERT
SETV
GENERAL DESCRIPTION
CLRB
An internal current sense amplifier measures voltage across the
sense resistor in the power path via the VCC pin and the SENSE pin.
A 12-bit ADC can measure the current seen in the sense resistor
and in the supply voltage on the VCC pin. An industry-standard
I2C interface allows a controller to read current and voltage
data from the ADC. Measurements can be initiated by an I2C
command. Alternatively, the ADC can run continuously, and
the user can read the latest conversion data whenever it is
required. Up to four unique I2C addresses can be created,
depending on the way the ADR pin is connected.
A SETV pin is also included. A voltage applied to this pin is
internally compared with the output voltage on the current sense
amplifier. The output of the SETV comparator asserts when the
current sense amplifier output exceeds the SETV voltage. This
event is detected at the ALERT block. The ALERT block then
charges up the external TIMER capacitor with a fixed current.
When this timing cycle is complete, the ALERT output asserts.
TIMER
Figure 1.
3.15V TO 26V
RSENSE
VCC
The ADM1192 is an integrated current sense amplifier that
offers digital current and voltage monitoring via an on-chip
12-bit analog-to-digital converter (ADC), communicated
through an I2C® interface.
Rev. D
GND
SENSE
ALERT
CONTROLLER
INTERRUPT
ADM1192
SDA
SCL
SETV
CLRB
P = VI
SDA
SCL
CLRB
TIMER
GND
ADR
05754-002
Power monitoring/power budgeting
Central office equipment
Telecommunications and data communications equipment
PCs/servers
05754-001
COMPARATOR
APPLICATIONS
Figure 2. Applications Diagram
The ALERT output can be used as a flag to warn a microcontroller or field programmable gate array (FPGA) of an
overcurrent condition. ALERT outputs of multiple ADM1192
devices can be tied together and used as a combined alert.
A basic P-channel FET hot swap circuit can be implemented
with the ALERT output. The value of the TIMER capacitor
should be set so that the charging time of this capacitor is much
longer than the period during which a higher than nominal
inrush current may be flowing.
The ADM1192 is packaged in a 10-lead MSOP.
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ADM1192
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Identifying the ADM1192 on the I2C Bus ............................... 10
Applications ....................................................................................... 1
General I2C Timing .................................................................... 10
General Description ......................................................................... 1
Write and Read Operations ........................................................... 12
Functional Block Diagram .............................................................. 1
Quick Command ........................................................................ 12
Revision History ............................................................................... 2
Write Command Byte ................................................................ 12
Specifications..................................................................................... 3
Write Extended Command Byte .............................................. 13
Absolute Maximum Ratings............................................................ 5
Read Voltage and/or Current Data Bytes ................................ 14
Thermal Characteristics .............................................................. 5
Applications Information .............................................................. 16
ESD Caution .................................................................................. 5
ALERT Output............................................................................ 16
Pin Configuration and Function Descriptions ............................. 6
SETV Pin ..................................................................................... 16
Typical Performance Characteristics ............................................. 7
Kelvin Sense Resistor Connection ........................................... 16
Voltage and Current Readback ..................................................... 10
Outline Dimensions ....................................................................... 17
Serial Bus Interface ..................................................................... 10
Ordering Guide .......................................................................... 17
REVISION HISTORY
7/13—Rev. C to Rev. D
Changed SETV Pin Rating, Table 2 ............................................... 5
Changes to CLRB Pin and ALERT Pin Descriptions, Table 4 .... 6
Changes to Table 15 ........................................................................ 15
Changes to the Implementing a Basic Hot Swap Circuit and the
SETV Pin Sections .......................................................................... 16
Changes to Figure 28 ...................................................................... 16
Moved the Kelvin Sense Resistor Connection Section .............. 16
6/12—Rev. B to Rev. C
Changes to Low Level Input Voltage, VIL Parameter, Test
Conditions/Comments Column, Table 1 and High Level Input
Voltage, VIH Parameter, Test Conditions/Comments Column,
Table 1 ................................................................................................ 3
Changes to SETV Pin Parameter, Rating Column, Table 2 ........ 5
Changes to Pin 3, Description Column, Table 4 and Pin 10
Description Column, Table 4 .......................................................... 6
Changes to Bit 2, Function Column, Table 9 .............................. 13
Changes to Overcurrent Flag Section .......................................... 16
Changes to Kelvin Sense Resistor Connection Section ............. 17
Deleted Figure 30; Renumbered Sequentially ............................ 17
Updated Outline Dimensions ....................................................... 18
Added ADC Conversion Time Parameter .....................................3
Changes to Input Current for 00 Decode, IADRLOW, Parameter ....4
Changes to Input Current for 11 Decode, IADRHIGH, Parameter ...4
Added Endnote 2 ...............................................................................4
Changes to Figure 6 ...........................................................................7
Changes to Figure 17.........................................................................9
Changes to General I2C Timing Section, Step 3 ......................... 10
Changes to Table 5.......................................................................... 10
Changes to Quick Command Section ......................................... 12
Changes to Figure 21...................................................................... 12
Changes to Table 7.......................................................................... 12
Changes to Write Extended Command Byte Section ................ 13
Changes to Figure 23...................................................................... 13
Changes to Table 9 and Table 11 .................................................. 13
Changes to Converting ADC Codes to Voltage and
Current Readings Section.............................................................. 14
Changes to Figure 27...................................................................... 16
4/07—Rev. 0 to Rev. A
Changes to Table 5.......................................................................... 10
Changes to Figure 18 and Figure 19............................................. 11
Changes to Figure 23...................................................................... 13
Changes to Figure 25 and Figure 26............................................. 14
Added Applications Information Heading ................................. 16
2/08—Rev. A to Rev. B
Changes to Figure 2 .......................................................................... 1
Changed VVCC to VCC Throughout ................................................. 3
9/06—Revision 0: Initial Version
Rev. D | Page 2 of 20
Data Sheet
ADM1192
SPECIFICATIONS
VCC = 3.15 V to 26 V, TA = −40°C to +85°C, typical values at TA = 25°C, unless otherwise noted.
Table 1.
Parameter
VCC PIN
Operating Voltage Range, VCC
Supply Current, ICC
Undervoltage Lockout, VUVLO
Undervoltage Lockout Hysteresis, VUVLOHYST
MONITORING ACCURACY 1
Current Sense Absolute Accuracy
0°C to +70°C
0°C to +85°C
−40°C to +85°C
Min
Typ
3.15
1.7
2.8
80
Max
Unit
26
2
V
mA
V
mV
Test Conditions/Comments
VCC rising
−1.45
+1.45
%
VSENSE = 75 mV
−1.8
+1.8
%
VSENSE = 50 mV
−2.8
+2.8
%
VSENSE = 25 mV
−5.7
+5.7
%
VSENSE = 12.5 mV
−1.5
+1.5
%
VSENSE = 75 mV
−1.8
+1.8
%
VSENSE = 50 mV
−2.95
+2.95
%
VSENSE = 25 mV
−6.1
+6.1
%
VSENSE = 12.5 mV
−1.95
+1.95
%
VSENSE = 75 mV
−2.45
+2.45
%
VSENSE = 50 mV
−3.85
+3.85
%
VSENSE = 25 mV
+6.7
%
VSENSE = 12.5 mV
−6.7
VSENSE for ADC Full Scale 2
Voltage Sense Accuracy
105.84
mV
0°C to +70°C
−0.85
+0.85
%
VCC = 3.0 V to 5.5 V (low range)
0°C to +85°C
−0.9
−0.85
+0.9
+0.85
%
%
VCC = 10.8 V to 16.5 V (high range)
VCC = 3.0 V to 5.5 V (low range)
−0.9
+0.9
%
VCC = 10.8 V to 16.5 V (high range)
−0.9
+0.9
%
VCC = 3.0 V to 5.5 V (low range)
−1.15
+1.15
%
VCC = 10.8 V to 16.5 V (high range)
−40°C to +85°C
VCC for ADC Full Scale 3
Low Range (VRANGE = 1)
High Range (VRANGE = 0)
CLRB PIN
Logic Low Threshold, VCLRBL
Input Current for Logic Low Input, ICLRBL
Logic High Threshold, VCLRBH
Input Current for Logic High Input, ICLRBH
ADC CONVERSION TIME 4
SENSE PIN
Input Current, ISENSE
SETV PIN
Overcurrent Trip Threshold
Overcurrent Trip Gain, VSETV/(VCC − VSENSE)
Input Current, ISETVLEAK
Glitch Filter, tSETVGLITCH
6.65
26.52
V
V
0.8
−40
1.6
−22
3
150
−1
98
49.5
100
50
18
−1
3
Rev. D | Page 3 of 20
6
V
µA
mV
µA
µs
VCLRB = 0 V to 0.8 V
VCLRB = 1.6 V to 5.5 V
+1
µA
VSENSE = VCC
102
50.5
mV
mV
+1
µA
µs
VSETV = 1.8 V
VSETV = 0.9 V
VSETV = 0.9 V to 1.9 V
VSETV = 0.9 V to 1.9 V
ADM1192
Parameter
TIMER PIN
Pull-Up Current (Overcurrent Fault), ITIMERUPOC
Pull-Down Current, ITIMERDN
Pin Threshold High, VTIMERH
ALERT PIN
Output Low Voltage, VALERTOL
Input Current, IALERT
ADR PIN
Set Address to 00, VADRLOWV
Set Address to 01, RADRLOWZ
Data Sheet
Min
Typ
Max
Unit
Test Conditions/Comments
−46
−62
100
1.3
−78
1.325
µA
µA
V
(18.125 × VSENSE) > VSETV, VTIMER = 1 V
Normal operation, VTIMER = 1 V
TIMER rising
0.05
1
0.1
1.5
+1
V
mA
µA
IALERT = −100 µA
IALERT = −2 mA
VALERT = VCC; ALERT asserted
0.8
160
V
kΩ
+0.3
µA
5.5
V
µA
Low state
Resistor to ground state, load pin with
specified resistance for 01 decode
Open state, maximum load allowed on
ADR pin for 10 decode
High state
VADR = 0 V to 0.8 V
6
µA
VADR = 2.0 V to 5.5 V
0.3 VBUS
VBUS = 3.0 V to 5.5 V
VBUS = 3.0 V to 5.5 V
IOL = 3 mA
CBUS = bus capacitance from SDA to GND
1.275
−1
0
80
Set Address to 10, IADRHIGHZ
−0.3
Set Address to 11, VADRHIGHV
Input Current for 00 Decode, IADRLOW
2
−40
120
−25
Input Current for 11 Decode, IADRHIGH
I C TIMING
Low Level Input Voltage, VIL
High Level Input Voltage, VIH
Low Level Output Voltage on SDA, VOL
Output Fall Time on SDA from VIHMIN to VILMAX
Maximum Width of Spikes Suppressed by
Input Filtering on SDA Pin and SCL Pin
Input Current, II, on SDA/SCL When Not
Driving a Logic Low Output
Input Capacitance on SDA/SCL
SCL Clock Frequency, fSCL
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for Repeated Start Condition, tSU;STA
SDA Output Data Hold Time, tHD;DAT
Setup Time for a Stop Condition, tSU;STO
Bus Free Time Between a Stop and a Start
Condition, tBUF
Capacitive Load for Each Bus Line
3
2
20 + 0.1 CBUS
50
0.4
250
250
V
V
V
ns
ns
−10
+10
µA
0.7 VBUS
5
400
600
1300
600
100
600
1300
900
400
pF
kHz
ns
ns
ns
ns
ns
ns
pF
Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC
error, and error in ADC full-scale code conversion factor.
2
This is an absolute value to be used when converting ADC codes to current readings; any inaccuracy in this value is factored into absolute current accuracy values (see the
Specifications for the Current Sense Absolute Accuracy parameter).
3
These are absolute values to be used when converting ADC codes to voltage readings; any inaccuracy in these values is factored into voltage accuracy values (see the
Specifications for the Voltage Sense Accuracy parameter).
4
Time between the receipt of the command byte and the actual ADC result being placed in the register.
1
Rev. D | Page 4 of 20
Data Sheet
ADM1192
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 2.
Parameter
VCC Pin
SENSE Pin
TIMER Pin
CLRB Pin
SETV Pin
ALERT Pin
SDA Pin, SCL Pin
ADR Pin
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
30 V
30 V
−0.3 V to +6 V
−0.3 V to +6 V
30 V
30 V
−0.3 V to +6 V
−0.3 V to +6 V
−65°C to +125°C
−40°C to +85°C
300°C
150°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
10-Lead MSOP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. D | Page 5 of 20
θJA
137.5
Unit
°C/W
ADM1192
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SETV 3
GND 4
TIMER 5
10 ALERT
ADM1192
9
CLRB
TOP VIEW
(Not to Scale)
8
ADR
7
SDA
6
SCL
05754-003
VCC 1
SENSE 2
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
VCC
2
SENSE
3
SETV
4
5
GND
TIMER
6
7
8
SCL
SDA
ADR
9
CLRB
10
ALERT
Description
Positive Supply Input Pin. The operating supply voltage range is 3.15 V to 26 V. An undervoltage lockout (UVLO)
circuit resets the ADM1192 when a low supply voltage is detected.
Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin generates a voltage across
a sense resistor. This voltage is proportional to the load current. A current sense amplifier amplifies this
voltage before it is digitized by the ADC.
Input Pin. The voltage driven onto this pin is compared with the output of the internal current sense amplifier.
The lower the voltage on the SETV, the lower the current level that causes the ALERT output to assert. Typical
response time is 1 µs to 2 µs.
Chip Ground Pin.
Timer Input Pin. An external capacitor, CTIMER, sets the timing period for masking overcurrent conditions. This
timing period should be sufficient to allow the inrush current to completely charge up the load without
tripping an overcurrent fault. This makes the device robust against false triggering due to current transients.
I2C Clock Pin. Open-drain input; requires an external resistive pull-up.
I2C Data I/O Pin. Open-drain input/output; requires an external resistive pull-up.
I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four I2C
addresses.
Clear Pin. A latched overcurrent condition can be cleared by toggling this pin low. Holding this pin low
disables the ALERT output.
Alert Output Pin. Active high, open-drain configuration. This pin asserts high when an overcurrent condition is
present. The level at which an overcurrent condition is detected depends on either the voltage on the SETV pin or
the value in the ALERT_TH register. The ALERT_EN register determines which is used in the comparison. This pin has
a latching function and must be cleared manually using either the ALERT_EN register or the CLRB pin.
Rev. D | Page 6 of 20
Data Sheet
ADM1192
TYPICAL PERFORMANCE CHARACTERISTICS
1000
1.8
900
1.6
800
HITS PER CODE (1000 READS)
2.0
1.2
1.0
0.8
0.6
0.4
0.2
4
8
12
16
24
20
28
Figure 4. Supply Current vs. Supply Voltage
400
300
200
0
2046
2047
2048
2049
2050
CODE
Figure 7. ADC Noise with Current Channel, Midcode Input, and 1000 Reads
1000
1.8
900
1.6
800
HITS PER CODE (1000 READS)
2.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
700
600
500
400
300
200
100
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 5. Supply Current vs. Temperature
00 DECODE
01 DECODE
779
780
781
782
783
CODE
Figure 8. ADC Noise with 14:1 Voltage Channel, 5 V Input, and 1000 Reads
1000
10 DECODE 11 DECODE
HITS PER CODE (1000 READS)
900
800
700
600
500
400
300
200
100
0
–30
–25
–20
–15
–10
–5
0
5
IADR (µA)
Figure 6. Address Pin Voltage vs. Address Pin Current
for Four Addressing Options on Each Address Pin
10
3078
05754-026
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–35
0
05754-022
0
–40
05754-061
ICC (mA)
500
05754-060
0
VCC (V)
VADR
600
100
05754-021
0
700
3079
3080
CODE
3081
3082
05754-062
ICC (mA)
1.4
Figure 9. ADC Noise with 7:1 Voltage Channel, 5 V Input, and 1000 Reads
Rev. D | Page 7 of 20
ADM1192
Data Sheet
0.60
4
0.55
3
0.50
ALERT OUTPUT LOW (V)
2
INL (LSB)
1
0
–1
–2
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
–3
500
1000
1500
2000
2500
3000
3500
4000
CODE
0
–40
05754-023
0
–20
0
20
40
60
05754-047
0.05
–4
80
TEMPERATURE (°C)
Figure 10. INL for ADC
Figure 13. ALERT Output Low Voltage vs. Temperature at 1 mA
1.0
4
3
0.8
ALERT OUTPUT LOW (V)
DNL (LSB)
2
1
0
–1
–2
0.6
0.4
0.2
0
500
1000
1500
2000
2500
3000
3500
4000
CODE
0
05754-024
4
6
8
10
12
14
16
18
20
22
24
26
28
Figure 14. ALERT Output Low Voltage vs. Supply Voltage at 1 mA
2.0
100
1.8
90
1.6
ALERT OUTPUT LOW (V)
80
70
60
50
40
30
1.4
1.2
1.0
0.8
0.6
20
0.4
10
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VSETV (V)
05754-046
VLIM (mV)
2
VCC (V)
Figure 11. DNL for ADC
0
0
Figure 12. Overcurrent Limit Threshold vs. SETV Pin Voltage
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
ILOAD (mA)
Figure 15. ALERT Output Low Voltage vs. Load Current
Rev. D | Page 8 of 20
05754-049
–4
05754-048
–3
ADM1192
2.0
1.8
1.8
1.6
1.6
HIGH
1.2
1.0
0.8
0.6
1.2
1.0
0.8
0.6
0.4
0.4
0.2
0.2
0
3
5
7
9
11
13
15
17
19
21
23
VCC (V)
25
HIGH
1.4
0
–40
–20
0
20
40
60
TEMPERATURE (°C)
Figure 17. Timer Threshold vs. Temperature
Figure 16. Timer Threshold vs. Supply Voltage
Rev. D | Page 9 of 20
80
05754-039
1.4
TIMER THRESHOLD (V)
2.0
05754-038
TIMER THRESHOLD (V)
Data Sheet
ADM1192
Data Sheet
VOLTAGE AND CURRENT READBACK
The ADM1192 contains the components to allow voltage and
current readback over an I2C bus. The voltage output of the
current sense amplifier and the voltage on the VCC pin are fed
into a 12-bit ADC via a multiplexer. The device can be instructed
to convert voltage and/or current at any time during operation
via an I2C command. When all conversions are complete, the
voltage and/or current values can be read back with 12-bit
accuracy in two or three bytes.
SERIAL BUS INTERFACE
Control of the ADM1192 is carried out via the serial system
management bus (I2C). This interface is compatible with the I2C
fast mode (400 kHz maximum). The ADM1192 is connected to
this bus as a slave device, under the control of a master device.
2.
IDENTIFYING THE ADM1192 ON THE I2C BUS
The ADM1192 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The five MSBs of the address are set to 01011; the two LSBs are
determined by the state of the ADR pin. There are four configurations available on the ADR pin that correspond to four I2C
addresses for the two LSBs (see Table 5). This scheme allows four
ADM1192 devices to operate on a single I2C bus.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such as
telling the slave device to expect a block write, or it can be
a register address that tells the slave where subsequent data
is to be written.
Because data can flow in only one direction, as defined by
the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it may be necessary to first execute a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.
GENERAL I2C TIMING
Figure 18 and Figure 19 show timing diagrams for general write
and read operations using the I2C. The I2C specification defines
conditions for different types of read and write operations, which
are discussed in the Write and Read Operations section. The
general I2C protocol operates as follows:
1.
The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains
high. This indicates that a data stream is to follow. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a 7-bit
slave address (MSB first) plus an R/W bit that determines the
direction of the data transfer, that is, whether data is written to
or read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse. All other devices on the bus now remain
idle while the selected device waits for data to be read from
it or written to it. If the R/W bit is 0, the master writes to
the slave device. If the R/W bit is 1, the master reads from
the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period because a low-to-high transition
when the clock is high can be interpreted as a stop signal.
3.
When all data bytes are read or written, stop conditions are
established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition.
In read mode, the master device releases the SDA line
during the SCL low period before the ninth clock pulse,
but the slave device does not pull it low. This is known as a
no acknowledge. The master then takes the data line low
during the SCL low period before the 10th clock pulse, and
then high during the 10th clock pulse to assert a stop
condition.
Table 5. Setting I2C Addresses via the ADR Pin
Base Address
01011
1
ADR Pin State
Ground
Resistor to ground
Floating
High
ADR Pin Logic State
00
01
10
11
X = don’t care.
Rev. D | Page 10 of 20
Address in Binary 1
0101100X
0101101X
0101110X
0101111X
Address in Hex
0x58
0x5A
0x5C
0x5E
Data Sheet
ADM1192
9
1
9
1
SCL
0
SDA
0
1
1
1
ADRA
ADRB
D7
R/W
D6
D5
ACKNOWLEDGE BY
SLAVE
START BY MASTER
FRAME 1
SLAVE ADDRESS
1
D4
D2
D3
D0
D1
ACKNOWLEDGE BY
SLAVE
FRAME 2
COMMAND CODE
1
9
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
ACKNOWLEDGE BY
SLAVE
FRAME 3
DATA BYTE
D3
D2
D1
D0
ACKNOWLEDGE BY STOP
BY
SLAVE
MASTER
FRAME N
DATA BYTE
05754-004
SDA
(CONTINUED)
Figure 18. General I2C Write Timing Diagram
9
1
9
1
SCL
0
SDA
0
1
1
1
ADRA
ADRB
D7
R/W
D6
D5
D4
ACKNOWLEDGE BY
SLAVE
START BY MASTER
FRAME 1
SLAVE ADDRESS
1
D2
D3
D0
D1
ACKNOWLEDGE BY
MASTER
FRAME 2
DATA BYTE
1
9
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
FRAME 3
DATA BYTE
D2
D1
D0
D7
D6
D5
ACKNOWLEDGE BY
MASTER
D4
D3
FRAME N
DATA BYTE
D2
D1
D0
NO ACKNOWLEDGE STOP
BY
MASTER
Figure 19. General I2C Read Timing Diagram
tLOW
tR
tHD;STA
tF
SCL
tHD;STA
tSU;STA
tHIGH
tHD;DAT
tSU;DAT
tSU;STO
tBUF
P
S
S
Figure 20. Serial Bus Timing Diagram
Rev. D | Page 11 of 20
P
05754-006
SDA
05754-005
SDA
(CONTINUED)
ADM1192
Data Sheet
WRITE AND READ OPERATIONS
WRITE COMMAND BYTE
The I2C specification defines several protocols for different
types of read and write operations. The operations used in the
ADM1192 are discussed in this section. Table 6 shows the
abbreviations used in the command diagrams (see Figure 21
to Figure 26).
In the write command byte operation, the master device sends
a command byte to the slave device, as follows:
Table 6. I2C Abbreviations
Abbreviation
S
P
R
W
A
N
3.
4.
Condition
Start
Stop
Read
Write
Acknowledge
No acknowledge
5.
6.
QUICK COMMAND
1
The quick command operation allows the master to check if the
slave is present on the bus, as follows:
3.
4.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address, followed by the
write bit (low).
The addressed slave device asserts an acknowledge on SDA.
The master asserts a stop condition on SDA to end the
transaction.
1
2
2
3
4
5 6
SLAVE
COMMAND
S ADDRESS W A
A P
BYTE
Figure 22. Write Command Byte
The seven LSBs of the command byte are used to configure and
control the ADM1192. Table 7 provides details of the function
of each bit.
3 4
SLAVE
S ADDRESS W A P
05754-007
1.
2.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address, followed by the
write bit (low).
The addressed slave device asserts an acknowledge on SDA.
The master sends the command byte. The command byte
is identified by an MSB = 0. An MSB = 1 indicates an
extended register write (see the Write Extended Command
Byte section).
The slave asserts an acknowledge on SDA.
The master asserts a stop condition on SDA to end the
transaction.
05754-008
1.
2.
Figure 21. Quick Command
Table 7. Command Byte Operations
Bit
C0
Default
0
Name
V_CONT
C1
0
V_ONCE
C2
0
I_CONT
C3
0
I_ONCE
C4
0
VRANGE
C5
C6
0
0
Not applicable
STATUS_RD
Function
LSB, set to convert voltage continuously. If readback is attempted before the first conversion is complete,
the ADM1192 asserts an acknowledge and returns all 0s in the returned data.
Set to convert voltage once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC
conversion is complete.
Set to convert current continuously. If readback is attempted before the first conversion is complete, the
ADM1192 asserts an acknowledge and returns all 0s in the returned data.
Set to convert current once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC
conversion is complete.
Selects different internal attenuation resistor networks for voltage readback. A 0 in C4 selects a 14:1
voltage divider. A 1 in C4 selects a 7:2 voltage divider. With an ADC full scale of 1.902 V, the voltage at the
VCC pin for an ADC full-scale result is 26.52 V for VRANGE = 0 and 6.65 V for VRANGE = 1.
Unused.
Status Read. When this bit is set, the data byte read back from the ADM1192 is the status byte. This
contains the status of the device alerts. See Table 15 for full details of the status byte.
Rev. D | Page 12 of 20
Data Sheet
ADM1192
7.
8.
In the write extended command byte operation, the master
device writes to one of the three extended registers of the slave
device, as follows:
1.
2.
3.
4.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address, followed by the
write bit (low).
The addressed slave device asserts an acknowledge on SDA.
The master sends the register address byte. The MSB of this
byte is set to 1 to indicate an extended register write. The two
LSBs indicate which of the three extended registers are to be
written to (see Table 8). All other bits should be set to 0.
The slave asserts an acknowledge on SDA.
The master sends the extended command byte (refer to
Table 9, Table 10, and Table 11).
The slave asserts an acknowledge on SDA.
The master asserts a stop condition on SDA to end the
transaction.
1
3
2
4
5
6
7 8
EXTENDED
SLAVE
REGISTER
S ADDRESS W A ADDRESS A COMMAND A P
BYTE
05754-009
WRITE EXTENDED COMMAND BYTE
Figure 23. Write Extended Byte
Table 9, Table 10, and Table 11 provide the details of each
extended register.
Table 8. Extended Register Addresses
A6
0
0
0
A5
0
0
0
A4
0
0
0
A3
0
0
0
A2
0
0
0
A1
0
1
1
A0
1
0
1
Extended Register
ALERT_EN
ALERT_TH
CONTROL
Table 9. ALERT_EN Register Operations
Bit
0
1
Default
0
0
Name
EN_ADC_OC1
EN_ADC_OC4
2
1
EN_OC_ALERT
3
0
EN_OFF_ALERT
4
0
CLEAR
Function
LSB, enabled if a single ADC conversion on the I channel exceeds the threshold set in the ALERT_TH register.
Enabled if four consecutive ADC conversions on the I channel exceed the threshold set in the
ALERT_TH register.
Enables the OC_ALERT register. If an overcurrent condition is present compared to the SETV threshold, and
the TIMER pin charges to 1.3 V, the OC_ALERT register captures and latches this condition.
Enables an alert if the hot swap operation is turned off by an operation that writes the SWOFF bit high.
This allows a software override of the ALERT output and turns on a P-channel FET controlled by ALERT.
Clears the OC_ALERT and ADC_ALERT status bits in the status register. The value of these bits can
immediately change if the source of the alert is not cleared and the alert function is not disabled.
The CLEAR bit self-clears to 0 after the STATUS register bits are cleared.
Table 10. ALERT_TH Register Operations
Bit
[7:0]
Default
FF
Function
The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit
value corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit
0
Default
0
Name
SWOFF
Function
LSB, forces the ALERT pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).
Rev. D | Page 13 of 20
ADM1192
Data Sheet
1
3
2
4
1
The ADM1192 digitizes both voltage and current. Three bytes
are read back in the format shown in Table 12.
SLAVE
S ADDRESS
R A
Byte
1
2
3
Contents
Voltage
MSBs
Current
MSBs
LSBs
B7
V11
B6
V10
B5
V9
B4
V8
B3
V7
B2
V6
B1
V5
B0
V4
I11
I10
I9
I8
I7
I6
I5
I4
V3
V2
V1
V0
I3
I2
I1
I0
Voltage Readback
The ADM1192 digitizes voltage only. Two bytes are read back in
the format shown in Table 13.
Table 13. Voltage Only Readback Format
Byte Contents
1
Voltage MSBs
2
Voltage LSBs
B7 B6 B5 B4 B3 B2
V11 V10 V9 V8 V7 V6
V3 V2 V1 V0 0
0
B1
V5
0
B0
V4
0
6
7
8
9 10
Figure 24. Three-Byte Read from ADM1192
Voltage and Current Readback
Table 12. Voltage and Current Readback Format
5
SLAVE
S ADDRESS R A DATA 1 A DATA 2 A DATA 3 N P
05754-010
Depending on how the device is configured, the ADM1192 can
be set up to provide information in three ways after a conversion
(or conversions): voltage and current readback, voltage only
readback, and current only read back. See the Write Command
Byte section for more details.
For cases where the master is reading voltage only or current
only, two data bytes are read and Step 7 and Step 8 are not required.
2
3
4
5
6
7 8
DATA 1
A
DATA 2
N P
05754-011
READ VOLTAGE AND/OR CURRENT DATA BYTES
Figure 25. Two-Byte Read from ADM1192
Converting ADC Codes to Voltage and Current Readings
Equation 1 and Equation 2 can be used to convert ADC codes
representing voltage and current from the ADM1175 12-bit
ADC into actual voltage and current values.
Voltage = (VFULLSCALE/4096) × Code
(1)
where:
VFULLSCALE = 6.65 V (7:2 range) or 26.52 V (14:1 range).
Code is the ADC voltage code read from the device
(Bit V11 to Bit V0).
Current = ((IFULLSCALE/4096) × Code)/Sense Resistor
(2)
where:
IFULLSCALE = 105.84 mV.
Code is the ADC current code read from the device
(Bit I11 to Bit I0).
Read Status Register
The ADM1192 digitizes current only. Two bytes are read back
in the format shown in Table 14.
Table 14. Current Only Readback Format
Byte Contents
1
Current MSBs
2
Current LSBs
B7
I11
I3
B6
I10
I2
B5 B4 B3 B2
I9 I8 I7 I6
I1 I0 0
0
B1
I5
0
B0
I4
0
A single register of status data can also be read from the
ADM1192 as follows:
1.
2.
3.
4.
5.
1
The following series of events occurs when the master receives
three bytes (voltage and current data) from the slave device:
1.
2.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address, followed by the
read bit (high).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master receives the first data byte.
5. The master asserts an acknowledge on SDA.
6. The master receives the second data byte.
7. The master asserts an acknowledge on SDA.
8. The master receives the third data byte.
9. The master asserts a no acknowledge on SDA.
10. The master asserts a stop condition on SDA, and the
transaction ends.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address, followed by the
read bit (high).
The addressed slave device asserts an acknowledge on SDA.
The master receives the status byte.
The master asserts an acknowledge on SDA.
2
3
SLAVE
S ADDRESS R A
4
5
STATUS
BYTE
A
05754-012
Current Readback
Figure 26. Status Read from ADM1192
Table 15 shows the ADM1192 STATUS registers in detail. Note
that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 (the
CLEAR bit) of the ALERT_EN register.
Rev. D | Page 14 of 20
Data Sheet
ADM1192
Table 15. Status Byte Operations
Bit
0
1
2
Name
ADC_OC
ADC_ALERT
OC
3
OC_ALERT
4
5
OFF_STATUS
OFF_ALERT
Function
An ADC-based overcurrent comparison has been detected on the last three conversions.
An ADC-based overcurrent trip has occurred, causing the alert. Cleared by writing to Bit 4 of the ALERT_EN register.
An overcurrent condition is present (that is, the output of the current sense amplifier is greater than the voltage on the
SETV input).
An overcurrent condition has caused the ALERT block to latch a fault, and the ALERT output has asserted. Cleared by
writing to Bit 4 of the ALERT_EN register or by toggling the CLRB pin low.
Set to 1 by writing to the SWOFF bit of the CONTROL register.
An alert has been caused by the SWOFF bit. Cleared by writing to Bit 4 of the ALERT_EN register.
Rev. D | Page 15 of 20
ADM1192
Data Sheet
APPLICATIONS INFORMATION
ALERT OUTPUT
SETV PIN
The ALERT output is an open-drain pin with 30 V tolerance.
There are two uses for this output.
The SETV pin allows the user to adjust the current level that
trips the ALERT output. The output of the current sense amplifier
is compared with the voltage driven onto the SETV pin. If the
current sense amplifier output is higher than the SETV voltage,
the output of the comparator asserts. By driving a different voltage
onto the SETV pin, the ADM1192 detects an overcurrent condition
at a different current level, with a gain of 18. The 100 mV ADC
full-scale sense voltage corresponds to 1.8 V on the SETV pin.
See Figure 12 for an illustration of this relationship.
Overcurrent Flag
The ALERT pin can be connected to the general-purpose logic
input of a controller. During normal operation, the ADM1192
drives this output low. When an overcurrent condition occurs,
the output asserts high. An external pull-up resistor should be
used. This pin is configured by default to trigger the SETV
threshold at power-up.
3.15V TO 26V
VCC
VCC
SENSE
ALERT
ADM1192
INTERRUPT
A
P = VI
SDA
SCL
CLRB
SDA
SCL
CURRENT
SENSE
AMPLIFIER
APPLIED
VOLTAGE
SETV
CLRB
TIMER
ALERT
ALERT
60µA
COMPARATOR
05754-013
ADR
GND
SENSE
CONTROLLER
ADM1192
SETV
ILOAD
RSENSE
RSENSE
1.3V
Implementing a Basic Hot Swap Circuit
A basic P-channel FET hot swap circuit can be created. The ALERT
output should be connected to the GATE pin of a P-channel FET
connected in series with the power path. A pull-up from GATE
to source ensures that the P-channel FET GATE is pulled up
and the device held off as soon as power is applied. When the
ADM1192 powers up, the GATE is pulled low by the ALERT
output. A capacitor on the ALERT pin determines the slew rate
of the GATE pin at startup. Note that, if a current fault occurs
during the operation, the ALERT output asserts high, turning
off the P-channel FET.
3.15V TO 26V
RSENSE
VCC
P-CHANNEL FET
SENSE
SDA
SCL
SETV
CLRB
SDA
SCL
CLRB
Figure 28. P-Channel FET Hot Swap Implementation
05754-014
ADR
When the output of the SETV comparator asserts, this tells the
ALERT block to begin charging the external TIMER capacitor
with a 62 μA charging current. When the voltage on the TIMER
capacitor reaches 1.3 V, the charging cycle is complete. The ALERT
output then asserts (goes high). Different values of TIMER
capacitor generate different time delays between current faults
occurring and the ALERT output asserting. When using the
ALERT output to implement a hot swap circuit, the TIMER
capacitor should be chosen to generate a large enough startup
delay to allow the maximum inrush current to completely
charge up the load without tripping an ALERT fault.
When using a low value sense resistor for high current
measurement, the problem of parasitic series resistance can arise.
The pad and solder resistance can be a substantial fraction of the
rated resistance, making the total resistance larger than expected.
P = VI
TIMER
GND
Figure 29. SETV Operation
KELVIN SENSE RESISTOR CONNECTION
CONTROLLER
ALERT
ADM1192
TIMER
05754-015
Figure 27. Using the ALERT Output as an Interrupt
This error problem can be largely avoided by using a Kelvin
sense connection. This type of connection separates the high
current path through the resistor and the voltage drop across the
resistor. A four pad resistor may be used or a split pad layout can be
used with a two pad sense resistor to achieve Kelvin sensing.
Rev. D | Page 16 of 20
Data Sheet
ADM1192
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
5.15
4.90
4.65
6
1
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.70
0.55
0.40
0.23
0.13
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 30. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADM1192-1ARMZ-R7
EVAL-ADM1192EBZ
1
Temperature Range
−40°C to +85°C
Package Description
10-Lead MSOP
Evaluation Board
Z = RoHS Compliant Part.
Rev. D | Page 17 of 20
Package Option
RM-10
Branding
M5M
ADM1192
Data Sheet
NOTES
Rev. D | Page 18 of 20
Data Sheet
ADM1192
NOTES
Rev. D | Page 19 of 20
ADM1192
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05754-0-7/13(D)
Rev. D | Page 20 of 20
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