FEATURES
FUNCTIONAL BLOCK DIAGRAM
Rev. 0
REFOUT REFGND
REFIN CDA
VREF
CCL
INTERCHIP
BUS
ADM1260
VX3
VX4
VX5
A0
EEPROM
FAULT
RECORDING
CONFIGURABLE
OUTPUT
DRIVERS
DUALFUNCTION
INPUTS
VX2
A1
SMBus
INTERFACE
12-BIT
SAR ADC
CLOSED-LOOP
MARGINING SYSTEM
VX1
SDA SCL
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
(LOGIC INPUTS
OR
SFDs)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
SEQUENCING
ENGINE
VP1
VP3
PROGRAMMABLE
RESET
GENERATORS
VP4
(SFDs)
VP2
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VH
AGND
PDO7
PDO8
PDO9
PDO10
PDOGND
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6
VDD
ARBITRATOR
VDDCAP
VCCP GND
12445-001
Complete supervisory and sequencing solution for up to
10 supplies per device
Interchip bus (ICB) simplifies multidevice connections and
sequencing system operation
Supports up to 4 devices
16 event deep black box nonvolatile fault recording
10 supply fault detectors enable supervision of supplies
DPLIMx
In addition, the DAC output buffer is three-stated if DNLIMx >
DPLIMx. By programming the limit registers this way, the user
can make it very difficult for the DAC output buffers to turn on
during normal system operation. The limit registers are among
the registers downloaded from EEPROM at startup.
Rev. 0 | Page 27 of 71
ADM1260
Data Sheet
APPLICATIONS INFORMATION
12V IN
12V OUT
5V IN
5V OUT
3V IN
3V OUT
IN
DC-TO-DC1
EN
VH
POWRON
3.3V STBY
VP1
VP2
VP3
VP4
VX1
VX2
VX3
PDO1
PDO2
VX4
PDO6
IN
DC-TO-DC2
PDO3
PDO4
PDO5
RESET
PDO7
VX5
PDO8
CDL
EN
SIGNAL VALID
DC-TO-DC3
EN
OUT
1.8V OUT
3.3V OUT
DAC1*
IN
REFIN VCCP VDDCAP GND
10µF
2.5V OUT
IN
SYSTEM RESET
PDO10
REFOUT
OUT
PWRGD
PDO9
CDA
10µF
3.3V OUT
LDO
EN
10µF
OUT
0.9V OUT
3.3V OUT
IN
*ONLY ONE MARGINING CIRCUIT SHOWN FOR
CLARITY. DAC1 TO DAC6 ALLOW MARGINING
FOR UP TO SIX VOLTAGE RAILS.
EN
OUT
1.2V OUT
TRIM
DC-TO-DC4
12445-068
5V OUT
3V OUT
3.3V OUT
2.5V OUT
1.8V OUT
1.2V OUT
0.9V OUT
OUT
ADM1260
Figure 35. Single Device Applications Diagram
MULTIPLE DEVICES LINKED BY ICB AND POWER
ISLAND MANAGEMENT
Figure 36 shows a sequencing system with two ADM1260 devices,
linked by the ICB, controlling a number of dc-to-dc supplies. In
some sequencing systems, there may be a need to manage groups
of supplies due to modules being plugged in and out, or a desire to
reduce energy usage by turning off portions of the board to save
power. Achieve these power management requirements by treating
each group as a power island.
These supplies are split into two power islands: one island is for the
main board, and the other island is for a plug in module. Note
that the dc-to-dc supplies in each power island can be split
between the ADM1260 as required; these supplied do not have to
be divided up in the blocks. The supplies are shown this way in
Figure 36 for clarity.
defined main board power-good state. In this state, the sequence
engine is programmed to look at the state of the VX5 digital input
pin, which provides a module detect signal. When this signal is
high, it is detected by Device 1 and initiates the power-up
sequence for the module power island.
The module detect signal is on Device 1, and all the module
supplies are on Device 2. When Device 1 sees that the module
detect signal is high, it signals an event to Device 2 using the ICB.
Then, Device 2 sequences the supplies for the module on.
Similarly, when the module detect signal goes low, Device 1 signals
Device 2, and the module power-down sequence is executed.
The design of the sequence engine allows two power islands to be
easily controlled in this manner. It is also possible to manage three
or perhaps four power islands, depending on the complexity of the
sequencing required.
At power-up, the main board supplies are sequenced on by the
ADM1260 devices, and the sequence engine enters the user
Rev. 0 | Page 28 of 71
Data Sheet
ADM1260
12V IN
12V OUT
IN
DC-TO-DC1
VH
3.3V OUT
2.5V OUT
1.8V OUT
0.9V OUT
MODULE_DETECT
BOARD
MANAGEMENT
CONTROLLER
VP1
VP2
VP3
VP4
VX1
VX2
VX3
VX4
EN
ADM1260
#1
PDO1
12V OUT
IN
DC-TO-DC2
EN
OUT
2.5V OUT
PDO5
PDO6
VX5
12V OUT
PDO7
PDO8
SCL
SDA
PDO9
CCL
CDA
A0
A1
3.3V OUT
PWRGD
SYSTEM
PDO2
RESET
PDO3
PDO4
OUT
IN
MAIN
BOARD
ISLAND
DC-TO-DC3
EN
OUT
1.8V OUT
PDO10
3.3V OUT
GND
IN
DC-TO-DC3
EN
OUT
0.9V OUT
12V OUT
IN
DC-TO-DC1
EN
12V IN
1.2V OUT
3.3V OUT
1.8V OUT
1.5V OUT
VP1
VP2
VP3
VP4
VX1
VX2
VX3
VX4
VX5
ADM1260
#2
PDO1
12V OUT
PDO2
PDO3
PDO4
IN
DC-TO-DC2
EN
OUT
3.3V OUT
PDO5
PDO6
12V OUT
PDO7
PDO8
SCL
SDA
PDO9
CCL
CDA
A0
A1
1.2V OUT
MODULE
ISLAND
IN
DC-TO-DC3
EN
OUT
1.8V OUT
PDO10
3.3V OUT
GND
IN
DC-TO-DC3
EN
Figure 36. Multiple Devices Linked by the ICB Managing a Power Island
Rev. 0 | Page 29 of 71
OUT
1.5V OUT
12445-031
3.3V STBY
VH
OUT
ADM1260
Data Sheet
COMMUNICATING WITH THE ADM1260
CONFIGURATION DOWNLOAD AT POWER-UP
Option 1
The configuration of the ADM1260 (undervoltage/overvoltage
thresholds, glitch filter timeouts, and PDOx configurations) is
dictated by the contents of the RAM. The RAM comprises digital
latches that are local to each function on the device. The latches
are double buffered and have two identical latches, Latch A and
Latch B. Therefore, when an update to a function occurs, the
contents of Latch A are updated first, and then the contents of
Latch B are updated with identical data. The advantages of this
architecture are explained in detail in the Updating the
Configuration section.
Update the configuration in real time. Write to the RAM across
the SMBus to update the configuration immediately.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must
be restored at power-up by downloading the contents of the
EEPROM (nonvolatile memory) to the local latches. This
download occurs in steps, as follows:
1.
With no power applied to the device, the PDOx pins are all
high impedance.
2. When 1.2 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPx), the PDOx pins are all weakly
pulled to GND with a 20 kΩ resistor.
3. When the supply rises above the UVLO threshold of the
device (2.5 V), the EEPROM starts to download to the RAM.
4. The EEPROM downloads its contents to all Latch As.
5. When the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
6. At 0.5 ms after the configuration download completes, the first
state definition is downloaded from the EEPROM into the SE.
Any attempt to communicate with the device prior to the
completion of the download causes the ADM1260 to issue a no
acknowledge .
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
the EEPROM into the RAM registers, the user may need to alter
the configuration of functions on the ADM1260, such as changing
the undervoltage or overvoltage limit of an SFD, changing the
fault output of an SFD, or adjusting the rise time delay of one of
the PDOx pins.
The ADM1260 provides several options that allow the user to
update the configuration over the SMBus interface. The following
three options are controlled in the UPDCFG register.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1260 remains unchanged
and continues to operate in the original setup until the
instruction is given to update the Latch Bs.
Option 3
Change the EEPROM register contents without changing the
RAM contents, and then download the revised EEPROM contents
to the RAM registers. With this method, the configuration of
the ADM1260 remains unchanged and continues to operate in
the original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents if
revisions to the configuration are unsatisfactory. For example,
to alter an overvoltage threshold, update the RAM register as
described in the Option 1 section. However, if the user is not
satisfied with the change and wants to revert to the original
programmed value, the device controller can issue a command to
download the EEPROM contents to the RAM again, as described
in the Option 3 section, restoring the ADM1260 to its original
configuration.
The topology of the ADM1260 makes this type of operation
possible. The local, volatile registers (RAM) are all double
buffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves
the double buffered latches open at all times. If Bit 0 is set to 0
when a RAM write occurs across the SMBus, only the first side
of the double buffered latch is written to. The user must then
write a 1 to Bit 1 of the UPDCFG register. This write generates a
pulse to update all the second latches simultaneously. EEPROM
writes occur in a similar way.
The final bit in this register can enable or disable EEPROM page
erasure. If this bit is set high, the contents of an EEPROM page
can all be set to 1. If this bit is set low, the contents of a page cannot
be erased, even if the command code for page erasure is programmed
across the SMBus. The bit map for the UPDCFG register is
shown in Figure 51. A flow diagram for download at power-up
and subsequent configuration updates is shown in Figure 37.
Rev. 0 | Page 30 of 71
Data Sheet
ADM1260
SMBus
E
E
P
R
O
M
L
D
DEVICE
CONTROLLER
R
A
M
L
D
D
A
T
A
U
P
D
LATCH A
LATCH B
EEPROM
FUNCTION
(OV THRESHOLD
ON VP1)
12445-035
POWER-UP
(VCC > 2.5V)
Figure 37. Configuration Update Flow Diagram
UPDATING THE SEQUENCING ENGINE
SE functions are not updated in the same way as regular
configuration latches. The SE has its own dedicated, 512-byte,
nonvolatile EEPROM for storing state definitions, providing 61
individual states each with a 64-bit word (one state is reserved).
At power-up, the first state is loaded from the SE EEPROM into
the engine itself. When the conditions of this state are met, the
next state is loaded from the EEPROM into the engine, and so
on. The loading of each new state takes approximately 45 μs.
The first EEPROM is split into 16, 32-byte pages (Page 0 to Page 15).
Page 0 to Page 4, from Address 0xF800 to Address 0xF89F, hold the
configuration data for the applications on the ADM1260, such as
the SFDs and PDOx pins. These EEPROM addresses are the same
as the RAM register addresses, prefixed by F8. Page 5 to Page 7,
from Address 0xF8A0 to Address 0xF8FF, are reserved.
To alter a state, the required changes must be made directly to
the EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to the EEPROM.
INTERNAL REGISTERS
The ADM1260 contains a large number of data registers. The
principal registers are the address pointer register and the
configuration registers.
Address Pointer Register
The address pointer register contains the address that selects
one of the other internal registers. When writing to the ADM1260,
the first byte of data is always a register address that is written to
the address pointer register.
Configuration Registers
The configuration registers provide control and configuration
for various operating parameters of the ADM1260.
EEPROM
The ADM1260 has two 512-byte cells of nonvolatile EEPROM
from Address 0xF800 to Address 0xFBFF. The EEPROM is used
for permanent storage of data that is not lost when the ADM1260 is
powered down. One EEPROM cell, Address 0xF800 to
Address 0xF9FF, contains the configuration data, user information,
and, if enabled, any fault records of the device. The other EEPROM
cell section, Address 0xFA00 to Address 0xFBFF, contains the
state definitions for the SE. Although referred to as read-only
memory, the EEPROM can be written to and read from using
the serial bus in exactly the same way as the other registers.
The major differences between the EEPROM and other
registers are as follows:
Restrict writing to the EEPROM because it has a limited
write/cycle life of typically 10,000 write operations due to
typical EEPROM wear out mechanisms.
Page 8 and Page 9 store information required by the GUI. Page 10
and Page 11 are available for the user to store any information
required by the customer in an application. Users can store
information on Page 12 to Page 15, or these pages can store the
fault records written by the sequencing engine if users decide to
enable writing of the fault records for different states.
Download data from the EEPROM to the RAM in one of the
following ways:
At power-up, when Page 0 to Page 4 are downloaded.
By setting Bit 0 of the UDOWNLD register (Register 0xD8),
which performs a user download of Page 0 to Page 4.
When the SE is enabled, it is not possible to access the section of
EEPROM from Address 0xFA00 to Address 0xFBFF. The SE
must be halted before it is possible to read or write to this range.
Attempting to read or write to this range if the sequence engine
is not halted generates a no acknowledge.
Read/write access to the configuration and the user EEPROM
ranges from Address 0xF800 to Address 0xF89F and
Address 0xF900 to Address 0xF9FF depends on whether
the black box fault recorder is enabled. If the fault recorder is
enabled and one or more states are set as fault record trigger
states, it is not possible to access any EEPROM location in this
range without first halting the black box. Attempts to read or write
this EEPROM range while the fault recorder is operating are
acknowledged by the device but do not return any useful data
or modify the EEPROM in any way.
If none of the states are set as fault record trigger states, the
black box is considered disabled, and read/write access is allowed
without having to first halt the black box fault recorder.
SERIAL BUS INTERFACE
An EEPROM location must be blank before it can be
written to. If it contains data, the data must first be erased.
Writing to the EEPROM is slower than writing to the RAM.
The ADM1260 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device under
Rev. 0 | Page 31 of 71
ADM1260
Data Sheet
the control of a master device. It takes approximately 1 ms after
power-up for the ADM1260 to download from the EEPROM.
Therefore, access to the ADM1260 is restricted until the
download is complete.
Identifying the ADM1260 on the SMBus
The ADM1260 has a 7-bit serial bus slave address. The device is
powered up with a default serial bus address. The five MSBs of
the address are set to 01100, and the two LSBs are determined
by the logical states of the A1 and A0 pins. This means it is possible
to have four ADM1260 devices connected to a single SMBus.
All the devices on the same SMBus must also be connected to
the same ICB because all devices connected to the ICB are
intended to operate together.
Table 11. Serial Bus Slave Addresses
A1 Pin
0
0
1
1
A0 Pin
0
1
0
1
Address
0x34
0x35
0x36
0x37
7-Bit Address
011 0100
011 0101
011 0110
011 0111
2.
The device also has several identification registers (read only)
that can be read across the SMBus. Table 12 lists these registers
with their values and functions.
Table 12. Identification Register Values and Functions
Name
MANID
Address
0xF4
Value
0x41
REVID
0xF5
0x2y
Function
Manufacturer ID for Analog
Devices
Super Sequencer family, 2
signifies the ADM1260 and y
signifies the silicon revision
General SMBus Timing
Figure 38, Figure 39, and Figure 40 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations section and the Read Operations section.
3.
The general SMBus protocol operates in the following three
steps:
1.
The master initiates data transfer by establishing a start
condition, defined as a high to low transition on the serial
Rev. 0 | Page 32 of 71
data line, SDA, while the serial clock line, SCL, remains
high. This indicates that a data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a 7-bit
slave address (MSB first) plus an R/W bit. This bit determines
the direction of the data transfer, that is, whether data is
written to or read from the slave device (0 = write, 1 = read).
The peripheral with an address corresponding to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the acknowledge bit, and by holding it low during the
high period of this clock pulse.
All other devices on the bus remain idle while the selected
device waits for data to be read from or written to it. If the
R/W bit is a 0, the master writes to the slave device. If the
R/W bit is a 1, the master reads from the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period because a low to high
transition when the clock is high may be interpreted as a
stop signal. If the operation is a write operation, the first
data byte after the slave address is a command byte. This
command byte tells the slave device what to expect next. It
may be an instruction telling the slave device to expect a
block write, or it may be a register address that tells the
slave where subsequent data is to be written. Because data
can flow in only one direction as defined by the R/W bit,
sending a command to a slave device during a read operation
is not possible. Before a read operation, it may be necessary
to perform a write operation to tell the slave what type of
read operation to expect and/or the address from which
data is to be read.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device releases
the SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is
known as a no acknowledge. The master then takes the
data line low during the low period before the 10th clock
pulse and then high during the 10th clock pulse to assert a
stop condition.
Data Sheet
ADM1260
1
9
1
9
SCL
1
1
0
1
A1
A0
D7
R/W
D6
D5
D4
D3
D2
D1
ACK BY
SLAVE
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND CODE
1
SCL
(CONTINUED)
SDA
(CONTINUED)
9
D7
D6
D5
D4
D3
D0
ACK BY
SLAVE
D2
D1
1
D7
D0
9
D6
D5
D4
ACK BY
SLAVE
FRAME 3
DATA BYTE
D3
D2
D1
D0
ACK BY
SLAVE
FRAME N
DATA BYTE
STOP
BY
MASTER
12445-036
0
SDA
Figure 38. General SMBus Write Timing Diagram
1
9
1
9
SCL
1
1
0
1
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK BY
SLAVE
START BY
MASTER
1
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
FRAME 1
SLAVE ADDRESS
D6
D5
D4
D3
9
D2
D1
D0
FRAME 2
DATA BYTE
1
D7
D6
D5
D4
ACK BY
MASTER
FRAME 3
DATA BYTE
D0
ACK BY
MASTER
9
D3
D2
D1
D0
STOP
BY
MASTER
NACK
FRAME N
DATA BYTE
12445-037
0
SDA
Figure 39. General SMBus Read Timing Diagram
tR
tF
tHD;STA
tLOW
SCL
tHIGH
tHD;STA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
tBUF
P
S
S
P
12445-038
SDA
Figure 40. Serial Bus Timing Diagram
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1260 contains volatile registers (RAM) and nonvolatile
registers (EEPROM). User RAM occupies Address 0x00 to
Address 0xDF, and the EEPROM occupies Address 0xF800 to
Address 0xFBFF.
Data can be written to and read from both the RAM and the
EEPROM as single data bytes. Data can be written only to
unprogrammed EEPROM locations. To write new data to a
programmed location, the location contents must first be erased.
EEPROM erasure cannot be done at the byte level. The EEPROM
is arranged as 32 pages of 32 bytes each, and an entire page
must be erased.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
Rev. 0 | Page 33 of 71
ADM1260
Data Sheet
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 41 to Figure 49:
S = start
P = stop
R = read
W = write
A = acknowledge
A = no acknowledge
Write Byte/Word
In a write byte/word operation, the master device sends a command
byte and one or two data bytes to the slave device, as follows:
1.
2.
Send Byte
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
1.
2.
3.
4.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an acknowledge on
SDA.
The master sends a command code.
The slave asserts an acknowledge on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
In the ADM1260, the write byte/word protocol is used for the
following three purposes:
To write a single byte of data to the RAM. In this case, the
command byte is RAM Address 0x00 to RAM Address 0xDF,
and the only data byte is the actual data, as shown in Figure 43.
1
In the ADM1260, the send byte protocol is used for the following
two purposes:
To write a register address to the RAM for a subsequent
single-byte read from the same address, or for a block read
or block write starting at that address, as shown in Figure 41.
1
S
2
SLAVE
ADDRESS
W
3
4
5
6
A
RAM
ADDRESS
(0x00 TO 0xDF)
A
P
S
2
SLAVE
ADDRESS
W
3
4
5
6
A
COMMAND
BYTE
(0xFE)
A
P
6
7 8
2
3
4
5
6
7 8
EEPROM
EEPROM
ADDRESS
ADDRESS
S SLAVE W A
A
A P
ADDRESS
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
Figure 44. Setting an EEPROM Address
Because a page consists of 32 bytes, only the three MSBs of the
address low byte are important for page erasure. The lower five
bits of the EEPROM address low byte specify the addresses
within a page and are ignored during an erase operation.
12445-040
1
5
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case, the
command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The only data byte is the low
byte of the EEPROM address, as shown in Figure 44.
1
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
programmed, the page(s) containing those locations must
first be erased. EEPROM memory is erased by writing a
command byte.
The master sends a command code telling the slave device to
erase the page. The ADM1260 command code for a page erasure is
0xFE (1111 1110). Note that for a page erasure to occur, the page
address must be given in the previous write word transaction (see
the Write Byte/Word section). In addition, Bit 2 in the UPDCFG
register (Address 0x90) must be set to 1.
4
Figure 43. Single Byte Write to the RAM
Figure 41. Setting a RAM Address for a Subsequent Read
3
RAM
SLAVE W A
S ADDRESS
ADDRESS
A DATA A P
(0x00 TO 0xDF)
12445-039
2
12445-041
The ADM1260 uses the SMBus write protocols discussed in the
following sections.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master sends a command code.
5. The slave asserts an acknowledge on SDA.
6. The master sends a data byte.
7. The slave asserts an acknowledge on SDA.
8. The master sends a data byte or asserts a stop condition.
9. The slave asserts an acknowledge on SDA.
10. The master asserts a stop condition on SDA to end the
transaction.
12445-042
As soon as the ADM1260 receives the command byte, page
erasure begins. The master device can send a stop command as
soon as it sends the command byte. Page erasure takes approximately 20 ms. If the ADM1260 is accessed before erasure is
complete, it responds with a no acknowledge .
Figure 42. EEPROM Page Erasure
Rev. 0 | Page 34 of 71
To write a single byte of data to the EEPROM. In this case,
the command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The first data byte is the low
byte of the EEPROM address, and the second data byte is
the actual data, as shown in Figure 45.
Data Sheet
4
5
6
7
8
9 10
EEPROM
EEPROM
ADDRESS
ADDRESS
S SLAVE W A
A
A DATA A P
ADDRESS
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
Note that the ADM1260 features a clock extend function for writes
to the EEPROM. Programming an EEPROM byte takes approximately 250 μs, which limits the SMBus clock for repeated or block
write operations. The ADM1260 pulls SCL low and extends the
clock pulse when it cannot accept any more data.
Figure 45. Single Byte Write to the EEPROM
Block Write
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
be set previously. In the ADM1260, a send byte operation sets a
RAM address, and a write byte/word operation sets an
EEPROM address, as follows:
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
READ OPERATIONS
The ADM1260 uses the SMBus read protocols discussed in the
following sections.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by
the write bit (low).
The addressed slave device asserts an acknowledge on SDA.
The master sends a command code that tells the slave
device to expect a block write. The ADM1260 command
code for a block write is 0xFC (1111 1100).
The slave asserts an acknowledge on SDA.
The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
The slave asserts an acknowledge on SDA.
The master sends N data bytes.
The slave asserts an acknowledge on SDA after each data byte.
The master asserts a stop condition on SDA to end the
transaction.
Receive Byte
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
1.
2.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts an acknowledge on SDA.
The master receives a data byte.
The master asserts a no acknowledge on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
3.
4.
5.
6.
In the ADM1260, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 46.
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
An address crosses a page boundary. In this case, both
pages must be erased before programming.
There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF) to avoid writing to
invalid addresses.
1
2
3
4
1
2
S
SLAVE
ADDRESS
R
3
4
5
6
A
DATA
A
P
12445-045
3
Figure 46. Single Byte Read from the EEPROM or RAM
5
6
7
8
9
10
SLAVE W A COMMAND 0xFC A BYTE A DATA A DATA A DATA A P
S ADDRESS
(BLOCK WRITE)
COUNT
1
2
N
Figure 47. Block Write to the EEPROM or RAM
Rev. 0 | Page 35 of 71
12445-044
2
12445-043
1
ADM1260
ADM1260
Data Sheet
Error Correction
The ADM1260 provides the option of issuing a packet error
correction (PEC) byte after a write to the RAM, a write to the
EEPROM, a block write to the RAM/EEPROM, or a block read
from the RAM/EEPROM. This option enables the user to verify
that the data received by or sent from the ADM1260 is correct.
The PEC byte is an optional byte sent after the last data byte is
written to or read from the ADM1260. The protocol is the same
as a block read for Step 1 to Step 12 and then proceeds as
follows:
Block Read
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
be set previously. In the ADM1260, this is achieved by a send
byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as follows:
5.
6.
7.
8.
9.
10.
11.
12.
13.
1
2
3
4
2.
3.
The ADM1260 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read, if the
PEC byte is incorrect.
A no acknowledge is generated after the PEC byte to signal
the end of the read.
The master asserts a stop condition on SDA to end the
transaction.
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
C(x) = x8 + x2 + x1 + 1
See the SMBus Version 1.1 specification for details. An example
of a block read with the optional PEC byte is shown in Figure 49.
5 6
7
8
9
10
11
12
SLAVE
COMMAND 0xFD
SLAVE
BYTE
DATA
A
S ADDRESS W A (BLOCK READ) A S ADDRESS R A COUNT A
1
13
DATA
A
32
P
12445-046
3.
4.
1.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an acknowledge on SDA.
The master sends a command code that tells the slave
device to expect a block read. The ADM1260 command
code for a block read is 0xFD (1111 1101).
The slave asserts an acknowledge on SDA.
The master asserts a repeat start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The slave asserts an acknowledge on SDA.
The ADM1260 sends a byte count data byte that tells the
master how many data bytes to expect. The ADM1260
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.
The master asserts an acknowledge on SDA.
The master receives 32 data bytes.
The master asserts an acknowledge on SDA after each data
byte and a no acknowledge is generated after the last byte
to signal the end of the read.
The master asserts a stop condition on SDA to end the
transaction.
Figure 48. Block Read from the EEPROM or RAM
1
2
3
4
5 6
7
8
9
10
11
12
SLAVE
COMMAND 0xFD
SLAVE
BYTE
DATA
A
S ADDRESS W A (BLOCK READ) A S ADDRESS R A COUNT A
1
13 14 15
DATA
A PEC A P
32
Figure 49. Block Read from the EEPROM or RAM with PEC
Rev. 0 | Page 36 of 71
12445-047
1.
2.
Data Sheet
ADM1260
INTERCHIP BUS
OVERVIEW
The interchip bus (ICB) is the fundamental way to solve scalability
from a hardware point of view. The ICB makes the linking of
multiple ADM1260 devices trivial to support sequencing,
monitoring, and managing a large number of supply rails. The
ICB uses only two dedicated pins (CCL, CDA) and supports up to
four ADM1260 devices on the same bus.
The ICB coordinates sequencing operations and transitions
between the SEs in a system with multiple ADM1260 devices.
For example, multiple devices are monitoring different input
supplies. If a fault condition is detected in one of the rails in a
particular device, that condition can be communicated to all the
other devices. The receipt of a message on the ICB informs the
other devices of the type of transition, and instructs those
devices to synchronize the transition of their SEs and, therefore,
their PDOx status change based on the sequence condition. The
ICB can be thought of as linking the SEs of multiple devices so
that all the devices can work as a single entity.
The ADI Power Studio software configures a sequencing system
built with multiple ADM1260 devices. The software provides an
abstraction to the end user for managing the complexity of dealing
with multiple devices by representing the devices as a single virtual
sequencer. The software maps the user configuration of the
virtual sequencer to each of the sequencer devices, using the
ICB to implement the virtual sequence defined by the user in
the ADI Power Studio. The software generates any pings and
pongs necessary, and the user does not need to manage them
manually.
Message priority is defined by the destination and event type;
broadcasts have higher priority than unicasts. Among the
broadcast messages, monitor events have the highest priority,
followed by timeout, and then sequence broadcast.
Every state transition generates one (1 byte) ICB message.
Typically, it takes 25 μs to transmit one message over the ICB.
State transition happens only after the message is successfully
transmitted.
ICB ADDRESSING AND EVENT
There are two types of ICB addressing: broadcast addressing
and unicast addressing. Broadcast address is set to 0x0 and is
used when a message is being sent to all devices. Unicast
addressing is used when a message is being sent to only one
device. Each ADM1260 on the ICB is given a unique ICB
address, and the address is independent of the I2C address.
Because a maximum number of four ADM1260 devices can be
cascaded, the valid range of an ICB address is 0x1 to 0x4.
There are two bits for defining the event type in a message, and
there are four defined events that can be sent on the ICB:
monitor exit, timeout exit, broadcast sequence exit, and local
sequence exit.
A monitor broadcast message is transmitted when an active
monitor condition occurs. When the message is received, it
causes a device to jump to the state defined by the monitor exit
state in the active physical state. There is no need for an active
monitor; the exit state is still followed in the case of a monitor
broadcast message.
The user can manage from the ADI Power Studio one virtual
sequencer with N × 10 rails instead of having to manage the
sequencing between N physical sequencer devices, with 10
supplies each. The user can turn on the N × 10 supply rails in
any order in the virtual sequencer. However, it is highly
recommended to sequence all the rails in one physical device
before moving to the next device to avoid using up states for a
ping-pong action. The software acknowledges the ICB and the
physical devices that monitor and control the rails. The software
uses this knowledge to coordinate and hand over sequencing
responsibilities between the devices while remaining transparent
to the user.
A timeout broadcast message is transmitted when an active
timeout condition occurs. When received, it causes a device
jump to the state defined by timeout exit state in the active
physical state. A timeout condition does not need to be defined
or enabled.
MESSAGE FORMATS
A local sequence unicast message is transmitted when a supply
monitoring or SMBus jump sequence condition triggers a sequence
exit condition. This message is sent by the device to its own
unicast address and is only for informational purposes.
1
2
3
4
5
7
8
S
ICB
ADDRESS
EVENT
BLACK
BOX
PARITY
A
P
A sequence broadcast message is transmitted when an active
sequence condition occurs and the sequence broadcast enable
bit is set in the active physical state. When the sequence broadcast
message is received by the other devices on the bus, it jumps to
the physical state that is defined locally in those devices.
12445-150
Each ICB message consists of 8 bits of data on the CDA line
followed by an acknowledge bit, and the message is transmitted
using a 400 kHz (typical) clock on the CCL line.
A sequence jump message can be one of two types: sequence
broadcast or local sequence unicast.
Figure 50. ICB Message Format
Rev. 0 | Page 37 of 71
ADM1260
Data Sheet
ICB FAULT HANDLING
The system jumps to a bus fault state in the case of a parity bit
error, or if either CDA or CCL is held low for more than 128 μs.
The local state machine jumps to the bus fault state defined by
the ICBCFG2 register.
If a device loses power, it pulls down the CDA line as the
VDDCAP pin enters UVLO. However, if the other devices on
the bus are operating normally, they recognize the CDA pulldown as a bus fault and jump to bus fault state.
ICB PULL-UP RESISTOR
Pull up the ICB line before or at the same time as the ADM1260
powers up. The pull-up must stay as long as the ADM1260 is
powered and operating. Keep the lines glitch free to avoid false
ICB fault triggering. It is recommended to use a 1.1 kΩ pull-up
resistor for voltages up to 5 V.
Rev. 0 | Page 38 of 71
Data Sheet
ADM1260
CONFIGURATION REGISTERS
UPDATING THE MEMORY, ENABLING BLOCK
ERASURE, AND DOWNLOADING EEPROM
The register and bit details in Figure 51 show the configurations
required to perform the following actions:
The ADM1260 contains both volatile and nonvolatile memory,
which must be set up correctly if any alterations to the configuration are to be updated properly in the device. The volatile
memory of the device is constructed with double buffered latches.
Update the volatile memory in real time.
Update the volatile memory offline, then update the
memory all at once.
Enable block erasure.
Download EEPROM contents to the RAM.
There are also a number of configuration bits that update the
sequencing engine. These bits are detailed in Table 13.
SMBus
E
E
P
R
O
M
L
D
DEVICE
CONTROLLER
R
A
M
L
D
D
A
T
A
U
P
D
LATCH A
LATCH B
EEPROM
FUNCTION,
FOR EXAMPLE,
OV THRESHOLD
ON VP1
12445-021
POWER-UP
(VCC > 2.5V)
Figure 51. Configuration Update Flow Diagram
Table 13. Configuration Bits to Update the Sequencing Engine
Register
Address
0x90
Register Name
UPDCFG
Bits
[7:3]
2
1
Bit Names
Not applicable
EEBLKERS
CFGUPD
R/W
Not applicable
R/W
W
0
CONTUPD
R/W
0xD8
UDOWNLD
[7:1]
0
Not applicable
EEDWNLD
Not applicable
W
0xF4
MANID
[7:0]
MANID
R
Description
These bits cannot be used.
This bit enables the configuration EEPROM block erasure.
This bit updates the configuration registers from holding
other registers; this bit self clears.
This bit enable the continuous update of the configuration
registers.
These bits cannot be used.
This bit downloads configuration data from EEPROM (which
also happens automatically at power-up); this bit self clears on
completion.
These bits are the manufacturer ID; they return 0x41 and can
be used to verify communication with the device.
Rev. 0 | Page 39 of 71
ADM1260
Data Sheet
INPUTS
The ADM1260 has 10 inputs. Five of these inputs are dedicated
supply fault detectors, highly programmable reset generators
with inputs that can detect overvoltage, undervoltage, or out of
window faults. With these five inputs, voltages from 0.573 V to
14.4 V can be supervised. The undervoltage and overvoltage
thresholds can all be programmed to an 8-bit resolution. The
comparators that detect faults on the inputs have digitally
programmable hysteresis to provide immunity to supply
bounce. Each of these inputs also has a glitch filter with a
timeout programmable up to 100 μs.
The other five inputs on the ADM1260 have dual functionality.
They can be used as analog inputs, as with the first five channels, as
previously described, or as general-purpose logic inputs. As
analog inputs, these channels function exactly the same as those
described earlier in this section. The major difference is that
these inputs do not have internal potentiometer resistors and
present a true high impedance to the input pin. Their input
range is thus limited to 0.573 V to 1.375 V, but the high
impedance means that an external resistor divider network can
be used to divide down any out of range supply to a value within
range. Therefore, −5 V, −12 V, +24 V, and +48 V can all be
supervised by these channels with the appropriate external resistor
divider network.
As digital inputs, these pins can be used to detect enable signals
(such as PWRGD and POWRON) and are TTL- and CMOScompatible. When used in this mode, the analog circuitry of
these pins can be mapped to their sister input pins (one of the
first five inputs previously described). Thus, VX1 can be used as
a second detector on VP1, VX2 can be used with VP2, and so
on. VX5 is mapped to VH. With a second detector available, the
user can program warnings as well as fault functions.
Table 14 details all of the registers used to configure the inputs
to perform the functions described in this section.
Table 14. Registers Used to Configure the Inputs
Input
VP1
Reg.
Addr.
0x00
0x01
Register
Name
PS1OVTH
PS1OVHYST
0x02
0x03
PS1UVTH
PS1UVHYST
0x04
0x05
VP2
SFDV1CFG
SFDV1SEL
0x08
0x09
PS2OVTH
PS2OVHYST
0x0A
PS2UVTH
Bits
[7:0]
[7:5]
[4:0]
[7:0]
[7:5]
[4:0]
[7:5]
[4:2]
Bit Name
OV7 to OV0
Not applicable
HY4 to HY0
UV7 to UV0
Not applicable
HY4 to HY0
Not applicable
GF2 to GF0
R/W
R/W
[1:0]
RS1 to RS0
R/W
[7:2]
[1:0]
Not applicable
SEL1 to SEL0
R/W
[7:0]
[7:5]
[4:0]
[7:0]
OV7 to OV0
Not applicable
HY4 to HY0
UV7 to UV0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
8-bit digital value for the overvoltage (OV) threshold on PS1 SFD.
These bits cannot be used.
5-bit hysteresis to be subtracted from PS1OVTH when OV is true.
8-bit digital value for the undervoltage threshold on PS1 SFD.
These bits cannot be used.
5-bit hysteresis to be added from PS1UVTH when undervoltage (UV) is true.
These bits cannot be used.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Selection
0
0
Overvoltage
0
1
Undervoltage or overvoltage
1
0
Undervoltage
1
1
Off
These bits cannot be used
SEL1
SEL0
Range Selection
0
0
Midrange (2.5 V to 6.0 V)
0
1
Low range (1.25 V to 3.00 V)
1
0
Ultralow range (0.573 V to 1.375 V)
1
1
Ultralow range (0.573 V to 1.375 V)
8-bit digital value for the overvoltage threshold on PS2 SFD.
These bits cannot be used.
5-bit hysteresis to be subtracted from PS2OVTH when OV is true.
8-bit digital value for the undervoltage threshold on PS2 SFD.
Rev. 0 | Page 40 of 71
Data Sheet
Input
Reg.
Addr.
0x0B
0x0C
0x0D
VP3
Register
Name
PS2UVHYST
SFDV2CFG
SFDV2SEL
0x10
0x11
PS3OVTH
PS3OVHYST
0x12
0x13
PS3UVTH
PS3UVHYST
0x14
0x15
SFDV3CFG
SFDV3SEL
ADM1260
Bits
[7:5]
[4:0]
[7:5]
[4:2]
Bit Name
Not applicable
HY4 to HY0
Not applicable
GF2 to GF0
R/W
[1:0]
RS1 to RS0
R/W
[7:2]
[1:0]
Not applicable
SEL1 to SEL0
R/W
[7:0]
[7:5]
[4:0]
[7:0]
[7:5]
[4:0]
[7:5]
[4:2]
OV7 to OV0
Not applicable
HY4 to HY0
UV7 to UV0
Not applicable
HY4 to HY0
Not applicable
GF2 to GF0
[1:0]
RS1 to RS0
R/W
[7:2]
[1:0]
Not applicable
SEL1 to SEL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
These bits cannot be used.
5-bit hysteresis to be added from PS2UVTH when UV is true.
These bits cannot be used.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Selection
0
0
Overvoltage
0
1
Undervoltage or overvoltage
1
0
Undervoltage
1
1
Off
These bits cannot be used.
SEL1
SEL0
Range Selection
0
0
Midrange (2.5 V to 6.0 V)
0
1
Low range (1.25 V to 3.00 V)
1
0
Ultralow range (0.573 V to 1.375 V)
1
1
Ultralow range (0.573 V to 1.375 V)
8-bit digital value for the overvoltage threshold on PS3 SFD.
These bits cannot be used.
5-bit hysteresis to be subtracted from PS3OVTH when OV is true.
8-bit digital value for the undevoltage threshold on PS3 SFD.
These bits cannot be used.
5-bit hysteresis to be added from PS3UVTH when UV is true.
These bits cannot be used.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Selection
0
0
Overvoltage
0
1
Undervoltage or overvoltage
1
0
Undervoltage
1
1
Off
These bits cannot be used.
SEL1
SEL0
Range Select
0
0
Midrange (2.5 V to 6.0 V)
0
1
Low range (1.25 V to 3.00 V)
1
0
Ultralow range (0.573 V to 1.375 V)
1
1
Ultralow range (0.573 V to 1.375 V)
Rev. 0 | Page 41 of 71
ADM1260
Input
VP4
Reg.
Addr.
0x18
0x19
Register
Name
PS4OVTH
PS4OVHYST
0x1A
0x1B
PS4UVTH
PS4UVHYST
0x1C
SFDV4CFG
0x1D
VH
Data Sheet
SFDV4SEL
0x20
0x21
PSVHOVTH
PSVHOVHYST
0x22
PSVHUVTH
0x24
SFDVHCFG
0x25
SFDVHSEL
Bits
[7:0]
[7:5]
[4:0]
[7:0]
[7:5]
[4:0]
[7:5]
[4:2]
Bit Name
OV7 to OV0
Not applicable
HY4 to HY0
UV7 to UV0
Not applicable
HY4 to HY0
Not applicable
GF2 to GF0
R/W
R/W
[1:0]
RS1 to RS0
R/W
[7:2]
[1:0]
Not applicable
SEL1 to SEL0
R/W
[7:0]
[7:5]
[4:0]
[7:0]
[4:0]
[7:5]
[4:2]
OV7 to OV0
Not applicable
HY4 to HY0
UV7 to UV0
HY4 to HY0
Not applicable
GF2 to GF0
R/W
R/W
R/W
[1:0]
RS1 to RS0
R/W
[7:1]
0
Not applicable
SEL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
8-bit digital value for the overvoltage threshold on PS4 SFD.
These bits cannot be used.
5-bit hysteresis to be subtracted from PS4OVTH when OV is true.
8-bit digital value for the undervoltage threshold on PS4 SFD.
These bits cannot be used.
5-bit hysteresis to be added from PS4UVTH when UV is true.
These bits cannot be used.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Selection
0
0
Overvoltage
0
1
Undervoltage or overvoltage
1
0
Undervoltage
1
1
Off
These bits cannot be used.
SEL1
SEL0
Range Selection
0
0
Midrange (2.5 V to 6.0 V)
0
1
Low range (1.25 V to 3.00 V)
1
0
Ultralow range (0.573 V to 1.375 V)
1
1
Ultralow range (0.573 V to 1.375 V)
8-bit digital value for the overvoltage threshold on PSVH SFD.
These bits cannot be used.
5-bit hysteresis to be subtracted from PSVHOVTH when OV is true.
8-bit digital value for the UV threshold on PSVH SFD.
5-bit hysteresis to be added from PSVHUVTH when UV is true.
These bits cannot be used.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Selection
0
0
Overvoltage
0
1
Undervoltage or overvoltage
1
0
Undervoltage
1
1
Off
These bits cannot be used.
SEL0
Range Selection
0
Low range (2.5 V to 6.0 V)
1
High range (6.0 V to 14.4 V)
Rev. 0 | Page 42 of 71
Data Sheet
Input
VX1
Reg.
Addr.
0x28
0x29
Register
Name
X1OVTH
X1OVHYST
0x2A
0x2B
X1UVTH
X1UVHYST
0x2C
SFDX1CFG
0x2D
0x2E
SFDVX1SEL
GPIX1CFG
ADM1260
Bits
[7:0]
[7:5]
[4:0]
[7:0]
[7:5]
[4:0]
[7:5]
[4:2]
Bit Name
OV7 to OV0
Not applicable
HY4 to HY0
UV7 to UV0
Not applicable
HY4 to HY0
Not applicable
GF2 to GF0
R/W
R/W
[1:0]
RS1 to RS0
R/W
[7:2]
[1:0]
Not applicable
SEL1 to SEL0
R/W
7
6
5
Not applicable
INVIN
INTYP
R/W
R/W
[4:3]
PULS1 to PULS0
R/W
[2:0]
GF2 to GF0
R/W
R/W
R/W
R/W
R/W
Description
8-bit digital value for the overvoltage threshold on the VX1 SFD.
These bits cannot be used.
5-bit hysteresis to be subtracted from X1OVTH when OV is true.
8-bit digital value for the undervoltage threshold on X1 SFD.
These bits cannot be used.
5-bit hysteresis to be added from X1UVTH when UV is true.
These bits cannot be used.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Selection
0
0
Overvoltage
0
1
Undervoltage or overvoltage
1
0
Undervoltage
1
1
Off
These bits cannot be used.
SEL1
SEL0
Function Selection
0
0
SFD (fault) only
0
1
GPI (fault) only
1
0
GPI (fault) + SFD (warning)
1
1
No function (input can still be used
as ADC input)
This bit cannot be used.
If this bit is high, the input is inverted.
This bit determines whether a level or an edge is detected on the pin.
INTYP Setting
Level or Edge Detection
0
Detects level
1
Detects edge
These bits determine the length of the pulse output after an edge is
detected on the input.
PULS1 Setting
PULS0 Setting
Pulse Length (μs)
0
0
10
0
1
100
1
0
1000
1
1
10,000
Glitch filter. These bits determine the length of time for which a pulse is
ignored.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
Rev. 0 | Page 43 of 71
ADM1260
Input
VX2
Data Sheet
Reg.
Addr.
0x30
0x31
Register
Name
X2OVTH
X2OVHYST
0x32
0x33
X2UVTH
X2UVHYST
0x34
SFDX2CFG
0x35
0x36
SFDVX2SEL
GPIX2CFG
Bits
[7:0]
[7:5]
[4:0]
[7:0]
[7:5]
[4:0]
[7:5]
[4:2]
Bit Name
OV7 to OV0
Not applicable
HY4 to HY0
UV7 to UV0
Not applicable
HY4 to HY0
Not applicable
GF2 to GF0
R/W
R/W
[1:0]
RS1 to RS0
R/W
[7:2]
[1:0]
Not applicable
SEL1 to SEL0
R/W
7
6
5
Not applicable
INVIN
INTYP
R/W
R/W
[4:3]
PULS1 to PULS0
R/W
[2:0]
GF2 to GF0
R/W
R/W
R/W
R/W
R/W
Description
8-bit digital value for the overvoltage threshold on the VX2 SFD.
These bits cannot be used.
5-bit hysteresis to be subtracted from X2OVTH when OV is true.
8-bit digital value for the undervoltage threshold on the VX2 SFD.
These bits cannot be used.
5-bit hysteresis to be added from X2UVTH when UV is true.
These bits cannot be used.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Selection
0
0
Overvoltage
0
1
Undervoltage or overvoltage
1
0
Undervoltage
1
1
Off
These bits cannot be used.
SEL1
SEL0
Function Selection
0
0
SFD (fault) only
0
1
GPI (fault) only
1
0
GPI (fault) + SFD (warning)
1
1
No function (input can still be used
as ADC input)
This bit cannot be used.
If this bit is high, the input is inverted.
This bit determines whether a level or an edge is detected on the pin.
INTYP Setting
Level or Edge Detection
0
Detects level
1
Detects edge
These bits determine the length of the pulse output after an edge is
detected on the input.
PULS1 Setting
PULS0 Setting Pulse Length (μs)
0
0
10
0
1
100
1
0
1000
1
1
10,000
Glitch filter. These bits determine the length of time for which a pulse is
ignored.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
Rev. 0 | Page 44 of 71
Data Sheet
Input
VX3
Reg.
Addr.
0x38
0x39
Register
Name
X3OVTH
X3OVHYST
0x3A
0x3B
X3UVTH
X3UVHYST 7
0x3C
SFDX3CFG
0x3D
0x3E
SFDVX3SEL
GPIX3CFG
ADM1260
Bits
[7:0]
[7:5]
[4:0]
[7:0]
[7:5]
[4:0]
[7:5]
[4:2]
Bit Name
OV7 to OV0
Not applicable
HY4 to HY0
UV7 to UV0
Not applicable
HY4 to HY0
Not applicable
GF2 to GF0
R/W
R/W
[1:0]
RS1 to RS0
R/W
[7:2]
[1:0]
Not applicable
SEL1 to SEL0
R/W
7
6
5
Not applicable
INVIN
INTYP
R/W
R/W
[4:3]
PULS1 to PULS0
R/W
[2:0]
GF2 to GF0
R/W
R/W
R/W
R/W
R/W
Description
8-bit digital value for the overvoltage threshold on the VX3 SFD.
These bits cannot be used.
5-bit hysteresis to be subtracted from X3OVTH when OV is true.
8-bit digital value for the undervoltage threshold on the VX3 SFD.
These bits cannot be used.
5-bit hysteresis to be added from X3UVTH when UV is true.
These bits cannot be used.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Selection
0
0
Overvoltage
0
1
Undervoltage or overvoltage
1
0
Undervoltage
1
1
Off
These bits cannot be used.
SEL1
SEL0
Function Selection
0
0
SFD (fault) only
0
1
GPI (fault) only
1
0
GPI (fault) + SFD (warning)
This bit cannot be used.
If this bit is high, the input is inverted.
This bit determines whether a level or an edge is detected on the pin.
INTYP Setting
Level or Edge Detection
0
Detects level
1
Detects edge
These bits determine the length of the pulse output after an edge is
detected on the input.
PULS1
PULS0
Pulse Length (μs)
0
0
10
0
1
100
1
0
1000
1
1
10,000
Glitch filter. These bits determine the length of time for which a pulse is
ignored.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
Rev. 0 | Page 45 of 71
ADM1260
Input
VX4
Data Sheet
Reg.
Addr.
0x40
0x41
Register
Name
X4OVTH
X4OVHYST
0x42
0x43
X4UVTH
X4UVHYST
0x44
SFDX4CFG
0x45
0x46
SFDVX4SEL
GPIX4CFG
Bits
[7:0]
[7:5]
[4:0]
[7:0]
[7:5]
[4:0]
[7:5]
[4:2]
Bit Name
OV7 to OVO
Not applicable
HY4 to HY0
UV7 to UV0
Not applicable
HY4 to HY0
Not applicable
GF2 to GF0
R/W
R/W
[1:0]
RS1 to RS0
R/W
[7:2]
[1:0]
Not applicable
SEL1 to SEL0
R/W
7
6
5
Not applicable
INVIN
INTYP
R/W
R/W
[4:3]
PULS1 to PULS0
R/W
[2:0]
GF2 to GF0
R/W
R/W
R/W
R/W
R/W
Description
8-bit digital value for the overvoltage threshold on the VX4 SFD.
These bits cannot be used.
5-bit hysteresis to be subtracted from X4OVTH when OV is true.
8-bit digital value for the undervoltage threshold on the VX4 SFD.
These bits cannot be used.
5-bit hysteresis to be added from X4UVTH when UV is true.
These bits cannot be used.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Selection
0
0
Overvoltage
0
1
Undervoltage or overvoltage
1
0
Undervoltage
1
1
Off
These bits cannot be used.
SEL1
SEL0
Function Selection
0
0
SFD (fault) only
0
1
GPI (fault) only
1
0
GPI (fault) + SFD (warning)
1
1
No function (input can still be used
as ADC input)
This bit cannot be used.
If this bit is high, the input is inverted.
This bit determines whether a level or an edge is detected on the pin.
INTYP Setting
Level or Edge Detection
0
Detects level
1
Detects edge
These bits determine the length of the pulse output after an edge is
detected on the input.
PULS1
PULS0
Pulse Length (μs)
0
0
0
0
1
100
1
0
1000
1
1
10,000
Glitch filter. These bits determine the length of time for which a pulse is
ignored.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
Rev. 0 | Page 46 of 71
Data Sheet
Input
VX5
Reg.
Addr.
0x48
0x49
Register
Name
X5OVTH
5OVHYST
0x4A
0x4B
X5UVTH
X5UVHYST
0x4C
SFDX5CFG
0x4D
0x4E
SFDVX5SEL
GPIX5CFG
ADM1260
Bits
[7:0]
[7:5]
[4:0]
[7:0]
[7:5]
[4:0]
[7:5]
[4:2]
Bit Name
OV7 to OV0
Not applicable
HY4 to HY0
UV7 to UV0
Not applicable
HY4 to HY0
Not applicable
GF2 to GF0
R/W
R/W
[1:0]
RS1 to RS0
R/W
[7:2]
[1:0]
Not applicable
SEL1 to SEL0
R/W
7
6
5
Not applicable
INVIN
INTYP
R/W
R/W
[4:3]
PULS1 to PULS0
R/W
[2:0]
GF2 to GF0
R/W
R/W
R/W
R/W
R/W
Description
8-bit digital value for the overvoltage threshold on the VX5 SFD.
These bits cannot be used.
5-bit hysteresis to be subtracted from X5OVTH when OV is true.
8-bit digital value for the undervoltage threshold on the VX5 SFD.
These bits cannot be used.
5-bit hysteresis to be added from X5UVTH when UV is true.
These bits cannot be used.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Selection
0
0
Overvoltage
0
1
Undervoltage or overvoltage
1
0
Undervoltage
1
1
Off
These bits cannot be used.
SEL1
SEL0
Function Selection
0
0
SFD (fault) only
0
1
GPI (fault) only
1
0
GPI (fault) + SFD (warning)
1
1
No function (input can still be used
as ADC input)
These bits cannot be used.
If this bit is high, the input is inverted.
This bit determines whether a level or an edge is detected on the pin.
INTYP Setting
Level or Edge Detection
0
Detects level
1
Detects edge
These bits determine the length of the pulse output after an edge is
detected on the input.
PULS1
PULS0
Pulse Length (μs)
0
0
0
0
1
100
1
0
1000
1
1
10,000
Glitch filter. These bits determine the length of time for which a pulse is
ignored.
GF2
GF1
GF0 Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
Rev. 0 | Page 47 of 71
ADM1260
Data Sheet
OUTPUTS
The ADM1260 has 10 programmable driver outputs. Supply
sequencing is achieved with the devices by using the PDOx pins
as control signals for supplies. The output drivers can be used
either as logic enables or FET drivers.
The PDOx pins can be used for a number of functions; the primary
function is to provide enable signals for LDOs or dc-to-dc
converters, which generate supplies locally on a board. The
PDOx pins can also be used to provide a power-good signal
when all of the SFDs are in tolerance or to provide a reset output if
one of the SFDs goes out of specification (this can be used as a
status signal for a DSP, FPGA, or other microcontroller).
The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an
external N-FET, which is used to isolate, for example, a card
side voltage from a backplane supply (when a PDOx pin sustains
greater than 10.5 V into a 1 μA load). The pull-down switches
can be used to drive status LEDs.
The data driving each of the PDOx pins can come from one of
three sources. The source can be enabled for a particular output,
that is, PDO1, in the PDOCFG configuration register. The data
sources are as follows:
The PDOx pins can be programmed to pull up to a number of
different options. The outputs can be programmed as follows:
Open drain, allowing the user to connect an external pullup resistor.
Open drain with a weak pull-up to VDDCAP.
Push-pull to VDDCAP.
Open drain with a weak pull-up to VPx.
Push-pull to VPx.
As a strong pull-down to GND.
Internally charge pumped high drive (12 V, PDO1 to PDO6).
An output from the SE.
Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDOs. Thus, a microcontroller can be used
to initiate a software power-up/power-down sequence.
An on-chip clock. A 100 kHz clock is generated on the
device. This clock can be made available on any of the
PDOx pins and can be used to clock an external device,
such as an LED.
Table 15 details all of the registers used to configure the outputs
to perform the functions described in this section.
Rev. 0 | Page 48 of 71
Data Sheet
ADM1260
Table 15. Registers Used to Configure the Outputs1
Output
PDO1
PDO2
Reg.
Addr.
0x07
0x0F
Register
Name
PDO1CFG
PDO2CFG
Bits
7
R/W
Description
This bit cannot be used.
[6:4]
Bit Name
Not
applicable
CFG6 to CFG4
R/W
[3:0]
CFG3 to CFG0
R/W
7
[6:4]
Not
applicable
CFG6 to CFG4
These bits control the logic source driving the PDOx pin, that is, the SE, the
internal clock, or the SMBus, directly.
CFG6
CFG5 CFG4
PDOx Status
0
0
0
Disabled, with a weak pull-down resistor
0
0
1
Enabled; follows the logic driven by the SE
0
1
0
Enables SMBus data, driven low
0
1
1
Enables SMBus data, driven high
1
X
X
Enables the 100 kHz clock out onto the pin
These bits determine the format of the pull-up resistor on the PDOx pin.
CFG3
CFG2 CFG1
CFG0
PDOx Pull-Up Resistor
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump
voltage
0
1
0
0
Weak, open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak, open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak, open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak, open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak, open-drain pull-up to
VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
This bit cannot be used.
R/W
[3:0]
CFG3 to CFG0
R/W
These bits control the logic source driving the PDOx pin, that is, the SE, the
internal clock, or the SMBus, directly.
CFG6
CFG5 CFG4 PDOx Status
0
0
0
Disabled, with a weak pull-down resistor
0
0
1
Enabled; follows the logic driven by the SE
0
1
0
Enables SMBus data, driven low
0
1
1
Enables SMBus data, driven high
1
X
X
Enables the 100 kHz clock out onto the pin
These bits determine the format of the pull-up resistor on the PDOx pin.
CFG3
CFG2 CFG1 CFG0
PDOx Pull-Up Resistor
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump
voltage
0
1
0
0
Weak, open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak, open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak, open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak, open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak, open-drain pull-up to
VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
Rev. 0 | Page 49 of 71
ADM1260
Output
PDO3
PDO4
Reg.
Addr.
0x17
0x1F
Data Sheet
Register
Name
PDO3CFG
PDO4CFG
Bits
7
R/W
Description
This bit cannot be used.
[6:4]
Bit Name
Not
applicable
CFG6 to CFG4
R/W
[3:0]
CFG3 to CFG0
R/W
7
[6:4]
Not
applicable
CFG6 to CFG4
These bits control the logic source driving the PDOx pin, that is, the SE, the
internal clock, or the SMBus, directly.
CFG6
CFG5 CFG4 PDOx Status
0
0
0
Disabled, with a weak pull-down resistor
0
0
1
Enabled; follows the logic driven by the SE
0
1
0
Enables SMBus data, driven low
0
1
1
Enables SMBus data, driven high
1
X
X
Enables the 100 kHz clock out onto the pin
These bits determine the format of the pull-up resistor on the PDOx pin.
CFG3
CFG2 CFG1
CFG0
PDOx Pull-Up Resistor
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump
voltage
0
1
0
0
Weak, open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak, open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak, open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak, open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak, open-drain pull-up to
VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
This bit cannot be used.
R/W
[3:0]
CFG3 to CFG0
R/W
These bits control the logic source driving the PDOx pin, that is, the SE, the
internal clock, or the SMBus, directly.
CFG6
CFG5 CFG4
PDOx Status
0
0
0
Disabled, with a weak pull-down resistor
0
0
1
Enabled; follows the logic driven by the SE
0
1
0
Enables SMBus data, driven low
0
1
1
Enables SMBus data, driven high
1
X
X
Enables the 100 kHz clock out onto the pin
These bits determine the format of the pull-up resistor on the PDOx pin.
CFG3
CFG2 CFG1
CFG0
PDOx Pull-Up Resistor
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump
voltage
0
1
0
0
Weak, open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak, open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak, open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak, open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak, open-drain pull-up to
VDDCAP
Rev. 0 | Page 50 of 71
Data Sheet
Output
PDO5
PDO6
Reg.
Addr.
0x27
0x2F
ADM1260
Register
Name
PDO5CFG
PDO6CFG
Bits
7
R/W
Description
This bit cannot be used.
[6:4]
Bit Name
Not
applicable
CFG6 to CFG4
R/W
[3:0]
CFG3 to CFG0
R/W
7
[6:4]
Not
applicable
CFG6 to CFG4
These bits control the logic source driving the PDOx pin, that is, the SE, the
internal clock, or the SMBus, directly.
CFG6
CFG5 CFG4
PDOx Status
0
0
0
Disabled, with a weak pull-down resistor
0
0
1
Enabled; follows the logic driven by the SE
0
1
0
Enables SMBus data, driven low
0
1
1
Enables SMBus data, driven high
1
X
X
Enables the 100 kHz clock out onto the pin
These bits determine the format of the pull-up resistor on the PDOx pin.
CFG3
CFG2
CFG1
CFG0
PDOx Pull-Up Resistor
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump
voltage
0
1
0
0
Weak, open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak, open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak, open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak, open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak, open-drain pull-up to
VDDCAP
This bit cannot be used.
R/W
[3:0]
CFG3 to CFG0
R/W
These bits control the logic source driving the PDOx pin, that is, the SE, the
internal clock, or the SMBus, directly.
CFG6
CFG5
CFG4
PDOx Status
0
0
0
Disabled, with a weak pull-down resistor
0
0
1
Enabled; follows the logic driven by the SE
0
1
0
Enables SMBus data, driven low
0
1
1
Enables SMBus data, driven high
1
X
X
Enables the 100 kHz clock out onto the pin
These bits determine the format of the pull-up resistor on the PDOx pin.
CFG3
CFG2
CFG1
CFG0
PDOx Pull-Up Resistor
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump
voltage
0
1
0
0
Weak, open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak, open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak, open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak, open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak, open-drain pull-up to
VDDCAP
1
1
1
1
None
Rev. 0 | Page 51 of 71
ADM1260
Output
PDO7
PDO8
Reg.
Addr.
0x37
0x3F
Data Sheet
Register
Name
PDO7CFG
PDO8CFG
Bits
7
R/W
Description
This bit cannot be used.
[6:4]
Bit Name
Not
applicable
CFG6 to CFG4
R/W
[3:0]
CFG3 to CFG0
R/W
7
[6:4]
Not
applicable
CFG6 to CFG4
These bits control the logic source driving the PDOx pin, that is, the SE, the
internal clock, or the SMBus, directly.
CFG6
CFG5
CFG4
PDOx Status
0
0
0
Disabled, with a weak pull-down resistor
0
0
1
Enabled; follows the logic driven by the SE
0
1
0
Enables SMBus data, driven low
0
1
1
Enables SMBus data, driven high
1
X
X
Enables the 100 kHz clock out onto the pin
These bits determine the format of the pull-up resistor on the PDOx pin.
CFG3
CFG2
CFG1
CFG0
PDOx Pull-Up Resistor
0
0
0
X
None
0
0
1
X
Do not use
0
1
0
0
Weak, open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak, open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak, open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak, open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak, open-drain pull-up to
VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
This bit cannot be used.
R/W
[3:0]
CFG3 to CFG0
R/W
These bits control the logic source driving the PDOx pin, that is, the SE, the
internal clock, or the SMBus, directly.
CFG6
CFG5
CFG4
PDOx Status
0
0
0
Disabled, with a weak pull-down resistor
0
0
1
Enabled; follows the logic driven by the SE
0
1
0
Enables SMBus data, driven low
0
1
1
Enables SMBus data, driven high
1
X
X
Enables the 100 kHz clock out onto the pin
These bits determine the format of the pull-up resistor on the PDOx pin.
CFG3
CFG2
CFG1
CFG0
PDOs Pull-Up Resistor
0
0
0
X
None
0
0
1
X
Do not use
0
1
0
0
Weak, open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak, open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak, open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak, open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak, open-drain pull-up to
VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
Rev. 0 | Page 52 of 71
Data Sheet
Output
PDO9
PDO10
1
Reg.
Addr.
0x47
0x4F
ADM1260
Register
Name
PDO9CFG
PDO10CFG
Bits
7
R/W
Description
This bit cannot be used.
[6:4]
Bit Name
Not
applicable
CFG6 to CFG4
R/W
[3:0]
CFG3 to CFG0
R/W
7
[6:4]
Not
applicable
CFG6 to CFG4
These bits control the logic source driving the PDOx pin, that is, the SE, the
internal clock, or the SMBus, directly.
CFG6
CFG5
CFG4
PDOx Status
0
0
0
Disabled, with a weak pull-down resistor
0
0
1
Enabled; follows the logic driven by the SE
0
1
0
Enables SMBus data, driven low
0
1
1
Enables SMBus data, driven high
1
X
X
Enables the 100 kHz clock out onto the pin
These bits determine the format of the pull-up resistor on the PDOx pin.
CFG3
CFG2
CFG1
CFG0
PDOx Pull-Up Resistor
0
0
0
X
None
0
0
1
X
Do not use
0
1
0
0
Weak, open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak, open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak, open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak, open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak, open-drain pull-up to
VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
This bit cannot be used.
R/W
[3:0]
CFG3 to CFG0
R/W
These bits control the logic source driving the PDOx pin, that is, the SE, the
internal clock, or the SMBus, directly.
CFG6
CFG5
CFG4
PDOx Status
0
0
0
Disabled, with a weak pull-down resistor
0
0
1
Enabled; follows the logic driven by the SE
0
1
0
Enables SMBus data, driven low
0
1
1
Enables SMBus data, driven high
1
X
X
Enables the 100 kHz clock out onto the pin
These bits determine the format of the pull-up resistor on the PDOx pin.
CFG3
CFG2 CFG1
CFG0
PDOx Pull-Up Resistor
0
0
0
X
None
0
0
1
X
Do not use
0
1
0
0
Weak, open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak, open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak, open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak, open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak, open-drain pull-up to
VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
X means don’t care.
Rev. 0 | Page 53 of 71
ADM1260
Data Sheet
SEQUENCING ENGINE
The ADM1260 incorporate a sequencing engine (SE) that
provides the user with powerful and flexible control of
sequencing. The SE implements state machine control of the
PDOx outputs, with state changes conditional on input events. SE
programs can enable complex control of boards, such as power-up
and power-down sequence control, fault event handling, and
interrupt generation on warnings. A watchdog function to verify
the continued operation of a processor clock can be integrated
into the SE program. The SE can also be controlled via the
SMBus, giving software or firmware control of the board
sequencing. Considering the function of the SE from an
applications viewpoint, it is best to think of the SE as providing
a state for a state machine.
The ADM1260 offers up to 61 such state definitions. Each state
is defined by a 64-bit word.
Table 17 shows the details of the 64 bits that define a state.
Table 20 details how to communicate with the SE in the
ADM1260.
Table 21 provides details of additional sequence engine control
registers present the ADM1260 that allow the sequence engine
to be restarted.
Table 16. Starting Address for Each State in the SE
State
Reserved state
State 1 (configured as bus fault state by the GUI)
State 2
State 3
State 4
State 5
State 6
State 7
State 8
State 9
State 10
State 11
State 12
State 13
State 14
State 15
State 16
State 17
State 18
State 19
State 20
State 21
State 22
State 23
State 24
State 25
State 26
State 27
State 28
State 29
State 30
State 31
State 32
State 33
State 34
State 35
State 36
State 37
State 38
State 39
Start Address (Hexadecimal)
0xFA00
0xFA08
0xFA10
0xFA18
0xFA20
0xFA28
0xFA30
0xFA38
0xFA40
0xFA48
0xFA50
0xFA58
0xFA60
0xFA68
0xFA70
0xFA78
0xFA80
0xFA88
0xFA90
0xFA98
0xFAA0
0xFAA8
0xFAB0
0xFAB8
0xFAC0
0xFAC8
0xFAD0
0xFAD8
0xFAE0
0xFAE8
0xFAF0
0xFAF8
0xFB00
0xFB08
0xFB10
0xFB18
0xFB20
0xFB28
0xFB30
0xFB38
Rev. 0 | Page 54 of 71
Data Sheet
ADM1260
State
State 40
State 41
State 42
State 43
State 44
State 45
State 46
State 47
State 48
State 49
State 50
State 51
State 52
State 53
State 54
State 55
State 56
State 57
State 58
State 59
State 60
State 61
State 62
State 63 (configured as sequence fault state by the GUI)
Start Address (Hexadecimal)
0xFB40
0xFB48
0xFB50
0xFB58
0xFB60
0xFB68
0xFB70
0xFB78
0xFB80
0xFB88
0xFB90
0xFB98
0xFBA0
0xFBA8
0xFBB0
0xFBB8
0xFBC0
0xFBC8
0xFBD0
0xFBD8
0xFBE0
0xFBE8
0xFBF0
0xFBF8
Table 17. Bit Map for the Definition of Each State in the SE
Bit No.
0
1
2
3
4
5
6
7
8
9
10
Operation/If Set to 0
Set PDO1 low
Set PDO2 low
Set PDO3 low
Set PDO4 low
Set PDO5 low
Set PDO6 low
Set PDO7 low
Set PDO8 low
Set PDO9 low
Set PDO10 low
Monitor fault if VP1 = 0
If Set to 1
Set PDO1 high
Set PDO2 high
Set PDO3 high
Set PDO4 high
Set PDO5 high
Set PDO6 high
Set PDO7 high
Set PDO8 high
Set PDO9 high
Set PDO10 high
Monitor fault if VP1 = 1
11
12
Mask VP1 monitoring
Monitor fault if VP2 = 0
Unmask VP1 monitoring
Monitor fault if VP2 = 1
13
14
Mask VP2 monitoring
Monitor Fault if VP3 = 0
Unmask VP2 monitoring
Monitor fault if VP3 = 1
15
16
Mask VP3 monitoring
Monitor fault if VP4 = 0
Unmask VP3 monitoring
Monitor fault if VP4 = 1
17
18
Mask VP4 monitoring
Monitor fault if VH = 0
Unmask VP4 monitoring
Monitor fault if VH = 1
19
Mask VH monitoring
Unmask VH monitoring
Description
PDO1 output data.
PDO2 output data
PDO3 output data.
PDO4 output data.
PDO5 output data.
PDO6 output data.
PDO7 output data.
PDO8 output data.
PDO9 output data.
PDO10 output data.
Monitoring of faults on VP1 must be unmasked for this
function to execute (next bit).
Bit 11 = 1; turns on monitoring on the VP1 channel.
Monitoring of faults on VP2 must be unmasked for this
function to execute (next bit).
Bit 13 = 1; turns on monitoring on the VP2 channel.
Monitoring of faults on VP3 must be unmasked for this
function to execute (next bit).
Bit 15 = 1; turns on monitoring on the VP3 channel.
Monitoring of faults on VP4 must be unmasked for this
function to execute (next bit).
Bit 17 = 1; turns on monitoring on the VP4 channel.
Monitoring of faults on VH must be unmasked for this
function to execute (next bit).
Bit 19 = 1; turns on monitoring on the VH channel.
Rev. 0 | Page 55 of 71
ADM1260
Data Sheet
Bit No.
20
Operation/If Set to 0
Monitor fault if VX1 = 0
If Set to 1
Monitor fault if VX1 = 1
21
22
Mask VX1 monitoring
Monitor fault if VX2 = 0
Unmask VX1 monitoring
Monitor fault if VX2 = 1
23
24
Mask VX2 monitoring
Monitor fault if VX3 = 0
Unmask VX2 monitoring
Monitor fault if VX3 = 1
25
26
Mask VX3 monitoring
Monitor fault if VX4 = 0
Unmask VX3 monitoring
Monitor fault if VX4 = 1
27
28
Mask VX4 monitoring
Monitor fault if VX5 = 0
Unmask VX4 monitoring
Monitor fault if VX5 = 1
29
30
[31:34]
[35:38]
39
[40:43]
Mask VX5 monitoring
Mask warning monitoring
TIMEOUT0 to TIMEOUT3
SEQCOND0 to SEQCOND3
Sequence on selected
input = high
SEQDELAY0 to SEQDELAY3
Unmask VX5 monitoring
Unmask warning monitoring
Not applicable
Not applicable
Sequence on selected
input = low
Not applicable
[44:49]
MONADDR0 to MONADDR5
Not applicable
[50:55]
TIMADDR0 to TIMADDR5
Not applicable
[56:61]
SEQADDR0 to SEQADDR5
Not applicable
62
63
Round robin disable
Do not send a broadcast
sequence message
Round robin enable
Send a broadcast sequence
message
Description
Monitoring of faults on VX1 must be unmasked for this
function to execute (next bit).
Bit 21 = 1; turns on monitoring on the VX1 channel.
Monitoring of faults on VX2 must be unmasked for this
function to execute (next bit).
Bit 23 = 1; turns on monitoring on the VX2 channel.
Monitoring of faults on VX3 must be unmasked for this
function to execute (next bit).
Bit 25 = 1; turns on monitoring on the VX3 channel.
Monitoring of faults on VX4 must be unmasked for this
function to execute (next bit).
Bit 27 = 1; turns on monitoring on the VX4 channel.
Monitoring of faults on VX5 must be unmasked for this
function to execute (next bit).
Bit 29 = 1; turns on monitoring on the VX5 channel.
Can only generate a monitor fault on warning = 1. Is unmasked.
Timeout length (see Table 18).
Sequence condition (see Table 18).
SEQSENSE.
Sequence delay (see Table 18). This is also used as the ICB
message address to send a ping when SEQCOND is set to send
a ping. When SEQCOND is set to wait for a ping, this is used as
the ICB message address to send the pong message back after
a ping.
MONADDRx is the state number to jump to if a monitor
function fault occurs.
TIMADDRx is the state number to jump to if a timeout fault
occurs.
SEQADDRx is the state number to jump to if a sequence fault
occurs.
This is OR’ed with the enable (Address 0x82, Bit 1).
When this bit is set to 1 and the SE exits due to a local
sequence condition, a broadcast sequence message is sent.
Table 18. Timeouts and Delays for Functions in the SE
TIMEOUT[3:0], SEQDELAY[3:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Delay (ms)
0 for SEQCONDx; disables the TIMEOUTx condition
0.1
0.2
0.4
0.7
1
2
4
7
10
20
40
70
100
200
400
Rev. 0 | Page 56 of 71
Ping-Pong ICB Message Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Data Sheet
ADM1260
Table 19. SEQCOND[3:0] and Sequence On Signal From Within the SE
SEQCOND[3:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Sequence on Signal Source
Never sequence; always set SEQSENSE(Bit 39) = 0 to ensure no sequence (see Table 17).
VP1.
VP2.
VP3.
VP4.
VH.
VX1.
VX2.
VX3.
VX4.
VX5.
Warning.
SMBus jump. Wait for the SMBus command before jumping to the next state. Set SEQSENSE = 0 to ensure proper operation.
Reserved.
Send ping to the ICB message address defined by SEQDELAY.
Wait for ping and respond to the ICB message address defined by SEQDELAY.
Table 20. Communicating with the SE
Reg.
Addr.
0x93
0xE9
Register
Name
SECTRL
SEADDR
Bits
[7:3]
2
Bit Name
Not applicable
SMBUS_JUMP
R/W
W
1
SWSTEP
R/W
0
Halt
R/W
[7:6]
[5:0]
Not applicable
ADDR
R
Description
Reserved.
This bit allows software control of the SE state changes. This bit forces an unconditional
jump to the next state and can be set as the condition for an end of step change. This
setting enables the user to clear external interrupts by moving forward a state. This bit
self clears to 0 after the state change occurs.
This bit steps the SE forward to the next state. Use this bit in conjunction with the halt bit to
step through a sequence. This bit can be used as a tool for debugging sequences.
This bit halts the SE, meaning that state changes do not occur. This bit must be set to
allow read, erase, or write access to the SE EEPROM.
Reserved.
This bit is the SE current state and is used in conjunction with the halt bit (Register 0x93,
Bit 0).
Table 21. Additional SE Control Registers
Reg.
Addr.
0xDA
Register
Name
UNLOCKSE
0xDB
SEDOWNLD
Bits
[7:0]
Bit Name
UNLOCK_KEY
R/W
W
[7:1]
0
Not applicable
Restart
W
Description
Writing 0x27 and then 0x10 to this register in consecutive writes unlocks the
SEDOWNLD register so that it can be written to. To reset the lock, write 0x00 to the
unlock key. Writing to SEDOWNLD does not reset the lock.
Reserved.
Writing a 1 to this bit causes the SE to restart immediately from the reserved state if the
SE is running, that is, if the halt bit in the SECTRL register = 0. If the SE is halted, that is, if
the halt bit in the SECTRL register = 1, the restart occurs when the halt bit in the
SECTRL register is written to 0. This bit self clears.
Rev. 0 | Page 57 of 71
ADM1260
Data Sheet
CONFIGURING SEQUENCE ENGINE STATES TO
WRITE INTO THE BLACK BOX EEPROM
EEPROM when the sequence engine enters a state that has its
corresponding BBWRTRGx bit set to 1.
The ADM1260 can use a section of EEPROM to store fault records
when the SE enters a user defined trigger state. These states are
defined in EEPROM and downloaded to registers along with the
other configuration data when the ADM1260 is being initialized.
The register locations of the black box write triggers are shown
in Table 22. These locations are loaded from the same locations
in the 0xF8xx EEPROM block. The BBWRTRGx registers are
read/write and, therefore, can be modified by software if
required after the download.
When the black box is enabled, all access to the configuration,
user, and black box EEPROM sections is inhibited unless a 1 is
written to the halt bit in the BBCTRL register (Register 0x9C,
Bit 0) to stop the black box.
When one or more of the bits in the BBWRTRx registers are set
to 1, the black box is enabled, and fault records are written into
When an ADM1260 powers up, the black box automatically
searches the black box section of EEPROM to find the first
unused location for the next fault record to be written. After
this section of EEPROM is erased, the black box may be instructted to perform this search again so that it uses the correct
location for the next fault record write. The reset bit in the
BBSEARCH register (Register 0xD9, Bit 0) initiates this action.
Table 22. Bit Map for Definition of the Black Box Write Triggers for Each SE State1
Reg.
Addr.
0x94
Register
Name
BBWRTRG1
0x95
BBWRTRG2
0x96
BBWRTRG3
0x97
BBWRTRG4
Bits
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit Name
STATE7
STATE6
STATE5
STATE4
STATE3
STATE2
STATE1
Reserved
STATE15
STATE14
STATE13
STATE12
STATE11
STATE10
STATE9
STATE8
STATE23
STATE22
STATE21
STATE20
STATE19
STATE18
STATE17
STATE16
STATE31
STATE30
STATE29
STATE28
STATE27
STATE26
STATE25
STATE24
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
State 7 write trigger.
State 6 write trigger.
State 5 write trigger.
State 4 write trigger.
State 3 write trigger.
State 2 write trigger.
State 1 black box trigger; must always be set to 0.
Reserved state black box trigger; must always be set to 0.
State 15 write trigger.
State 14 write trigger.
State 13 write trigger.
State 12 write trigger.
State 11 write trigger.
State 10 write trigger.
State 9 write trigger.
State 8 write trigger.
State 23 write trigger.
State 22 write trigger.
State 21 write trigger.
State 20 write trigger.
State 19 write trigger.
State 18 write trigger.
State 17 write trigger.
State 16 write trigger.
State 31 write trigger.
State 30 write trigger.
State 29 write trigger.
State 28 write trigger.
State 27 write trigger.
State 26 write trigger.
State 25 write trigger.
State 24 write trigger.
Rev. 0 | Page 58 of 71
Data Sheet
Reg.
Addr.
0x98
Register
Name
BBWRTRG5
0x99
BBWRTRG6
0x9A
BBWRTRG7
0x9B
BBWRTRG8
1
ADM1260
Bits
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit Name
STATE39
STATE38
STATE37
STATE36
STATE35
STATE34
STATE33
STATE32
STATE47
STATE46
STATE45
STATE44
STATE43
STATE42
STATE41
STATE40
STATE55
STATE54
STATE53
STATE52
STATE51
STATE50
STATE49
STATE48
STATE63
STATE62
STATE61
STATE60
STATE59
STATE58
STATE57
STATE56
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
State 39 write trigger.
State 38 write trigger.
State 37 write trigger.
State 36 write trigger.
State 35 write trigger.
State 34 write trigger.
State 33 write trigger.
State 32 write trigger.
State 47 write trigger.
State 46 write trigger.
State 45 write trigger.
State 44 write trigger.
State 43 write trigger.
State 42 write trigger.
State 41 write trigger.
State 40 write trigger.
State 55 write trigger.
State 54 write trigger.
State 53 write trigger.
State 52 write trigger.
State 51 write trigger.
State 50 write trigger.
State 49 write trigger.
State 48 write trigger.
State 63 black box trigger; must always be set to 0.
State 62 write trigger.
State 61 write trigger.
State 60 write trigger.
State 59 write trigger.
State 58 write trigger.
State 57 write trigger.
State 56 write trigger.
When the trigger bit for a given state is set to 1, a fault record is written into the next free location in the black box section of EEPROM when the SE enters that state.
When the trigger bit is set to 0, no fault record is written.
Table 23. ADM1260 Black Box Control Registers
Reg.
Addr.
0x9C
0xD9
Register
Name
BBCTRL
BBSEARCH
Bits
[7:1]
0
Bit Name
Not applicable
Halt
R/W
R/W
[7:1]
0
Not applicable
Reset
R
Description
These bits cannot be used.
The black box function is enabled when one or more of the BBWRTRGx register
bits are set to 1. When the black box is enabled, it is no longer possible to read or
write to the configuration, user, and black box sections of EEPROM.
Writing this bit to 1 disables the black box and enables read and write access to
the configuration, user, and black box sections of EEPROM.
This bit cannot be set while a fault record is being written into the EEPROM; therefore,
this bit must always be read after a write to ensure that the bit is set correctly.
These bits cannot be used.
When written to 1, the black box searches from Address 0xF980 to find the first
unused fault record. After erasing the section of EEPROM holding the black box
fault records, and for the black box to start writing records from the first location,
write a 1 to this bit.
Rev. 0 | Page 59 of 71
ADM1260
Data Sheet
ADC
The ADM1260 features an on-chip, 12-bit ADC. The ADC has
a 12-channel analog mux on the front end. Any or all of these
inputs can be selected to be read by the ADC; therefore, the
ADC can be set up to continuously read the selected channels.
The circuit controlling this operation is called the round robin.
The user selects the channels to operate on, and the ADC
performs a conversion on each in turn. Averaging can be turned
on, setting the round robin to take 16 conversions on each channel;
otherwise, a single conversion is made on each channel. At the
end of this cycle, the results are written to the output registers
and, at the same time, compared with preset thresholds provided
on the ADM1260, which can be programmed to a maximum or
minimum allowable threshold. Only one register is provided for
each input channel; therefore, a UV or OV threshold, but not
both, can be set for a given channel. Exceeding the threshold
generates a warning that can be read back from the status
registers or input into the SE via an OR gate. The round robin
can be enabled via an SMBus write or can be programmed to turn
on at a particular point in the SE program; for instance, it can
be set to start once a power-up sequence is complete and all
supplies are known to be within expected fault limits.
Table 24 through Table 28 show the details of the registers
required to set up the ADC and its inputs.
ADC Readback Configuration Registers
Table 24. Limit Registers1
Input
VP1
VP2
VP3
VP4
VH
VX1
VX2
VX3
VX4
VX5
1
Reg.
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
Reg. Name
ADCVP1LIM
ADCVP2LIM
ADCVP3LIM
ADCVP4LIM
ADCVHLIM
ADCVX1LIM
ADCVX2LIM
ADCVX3LIM
ADCVX4LIM
ADCVX5LIM
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Limit register for ADC conversion on the VP1 input
Limit register for ADC conversion on the VP2 input
Limit register for ADC conversion on the VP3 input
Limit register for ADC conversion on the VP4 input
Limit register for ADC conversion on the VH input
Limit register for ADC conversion on the VX1 input
Limit register for ADC conversion on the VX2 input
Limit register for ADC conversion on the VX3 input
Limit register for ADC conversion on the VX4 input
Limit register for ADC conversion on the VX5 input
An ADC reading above or below these limits generates a warning.
Table 25. Sense Registers1, 2
Reg. Reg. Name
0x7D LSENSE1
0x7E LSENSE2
Bits Bit Name
7
SENS7
R/W
R/W
6
SENS6
R/W
5
SENS5
R/W
4
SENS4
R/W
3
SENS3
R/W
2
SENS2
R/W
1
SENS1
R/W
0
SENS0
R/W
7
6
5
4
3
2
SENS7
SENS6
SENS5
SENS4
SENS3
SENS2
Description
Limit sense for VX3. 0 = ADC > ADCVX3LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVX3LIM gives a warning, that is, undervoltage.
Limit sense for VX2. 0 = ADC > ADCVX2LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVX2LIM gives a warning, that is, undervoltage.
Limit sense for VX1. 0 = ADC > ADCVX1LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVX1LIM gives a warning, that is, undervoltage.
Limit sense for VH. 0 = ADC > ADCVHLIM gives a warning, that is, overvoltage;
1 = ADC < ADCVHLIM gives a warning, that is, undervoltage.
Limit sense for VP4. 0 = ADC > ADCVP4LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVP4LIM gives a warning, that is, undervoltage.
Limit sense for VP3 0 = ADC > ADCVP3LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVP3LIM gives a warning, that is, undervoltage.
Limit sense for VP2. 0 = ADC > ADCVP2LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVP2LIM gives a warning, that is, undervoltage.
Limit sense for VP1. 0 = ADC > ADCVP1LIM gives a warning, that is,
overvoltage; 1= ADC < ADCVP1LIM gives a warning, that is, undervoltage.
This bit cannot be used.
This bit cannot be used.
This bit cannot be used.
This bit cannot be used.
This bit cannot be used.
This bit cannot be used.
Rev. 0 | Page 60 of 71
Input
VX3
VX2
VX1
VH
VP4
VP3
VP2
VP1
N/A
N/A
N/A
N/A
N/A
N/A
Data Sheet
Reg. Reg. Name
1
2
ADM1260
Bits Bit Name
1
SENS1
R/W
R/W
0
R/W
SENS0
Description
Limit sense for VX5. 0 = ADC > ADCVX5LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVX5LIM gives a warning, that is, undervoltage.
Limit sense for VX4. 0 = ADC > ADCVX4LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVX4LIM gives a warning, that is, undervoltage.
Input
VX5
VX4
These registers determine when a warning is generated.
N/A means not applicable.
Table 26. Round Robin (RR) Select Registers1, 2
Input
VX3
VX2
VX1
VH
VP4
VP3
VP2
VP1
N/A
N/A
N/A
N/A
N/A
N/A
VX5
VX4
1
2
Reg. Addr.
0x80
Register
Name
RRSEL1
0x81
RRSEL2
Bits
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit Name
VX3CHAN
VX2CHAN
VX1CHAN
VHCHAN
VP4CHAN
VP3CHAN
VP2CHAN
VP1CHAN
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
VX5CHAN
VX4CHAN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
0 = VX3 is included in RR. 1 = VX3 is excluded from RR.
0 = VX2 is included in RR. 1 = VX2 is excluded from RR.
0 = VX1 is included in RR. 1 = VX1 is excluded from RR.
0 = VH is included in RR. 1 = VH is excluded from RR.
0 = VP4 is included in RR. 1 = VP4 is excluded from RR.
0 = VP3 is included in RR. 1 = VP3 is excluded from RR.
0 = VP2 is included in RR. 1 = VP2 is excluded from RR.
0 = VP1 is included in RR. 1 = VP1 is excluded from RR.
This bit cannot be used.
This bit cannot be used.
This bit cannot be used.
This bit cannot be used.
This bit cannot be used.
This bit cannot be used.
0 = VX5 is included in RR. 1= VX5 is excluded from RR.
0 = VX4 is included in RR. 1= VX4 is excluded from RR.
These registers determine which inputs are actually read by the ADC as it cycles.
N/A means not applicable.
Table 27. Round Robin Control Register1
Reg.
Addr.
0x82
1
Register
Name
RRCTRL
Bits
[7:5]
4
3
2
1
0
Bit Name
R/W
CLEARLIM
STOPWRITE
AVERAGE
ENABLE
GO
R/W
R/W
R/W
R/W
R/W
Description
These bits cannot be used.
Write this bit high to clear limit warnings. Then, this bit self clears.
This bit inhibits the RR from writing the results to the output registers.
This bit turns on 16× averaging.
This bit turns on the RR for continuous operation.
This bit starts the RR.
This register activates an ADC read and determines whether averaging is used and whether there is a continuous read present.
Table 28. ADC Value Registers
Input
VP1
Reg.
Addr.
0xA0
0xA1
Register
Name
ADCHVP1
ADCLVP1
Bits
[7:4]
[3:0]
Bit Name
Not applicable
OUT3 to OUT0
R/W
R/W
[7:0]
OUT7 to OUT0
R/W
[7:0]
OUT7 to OUT0
R/W
Description
These bits are not used if Register 0x82, Bit 2 (average) = 0.
These bits are the 4 MSBs of the 12-bit result of the ADC conversions on VP1
when Register 0x82, Bit 2 (average) = 0.
These bits are the 8 MSBs of the 16-bit result of the ADC conversions on VP1
when Register 0x82, Bit 2 (average) = 1.
These bits are the 8 LSBs of 12-bit or 16-bit result of the ADC conversions on
the VP1 input.
Rev. 0 | Page 61 of 71
ADM1260
Input
VP2
VP3
VP4
VH
VX1
VX2
VX3
Reg.
Addr.
0xA2
Data Sheet
Register
Name
ADCHVP2
Bits
[7:4]
[3:0]
Bit Name
Not applicable
OUT3 to OUT0
R/W
R/W
[7:0]
OUT7 to OUT0
R/W
0xA3
ADCLVP2
[7:0]
OUT7 to OUT0
R/W
0xA4
ADCHVP3
[7:4]
[3:0]
Not applicable
OUT3 to OUT0
R/W
[7:0]
OUT7 to OUT0
R/W
0xA5
ADCLVP3
[7:0]
OUT7 to OUT0
R/W
0xA6
ADCHVP4
[7:4]
[3:0]
Not applicable
OUT3 to OUT0
R/W
[7:0]
OUT7 to OUT0
R/W
0xA7
ADCLVP4
[7:0]
OUT7 to OUT0
R/W
0xA8
ADCHVH
[7:4]
[3:0]
Not applicable
OUT3 to OUT0
R/W
[7:0]
OUT7 to OUT0
R/W
0xA9
ADCLVH
[7:0]
OUT7 to OUT0
R/W
0xAA
ADCHVX1
[7:4]
[3:0]
Not applicable
OUT3 to OUT0
R/W
[7:0]
OUT7 to OUT0
R/W
0xAB
ADCLVX1
[7:0]
OUT7 to OUT0
R/W
0xAC
ADCHVX2
[7:4]
[3:0]
Not applicable
OUT3 to OUT0
R/W
[7:0]
OUT7 to OUT0
R/W
0xAD
ADCLVX2
[7:0]
OUT7 to OUT0
R/W
0xAE
ADCHVX3
[7:4]
[3:0]
Not applicable
OUT3 to OUT0
R/W
[7:0]
OUT7 to OUT0
R/W
[7:0]
OUT7 to OUT0
R/W
0xAF
ADCLVX3
Description
These bits are not used if Register 0x82, Bit 2 (average) = 0.
These bits are the 4 MSBs of the 12-bit result of the ADC conversions on VP2
when Register 0x82, Bit 2 (average) = 0.
These bits are the 8 MSBs of the 16-bit result of the ADC conversions on VP2
when Register 0x82, Bit 2 (average) = 1.
These bits are the 8 LSBs of 12-bit or 16-bit result of the ADC conversions on
the VP2 input.
These bits are not used if Register 0x82, Bit 2 (average) = 0.
These bits are the 4 MSBs of the 12-bit result of the ADC conversions on VP3
when Register 0x82, Bit 2 (average) = 0.
These bits are the 8 MSBs of the 16-bit result of the ADC conversions on VP3
when Register 0x82, Bit 2 (average) = 1.
These bits are the 8 LSBs of 12-bit or 16-bit result of the ADC conversions on
the VP3 input.
These bits are not used if Register 0x82, Bit 2 (average) = 0.
These bits are the 4 MSBs of the 12-bit result of the ADC conversions on VP4
when Register 0x82, Bit 2 (average) = 0.
These bits are the 8 MSBs of the 16-bit result of the ADC conversions on VP4
when Register 0x82, Bit 2 (average) = 1.
These bits are the 8 LSBs of 12-bit or 16-bit result of the ADC conversions on
the VP4 input.
These bits are not used if Register 0x82, Bit 2 (average) = 0.
These bits are the 4 MSBs of the 12-bit result of the ADC conversions on VH
when Register 0x82, Bit 2 (average) = 0.
These bits are the 8 MSBs of the 16-bit result of the ADC conversions on VH
when Register 0x82, Bit 2 (average) = 1.
These bits are the 8 LSBs of 12-bit or 16-bit result of the ADC conversions on
the VH input.
These bits are not used if Register 0x82, Bit 2 (average) = 0.
These bits are the 4 MSBs of the 12-bit result of the ADC conversions on VX1
when Register 0x82, Bit 2 (average) = 0.
These bits are the 8 MSBs of the 16-bit result of the ADC conversions on VX1
when Register 0x82, Bit 2 (average) = 1.
These bits are the 8 LSBs of 12-bit or 16-bit result of the ADC conversions on
the VX1 input.
These bits are not used if Register 0x82, Bit 2 (average) = 0.
These bits are the 4 MSBs of the 12-bit result of the ADC conversions on VX2
when Register 0x82, Bit 2 (average) = 0.
These bits are the 8 MSBs of the 16-bit result of the ADC conversions on VX2
when Register 0x82, Bit 2 (average) = 1.
These bits are the 8 LSBs of 12-bit or 16-bit result of the ADC conversions on
the VX2 input.
These bits are not used if Register 0x82, Bit 2 (average) = 0.
These bits are the 4 MSBs of the 12-bit result of the ADC conversions on VX3
when Register 0x82, Bit 2 (average) = 0.
These bits are the 8 MSBs of the 16-bit result of the ADC conversions on VX3
when Register 0x82, Bit 2 (average) = 1.
These bits are the 8 LSBs of 12-bit or 16-bit result of the ADC conversions on
the VX3 input.
Rev. 0 | Page 62 of 71
Data Sheet
Input
VX4
VX5
Reg.
Addr.
0xB0
Register
Name
ADCHVX4
ADM1260
Bits
[7:4]
[3:0]
Bit Name
Not applicable
OUT3 to OUT0
R/W
R/W
[7:0]
OUT7 to OUT0
R/W
0xB1
ADCLVX4
[7:0]
OUT7 to OUT0
R/W
0xB2
ADCHVX5
[7:4]
[3:0]
Not applicable
OUT3 to OUT0
R/W
[7:0]
OUT7 to OUT0
R/W
[7:0]
OUT7 to OUT0
R/W
0xB3
ADCLVX5
Description
These bits are not used if Register 0x82, Bit 2 (average) = 0.
These bits are the 4 MSBs of the 12-bit result of the ADC conversions on VX4
when Register 0x82, Bit 2 (average) = 0.
These bits are the 8 MSBs of the 16-bit result of the ADC conversions on VX4
when Register 0x82, Bit 2 (average) = 1.
These bits are the 8 LSBs of 12-bit or 16-bit result of the ADC conversions on
the VX4 input.
These bits are not used if Register 0x82, Bit 2 (average) = 0.
These bits are the 4 MSBs of the 12-bit result of the ADC conversions on VX5
when Register 0x82, Bit 2 (average) = 0.
These bits are the 8 MSBs of the 16-bit result of the ADC conversions on VX5
when Register 0x82, Bit 2 (average) = 1.
These bits are the 8 LSBs of 12-bit or 16-bit result of the ADC conversions on
the VX5 input.
DACS
The ADM1260 features six voltage output DACs. These DACs
are primarily used to adjust the output voltage of a dc-to-dc
converter by altering the current at its feedback node. These
DACs, therefore, provide an open-loop margining system. The
ADC on the ADM1260, along with an external microcontroller,
can be used to close this loop.
When the DACx output buffer is turned on, it has very little
effect on the dc-to-dc output. The DAC output buffer is designed
to power up without glitching. The output buffer accomplishes
this by first powering up the buffer to follow the pin voltage; the
voltage on the feedback pin of the LDO does not drive out onto
the pin at this time. After the output buffer is properly enabled,
the buffer input is switched over to the DAC, and the output
stage of the buffer is turned on. Output glitching is negligible.
Four DAC ranges are available and placed with midcode
(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V to correspond to
the most common feedback voltages. Centering the DAC outputs
in this way provides the best use of the DAC resolution; that is,
for most supplies it is possible to place the DAC midcode at the
point where the dc-to-dc output is not modified, thus giving
each of the DACs one half of the full range to margin up and
down. The DAC output voltage is set by the code written to the
DACx register. The voltage is linear with the unsigned binary
number in this register. Code 0x7F is placed at the midcode
voltage.
The output voltage is given by the following equation:
DAC Output = (DACx − 0x7F)/255 × 0.6015 + VOFF
where VOFF is one of the four offset voltages described earlier in
this section.
Limit registers on the device (DPLIMx and DNLIMx) offer the
user some protection from firmware bugs that can cause catastrophic board problems by forcing supplies beyond their allowable
output ranges. The DAC code written into the DACx register is
clipped so that the code used to set the DAC voltage is actually
given by
DACCode
= DACx, DNLIMx ≤ DACx ≤ DPLIMx
= DNLIMx, DACx < DPLIMx
= DPLIMx, DACx > DPLIMx
The DAC output buffer is three-stated if DNLIMx > DPLIMx.
The user can make it difficult for the DAC output buffers to be
turned on at all in normal system operation by programming
the limit registers in this way (these are among the registers
downloaded from EEPROM at startup).
Table 29 shows the detail of the registers required to set up
the DACs.
Rev. 0 | Page 63 of 71
ADM1260
Data Sheet
Table 29. DAC Configuration Registers
Output
DAC1
DAC2
DAC3
Reg.
Addr.
0x50
Register
Name
DACCTRL1
Bits
[7:3]
2
[1:0]
Bit Name
Not applicable
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
R/W
0x58
0x60
DAC1
DPLIM1
[7:0]
[7:0]
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x68
DNLIM1
[7:0]
LIM7 to LIM0
R/W
0x51
DACCTRL2
[7:3]
2
[1:0]
Not applicable
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
0x59
0x61
DAC2
DPLIM2
[7:0]
[7:0]
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x69
DNLIM2
[7:0]
LIM7 to LIM0
R/W
0x52
DACCTRL3
[7:3]
2
[1:0]
Not applicable
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
0x5A
0x62
DAC3
DPLIM3
[7:0]
[7:0]
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x6A
DNLIM3
[7:0]
LIM7 to LIM0
R/W
Description
These bits cannot be used.
This bit enables DAC1.
These bits select the center voltage (midcode) output of DAC1.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage (V)
0
0
1.25
0
1
1.0
1
0
0.8
1
1
0.6
These bits are the 8-bit DAC code (0x7F is midcode).
These bits are the 8-bit DAC positive limit code. If DAC1 is set to a
higher code, the DAC code limits to the contents of this register.
These bits are the 8-bit DAC negative limit code. If DAC1 is set to a
lower code, the DAC code limits to the contents of this register. Note
that if DNLIM1 is set to be greater than DPLIM1, the DAC output is
always disabled (this is a safety feature).
These bits cannot be used.
This bit enables DAC2.
These bits select the center voltage (midcode) output of DAC2.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage (V)
0
0
1.25
0
1
1.0
1
0
0.8
1
1
0.6
8-bit DAC code (0x7F is midcode).
These bits are the 8-bit DAC positive limit code. If DAC2 is set to a
higher code, the DAC code limits to the contents of this register.
These bits are the 8-bit DAC negative limit code. If DAC2 is set to a
lower code, the DAC code limits to the contents of this register.
Note that if DNLIM2 is set to be greater than DPLIM2, the DAC
output is always disabled (this is a safety feature).
These bits cannot be used.
This bit enables DAC3.
These bits select the center voltage (midcode) output of DAC3.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage (V)
0
0
1.25
0
1
1.0
1
0
0.8
1
1
0.6
These bits are the 8-bit DAC code (0x7F is midcode).
These bits are the 8-bit DAC positive limit code. If DAC3 is set to a
code higher than this, the DAC code limits to the contents of this
register.
These bits are the 8-bit DAC negative limit code. If DAC3 is set to a
code lower than this, the DAC code limits to the contents of this
register. Note that if DNLIM3 is set to be greater than DPLIM3, the
DAC output is always disabled (this is a safety feature).
Rev. 0 | Page 64 of 71
Data Sheet
Output
DAC4
DAC5
DAC6
Reg.
Addr.
0x53
ADM1260
Register
Name
DACCTRL4
Bits
[7:3]
2
[1:0]
Bit Name
Not applicable
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
R/W
0x5B
0x63
DAC4
DPLIM4
[7:0]
[7:0]
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x6B
DNLIM4
[7:0]
LIM7 to LIM0
R/W
0x54
DACCTRL5
[7:3]
2
[1:0]
Not applicable
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
0x5C
0x64
DAC5
DPLIM5
[7:0]
[7:0]
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x6C
DNLIM5
[7:0]
LIM7 to LIM0
R/W
0x55
DACCTRL6
[7:3]
2
[1:0]
Not applicable
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
0x5D
0x65
DAC6
DPLIM6
7:0
7:0
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x6D
DNLIM6
7:0
LIM7 to LIM0
R/W
Description
These bits cannot be used.
This bit enables DAC4.
These bits select the center voltage (midcode) output of DAC4.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage (V)
0
0
1.25
0
1
1.0
1
0
0.8
1
1
0.6
These bits are the 8-bit DAC code (0x7F is midcode).
These bits are the 8-bit DAC positive limit code. If DAC4 is set to a
higher code, the DAC code limits to the contents of this register.
These bits are the 8-bit DAC negative limit code. If DAC4 is set to a
lower code, the DAC code limits to the contents of this register.
Note that if DNLIM4 is set to be greater than DPLIM4, the DAC
output is always disabled (this is a safety feature).
These bits cannot be used.
This bit enables DAC5.
These bits select the center voltage (midcode) output of DAC5.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage (V)
0
0
1.25
0
1
1.0
1
0
0.8
1
1
0.6
These bits are the 8-bit DAC code (0x7F Is midcode).
These bits are the 8-bit DAC positive limit code. If DAC5 is set to a
higher code, the DAC code limits to the contents of this register.
These bits are the 8-bit DAC negative limit code. If DAC5 is set to a
lower code, the DAC code limits to the contents of this register.
Note that if DNLIM5 is set to be greater than DPLIM5, the DAC
output is always disabled (this is a safety feature).
These bits cannot be used.
This bit enables DAC6.
These bits select the center voltage (midcode) output of DAC6.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage (V)
0
0
1.25
0
1
1.0
1
0
0.8
1
1
0.6
These bits are the 8-bit DAC code (0x7F is midcode).
These bits are the 8-bit DAC positive limit code. If DAC6 is set to a
higher code, the DAC code limits to the contents of this register.
These bits are the 8-bit DAC negative limit code. If DAC6 is set to a
lower code, the DAC code limits to the contents of this register.
Note that if DNLIM6 is set to be greater than DPLIM6, the DAC
output is always disabled (this is a safety feature).
Rev. 0 | Page 65 of 71
ADM1260
Data Sheet
WARNINGS, FAULTS, AND STATUS
Warnings
The ADM1260 features a low level of fault detection that can be
used in conjunction with the fault detection provided on the
inputs. These low level fault reports are provided by the ADC
limit registers and by the secondary SFDs on the VP1 to VP4
and VH inputs. The secondary SFDs are available on these pins
when VX1 to VX5 are used as digital inputs.
Warning is provided as a single input to the SE. It consists of a
wide OR of the ADC limit registers and the secondary SFD
outputs. Selecting warning as an input to the SE is shown in the
Sequencing Engine section.
Status Reporting
The ADM1260 features a number of status registers that can be
read at any time to determine the status of the inputs. The
contents of these registers can change at any time; that is, the
data is not latched in these registers. Table 30 shows the details
of status registers.
Table 30. Status Registers
Register
Address
0xE2
Register
Name
OVSTAT1
0xE3
OVSTAT2
0xE4
UVSTAT1
0xE5
UVSTAT2
0xE6
LIMSTAT1
0xE7
LIMSTAT2
0xE8
GPISTAT
Bits
7
6
5
4
3
2
1
0
[7:2]
1
0
7
6
5
4
3
2
1
0
[7:2]
1
0
7
6
5
4
3
2
1
0
[7:2]
1
0
[7:5]
4
3
2
1
0
Bit Name
OV_VX3
OV_VX2
OV_VX1
OV_VH
OV_VP4
OV_VP3
OV_VP2
OV_VP1
Not applicable
OV_VX5
OV_VX4
UV_VX3
UV_VX2
UV_VX1
UV_VH
UV_VP4
UV_VP3
UV_VP2
UV_VP1
Not applicable
UV_VX5
UV_VX4
VX3 CH
VX2 CH
VX1 CH
VH CH
VP4 CH
VP3 CH
VP2 CH
VP1 CH
Not applicable
VX5 CH
VX4 CH
Not applicable
VX5_STAT
VX4_STAT
VX3_STAT
VX2_STAT
VX1_STAT
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Description
Overvoltage threshold exceeded on VX3 (SFD) or VP3 (warning).
Overvoltage threshold exceeded on VX2 (SFD) or VP2 (warning).
Overvoltage threshold exceeded on VX1 (SFD) or VP1 (warning).
Overvoltage threshold exceeded on the VH SFD.
Overvoltage threshold exceeded on the VP4 SFD.
Overvoltage threshold exceeded on the VP3 SFD.
Overvoltage threshold exceeded on the VP2 SFD.
Overvoltage threshold exceeded on the VP1 SFD.
These bits cannot be used.
Overvoltage threshold exceeded on VX5 (SFD) or VH (warning).
Overvoltage threshold exceeded on VX4 (SFD) or VP4 (warning).
Undervoltage threshold exceeded on VX3 (SFD) or VP3 (warning).
Undervoltage threshold exceeded on VX2 (SFD) or VP2 (warning).
Undervoltage threshold exceeded on VX1 (SFD) or VP1 (warning).
Undervoltage threshold exceeded on the VH SFD.
Undervoltage threshold exceeded on the VP4 SFD.
Undervoltage threshold exceeded on the VP3 SFD.
Undervoltage threshold exceeded on the VP2 SFD.
Undervoltage threshold exceeded on the VP1 SFD.
These bits cannot be used.
Undervoltage threshold exceeded on VX5 (SFD) or VH (warning).
Undervoltage threshold exceeded on VX4 (SFD) or VP4 (warning).
VX3 limit status; used with LSENSE 1.
VX2 limit status; used with LSENSE 1.
VX1 limit status; used with LSENSE 1.
VH limit status; used with LSENSE 1.
VP4 limit status; used with LSENSE 1.
VP3 limit status; used with LSENSE 1.
VP2 limit status; used with LSENSE 1.
VP1 limit status; used with LSENSE 1.
These bits cannot be used.
VX5 CH limit status; used with LSENSE 2.
VX4 CH limit status; used with LSENSE 2.
These bits cannot be used.
VX5 GPI input status (after signal conditioning).
VX4 GPI input status (after signal conditioning).
VX3 GPI input status (after signal conditioning).
VX2 GPI input status (after signal conditioning).
VX1 GPI input status (after signal conditioning).
Rev. 0 | Page 66 of 71
Data Sheet
ADM1260
BLACK BOX STATUS REGISTERS AND FAULT
RECORDS
The checksum byte is a simple addition of the values written
into the seven other EEPROM location for a given fault record.
Each time the ADM1260 SE changes state, the contents of the
UVSTATx, OVSTATx, LIMSTATx, and GPISTATx registers,
along with some other pieces of information relating to the SE
state and the cause of the last state transition, are latched into
seven black box status registers.
The order of the bytes in a fault record stored in EEPROM is as
follows:
These registers provide a snapshot of the state of the inputs
being monitored by the ADM1260, what the last state was, and
what caused the last state change.
After the SE changes state, if the new state it enters has its
corresponding STATEx bit set (see the BBWRTRGx registers),
the seven black box status registers are written sequentially into
the next available location in the black box EEPROM section.
After the seven bytes are written, an eighth checksum byte is
written to provide a method to check data integrity. This check
is important if only a partial record is written because all the
supplies powering the device failed.
1.
2.
3.
4.
5.
6.
7.
8.
PREVSTEXT
PREVSEQST
BBSTAT1
BBSTAT2
BBSTAT3
BBSTAT4
BBSTAT5
CHECKSUM
The bytes are stored from lowest to the highest EEPROM address;
therefore, for the first fault record location in the black box
EEPROM, PREVSTEXT is stored at 0xF980 and CHECKSUM at
0xF987.
Table 31. Black Box Fault and Status Registers1
Register
Address
0xEA
0xEB
0xEC
Register
Name
PREVSTEXT
PREVSEQST
BBSTAT1
Bits
7
Bit Name
BBUSED
R/W
N/A
6
ICBMSG
R
5
SMBJUMP
R
4
LIMWARN
R
3
SFDCMP
R
2
Timeout
R
1
Monitor
R
0
Sequence
R
[5:0]
7
6
5
4
3
2
1
0
PREVADDR
UV_VX3
UV_VX2
UV_VX1
UV_VH
UV_VP4
UV_VP3
UV_VP2
UV_VP1
R
R
R
R
R
R
R
R
R
Description
This bit always reads as 0. When this bit is written to the first byte of a fault
record in EEPROM, it marks all eight bytes in use. When the black box is searching
for the next free location to use, this bit is examined. If this bit is 0, then even if
the previous fault record is only partially written to EEPROM, the eight bytes of
the fault record are ignored.
This bit indicates that the previous state transition was triggered by a message
received on the ICB.
This bit indicates that the previous state transition was due to an SMB jump
being received.
This bit indicates that the previous state transition was due to one or more ADC
warning limits being exceeded.
This bit indicates that the previous state transition was due to one or more
supply fault detector limits being exceeded.
This bit indicates that the previous state transition was due to the timeout
condition becoming true.
This bit indicates that the previous state transition was due to the monitor
condition becoming true.
This bit indicates that the previous state transition was due to the sequence
condition becoming true.
State number of the state that was active immediately prior to the current state.
Undervoltage threshold exceeded on VX3 (SFD) or VP3 (warning).
Undervoltage threshold exceeded on VX2 (SFD) or VP2 (warning).
Undervoltage threshold exceeded on VX1 (SFD) or VP1 (warning).
Undervoltage threshold exceeded on the VH SFD.
Undervoltage threshold exceeded on the VP4 SFD.
Undervoltage threshold exceeded on the VP3 SFD.
Undervoltage threshold exceeded on the VP2 SFD.
Undervoltage threshold exceeded on the VP1 SFD.
Rev. 0 | Page 67 of 71
ADM1260
Register
Address
0xED
Register
Name
BBSTAT2
0xEE
BBSTAT3
0xEF
BBSTAT4
0xF0
BBSTAT5
0xF1
1
BBADDR
Data Sheet
Bits
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
[7:3]
2
1
0
[7:0]
Bit Name
OV_VX1
OV_VH
OV_VP4
OV_VP3
OV_VP2
OV_VP1
UV_VX5
UV_VX4
VX4_STAT
VX3_STAT
VX2_STAT
VX1_STAT
OV_VX5
OV_VX4
OV_VX3
OV_VX2
VX2 CH
VX1 CH
VH CH
VP4 CH
VP3 CH
VP2 CH
VP1 CH
VX5_STAT
Reserved
VX5 CH
VX4 CH
VX3 CH
ADDR
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Description
Overvoltage threshold exceeded on VX1 (SFD) or VP1 (warning).
Overvoltage threshold exceeded on the VH SFD.
Overvoltage threshold exceeded on the VP4 SFD.
Overvoltage threshold exceeded on the VP3 SFD.
Overvoltage threshold exceeded on the VP2 SFD.
Overvoltage threshold exceeded on the VP1 SFD.
Undervoltage threshold exceeded on VX5 (SFD) or VH (warning).
Undervoltage threshold exceeded on VX4 (SFD) or VP4 (warning).
VX4 GPI input status (after signal conditioning).
VX3 GPI input status (after signal conditioning).
VX2 GPI input status (after signal conditioning).
VX1 GPI input status (after signal conditioning).
Overvoltage threshold exceeded on VX5 (SFD) or VH (warning).
Overvoltage threshold exceeded on VX4 (SFD) or VP4 (warning).
Overvoltage threshold exceeded on VX3 (SFD) or VP3 (warning).
Overvoltage threshold exceeded on VX2 (SFD) or VP2 (warning).
VX2 limit status; used with LSENSE 1.
VX1 limit status; used with LSENSE 1.
VH limit status; used with LSENSE 1.
VP4 limit status; used with LSENSE 1.
VP3 limit status; used with LSENSE 1.
VP2 limit status; used with LSENSE 1.
VP1 limit status; used with LSENSE 1.
VX5 GPI input status (after signal conditioning).
These bits cannot be used.
VX5 CH limit status; used with LSENSE 2.
VX4 CH limit status; used with LSENSE 2.
VX3 limit status; used with LSENSE 1.
These bits are the low byte of the address location in the 0xF980 to 0xF9FF
range that the next fault record is written to. When no fault records are written,
the value is 0x80, and increments by 8 each time a fault record is written. The
value is 0x F8 when there is only one fault record not written. When all locations
are written to and the black box EEPROM is full, the value is 0x00.
N/A means not applicable.
Rev. 0 | Page 68 of 71
Data Sheet
ADM1260
USE OF THE REVID REGISTER
INTERCHIP BUS CONFIGURATION
The ADM1066, ADM1166, and ADM1260 have the same I2C
addresses range, and both return the value of 0x41 when the
MANID register is read. REVID is a read only register that
determines whether a device at a given address is an ADM1066,
an ADM1166, or an ADM1260 (see Table 32).
The ADM1260 uses a dedicated interchip bus (ICB) to
coordinate sequencing activities between multiple devices.
Each device on the ICB is assigned a unique address to identify
it to other devices.
The ICBADDR bits are independent of the I2C address assigned
by the A0 and A1 address pins.
Table 32. Decoding the REVID Register
Reg.
Addr.
0xF5
Register
Name
REVID
Bits
[7:4]
[3:0]
Bit Name
Family
HWVER
R/W
R
R
Description
When the value of these bits is 0x2, the device is an ADM1260.
The value on these bits is the hardware revision number.
Table 33. Fault and Status Registers
Reg. Addr.
0x56
0x57
0x5E
Register
Name
ICBCFG1
ICBCFG2
ICBCFG3
Bits
[7:4]
[3:0]
Bit Name
Reserved
ICBADDR
R/W
[7:6]
[5:0]
Reserved
BUSFAULT
R/W
[7:6]
[5:0]
Reserved
SEQFAULT
R/W
R/W
Description
These bits cannot be used.
These bits are the address used to identify the device on the ICB and is different
from the SMBus address. The ADM1260 has an address range of 1 to 4. A value
of 0 is not a valid device address because that is used by broadcast messages.
These bits cannot be used.
These bits set the state to jump in case of a bus fault on the ICB. These bits are
set by the GUI.
These bits cannot be used.
These bits set the state to jump in case of a sequence fault. These bits are set by
the GUI.
Rev. 0 | Page 69 of 71
ADM1260
Data Sheet
REGISTER MAP QUICK REFERENCE
Table 34 provides a quick reference for the registers described in this data sheet.
Table 34. Register Map Quick Reference1
Base
(Hex)
00
08
10
18
20
28
30
38
40
48
50
58
60
68
70
78
80
88
90
98
A0
A8
B0
B8
C0
C8
D0
D8
E0
E8
F0
F8
1
Function
0
VP1
PS1OVTH
VP2
PS2OVTH
VP3
PS3OVTH
VP4
PS4OVTH
VH
PSVHOVTH
VX1
X1OVTH
VX2
X2OVTH
VX3
X3OVTH
VX4
X4OVTH
VX5
X5OVTH
DAC control
DACCTRL1
DAC code
DAC1
DAC upper limit DPLIM1
DAC lower limit DNLIM1
ADCLIM
ADCVP1LIM
ADCLIM
ADCVX4LIM
ADC setup
RRSEL1
N/A
N/A
Miscellaneous
UPDCFG
Miscellaneous
BBWRTRG5
ADC readback
ADCHVP1
ADC readback
ADCHVH
ADC readback
ADCHVX4
ADC readback
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Miscellaneous
UDOWNLD
Fault (read only) N/A
Fault (read only) GPISTAT
Miscellaneous
BBSTAT5
Commands
EEALOW
1
PS1OVHYST
PS2OVHYST
PS3OVHYST
PS4OVHYST
PSVHOVHYST
X1OVHYST
X2OVHYST
X3OVHYST
X4OVHYST
X5OVHYST
DACCTRL2
DAC2
DPLIM2
DNLIM2
ADCVP2LIM
ADCVX5LIM
RRSEL2
N/A
PDEN1
BBWRTRG6
ADCLVP1
ADCLVH
ADCLVX4
N/A
N/A
N/A
N/A
BBSEARCH
N/A
SEADDR
BBADDR
EEAHIGH
2
PS1UVTH
PS2UVTH
PS3UVTH
PS4UVTH
PSVHUVTH
X1UVTH
X2UVTH
X3UVTH
X4UVTH
X5UVTH
DACCTRL3
DAC3
DPLIM3
DNLIM3
ADCVP3LIM
N/A
RRCTRL
N/A
PDEN2
BBWRTRG7
ADCHVP2
ADCHVX1
ADCHVX5
N/A
N/A
N/A
N/A
UNLOCKSE
OVSTAT1
PREVSTEXT
N/A
EEBLOW
3
PS1UVHYST
PS2UVHYST
PS3UVHYST
PS4UVHYST
PSVHUVHYST
X1UVHYST
X2UVHYST
X3UVHYST
X4UVHYST
X5UVHYST
DACCTRL4
DAC4
DPLIM4
DNLIM4
ADCVP4LIM
N/A
N/A
N/A
SECTRL
BBWRTRG8
ADCLVP2
ADCLVX1
ADCLVX5
N/A
N/A
N/A
N/A
SEDOWNLD
OVSTAT2
PREVSEQST
N/A
EEBHIGH
N/A means not applicable and indicates that a register location does not exist.
Rev. 0 | Page 70 of 71
4
SFDV1CFG
SFDV2CFG
SFDV3CFG
SFDV4CFG
PSVHDVHCFG
SFDX1CFG
SFDX2CFG
SFDX3CFG
SFDX4CFG
SFDX5CFG
DACCTRL5
DAC5
DPLIM5
DNLIM5
ADCVHLIM
N/A
N/A
N/A
BBWRTRG1
BBCTRL
ADCHVP3
ADCHVX2
N/A
N/A
N/A
N/A
N/A
N/A
UVSTAT1
BBSTAT1
MANID
BLKWR
5
SFDV1SEL
SFDV2SEL
SFDV3SEL
SFDV4SEL
SFDVHSEL
SFDVX1SEL
SFDVX2SEL
SFDVX3SEL
SFDVX4SEL
SFDVX5SEL
DACCTRL6
DAC6
DPLIM6
DNLIM6
ADCVX1LIM
LSENSE1
N/A
N/A
BBWRTRG2
N/A
ADCLVP3
ADCLVX2
N/A
N/A
N/A
N/A
N/A
N/A
UVSTAT2
BBSTAT2
REVID
BLKRD
6
N/A
N/A
N/A
N/A
N/A
XGPI1CFG
XGPI2CFG
XGPI3CFG
XGPI4CFG
XGPI5CFG
ICBCFG1
ICBCFG3
N/A
N/A
ADCVX2LIM
LSENSE2
N/A
N/A
BBWRTRG3
N/A
ADCHVP4
ADCHVX3
N/A
N/A
N/A
N/A
N/A
N/A
LIMSTAT1
BBSTAT4
N/A
BLKER
7
PDO1CFG
PDO2CFG
PDO3CFG
PDO4CFG
PDO5CFG
PDO6CFG
PDO7CFG
PDO8CFG
PDO9CFG
PDO10CFG
ICBCFG2
N/A
N/A
N/A
ADCVX3LIM
N/A
N/A
N/A
BBWRTRG4
N/A
ADCLVP4
ADCLVX3
N/A
N/A
N/A
N/A
N/A
N/A
LIMSTAT2
BBSTAT4
N/A
N/A
Data Sheet
ADM1260
OUTLINE DIMENSIONS
0.30
0.25
0.18
31
40
30
0.50
BSC
1
TOP VIEW
0.80
0.75
0.70
10
11
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*4.70
4.60 SQ
4.50
EXPOSED
PAD
21
0.45
0.40
0.35
PIN 1
INDICATOR
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
02-02-2010-A
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
Figure 52. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.75 mm Package Height
(CP-40-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADM1260ACPZ
ADM1260ACPZ-RL7
EVAL-ADM1260EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Kit
Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12445-0-4/16(0)
Rev. 0 | Page 71 of 71
Package Option
CP-40-7
CP-40-7
工商网监
湘ICP备2023018690号
