ADM1275-3ACPZ

FEATURES APPLICATIONS DIAGRAM Controls supply voltages from 2 V to 20 V 370 ns response time to short circuit Resistor-programmable 5 mV to 25 mV current limit ±1% accurate, 12-bit ADC for current, VIN/VOUT readback Charge-pumped gate drive for multiple external N-channel FETs High gate drive voltage to ensure lowest RDSON Foldback for tighter FET SOA protection Automatic retry or latch-off on current fault Programmable current limit timer for SOA Programmable, multifunction GPOs Power-good status output Analog UV and OV protection ENABLE pin (ADM1275-3 only) Peak detect registers for current and voltage PMBus fast mode compliant interface 16-lead QSOP and 20-lead QSOP and LFCSP APPLICATIONS RSENSE 2V TO 20V 2.95V TO 20V SENSE+ CHARGE PUMP VCP IOUT 1.0V ISET ADM1275-1 LDO UV OV SENSE– + – ×50 VCC VCAP Q1 + – – 1.0V + REF SELECT 1.0V SS GATE DRIVE/ LOGIC TIMEOUT CURRENT LIMIT TIMER ON + – CURRENT LIMIT CONTROL VCBOS TIMER ON TIMER TIMER SENSE+ VOUT IOUT FLB TIMEOUT 12-BIT ADC LOGIC AND PMBus GND Power monitoring and control/power budgeting Central office equipment Telecommunication and data communication equipment PCs/servers GATE VOUT PWRGD GPO1/ALERT1/CONV GPO2/ALERT2 LATCH SCL SDA ADR 08931-001 Data Sheet Hot-Swap Controller and Digital Power Monitor with PMBus Interface ADM1275 Figure 1. GENERAL DESCRIPTION The ADM1275 is a hot-swap controller that allows a circuit board to be removed from or inserted into a live backplane. It also features current and voltage readback via an integrated 12-bit analog-todigital converter (ADC), accessed using a PMBus™ interface. The load current is measured using an internal current sense amplifier that measures the voltage across a sense resistor in the power path via the SENSE+ and SENSE− pins. A default limit of 20 mV is set, but this limit can be adjusted, if required, using a resistor divider network from the internal reference voltage to the ISET pin. The ADM1275 limits the current through the sense resistor by controlling the gate voltage of an external N-channel FET in the power path, via the GATE pin. The sense voltage—and, therefore, the load current—is maintained below the preset maximum. The ADM1275 protects the external FET by limiting the time that the FET remains on while the current is at its maximum value. This current limit time is set by the choice of capacitor connected to the TIMER pin. In addition, a foldback resistor network can be used to actively lower the current limit as the voltage across the FET is increased. This helps to maintain constant power in the FET and allows the safe operating area (SOA) to be adhered to in an effective manner. Rev. E In case of a short-circuit event, a fast internal overcurrent detector responds within 370 ns and signals the gate to shut down. A 1500 mA pull-down device ensures a fast FET response. The ADM1275 features overvoltage and undervoltage protection, programmed using external resistor dividers on the UV and OV pins. A PWRGD signal can be used to detect when the output supply is valid, using the FLB pin to monitor the output. GPO pins can be configured as various output signals that can be asserted when a programmed current or voltage level is reached. The 12-bit ADC can measure the current in the sense resistor, as well as the supply voltage on the SENSE+ pin or the output voltage. A PMBus interface allows a controller to read current and voltage data from the ADC. Measurements can be initiated by a PMBus command. Alternatively, the ADC can run continuously, and the user can read the latest conversion data whenever required. Up to four unique PMBus addresses can be selected, depending on the way that the ADR pin is connected. The ADM1275-1 and ADM1275-3 are available in a 20-lead QSOP and 20-lead LFCSP and have a LATCH pin that can be configured for automatic retry or latch-off when an overcurrent fault occurs. The ADM1275-2 is available in a 16-lead QSOP with latch-off mode only. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADM1275 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Status Commands ...................................................................... 30 Applications ....................................................................................... 1 GPO and Alert Pin Setup Commands .................................... 31 Applications Diagram ...................................................................... 1 Power Monitor Commands ...................................................... 31 General Description ......................................................................... 1 Warning Limit Setup Commands ............................................ 32 Revision History ............................................................................... 3 PMBus Direct Format Conversion .......................................... 32 Specifications..................................................................................... 4 Voltage and Current Conversion using LSB values ............... 33 Serial Bus Timing Characteristics .............................................. 7 ADM1275 Alert Pin Behavior ...................................................... 34 Absolute Maximum Ratings............................................................ 8 Faults and Warnings .................................................................. 34 Thermal Characteristics .............................................................. 8 Generating an Alert ................................................................... 34 ESD Caution .................................................................................. 8 Handling/Clearing an Alert ...................................................... 34 Pin Configurations and Function Descriptions ........................... 9 SMBus Alert Response Address ............................................... 35 Typical Performance Characteristics ........................................... 14 Example Use of SMBus Alert Response Address ................... 35 Functional Block Diagrams ........................................................... 20 PMBus Command Reference........................................................ 36 Theory of Operation ...................................................................... 21 OPERATION .............................................................................. 37 Powering the ADM1275 ............................................................ 21 CLEAR_FAULTS ........................................................................ 37 Current Sense Inputs.................................................................. 21 CAPABILITY .............................................................................. 37 Current Limit Reference ............................................................ 22 VOUT_OV_WARN_LIMIT ..................................................... 37 Setting the Current Limit (ISET) ............................................. 22 VOUT_UV_WARN_LIMIT ..................................................... 37 Soft Start ...................................................................................... 23 IOUT_OC_WARN_LIMIT ...................................................... 37 Foldback....................................................................................... 23 IOUT_WARN2_LIMIT............................................................. 38 Timer ............................................................................................ 24 VIN_OV_WARN_LIMIT ......................................................... 38 Hot-Swap Retry Duty Cycle ...................................................... 24 VIN_UV_WARN_LIMIT ......................................................... 38 FET Gate Drive Clamps ............................................................. 24 STATUS_BYTE .......................................................................... 38 Fast Response to Severe Overcurrent ...................................... 25 STATUS_WORD ........................................................................ 39 Undervoltage and Overvoltage ................................................. 25 STATUS_VOUT ......................................................................... 39 ENABLE Input (ADM1275-3 Only) ........................................ 25 STATUS_IOUT .......................................................................... 39 Power Good................................................................................. 25 STATUS_INPUT ........................................................................ 40 VOUT Measurement ................................................................. 26 STATUS_MFR_SPECIFIC ........................................................ 40 FET Health .................................................................................. 26 READ_VIN ................................................................................. 40 Power Monitor ............................................................................ 26 READ_VOUT ............................................................................. 41 PMBus Interface ............................................................................. 27 READ_IOUT .............................................................................. 41 Device Addressing ...................................................................... 27 PMBUS_REVISION .................................................................. 41 SMBus Protocol Usage ............................................................... 27 MFR_ID....................................................................................... 41 Packet Error Checking ............................................................... 27 MFR_MODEL ............................................................................ 41 2 Partial Transactions on I C Bus ................................................ 27 MFR_REVISION........................................................................ 42 SMBus Message Formats ........................................................... 28 PEAK_IOUT ............................................................................... 42 Group Commands ...................................................................... 29 PEAK_VIN.................................................................................. 42 Hot-Swap Control Commands ................................................. 30 PEAK_VOUT ............................................................................. 42 ADM1275 Information Commands ........................................ 30 PMON_CONTROL ................................................................... 42 Rev. E | Page 2 of 48 Data Sheet ADM1275 PMON_CONFIG ........................................................................43 POWER_CYCLE ........................................................................ 45 ALERT1_CONFIG .....................................................................43 Outline Dimensions ........................................................................ 46 ALERT2_CONFIG .....................................................................44 Ordering Guide ........................................................................... 47 DEVICE_CONFIG .....................................................................45 REVISION HISTORY 5/2019—Rev. D to Rev. E Added Endnote 1, Table 2 ................................................................ 7 11/2013—Rev. C to Rev. D Changes to GATE Pin Parameter, Table 1...................................... 4 4/2013—Rev. B to Rev. C Added Partial Transactions on I2C Bus Section ..........................27 6/2011—Rev. A to Rev. B Changes to tBUF Parameter ................................................................ 7 Added Conditions Statement to Table 2 ....................................... 7 Changes to VOUT Pin Description, Table 5 ...............................10 Changes to VOUT Pin Description, Table 6 ...............................13 Changes to Figure 42 .....................................................................19 Changes to Current Sense Inputs Section ....................................21 Added PMBus Direct Format Conversion Section .................... 32 Added Voltage and Current Conversion Using LSB Values Section .................................................................................. 33 Changes to Handling/Clearing and Alert Section ...................... 34 10/2010—Rev. 0 to Rev. A Added 20-Lead LFCSP ...................................................... Universal Changes to Table 4 ............................................................................ 8 Added Figure 4; Renumbered Figures Sequentially ..................... 9 Changes to Table 5 ............................................................................ 9 Added Table 6; Renumbered Tables Sequentially ....................... 11 Added Figure 7 and Table 7 ........................................................... 12 Updated Outline Dimensions........................................................ 48 Changes to Ordering Guide ........................................................... 48 9/2010—Revision 0: Initial Version Rev. E | Page 3 of 48 ADM1275 Data Sheet SPECIFICATIONS VCC = 2.95 V to 20 V, VCC ≥ VSENSE+, VSENSE+ = 2 V to 20 V, VSENSE = (VSENSE+ − VSENSE−) = 0 V, TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter POWER SUPPLY Operating Voltage Range, VCC Undervoltage Lockout Undervoltage Hysteresis Quiescent Current, ICC UV PIN Input Current, IUV UV Threshold, UVTH UV Threshold Hysteresis, UVHYST UV Glitch Filter, UVGF UV Propagation Delay, UVPD OV PIN Input Current, IOV OV Threshold, OVTH OV Threshold Hysteresis, OVHYST OV Glitch Filter, OVGF OV Propagation Delay, OVPD SENSE+ AND SENSE− PINS Input Current, ISENSEx Input Imbalance, IΔSENSE VCAP PIN Internally Regulated Voltage, VVCAP ISET PIN Reference Select Threshold, VISETRSTH Internal Reference, VCLREF Gain of Current Sense Amplifier, AVCSAMP Input Current, IISET GATE PIN Gate Drive Voltage, ΔVGATE Gate Pull-Up Current, IGATEUP Gate Pull-Down Current, IGATEDN_REG Gate Pull-Down Current, IGATEDN_SLOW Gate Pull-Down Current, IGATEDN_FAST Gate Holdoff Resistance HOT-SWAP SENSE VOLTAGE Hot-Swap Sense Voltage Current Limit, VSENSECL Foldback Inactive Foldback Active Min Typ 2.95 2.4 90 0.97 40 2 1.0 50 5 0.97 50 0.5 1.0 60 1.0 Max Unit Test Conditions/Comments 20 2.7 120 5 V V mV mA 100 1.03 60 7 8 nA V mV μs μs 100 1.03 70 1.5 2 nA V mV μs μs 150 5 μA μA Per individual pin; SENSE+, SENSE− = 20 V IΔSENSE = (ISENSE+) − (ISENSE−) VCC rising GATE on and power monitor running UV ≤ 3.6 V UV falling 50 mV overdrive UV low to GATE pull-down active ADM1275-1 and ADM1275-3 OV ≤ 3.6 V OV rising 50 mV overdrive OV high to GATE pull-down active 2.66 2.7 2.74 V 0 µA ≤ IVCAP ≤ 100 µA; CVCAP = 1 μF 1.35 1.5 1 50 1.65 V V V/V nA If VISET > VISETRSTH, an internal 1 V reference (VCLREF) is used Accuracies included in total sense voltage accuracies Accuracies included in total sense voltage accuracies VISET ≤ VVCAP Maximum voltage on the gate is always clamped to ≤31 V ΔVGATE = VGATE − VSENSE+ 15 V ≥ VCC ≥ 8 V; IGATE ≤ 5 μA 20 V ≥ VCC ≥ 15 V; IGATE ≤ 5 μA VSENSE+ = VCC = 5 V; IGATE ≤ 5 μA VSENSE+ = VCC = 2.95 V; IGATE ≤ 1 μA VGATE = 0 V VGATE ≥ 2 V; VISET = 1.0 V; (SENSE+) − (SENSE−) = 30 mV VGATE ≥ 2 V VGATE ≥ 12 V; VCC ≥ 12 V VCC = 0 V 100 10 4.5 8 4.5 −20 45 5 750 12 60 10 1500 20 14 13 10 6 −30 75 15 2000 V V V V μA μA mA mA Ω 19.6 20 20.4 mV 24.6 19.6 9.6 4.6 3.5 9.6 25 20 10 5 4 10 25.4 20.4 10.4 5.4 4.5 10.4 mV mV mV mV mV mV Rev. E | Page 4 of 48 VISET > 1.65 V; VFLB > 1.12 V; VGATE = (SENSE+) + 3 V; IGATE = 0 μA; VSS ≥ 2 V VGATE = (SENSE+) + 3 V; IGATE = 0 μA; VSS ≥ 2 V VISET = 1.25 V; VFLB > 1.395 V VISET = 1.0 V; VFLB > 1.12 V VISET = 0.5 V; VFLB > 0.57 V VISET = 0.25 V; VFLB > 0.295 V VFLB = 0 V; VGATE = (SENSE+) + 3 V; IGATE = 0 μA; VSS ≥ 1 V VISET > 1.0 V; VFLB = 0.5 V; VGATE = (SENSE+) + 3 V; IGATE = 0 μA; VSS ≥ 1 V Data Sheet Parameter Circuit Breaker Offset, VCBOS SEVERE OVERCURRENT Voltage Threshold, VSENSEOC Short Glitch Filter Duration Long Glitch Filter Duration (Default) Response Time With Short Glitch Filter With Long Glitch Filter SOFT START (SS PIN) SS Pull-Up Current, ISS Default VSENSECL Limit SS Pull-Down Current TIMER PIN Timer Pull-Up Current (POR), ITIMERUPPOR Timer Pull-Up Current (OC Fault), ITIMERUPFLT Timer Pull-Down Current (Retry), ITIMERDNRT Timer Retry/OC Fault Current Ratio Timer Pull-Down Current (Hold), ITIMERDNHOLD Timer High Threshold, VTIMERH Timer Low Threshold, VTIMERL FOLDBACK (FLB PIN) FLB and PWRGD Threshold, VFLBTH Input Current, IFLB Hysteresis Current Internal Hysteresis Voltage Power-Good Glitch Filter, PWRGDGF Minimum Foldback Clamp VOUT PIN Input Current LATCH PIN Output Low Voltage, VOL_LATCH ADM1275 Min 0.6 Max 1.12 Unit mV Test Conditions/Comments Circuit breaker trip voltage, VCB = VSENSECL − VCBOS 40 9.5 90 50 13.0 200 mV mV ns 530 900 ns VISET = 1.0 V; VFLB > 1.1 V; VSS ≥ 2 V VISET = 0.25 V; VFLB > 1.1 V; VSS ≥ 2 V VISET > 1.65 V; VSENSE driven from 18 mV to 52 mV; selectable via PMBus VSENSE driven from 18 mV to 52 mV 180 645 370 1020 ns ns 2 mV overdrive maximum severe overcurrent threshold −8 1.8 µA mV µA VSS = 0 V When VSENSE reaches this level, ISS is enabled, ramping VSENSECL; VSS = 0 V VSS = 1 V Initial power-on reset; VTIMER = 0.5 V Overcurrent fault; 0.2 V ≤ VTIMER ≤ 1 V After fault when GATE is off; VTIMER = 0.5 V Defines the limits of the autoretry duty cycle Holds TIMER at 0 V when inactive; VTIMER = 0.5 V −12 0.5 −2 −57 1.7 −3 −60 2 3.33 100 −4 −63 2.3 3.8 µA µA µA % µA 0.98 0.18 1.0 0.2 1.02 0.22 V V 1.08 1.1 1.12 100 100 2.3 3.1 1 V nA nA μA mV μs mV 20 μA 0.4 1.5 100 1 V V nA µA 1.7 1.9 0.3 GPO1/ALERT1/CONV PIN (ADM1275-1 and ADM1275-2), ENABLE PIN (ADM1275-3) Output Low Voltage, VOL_GPO1 0.7 200 FLB rising; VISET = 1.0 V VFLB ≤ 1.0 V; VISET = 1.25 V VVCAP ≤ VFLB ≤ 20 V Voltage drop across the internal 1.3 kΩ resistor 50 mV overdrive Accuracies included in total sense voltage accuracies ADM1275-1 and ADM1275-3 VOUT = 20 V ADM1275-1 and ADM1275-3 ILATCH = 1 mA ILATCH = 5 mA VLATCH ≤ 2 V; LATCH output high-Z VLATCH = 20 V; LATCH output high-Z No internal pull-up present on these pins 0.4 1.5 100 1 Leakage Current Leakage Current −10 1.25 100 Leakage Current Input High Voltage, VIH Input Low Voltage, VIL GPO2/ALERT2 PIN Output Low Voltage, VOL_GPO2 Typ 0.88 0.8 V V nA µA V V 0.4 1.5 100 1 V V nA µA 1.1 Rev. E | Page 5 of 48 IGPO1 = 1 mA IGPO1 = 5 mA VGPO1 ≤ 2 V; GPO output high-Z VGPO1 = 20 V; GPO output high-Z ADM1275-1 and ADM1275-3 IGPO2 = 1 mA IGPO2 = 5 mA VGPO2 ≤ 2 V; GPO output high-Z VGPO2 = 20 V; GPO output high-Z ADM1275 Parameter PWRGD PIN Output Low Voltage, VOL_PWRGD VCC That Guarantees Valid Output Leakage Current Data Sheet Min Typ Max Unit Test Conditions/Comments 0.4 1.5 V V V nA µA IPWRGD = 1 mA IPWRGD = 5 mA ISINK = 100 μA; VOL_PWRGD = 0.4 V VPWRGD ≤ 2 V; PWRGD output high-Z VPWRGD = 20 V; PWRGD output high-Z 1 100 1 CURRENT AND VOLTAGE MONITORING Current Sense Absolute Error ±0.2 ±0.08 ±0.7 250 ±0.75 ±0.8 ±1.1 ±2.0 ±4.3 ±1.0 ±1.0 305 % % % % % % % % % % % % % % % % % % % % % µs 4000 4880 µs 0.8 V μA kΩ μA V μA ±1.0 ±0.08 ±0.2 ±1.0 ±0.08 ±0.2 ±2.8 ±0.09 ±0.2 ±0.7 ±0.04 ±0.15 SENSE+/VOUT Absolute Error ADC Conversion Time ADR PIN Address Set to 00 Input Current for Address 00 Address Set to 01 Address Set to 10 Address Set to 11 Input Current for Address 11 SERIAL BUS DIGITAL INPUTS (SDA, SCL) Input High Voltage, VIH Input Low Voltage, VIL Output Low Voltage, VOL Input Leakage, ILEAK-PIN Nominal Bus Voltage, VDD Capacitance for SDA, SCL Pin, CPIN Input Glitch Filter, tSP 0 −40 135 −1 2 −22 150 3 165 +1 10 1.1 0.8 0.4 +10 +5 5.5 −10 −5 2.7 5 0 50 V V V μA μA V pF ns Rev. E | Page 6 of 48 25 mV input range; 128 sample averaging (unless otherwise noted) VSENSE = 20 mV; VSENSE+ = 12 V; TA = 0°C to 65°C VSENSE = 20 mV; VSENSE+ = 12 V; TA = 25°C VSENSE = 20 mV VSENSE = 20 mV; TA = 25°C VSENSE = 20 mV; TA = 0°C to 65°C VSENSE = 20 mV; 16 sample averaging VSENSE = 20 mV; 16 sample averaging; TA = 25°C VSENSE = 20 mV; 16 sample averaging; TA = 0°C to 65°C VSENSE = 20 mV; 1 sample averaging VSENSE = 20 mV; 1 sample averaging; TA = 25°C VSENSE = 20 mV; 1 sample averaging; TA = 0°C to 65°C VSENSE = 25 mV; VSENSE+ = 12 V VSENSE = 25 mV; VSENSE+ = 12 V; TA = 25°C VSENSE = 25 mV; VSENSE+ = 12 V; TA = 0°C to 65°C VSENSE = 20 mV; VSENSE+ = 12 V VSENSE = 15 mV; VSENSE+ = 12 V VSENSE = 10 mV; VSENSE+ = 12 V VSENSE = 5 mV; VSENSE+ = 12 V VSENSE = 2.5 mV; VSENSE+ = 12 V Low input range; input voltage ≥ 3 V High input range; input voltage ≥ 10 V 1 sample of voltage and current; from command received to valid data in register 16 samples of voltage and current averaged; from command received to valid data in register Connect to GND VADR = 0 V to 0.8 V Resistor to GND No connect state; maximum leakage current allowed Connect to VCAP VADR = 2.0 V to VCAP; must not exceed the maximum allowable current draw from VCAP IOL = 4 mA Device is not powered 3 V to 5 V ± 10% Data Sheet ADM1275 SERIAL BUS TIMING CHARACTERISTICS tR = (VIL(MAX) – 0.15) to (VIH3V3 + 0.15) and tF = 0.9VDD to (VIL(MAX) – 0.15); where VIH3V3 = 2.1 V and VDD = 3.3 V. Table 2. Parameter fSCLK tBUF Description Clock frequency Bus free time tHD;STA tSU;STA tSU;STO tHD;DAT tSU;DAT tLOW tHIGH tR1 t F1 Start hold time Start setup time Stop setup time SDA hold time SDA setup time SCL low time SCL high time SCL, SDA rise time SCL, SDA fall time 1 Min Typ Max 400 1.3 4.7 0.6 0.6 0.6 300 100 1.3 0.6 20 20 900 300 300 Unit kHz μs μs μs μs μs ns ns μs μs ns ns Test Conditions/Comments Following the stop condition of a read transaction Following the stop condition of a write transaction The interface is specified to meet the I2C fast mode requirements. It is also capable of receiving signals complying with the I2C standard mode. The ADM1275 is guaranteed by design to accept edges as fast as 10 ns. Timing Diagram tLOW VIL tHD;DAT tHD;STA SDA tF tHIGH tSU;STA tSU;DAT tSU;STO VIH VIL P tBUF S S Figure 2. Serial Bus Timing Diagram Rev. E | Page 7 of 48 P 08931-002 SCL tR VIH ADM1275 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VCC Pin UV Pin OV Pin SS Pin TIMER Pin VCAP Pin ISET Pin LATCH Pin SCL Pin SDA Pin ADR Pin GPO1/ALERT1/CONV Pin, ENABLE Pin GPO2/ALERT2 Pin PWRGD Pin FLB Pin VOUT Pin GATE Pin (Internal Supply Only) 1 SENSE+ Pin SENSE− Pin VSENSE (VSENSE+ − VSENSE−) Continuous Current into Any Pin Storage Temperature Range Operating Temperature Range Lead Temperature, Soldering (10 sec) Junction Temperature 1 Rating −0.3 V to +25 V −0.3 V to +4 V −0.3 V to +4 V −0.3 V to VCAP + 0.3 V −0.3 V to VCAP + 0.3 V −0.3 V to +4 V −0.3 V to VCAP + 0.3 V −0.3 V to +25 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to VCAP + 0.3 V −0.3 V to +25 V −0.3 V to +25 V −0.3 V to +25 V −0.3 V to +25 V −0.3 V to +25 V −0.3 V to +36 V −0.3 V to +25 V −0.3 V to +25 V ±0.3 V ±10 mA −65°C to +125°C −40°C to +85°C 300°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL CHARACTERISTICS θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 16-lead QSOP (RQ-16) 20-lead QSOP (RQ-20) 20-lead LFCSP (CP-20-9) ESD CAUTION The GATE pin has internal clamping circuits to prevent the GATE pin voltage from exceeding the maximum ratings of a MOSFET with VGSMAX = 20 V and internal process limits. Applying a voltage source to this pin externally may cause irreversible damage. Rev. E | Page 8 of 48 θJA 150 126 30.4 Unit °C/W °C/W °C/W Data Sheet ADM1275 20 SENSE+ UV 2 19 SENSE– OV 3 18 GATE VCAP 4 17 GND ADM1275-1 ADR 9 GPO1/ALERT1/CONV 10 15 FLB 14 PWRGD PIN 1 INDICATOR ADM1275-1 TOP VIEW (Not to Scale) 15 GND 14 VOUT 13 FLB 12 PWRGD 11 SCL 13 SCL 12 SDA 11 GPO2/ALERT2 Figure 3. ADM1275-1 Pin Configuration, QSOP NOTES 1. SOLDER THE EXPOSED PADDLE TO THE BOARD TO IMPROVE THERMAL DISSIPATION. THE EXPOSED PADDLE CAN BE CONNECTED TO GROUND. 08931-109 TIMER 7 LATCH 8 16 VOUT 1 2 3 4 5 LATCH 6 ADR 7 GPO1/ALERT1/CONV 8 GPO2/ALERT2 9 SDA 10 SS 6 TOP VIEW (Not to Scale) OV VCAP ISET SS TIMER 08931-006 ISET 5 20 19 18 17 16 VCC 1 UV VCC SENSE+ SENSE– GATE PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. ADM1275-1 Pin Configuration, LFCSP Table 5. ADM1275-1 Pin Function Descriptions Pin No. QSOP LFCSP 1 19 Mnemonic VCC 2 20 UV 3 1 OV 4 2 VCAP 5 3 ISET 6 4 SS 7 5 TIMER 8 6 LATCH 9 7 ADR 10 8 GPO1/ALERT1/ CONV 11 9 GPO2/ALERT2 Description Positive Supply Input Pin. An undervoltage lockout (UVLO) circuit resets the device when a low supply voltage is detected. GATE is held low when the supply is below UVLO. During normal operation, this pin should remain greater than or equal to SENSE+ to ensure that specifications are adhered to. No sequencing is required. Undervoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect whether the supply is under the UV limit. Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect whether the supply is above the OV limit. Internal Regulated Supply. A capacitor with a value of 1 µF or greater should be placed on this pin to maintain good accuracy. This pin can be used as a reference to program the ISET pin voltage. This pin allows the current limit threshold to be programmed. The default limit is set when this pin is connected directly to VCAP. To achieve a user-defined sense voltage, the current limit can be adjusted using a resistor divider from VCAP. An external reference can also be used. Soft Start Pin. A capacitor is used on this pin to set the soft start ramp profile. The voltage on the SS pin controls the current sense voltage limit, which controls the inrush current profile. Timer Pin. An external capacitor, CTIMER, sets an initial timing cycle delay and a fault delay. The GATE pin is pulled low when the voltage on the TIMER pin exceeds the upper threshold. Signals that the device is latching off after an overcurrent fault. The device can be configured for automatic retry after latch-off by connecting this pin directly back to the UV pin. PMBus Address Pin. This pin can be tied to GND, tied to VCAP, left floating, or tied low through a resistor to set four different PMBus addresses (see the Device Addressing section). General-Purpose Digital Output (GPO1). Alert (ALERT1). This pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. Conversion (CONV). This pin can be used as an input signal to control when a power monitor ADC sampling cycle begins. At power-up, this pin defaults to a high impedance state. There is no internal pull-up on this pin. General-Purpose Digital Output (GPO2). Alert (ALERT2). This pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. At power-up, this pin indicates the FET health mode by default. There is no internal pull-up on this pin. Rev. E | Page 9 of 48 ADM1275 Data Sheet Pin No. QSOP LFCSP 12 10 13 11 14 12 Mnemonic SDA SCL PWRGD 15 13 FLB 16 14 VOUT 17 18 15 16 GND GATE 19 17 SENSE− 20 18 SENSE+ N/A EP EPAD Description Serial Data Input/Output Pin. Open-drain input/output. Requires an external resistive pull-up. Serial Clock Pin. Open-drain input. Requires an external resistive pull-up. Power-Good Signal. Used to indicate that the supply is within tolerance. This signal is based on the voltage present on the FLB pin. Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback is used to reduce the current limit when the source voltage drops. The foldback feature ensures that the power through the FET is not increased beyond the SOA limits. This pin is used to read back the output voltage using the internal ADC. A 1 kΩ resistor should be inserted in series between the source of a FET and the VOUT pin. Chip Ground Pin. Gate Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the FET drive controller, which uses a charge pump to provide a pull-up current to charge the FET gate pin. The FET drive controller regulates to a maximum load current by regulating the GATE pin. GATE is held low when the supply is below UVLO. Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot-swap operation of the ADM1275 controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−). This pin also connects to the FET drain pin. Positive Current Sense Input Pin. This pin connects to the main supply input. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot-swap operation of the ADM1275 controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−). This pin is also used to measure the supply input voltage using the ADC. Exposed Paddle on Underside of LFCSP. Solder the exposed paddle to the board to improve thermal dissipation. The exposed paddle can be connected to ground. Rev. E | Page 10 of 48 Data Sheet ADM1275 VCC 1 16 SENSE+ UV 2 15 SENSE– VCAP 3 ISET 4 ADM1275-2 13 GND SS 5 TOP VIEW (Not to Scale) 12 FLB TIMER 6 11 PWRGD ADR 7 10 SCL GPO1/ALERT1/CONV 8 9 SDA 08931-007 14 GATE Figure 5. ADM1275-2 Pin Configuration Table 6. ADM1275-2 Pin Function Descriptions Pin No. 1 Mnemonic VCC 2 UV 3 VCAP 4 ISET 5 SS 6 TIMER 7 ADR 8 GPO1/ALERT1/CONV 9 10 11 SDA SCL PWRGD 12 FLB 13 14 GND GATE 15 SENSE− 16 SENSE+ Description Positive Supply Input Pin. An undervoltage lockout (UVLO) circuit resets the device when a low supply voltage is detected. GATE is held low when the supply is below UVLO. During normal operation, this pin should remain greater than or equal to SENSE+ to ensure that specifications are adhered to. No sequencing is required. Undervoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect whether the supply is under the UV limit. Internal Regulated Supply. A capacitor with a value of 1 μF or greater should be placed on this pin to maintain good accuracy. This pin can be used as a reference to program the ISET pin voltage. This pin allows the current limit threshold to be programmed. The default limit is set when this pin is connected directly to VCAP. To achieve a user-defined sense voltage, the current limit can be adjusted using a resistor divider from VCAP. An external reference can also be used. Soft Start Pin. A capacitor is used on this pin to set the soft start ramp profile. The voltage on the SS pin controls the current sense voltage limit, which controls the inrush current profile. Timer Pin. An external capacitor, CTIMER, sets an initial timing cycle delay and a fault delay. The GATE pin is pulled low when the voltage on the TIMER pin exceeds the upper threshold. PMBus Address Pin. This pin can be tied to GND, tied to VCAP, left floating, or tied low through a resistor to set four different PMBus addresses (see the Device Addressing section). General-Purpose Digital Output (GPO1). Alert (ALERT1). This pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. Conversion (CONV). This pin can be used as an input signal to control when a power monitor ADC sampling cycle begins. At power-up, this pin defaults to a high impedance state. There is no internal pull-up on this pin. Serial Data Input/Output Pin. Open-drain input/output. Requires an external resistive pull-up. Serial Clock Pin. Open-drain input. Requires an external resistive pull-up. Power-Good Signal. Used to indicate that the supply is within tolerance. This signal is based on the voltage present on the FLB pin. Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback is used to reduce the current limit when the source voltage drops. The foldback feature ensures that the power through the FET is not increased beyond the SOA limits. Chip Ground Pin. Gate Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the FET drive controller, which uses a charge pump to provide a pull-up current to charge the FET gate pin. The FET drive controller regulates to a maximum load current by regulating the GATE pin. GATE is held low when the supply is below UVLO. Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot-swap operation of the ADM1275 controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−). This pin also connects to the FET drain pin. Positive Current Sense Input Pin. This pin connects to the main supply input. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot-swap operation of the ADM1275 controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−). This pin is also used to measure the supply input voltage using the ADC. Rev. E | Page 11 of 48 Data Sheet SENSE– OV 3 18 GATE VCAP 4 17 GND ISET 5 16 VOUT SS 6 15 FLB TIMER 7 14 PWRGD LATCH 8 13 SCL 9 12 SDA ENABLE 10 11 GPO2/ALERT2 ADR ADM1275-3 TOP VIEW (Not to Scale) OV VCAP ISET SS TIMER 1 2 3 4 5 PIN 1 INDICATOR ADM1275-3 TOP VIEW (Not to Scale) 15 GND 14 VOUT 13 FLB 12 PWRGD 11 SCL Figure 6. ADM1275-3 Pin Configuration, QSOP NOTES 1. SOLDER THE EXPOSED PADDLE TO THE BOARD TO IMPROVE THERMAL DISSIPATION. THE EXPOSED PADDLE CAN BE CONNECTED TO GROUND. 08931-110 SENSE+ 19 20 19 18 17 16 20 2 LATCH 6 ADR 7 ENABLE 8 GPO2/ALERT2 9 SDA 10 1 UV 08931-008 VCC UV VCC SENSE+ SENSE– GATE ADM1275 Figure 7. ADM1275-3 Pin Configuration, LFCSP Table 7. ADM1275-3 Pin Function Descriptions Pin No. QSOP LFCSP 1 19 Mnemonic VCC 2 20 UV 3 1 OV 4 2 VCAP 5 3 ISET 6 4 SS 7 5 TIMER 8 6 LATCH 9 7 ADR 10 8 ENABLE 11 9 GPO2/ALERT2 12 13 14 10 11 12 SDA SCL PWRGD 15 13 FLB Description Positive Supply Input Pin. An undervoltage lockout (UVLO) circuit resets the device when a low supply voltage is detected. GATE is held low when the supply is below UVLO. During normal operation, this pin should remain greater than or equal to SENSE+ to ensure that specifications are adhered to. No sequencing is required. Undervoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect whether the supply is under the UV limit. Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect whether the supply is above the OV limit. Internal Regulated Supply. A capacitor with a value of 1 μF or greater should be placed on this pin to maintain good accuracy. This pin can be used as a reference to program the ISET pin voltage. This pin allows the current limit threshold to be programmed. The default limit is set when this pin is connected directly to VCAP. To achieve a user-defined sense voltage, the current limit can be adjusted using a resistor divider from VCAP. An external reference can also be used. Soft Start Pin. A capacitor is used on this pin to set the soft start ramp profile. The voltage on the SS pin controls the current sense voltage limit, which controls the inrush current profile. Timer Pin. An external capacitor, CTIMER, sets an initial timing cycle delay and a fault delay. The GATE pin is pulled low when the voltage on the TIMER pin exceeds the upper threshold. Signals that the device is latching off after an overcurrent fault. The device can be configured for automatic retry after latch-off by connecting this pin directly back to the UV pin. PMBus Address Pin. This pin can be tied to GND, tied to VCAP, left floating, or tied low through a resistor to set four different PMBus addresses (see the Device Addressing section). Digital Logic Input. This input must be high to allow the ADM1275-3 hot-swap controller to begin a power-up sequence. If this pin is held low, the ADM1275-3 is prevented from powering up. There is no internal pull-up on this pin. General-Purpose Digital Output (GPO2). Alert (ALERT2). This pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. At power-up, this pin indicates the FET health mode by default. There is no internal pull-up on this pin. Serial Data Input/Output Pin. Open-drain input/output. Requires an external resistive pull-up. Serial Clock Pin. Open-drain input. Requires an external resistive pull-up. Power-Good Signal. Used to indicate that the supply is within tolerance. This signal is based on the voltage present on the FLB pin. Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback is used to reduce the current limit when the source voltage drops. The foldback feature ensures that the power through the FET is not increased beyond the SOA limits. Rev. E | Page 12 of 48 Data Sheet ADM1275 Pin No. QSOP LFCSP 16 14 Mnemonic VOUT 17 18 15 16 GND GATE 19 17 SENSE− 20 18 SENSE+ N/A EP EPAD Description This pin is used to read back the output voltage using the internal ADC. A 1 kΩ resistor should be inserted in series between the source of a FET and the VOUT pin. Chip Ground Pin. Gate Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the FET drive controller, which uses a charge pump to provide a pull-up current to charge the FET gate pin. The FET drive controller regulates to a maximum load current by regulating the GATE pin. GATE is held low when the supply is below UVLO. Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot-swap operation of the ADM1275 controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−). This pin also connects to the FET drain pin. Positive Current Sense Input Pin. This pin connects to the main supply input. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot-swap operation of the ADM1275 controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−). This pin is also used to measure the supply input voltage using the ADC. Exposed Paddle on Underside of LFCSP. Solder the exposed paddle to the board to improve thermal dissipation. The exposed paddle can be connected to ground. Rev. E | Page 13 of 48 ADM1275 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 5 VCC = 12V 14 12 4 IGATEDN_SLOW (mA) +25°C +85°C ICC (mA) 3 –40°C 2 10 8 6 4 1 2 4 6 8 10 12 14 16 18 20 VCC (V) 0 –40 08931-009 0 –20 0 20 40 60 08931-012 2 80 TEMPERATURE (°C) Figure 8. Supply Current (ICC) vs. Supply Voltage (VCC) Figure 11. Gate Pull-Down Current (IGATEDN_SLOW) vs. Temperature 15 5 14 13 VCC = 20V 12 VCC = 12V 11 VCC = 2.95V IGATEDN_SLOW (mA) ICC (mA) 4 3 2 10 9 8 7 6 5 4 3 1 2 20 0 40 60 80 TEMPERATURE (°C) 0 08931-010 –20 Figure 9. Supply Current (ICC) vs. Temperature 0 5 10 15 20 25 VGATE (V) 08931-013 1 0 –40 Figure 12. Gate Pull-Down Current (IGATEDN_SLOW) vs. Gate Voltage (VGATE) 0 14 –5 +25°C 10 –40°C –10 IGATEUP (µA) 8 +85°C 6 4 –20 –25 –30 2 –35 2 4 6 8 10 12 VCC (V) 14 16 18 20 08931-011 0 –15 Figure 10. Gate Pull-Down Current (IGATEDN_SLOW) vs. Supply Voltage (VCC) Rev. E | Page 14 of 48 –40 2 4 6 8 10 12 14 16 18 20 VCC (V) Figure 13. Gate Pull-Up Current (IGATEUP) vs. Supply Voltage (VCC) 08931-014 IGATEDN_SLOW (mA) 12 Data Sheet ADM1275 30 16 VCC = 12V 14 25 +85°C +25°C 12 VCC = 2.95V 15 10 ΔVGATE (V) IGATEUP (µA) 20 –40°C 8 6 10 4 5 5 10 15 20 25 VGATE (V) Figure 14. Gate Pull-Up Current (IGATEUP) vs. Gate Voltage (VGATE) 0 0 08931-016 0 4 6 8 10 12 14 16 18 20 VCC (V) Figure 17. Gate Drive Voltage (ΔVGATE) vs. Supply Voltage (VCC), 5 μA Load 16 VCC = 12V –5 14 –10 12 –15 ΔVGATE (V) –20 –25 –30 VCC = 12V 10 VCC = 20V 8 6 VCC = 2.95V 4 –35 2 –20 0 20 40 60 80 TEMPERATURE (°C) 0 –40 08931-015 –40 –40 0 20 40 60 80 TEMPERATURE (°C) Figure 15. Gate Pull-Up Current (IGATEUP) vs. Temperature Figure 18. Gate Drive Voltage (ΔVGATE) vs. Temperature, No Load 16 0 14 –2 +85°C –20 08931-019 IGATEUP (µA) 2 08931-018 2 0 +25°C VCC = 12V –4 12 ISS PULL-UP (µA) ΔVGATE (V) –6 10 –40°C 8 6 –8 –10 –12 –14 4 –16 2 2 4 6 8 10 12 VCC (V) 14 16 18 20 Figure 16. Gate Drive Voltage (ΔVGATE) vs. Supply Voltage (VCC), No Load Rev. E | Page 15 of 48 –20 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 19. Soft Start Pull-Up Current (ISS) vs. Temperature 08931-020 –18 08931-017 0 ADM1275 0 Data Sheet 1100 VCC = 12V HIGH THRESHOLD (VCC = 12V) 1000 –10 900 TIMER THRESHOLD (mV) ITIMERUPFLT (µA) –20 –30 –40 –50 –60 800 700 600 500 400 300 LOW THRESHOLD (VCC = 12V) 200 –70 40 60 80 TEMPERATURE (°C) 0 –40 20 40 60 80 80 80 Figure 23. Timer Thresholds vs. Temperature 1.3 VCC = 12V 1.2 1.1 FOLDBACK THRESHOLD (V) –2 ITIMERUPPOR (µA) 0 TEMPERATURE (°C) Figure 20. Timer Pull-Up Current, Overcurrent Fault (ITIMERUPFLT) vs. Temperature 0 –20 08931-024 20 08931-025 0 08931-021 –20 08931-026 100 –80 –40 –4 –6 –8 2.95V 12V 20V 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 –20 0 20 40 60 80 TEMPERATURE (°C) 0 –40 08931-022 –10 –40 FOLDBACK HYSTERESIS CURRENT (µA) 1.5 0 20 40 60 TEMPERATURE (°C) 80 08931-023 ITIMERDNRT (µA) 40 60 3.0 3.0 –20 20 Figure 24. Foldback Threshold vs. Temperature VCC = 12V 0 –40 0 TEMPERATURE (°C) Figure 21. Timer Pull-Up Current, Power-On Reset (ITIMERUPPOR) vs. Temperature 4.5 –20 2.5 2.0 2.95V 12V 20V 1.5 1.0 0.5 0 –40 –20 0 20 40 60 TEMPERATURE (°C) Figure 22. Timer Pull-Down Current, Retry (ITIMERDNRT) vs. Temperature Figure 25. Foldback Hysteresis Current vs. Temperature Rev. E | Page 16 of 48 Data Sheet 2.0 VCC = 12V 240 220 1.8 200 1.6 180 1.4 160 VCBOS (mV) 140 120 100 80 –40°C 0 20 40 60 0 08931-027 –20 80 TEMPERATURE (°C) 6 8 10 12 14 16 20 18 Figure 29. Circuit Breaker Offset (VCBOS) vs. Supply Voltage (VCC) 30 +85°C 325 300 275 4 VCC (V) Figure 26. Foldback Clamp vs. Temperature 400 375 350 2 08931-130 0.2 0 –40 VCC = 12V 25 +25°C –40°C VSENSECL (mV) 250 225 200 175 150 125 20 15 10 100 75 50 2 4 6 8 10 12 14 16 18 20 VCC (V) 0 –40 20 40 60 80 Figure 30. Hot-Swap Sense Voltage Current Limit (VSENSECL) vs. Temperature 400 30 375 350 +25°C 0 TEMPERATURE (°C) Figure 27. Severe Overcurrent Response Time vs. Supply Voltage (VCC), VISET = 0.25 V 325 –20 08931-131 5 08931-128 OC RESPONSE TIME (ns) 0.8 0.4 20 25 0 +85°C +25°C 1.0 0.6 60 40 TA = 25°C 25 +85°C 300 275 250 225 VSENSECL (mV) OC RESPONSE TIME (ns) 1.2 –40°C 200 175 150 125 20 15 10 100 75 5 25 0 2 4 6 8 10 12 VCC (V) 14 16 18 20 08931-129 50 Figure 28. Severe Overcurrent Response Time vs. Supply Voltage (VCC), VISET = 1 V Rev. E | Page 17 of 48 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VFLB (V) Figure 31. Hot-Swap Sense Voltage Current Limit (VSENSECL) vs. Foldback Voltage (VFLB) 08931-132 FOLDBACK CLAMP (mV) ADM1275 ADM1275 Data Sheet 50 20 45 40 15 VCC = 20V 30 ΔVGATE (V) 25 20 10 15 VCC = 2.95V 5 10 5 TA = 25°C 4 6 8 10 12 14 16 18 20 VCC (V) 0 Figure 32. Severe Overcurrent Voltage Threshold (VSENSEOC) vs. Supply Voltage (VCC), VISET = VVCAP –2 –4 –6 –8 –10 –12 –14 –16 –18 –20 –22 –24 –26 IGATEUP (µA) Figure 35. Gate Drive Voltage (ΔVGATE) vs. Gate Pull-Up Current (IGATEUP) 50 2.0 45 1.8 40 1.6 35 1.4 30 VOL_PWRGD (V) VSENSEOC (mV) 0 08931-135 2 08931-133 0 VCC = 12V 25 20 15 VCC = 2.95V 1.2 1.0 0.8 VCC = 12V 0.6 10 0.4 5 0.2 0 20 40 60 0 08931-144 VCC = 12V 0 –40 –20 80 TEMPERATURE (°C) 0 1 Figure 33. Severe Overcurrent Voltage Threshold (VSENSEOC) vs. Temperature, VISET = VVCAP 2 3 4 5 6 IOL (mA) 7 8 9 10 08931-136 VSENSEOC (mV) 35 Figure 36. PWRGD Pin, VOL_PWRGD vs. IOL 150 2.0 1.8 1.6 1.4 ISENSEx (µA) 100 VCC = 12V VOL (V) 1.2 1.0 VCC = 2.95V 0.8 50 0.6 0.4 1 2 3 4 5 6 7 VSENSEx (V) 8 9 10 11 12 Figure 34. SENSE+/SENSE− Input Current (ISENSEx) vs. Voltage (VSENSEx) 0 0 1 2 3 4 5 6 IOL (mA) 7 8 9 10 Figure 37. LATCH and GPOx/ALERTx Digital Outputs, VOL vs. IOL Rev. E | Page 18 of 48 08931-137 0 08931-134 0.2 0 Data Sheet ADM1275 3.0 3.0 2.5 10 DECODE 11 DECODE 2.0 VADR (V) 1.5 1.0 1.5 1.0 0.5 0.5 0 50 100 IVCAP (µA) 08931-138 +85°C +25°C –40°C 0 –25 1100 –15 –10 –5 0 5 IADR (µA) Figure 38. VCAP Voltage (VVCAP) vs. VCAP Load (IVCAP) 1200 –20 08931-141 VVCAP (V) 01 DECODE 2.5 2.0 0 00 DECODE Figure 41. ADR Pin Voltage (VADR) vs. Current (IADR) 10 VCC = 12V 9 1000 8 7 800 ACCURACY (%) 700 600 500 400 16× AVERAGING 1 100 –20 0 20 40 60 80 TEMPERATURE (°C) 0 08931-139 0 –40 Figure 39. UV Threshold (UVTH) vs. Temperature 900 800 700 600 500 400 300 200 0 20 40 60 TEMPERATURE (°C) 80 08931-140 100 –20 5 10 15 20 25 30 Figure 42. Worst-Case Current Sense Power Monitor Error vs. Current Sense Voltage (VSENSE), 0°C to 65°C, VSENSE+ = 12 V VCC = 12V 0 –40 128× AVERAGING 0 SENSE VOLTAGE (mV) 1000 OV THRESHOLD (mV) 4 2 200 1100 5 3 300 1200 6 08931-142 UV THRESHOLD (mV) 900 Figure 40. OV Threshold (OVTH) vs. Temperature Rev. E | Page 19 of 48 ADM1275 Data Sheet FUNCTIONAL BLOCK DIAGRAMS SENSE– VCC CHARGE PUMP LDO IOUT UV VCP + GATE DRIVE/ LOGIC 1.0V – OV – 1.0V + 1.0V TIMER VOUT CURRENT LIMIT ISET TIMEOUT LOGIC AND PMBus 12-BIT ADC PWRGD GPO1/ALERT1/CONV GPO2/ALERT2 LATCH SCL SDA ADR GND TIMER VCAP CHARGE PUMP IOUT 1.0V ISET + – REF SELECT 1.0V SS VCP GATE DRIVE/ LOGIC + – TIMER TIMER SENSE+ VOUT IOUT GATE TIMEOUT CURRENT LIMIT CURRENT LIMIT CONTROL CURRENT LIMIT FLB TIMEOUT 12-BIT ADC LOGIC AND PMBus PWRGD GPO1/ALERT1/CONV SCL SDA ADR GND TIMEOUT CURRENT LIMIT CURRENT LIMIT CONTROL TIMER FLB TIMEOUT 12-BIT ADC LOGIC AND PMBus PWRGD GPO2/ALERT2 LATCH SCL SDA ADR Figure 45. ADM1275-3 Functional Block Diagram ADM1275-2 LDO UV + – GATE VOUT GND 08931-004 VCC GATE DRIVE/ LOGIC REF SELECT SENSE+ VOUT IOUT SENSE– + – ×50 + – – + 1.0V VCP CURRENT LIMIT Figure 43. ADM1275-1 Functional Block Diagram SENSE+ IOUT SS FLB SENSE+ VOUT IOUT CHARGE PUMP LDO 1.0V CURRENT LIMIT TIMER OV CURRENT LIMIT CONTROL SS ADM1275-3 1.0V GATE TIMEOUT + – REF SELECT ISET VCAP ENABLE UV SENSE– + – ×50 VCC 08931-003 VCAP SENSE+ ADM1275-1 + – ×50 Figure 44. ADM1275-2 Functional Block Diagram Rev. E | Page 20 of 48 08931-005 SENSE+ Data Sheet ADM1275 THEORY OF OPERATION When circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. These transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system. RSENSE 2.95V TO 20V 22Ω SENSE– SENSE+ The ADM1275 is designed to control the powering on and off of a system in a controlled manner, allowing a board to be removed from, or inserted into, a live backplane by protecting it from excess currents. The ADM1275 can reside on the back-plane or on the removable board. VCC GATE ADM1275 08931-029 330nF GND POWERING THE ADM1275 A supply voltage from 2.95 V to 20 V is required to power the ADM1275 via the VCC pin. The VCC pin provides the majority of the bias current for the device; the remainder of the current needed to control the gate drive and best regulate the VGS voltage is supplied by the SENSE+ pin. To ensure correct operation of the ADM1275, the voltage on the VCC pin must be greater than or equal to the voltage on the SENSE+ pin. No sequencing of the VCC and SENSE+ rails is necessary. The SENSE+ pin can be as low as 2 V for normal operation provided that a voltage of at least 2.95 V is connected to the VCC pin. In most applications, both the VCC and SENSE+ pins are connected to the same voltage rail, but they are connected via separate traces to prevent accuracy loss in the sense voltage measurement (see Figure 46). RSENSE Figure 47. Transient Glitch Protection Using an RC Network CURRENT SENSE INPUTS The load current is monitored by measuring the voltage drop across an external sense resistor, RSENSE (see Figure 48). An internal current sense amplifier provides a gain of 50 to the voltage drop detected across RSENSE. The result is compared to an internal reference and used by the hot-swap control logic to detect when an overcurrent condition occurs. RSENSE SENSE+ SENSE– + Q1 ×50 VCC REFERENCE SENSE+ Q1 – + – OVERCURRENT GATE SENSE– ADM1275 GND ADM1275 Figure 48. Hot-Swap Current Sense Amplifier GATE GND The SENSE inputs may be connected to multiple parallel sense resistors, which can affect the voltage drop detected by the ADM1275. The current flowing through the sense resistors creates an offset, resulting in reduced accuracy. 08931-028 VCC 08931-030 2.95V TO 20V Q1 Figure 46. Powering the ADM1275 To protect the ADM1275 from unnecessary resets due to transient supply glitches, an external resistor and capacitor can be added, as shown in Figure 47. The values of these components should be chosen to provide a time constant that can filter any expected glitches. The resistor should, however, be small enough to keep voltage drops due to quiescent current to a minimum. A supply decoupling capacitor should not be placed on the rail before the FET unless a resistor is used to limit the inrush current. To achieve better accuracy, averaging resistors sum the current from the nodes of each sense resistor, as shown in Figure 49. The typical value for the averaging resistors is 10 Ω. The value of the averaging resistors is chosen to be much greater than the trace resistance between the sense resistors terminals and the inputs to the ADM1275. This greatly reduces the effects of differences in the trace resistances. Rev. E | Page 21 of 48 ADM1275 Data Sheet 2.95V TO 20V V Q1 SS SENSE+ FLB SENSE– 1V ISET CURRENT LIMIT REFERENCE BIAS CURRENT GATE 08931-031 VCC 0.2V Figure 49. Connection of Multiple Sense Resistors to the SENSE Pins 0.1V CURRENT LIMIT REFERENCE The current limit reference voltage determines the load current level to which the ADM1275 limits the current during an overcurrent event. This reference voltage is compared to the gained-up current sense voltage to determine whether the limit is reached. An internal current limit reference selector block continuously compares the ISET, soft start, and foldback voltages to determine which voltage is the lowest at any given time; the lowest voltage is used as the current limit reference. This ensures that the programmed current limit, ISET, is used in normal operation, and that the soft start and foldback features reduce the current limit when required during startup and/or fault conditions. SENSE+ ×50 OVERCURRENT The maximum current limit is partially determined by selecting a sense resistor to match the current sense voltage limit on the controller for the desired load current. However, as currents become larger, the sense resistor requirements become smaller, and resolution can be difficult to achieve when selecting the appropriate sense resistor. The ADM1275 provides an adjustable current sense voltage limit to handle this issue. The device allows the user to program the required current sense voltage limit from 5 mV to 25 mV. The default value of 20 mV is achieved by connecting the ISET pin directly to the VCAP pin. This configures the device to use an internal 1 V reference, which equates to 20 mV at the sense inputs (see Figure 52). SENSE– ISET SS FLB SETTING THE CURRENT LIMIT (ISET) VCAP GATE ADM1275 GND C1 08931-032 VCC Q1 Figure 51. Interaction of Soft Start, Foldback, and ISET Current Limits ISET Figure 50. Current Limit Reference Selection The foldback and soft start voltages vary during different modes of operation and are, therefore, clamped to minimum levels of 200 mV and 100 mV, respectively, to prevent zero current flow due to the current limit being too low. Figure 51 provides an example of how the soft start, foldback, and ISET voltages interact during startup as the ADM1275 is enhancing the FET and charging the load capacitances. Depending on how the soft start and foldback features are configured, the hand-off point can vary to ensure that the FET is operated correctly. ADM1275 GND 08931-034 RSENSE t 08931-033 GND Figure 52. Fixed 20 mV Current Sense Limit To program the sense voltage from 5 mV to 25 mV, a resistor divider is used to set a reference voltage on the ISET pin (see Figure 53). Rev. E | Page 22 of 48 Data Sheet ADM1275 SENSE+ SENSE– VCAP ADM1275 + – ×50 C1 R1 VCP ISET GATE DRIVE/ LOGIC ADM1275 REF SELECT ISET R2 VCAP + – GATE TIMEOUT CURRENT LIMIT 1.0V SS 10µA CURRENT LIMIT CONTROL FLB Figure 53. Adjustable 5 mV to 25 mV Current Sense Limit The VCAP pin has a 2.7 V (±1.5%) internal generated voltage that can be used to set a voltage at the ISET pin. Assuming that VISET equals the voltage on the ISET pin, the resistor divider should be sized to set the ISET voltage as follows: VISET = VSENSE × 50 where VSENSE is the current sense voltage limit. The VCAP rail can also be used as the pull-up supply for setting the I2C address. The VCAP pin should not be used for any other purpose. To guarantee accuracy specifications, care should be taken not to load the VCAP pin by more than 100 μA. SOFT START A capacitor connected to the SS pin determines the inrush current profile. Before the FET is enabled, the output voltage of the current limit reference selector block is clamped at 100 mV. This, in turn, holds the hot-swap sense voltage current limit, VSENSECL, at approximately 2 mV. When the FET is requested to turn on, the SS pin is held at ground until the voltage between the SENSE+ and SENSE− pins (VSENSE) reaches the circuit breaker voltage, VCB. VCB = VSENSECL − VCBOS where VCBOS is typically 0.88 mV, making VCB = 1.12 mV. When the load current generates a sense voltage equal to VCB, a 10 μA current source is enabled, which charges the SS capacitor and results in a linear ramping voltage on the SS pin. The current limit reference also ramps up accordingly, allowing the regulated load current to ramp up while avoiding sudden transients during power-up. The SS capacitor value is given by C SS  I SS  t VISET where: ISS = 10 μA. t = SS ramp time. For example, a 10 nF capacitor gives a soft start time of 1 ms. GND 08931-036 GND 08931-035 CURRENT LIMIT Figure 54. Soft Start FOLDBACK Foldback is a method to actively reduce the current limit as the voltage drop across the FET increases. It keeps the power across the FET to a minimum during power-up, overcurrent, or shortcircuit events. It also avoids the need to oversize the FET to accommodate worst-case conditions, resulting in board size and cost savings. The ADM1275 detects the voltage drop across the FET by looking at a resistor-divided version of the output voltage. It is assumed that the supply voltage remains constant and within tolerance. The device therefore relies on the principle that the drain of the FET is at the maximum expected supply voltage, and that the magnitude of the output voltage is relative to that of the VDS of the FET. Using a resistor divider from the output voltage to the FLB pin, a relationship from VOUT, and thus VDS, to VFLB can be derived. The resistor divider should be designed to output a voltage equal to ISET when VOUT falls below the desired level. This should be well below the working tolerance of the supply rail. As VOUT continues to drop, the current limit reference follows VFLB because it is now the lowest voltage input to the current limit reference selector block. This results in a reduction of the current limit and, therefore, the regulated load current. To prevent complete current flow restriction, a clamp becomes active when the current limit reference reaches 200 mV. The current limit cannot drop below this level. To suit the SOA characteristics of a particular FET, the required minimum current for this clamp varies from design to design. However, the current limit reference fixes this clamp at 200 mV, which equates to 4 mV at the sense resistor. Therefore, the main ISET voltage can be adjusted to align this clamp to the required percentage current reduction. For example, if ISET equals 0.8 V, the clamp can be set at 25% of the maximum current. Note that the SS voltage may intersect with the FLB (foldback) voltage, and the current limit reference may change to follow FLB (see Figure 51). This change has minimal impact on startup because the output voltage rises at a similar rate to the SS voltage. Rev. E | Page 23 of 48 ADM1275 Data Sheet TIMER However, if the overcurrent condition is continuous and the sense voltage remains above the circuit breaker trip voltage, the 60 µA pull-up remains active and the FET remains in regulation. The TIMER pin handles several timing functions with an external capacitor, CTIMER. The two comparator thresholds are VTIMERL (0.2 V) and VTIMERH (1 V). There are four timing current sources: a 3 μA pull-up, a 60 μA pull-up, a 2 μA pull-down, and a 100 μA pull-down. This allows the TIMER pin to reach VTIMERH and initiate the GATE shutdown. On the ADM1275-1 and ADM1275-3, the LATCH pin is pulled low immediately. These current and voltage levels, together with the value of CTIMER chosen by the user, determine the initial timing cycle time, the fault current limit time, and the hot-swap retry duty cycle. The TIMER capacitor value is determined using the following equation: In latch-off mode, the TIMER pin is switched to the 2 µA pull-down when it reaches the VTIMERH threshold. The LATCH pin (ADM1275-1 and ADM1275-3) remains low. While the TIMER pin is being pulled down, the hot-swap controller is kept off and cannot be turned back on. CTIMER = (tON × 60 μA)/VTIMERH where tON is the time that the FET is allowed to spend in regulation at the set current limit. The choice of FET is based on matching this time with the SOA requirements of the FET. Foldback can be used to simplify the selection. When VCC is connected to the backplane supply, the internal supply of the ADM1275 must be charged up. In a very short time, the internal supply is fully charged up and, because the undervoltage lockout (UVLO) voltage is exceeded at VCC, the device comes out of reset. During this first short reset period, the GATE and TIMER pins are both held low. The ADM1275 then goes through an initial timing cycle. The TIMER pin is pulled high with 3 μA. When the TIMER reaches the VTIMERH threshold (1.0 V), the first portion of the initial timing cycle is complete. The 100 μA current source then pulls down the TIMER pin until it reaches VTIMERL (0.2 V). The initial timing cycle duration is related to CTIMER by the following equation: t INITIAL = VTIMERH × CTIMER 3 µA + (VTIMERH − VTIMERL ) × CTIMER 100 µA For example, a 100 nF capacitor results in a delay of approximately 34 ms. If the UV and OV inputs indicate that the supply is within the defined window of operation when the initial timing cycle terminates, the device is ready to start a hot-swap operation. When the voltage across the sense resistor reaches the circuit breaker trip voltage, VCB, the 60 µA timer pull-up current is activated, and the gate begins to regulate the current at the current limit. This initiates a ramp-up on the TIMER pin. If the sense voltage falls below this circuit breaker trip voltage before the TIMER pin reaches VTIMERH, the 60 µA pull-up is disabled and the 2 µA pull-down is enabled. The circuit breaker trip voltage is not the same as the hot-swap sense voltage current limit. There is a small circuit breaker offset, VCBOS, which means that the timer actually starts a short time before the current reaches the defined current limit. When the voltage on the TIMER pin goes below the VTIMERL threshold, the hot-swap controller can be reenabled by toggling the UV pin or by using the PMBus OPERATION command to toggle the ON bit from on to off and then on again. HOT-SWAP RETRY DUTY CYCLE The ADM1275-1 and ADM1275-3 turn off the FET after an overcurrent fault and then use the capacitor on the TIMER pin to provide a delay before automatically retrying the hot-swap operation. To configure the ADM1275-1 and ADM1275-3 for autoretry mode, the LATCH pin is tied to the UV pin or to the ENABLE pin (ADM1275-3 only). Note that a pull-up is required on the LATCH pin. When an overcurrent fault occurs, the TIMER capacitor is charged with a 60 μA pull-up current. When the TIMER pin reaches VTIMERH, the GATE pin is pulled down. When the LATCH pin is tied to the UV pin or the ENABLE pin for autoretry mode, the TIMER pin is pulled down with a 2 μA current sink. When the TIMER pin reaches VTIMERL (0.2 V), it automatically restarts the hot-swap operation. The duty cycle of this automatic retry cycle is set by the ratio of 2 µA/60 µA, which approximates to being on about 4% of the time. The value of the timer capacitor determines the on time of this cycle, which is calculated as follows: tON = VTIMERH × (CTIMER/60 μA) tOFF = (VTIMERH − VTIMERL) × (CTIMER/2 μA) A 100 nF TIMER capacitor gives an on time of 1.67 ms and an off time of 40 ms. The device retries indefinitely in this manner and can be disabled manually by holding the UV or ENABLE pin low or by disconnecting the LATCH pin. To prevent thermal stress, an RC network can be used to extend the retry time to any desired level. FET GATE DRIVE CLAMPS The charge pump used on the GATE pin is capable of driving the pin to VCC + (2 × VCC), but it is clamped to less than 14 V above the SENSE pins and less than 31 V. These clamps ensure that the maximum VGS rating of the FET is not exceeded. Rev. E | Page 24 of 48 Data Sheet ADM1275 FAST RESPONSE TO SEVERE OVERCURRENT The ADM1275 features a separate high bandwidth current sense amplifier that is used to detect a severe overcurrent that is indicative of a short-circuit condition. A fast response time allows the ADM1275 to handle events of this type that could otherwise cause catastrophic damage if not detected and acted on very quickly. The fast response circuit ensures that the ADM1275 can detect an overcurrent event at approximately 200% to 250% of the normal current limit (ISET) and can respond to and control the current within 1 μs, in most cases. If an enable function is required on the ADM1275-1 or ADM1275-2, which do not have a dedicated ENABLE pin, a similar function can be achieved using the UV pin directly. Alternatively, if the UV divider function is still required, the configuration shown in Figure 56 can be used. VIN SYSTEM CONTROL EN D1 R2 Figure 55 illustrates the voltage monitoring input connections. An external resistor network divides the supply voltage for monitoring. An undervoltage event is detected when the voltage connected to the UV pin falls below 1 V, and the gate is shut down using the 10 mA pull-down device. Similarly, when an overvoltage event occurs and the voltage on the OV pin exceeds 1 V, the gate is shut down using the 10 mA pull-down device. OV + 1V – ×50 ADM1275 – IOUT GATE DRIVE – 1V + GND Diode D1 prevents the external driver pull-up from affecting the UV threshold. Select Diode D1 using the following criteria: (VF × D1) + (VOL × EN) 2 mV. VGATE < ~1 V, that is, less than the FET gate threshold. POWER MONITOR The ADM1275 features an integrated ADC that is used to accurately measure the current sense voltage and either the input or output voltage. Because the ADM1275-1 and ADM1275-3 have a VOUT pin, the power monitor can be configured using the PMBus to measure either the input or the output voltage. The ADM1275-2 does not have a VOUT pin, so only the input voltage at the SENSE+ pin can be measured. The ADM1275 can report the measured current and either the input or output voltage. The PEAK_IOUT, PEAK_VIN, and PEAK_VOUT commands can be used to read the highest peak current or voltage since the value was last cleared. An averaging function is provided for voltage and current that allows a number of samples to be averaged by the ADM1275. This function reduces the need for postprocessing of sampled data by the host processor. The number of samples that can be averaged is 2N, where N is in the range of 0 to 7. The power monitor current sense amplifier is bipolar and can measure both positive and negative currents. The power monitor amplifier has an input range of ±25 mV. Two input voltage ranges are available and can be selected using the PMBus interface: 0 V to 6 V (low input range) and 0 V to 20 V (high input range). The two basic modes of operation for the power monitor are single shot and continuous. In single-shot mode, the power monitor samples the input voltage and current a number of times, depending on the averaging value selected by the user. The ADM1275 returns a single value corresponding to the average voltage and current measured. When configured for continuous mode, the power monitor continuously samples voltage and current, making the most recent sample available to be read. The single-shot mode can be triggered in a number of ways. The simplest is by selecting the single-shot mode using the PMON_CONFIG command and writing the CONVERT bit using the PMON_CONTROL command. The CONVERT bit can also be written as part of a PMBus group command. Using a group command allows multiple devices to be written to as part of the same I2C bus transaction, with all devices executing the command when the stop condition appears on the bus. In this way, several devices can be triggered to sample at the same time. When the GPO1/ALERT1/CONV pin is set to the convert (CONV) mode, an external hardware signal can be used to trigger the single-shot sampling of one or more parts at the same time. Rev. E | Page 26 of 48 Data Sheet ADM1275 PMBus INTERFACE The I2C bus is a common, simple serial bus used by many devices to communicate. It defines the electrical specifications, the bus timing, the physical layer, and some basic protocol rules. SMBus is based on I2C and aims to provide a more robust and fault-tolerant bus. Functions such as bus timeout and packet error checking are added to help achieve this robustness, along with more specific definitions of the bus messages used to read and write data to devices on the bus. PMBus is layered on top of SMBus and, in turn, on I2C. Using the SMBus defined bus messages, PMBus defines a set of standard commands that can be used to control a device that is part of a power chain. The ADM1275 command set is based upon the PMBus™ Power System Management Protocol Specification, Part I and Part II, Revision 1.1. This version of the standard is intended to provide a common set of commands for communicating with dc-to-dc type devices. However, many of the standard PMBus commands can be mapped directly to the functions of a hot-swap controller. Part I and Part II of the PMBus standard describe the basic commands and how they can be used in a typical PMBus setup. The following sections describe how the PMBus standard and the ADM1275 specific commands are used. DEVICE ADDRESSING The ADM1275 is available in three models: the ADM1275-1, the ADM1275-2, and the ADM1275-3. The PMBus address is 7 bits in size. The upper 5 bits (MSBs) of the address word are fixed and are different for each model, as follows: • • • ADM1275-1: Base address is 00100xx (0x10) ADM1275-2: Base address is 00110xx (0x18) ADM1275-3: Base address is 01000xx (0x20) The ADM1275-1, ADM1275-2, and ADM1275-3 all have a single ADR pin that is used to select one of four possible addresses for a given model. The ADR pin connection selects the lowest two bits (LSBs) of the 7-bit address word (see Table 8). Table 8. PMBus Addresses and ADR Pin Connection Value of Address LSBs 00 01 10 11 ADR Pin Connection Connect to GND 150 kΩ resistor to GND No connection (floating) Connect to VCAP SMBus PROTOCOL USAGE All I2C transactions on the ADM1275 are done using SMBus defined bus protocols. The following SMBus protocols are implemented by the ADM1275: • • • • • • • Send byte Receive byte Write byte Read byte Write word Read word Block read PACKET ERROR CHECKING The ADM1275 PMBus interface supports the use of the packet error checking (PEC) byte that is defined in the SMBus standard. The PEC byte is transmitted by the ADM1275 during a read transaction or sent by the bus host to the ADM1275 during a write transaction. The ADM1275 supports the use of PEC with all the SMBus protocols that it implements. The use of the PEC byte is optional. The bus host can decide whether to use the PEC byte with the ADM1275 on a messageby-message basis. There is no need to enable or disable PEC in the ADM1275. The PEC byte is used by the bus host or the ADM1275 to detect errors during a bus transaction, depending on whether the transaction is a read or a write. If the host determines that the PEC byte read during a read transaction is incorrect, it can decide to repeat the read if necessary. If the ADM1275 determines that the PEC byte sent during a write transaction is incorrect, it ignores the command (does not execute it) and sets a status flag. Within a group command, the host can choose to send or not send a PEC byte as part of the message to the ADM1275. PARTIAL TRANSACTIONS ON I2C BUS In the event of a specific sequence of events occurring on the I2C bus, it is possible for the I2C interface on the device to go into a state where it fails to ACK the next I2C transaction directed to it. There are two ways that this behavior can be triggered: • • A partial I2C transaction consisting of a start condition, followed by a single SCL clock pulse and stop condition. If the I2C bus master does not follow the 300 ns SDA data hold time when signaling the ACK/NACK bit at the end of a transaction. The device sees this as a single SCL clock partial transaction. In the event that the device NACKs a transaction, then the I2C interface on the device can be reset by sending a series of up to 16 SCL clock pulses, or performing a dummy transaction to another I2C address on the bus. Rev. E | Page 27 of 48 ADM1275 Data Sheet R = read bit W = write bit A = acknowledge bit (0) A = acknowledge bit (1) “A” represents the ACK (acknowledge) bit. The ACK bit is typically active low (Logic 0) if the transmitted byte is successfully received by a device. However, when the receiving device is the bus master, the acknowledge bit for the last byte read is a Logic 1, indicated by A. SMBus MESSAGE FORMATS Figure 58 to Figure 65 show all the SMBus protocols supported by the ADM1275, along with the PEC variant. In these figures, unshaded cells indicate that the bus host is actively driving the bus; shaded cells indicate that the ADM1275 is driving the bus. Figure 58 to Figure 65 use the following abbreviations: S = start condition Sr = repeated start condition P = stop condition S SLAVE ADDRESS W A DATA BYTE A SLAVE ADDRESS W A DATA BYTE A P PEC A P PEC A P 08931-040 S MASTER TO SLAVE SLAVE TO MASTER Figure 58. Send Byte and Send Byte with PEC SLAVE ADDRESS R A DATA BYTE A S SLAVE ADDRESS R A DATA BYTE A P 08931-041 S MASTER TO SLAVE SLAVE TO MASTER Figure 59. Receive Byte and Receive Byte with PEC SLAVE ADDRESS W A COMMAND CODE A DATA BYTE A S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE A P PEC A P 08931-042 S MASTER TO SLAVE SLAVE TO MASTER Figure 60. Write Byte and Write Byte with PEC SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE A S SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE A P PEC A P 08931-043 S MASTER TO SLAVE SLAVE TO MASTER Figure 61. Read Byte and Read Byte with PEC SLAVE ADDRESS W A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A P PEC A MASTER TO SLAVE SLAVE TO MASTER Figure 62. Write Word and Write Word with PEC SLAVE ADDRESS DATA BYTE HIGH S W A SLAVE ADDRESS DATA BYTE HIGH COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE LOW A A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE LOW A P W A A PEC A P 08931-045 S P 08931-044 S MASTER TO SLAVE SLAVE TO MASTER Figure 63. Read Word and Read Word with PEC Rev. E | Page 28 of 48 Data Sheet S ADM1275 SLAVE ADDRESS W DATA BYTE 1 S A DATA BYTE 2 A SLAVE ADDRESS W DATA BYTE 1 A A SLAVE ADDRESS DATA BYTE N A Sr COMMAND CODE DATA BYTE 2 A R DATA BYTE N BYTE COUNT = N A A BYTE COUNT = N A P A SLAVE ADDRESS A R A PEC A P 08931-046 A A Sr COMMAND CODE MASTER TO SLAVE SLAVE TO MASTER Figure 64. Block Read and Block Read with PEC ONE OR MORE DATA BYTES S DEVICE 1 ADDRESS W A COMMAND CODE 1 A LOW DATA BYTE A HIGH DATA BYTE A ONE OR MORE DATA BYTES Sr DEVICE 2 ADDRESS W A COMMAND CODE 2 A LOW DATA BYTE Sr DEVICE N ADDRESS W A COMMAND CODE N A LOW DATA BYTE A HIGH DATA BYTE A ONE OR MORE DATA BYTES HIGH DATA BYTE A P 08931-047 A MASTER TO SLAVE SLAVE TO MASTER ONE OR MORE DATA BYTES S DEVICE 1 ADDRESS W A COMMAND CODE 1 A LOW DATA BYTE A HIGH DATA BYTE A PEC 1 A A PEC 2 A A PEC N A ONE OR MORE DATA BYTES Sr DEVICE 2 ADDRESS W A COMMAND CODE 2 A LOW DATA BYTE Sr DEVICE N ADDRESS W A COMMAND CODE N A LOW DATA BYTE A HIGH DATA BYTE ONE OR MORE DATA BYTES HIGH DATA BYTE P 08931-048 A MASTER TO SLAVE SLAVE TO MASTER Figure 65. Group Command and Group Command with PEC GROUP COMMANDS The PMBus standard defines what are known as group commands. Group commands are single bus transactions that send commands or data to more than one device at the same time. Each device is addressed separately, using its own address; there is no special group command address. A group command transaction can contain only write commands that send data to a device. It is not possible to use a group command to read data from devices. From an I2C protocol point of view, a normal write command consists of the following: • • • • I2C start condition Slave address bits and a write bit (followed by ACK from the slave device) One or more data bytes (each of which is followed by ACK from the slave device) I2C stop condition to end the transaction A group command differs from a nongroup command in that after the data is written to one slave device, a repeated start condition is put on the bus followed by the address of the next slave device and data. This continues until all the devices have been written to, at which point the stop condition is put on the bus by the master device. The format of a group command and a group command with PEC is shown in Figure 65. Each device that is written to as part of the group command does not immediately execute the command written. The device must wait until the stop condition appears on the bus. At that point, all devices execute their commands at the same time. Using a group command, it is possible, for example, to turn multiple PMBus devices on or off at the same time. In the case of the ADM1275, it is also possible to issue a power monitor command that initiates a conversion, causing multiple ADM1275 devices to sample together at the same time. This is analogous to connecting the GPO1/ALERT1/CONV pins together and configuring the pin in the convert (CONV) mode to drive the power monitor sampling. Rev. E | Page 29 of 48 ADM1275 Data Sheet HOT-SWAP CONTROL COMMANDS POWER_CYCLE Command OPERATION Command The POWER_CYCLE command can be used to request that the ADM1275 be turned off for ~4 seconds and then back on. This command can be useful if the processor that controls the ADM1275 is also powered off when the ADM1275 is turned off. This command allows the processor to request that the ADM1275 turn off and back on again as part of a single command. The GATE pin that drives the FET is controlled by a dedicated hot-swap state machine. The UV and OV input pins, along with the TIMER and SS pins and the current sense, all feed into the state machine and control when and how strongly the gate is turned off. It is also possible to control the hot-swap GATE output using commands over the PMBus interface. The OPERATION command can be used to request the hot-swap output to turn on. However, if the UV pin indicates that the input supply is less than required, the hot-swap output is not turned on, even if the OPERATION command indicates that the output should be enabled. If the OPERATION command is used to disable the hot-swap output, the GATE pin is held low, even if all hot-swap state machine control inputs indicate that it can be enabled. The default state of the OPERATION command ON bit is 1, so the hot-swap output is always enabled when the ADM1275 comes out of UVLO. If the ON bit is never changed, the UV input (or the ENABLE input on the ADM1275-3) is the hotswap master on/off control signal. ADM1275 INFORMATION COMMANDS CAPABILITY Command The CAPABILITY command can be used by host processors to determine the I2C bus features supported by the ADM1275. The features reported are the maximum bus speed and whether the device supports the packet error checking (PEC) byte and the SMBAlert reporting function. PMBUS_REVISION Command The PMBUS_REVISION command reports the version of Part I and Part II of the PMBus standard. MFR_ID, MFR_MODEL, and MFR_REVISION Commands The MFR_ID, MFR_MODEL, and MFR_REVISION commands return ASCII strings that can be used to facilitate detection and identification of the ADM1275 on the bus. By default at power-up, the OPERATION command is disabled and must be enabled using the DEVICE_CONFIG command. This prevents inadvertent shutdowns of the hot-swap controller by software. These commands are read using the SMBus block read message type. This message type requires that the ADM1275 return a byte count corresponding to the length of the string data that is to be read back. If the ON bit is set to 0 while the UV signal is high, the hot-swap output is turned off. If the UV signal is low or if the OV signal is high, the hot-swap output will already be off and the status of the ON bit has no effect. STATUS COMMANDS If the ON bit is set to 1, the hot-swap output is requested to turn on. If the UV signal is low or if the OV signal is high, setting the ON bit to 1 has no effect, and the hot-swap output remains off. It is possible to determine at any time whether the hot-swap output is enabled using the STATUS_BYTE or the STATUS_WORD command (see the Status Commands section). The OPERATION command can also be used to clear any latched faults in the status registers. To clear latched faults, set the ON bit to 0 and then reset it to 1. DEVICE_CONFIG Command The DEVICE_CONFIG command is used to configure certain settings within the ADM1275, for example, to enable or disable foldback in the hot-swap controller or to modify the duration of the severe overcurrent glitch filter. This command is also used to configure the polarity of the second IOUT current warnings. At power-up, the OPERATION command is disabled and the ADM1275 responds with a NACK if the OPERATION command is received. To allow use of the OPERATION command, the OPERATION_CMD_EN bit must be set using the DEVICE_CONFIG command. The ADM1275 provides a number of status bits that are used to report faults and warnings from the hot-swap controller and the power monitor. These status bits are located in six different registers that are arranged in a hierarchy. The STATUS_BYTE and STATUS_WORD commands provide 8 bits and 16 bits of high level information, respectively. The STATUS_BYTE and STATUS_WORD commands contain the most important status bits, as well as pointer bits that indicate whether any of the four other status registers need to be read for more detailed status information. In the ADM1275, a particular distinction is made between faults and warnings. A fault is always generated by the hot-swap controller and is defined by hardware component values. Three events can generate a fault: • • • Overcurrent condition that causes the hot-swap timer to time out Overvoltage condition on the OV pin Undervoltage condition on the UV pin When a fault occurs, the hot-swap controller always takes some action, usually to turn off the GATE pin, which is driving the FET. A fault can also generate an SMBAlert on one or both of the GPOx/ALERTx pins. Rev. E | Page 30 of 48 Data Sheet ADM1275 All warnings in the ADM1275 are generated by the power monitor sampling voltage and current and then comparing these measurements to the threshold values set by the various limit commands. A warning has no effect on the hot-swap controller, but it may generate an SMBAlert on one or both of the GPOx/ALERTx output pins. When a status bit is set, it always means that the status condition— fault or warning—is active or was active at some point in the past. When a fault or warning bit is set, it is latched until it is explicitly cleared using either the OPERATION or the CLEAR_FAULTS command. Some other status bits are live, that is, they always reflect a status condition and are never latched. STATUS_BYTE and STATUS_WORD Commands The STATUS_BYTE and STATUS_WORD commands can be used to obtain a snapshot of the overall part status. These commands indicate whether it is necessary to read more detailed information using the other status commands. The low byte of the word returned by the STATUS_WORD command is the same byte returned by the STATUS_BYTE command. The high byte of the word returned by the STATUS_WORD command provides a number of bits that can be used to determine which of the other status commands needs to be issued to obtain all active status bits. STATUS_INPUT Command The STATUS_INPUT command returns a number of bits relating to voltage faults and warnings on the input supply. GPO AND ALERT PIN SETUP COMMANDS Two multipurpose pins are provided on the ADM1275-1: GPO1/ ALERT1/CONV and GPO2/ALERT2. One multi-purpose pin is provided on the ADM1275-2 (GPO1/ALERT1/CONV), and on the ADM1275-3 (GPO2/ALERT2). The GPO1/ALERT1/CONV and GPO2/ALERT2 pins have two output modes of operation. These pins can be configured independently over the PMBus as general-purpose digital outputs. They can both be configured to generate an SMBAlert when one or more fault/warning status bits become active in the PMBus status registers. For an example of how to configure these pins to generate an SMBAlert and how to respond and clear the condition, see the Example Use of SMBUS Alert Response Address section. The GPO1/ALERT1/CONV pin can also be configured as an input (CONV) to drive the power monitor in single-shot run mode and to control when a power monitor ADC sampling cycle begins. This function can be used to synchronize sampling across multiple ADM1275 devices, if required. ALERT1_CONFIG and ALERT2_CONFIG Commands Using combinations of bit masks, the ALERT1_CONFIG and ALERT2_CONFIG commands can be used to select the status bits that, when set, generate an SMBAlert signal to a processor. They can also be used to set a GPO mode on the pin, so that it is under software control. If this mode is set, the SMBAlert masking bits are ignored. On the ADM1275-1, one of the inputs can also be configured as a hardware-based convert control signal. If this mode is set, the GPO and SMBAlert masking bits are ignored. STATUS_VOUT Command The STATUS_VOUT command returns a number of bits relating to voltage faults and warnings on the output supply. This command is not available on the ADM1275-2. POWER MONITOR COMMANDS The ADM1275 provides a high accuracy, 12-bit current and voltage power monitor. The power monitor can be configured in a number of different modes of operation and can run in either continuous mode or single-shot mode with a number of different sample averaging options. STATUS_IOUT Command The STATUS_IOUT command returns a number of bits relating to current faults and warnings on the output supply. STATUS_MFR_SPECIFIC Command The STATUS_MFR_SPECIFIC command is a standard PMBus command, but the contents of the byte returned is specific to the ADM1275. CLEAR_FAULTS Command The CLEAR_FAULTS command is used to clear fault and warnings bits when they are set. Fault and warnings bits are latched when they are set. In this way, a host can read the bits any time after the fault or warning condition occurs and determine which problem actually occurred. If the CLEAR_FAULTS command is issued and the fault or warning condition is no longer active, the status bit is cleared. If the condition is still active—for example, if an input voltage is below the undervoltage threshold of the UV pin—the CLEAR_FAULTS command attempts to clear the status bit, but that status bit is immediately set again. PMON_CONFIG Command The power monitor can run in a number of different modes with different input voltage range settings. The PMON_CONFIG command is used to set up the power monitor. The settings that can be configured are as follows: • • • • Single-shot or continuous sampling VIN or VOUT sampling (no VOUT sampling for the ADM1275-2) Voltage input range Current and voltage sample averaging Modifying the power monitor settings while the power monitor is sampling is not supported. The power monitor must be stopped before any of these settings are changed to ensure correct operation and avoid any potential spurious data and status alerts being generated. Rev. E | Page 31 of 48 ADM1275 Data Sheet PMON_CONTROL Command on the output voltage, as measured at the VOUT pin on the ADM1275-1 and ADM1275-3. Power monitor sampling can be initiated via software or via hardware, as follows: • • IOUT_OC_WARN_LIMIT Command PMON_CONTROL command. This command can be used with single-shot or continuous mode. GPO1/ALERT1/CONV pin. If this pin is configured for convert mode, an external hardware signal can be used to take this pin high, triggering the single-shot sampling of one or more parts together. READ_VIN, READ_VOUT, and READ_IOUT Commands The ADM1275 power monitor measures the voltage developed across the sense resistor to provide a current measurement. On the ADM1275-1 and ADM1275-3, the user can choose to measure either the input voltage from the SENSE+ pin or the output voltage present on the VOUT pin. The ADM1275-2 can measure only the input voltage from the SENSE+ pin. PEAK_IOUT, PEAK_VIN, and PEAK_VOUT Commands In addition to the standard PMBus commands for reading voltage and current, the ADM1275 provides commands that can report the maximum peak voltage or current sample since the peak value was last cleared. The peak values are updated only after the power monitor has sampled and averaged the current and voltage measurements. Individual peak values are cleared by writing a 0 value with the corresponding command. WARNING LIMIT SETUP COMMANDS The ADM1275 power monitor can monitor a number of different warning conditions simultaneously and report any current or voltage values that exceed the user-defined thresholds using the status commands. All comparisons performed by the power monitor require the measured voltage or current value to be strictly greater or less than the threshold value. At power-up, all threshold limits are set to either minimum scale (for undervoltage or undercurrent conditions) or to maximum scale (for overvoltage or overcurrent conditions). This effectively disables the generation of any status warnings by default; warning bits are not set in the status registers until the user explicitly sets the threshold values. VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT Commands The VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT commands are used to set the OV and UV thresholds on the input voltage, as measured at the SENSE+ pin. VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT Commands The VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_ LIMIT commands are used to set the OV and UV thresholds The IOUT_OC_WARN_LIMIT command is used to set the OC threshold for the current flowing through the sense resistor. IOUT_WARN2_LIMIT Command The IOUT_WARN2_LIMIT command provides a second current warning threshold that can be programmed. The polarity of this warning can be set to overcurrent or undercurrent using the DEVICE_CONFIG command. PMBus DIRECT FORMAT CONVERSION The ADM1275 uses the PMBus direct format to represent realworld quantities such as voltage and current values. A direct format number takes the form of a 2-byte, twos complement, binary integer value. It is possible to convert between direct format value and realworld quantities using the following equations. Equation 1 converts from real-world quantities to PMBus direct values, and Equation 2 converts PMBus direct format values to realworld values. Y = (mX + b) × 10R (1) X = 1/m × (Y × 10 − b) (2) −R where: Y is the value in PMBus direct format. X is the real-world value. m is the slope coefficient, a 2-byte, twos complement integer. b is the offset, a 2-byte, twos complement integer. R is a scaling exponent, a 1-byte, twos complement integer. The same equations are used for voltage and current conversions, the only difference being the values of the m, b, and R coefficients that are used. Table 9 lists all the coefficients required for the ADM1275. The current coefficients shown are dependent on the value of the external sense resistor used in a given application. This means that an additional calculation must be performed to take the sense resistor value into account to obtain the coefficients for a specific sense resistor value. The sense resistor value used in the calculations to obtain the coefficients is expressed in milliohms. The m coefficients are defined as 2-byte twos complement numbers in the PMBus standard, therefore the maximum positive value that can be represented is 32767. If the m value is greater than that, and is to be stored in PMBus standard form, then the m coefficients should be divided by 10, and the R coefficient increased by a value of 1. For example, if on the 20 V range, a 10 milliohm sense resistor is used, the m coefficient is 6043, and the R coefficient is −1. Rev. E | Page 32 of 48 Data Sheet ADM1275 Table 9. PMBus Conversion to Real-World Coefficients Coefficient m b R Current (A) 807 × RSENSE 20,475 −1 0 V to 6 V Range 6720 0 −1 Example 1 Voltage (V) 0 V to 20 V Range 19,199 0 −2 To convert an ADC code to current in amperes, the following formulas can be used: IOUT_OC_WARN_LIMIT requires a current-limit value expressed in direct format. VSENSE = LSB25mV × (IADC − 2048) If the required current limit is 10 A, and the sense resistor is 2 mΩ, then the first step is to determine the voltage coefficient. This is simply m = 807 × 2, giving 1614. Using Equation 1 and expressing X, in units of Amps Y = ((1614 × 10) + 20,475) × 10−1 Y = 3661.5 = 3662 (rounded up to integer form) Writing a value of 3662 with the IOUT_OC_WARN_LIMIT command sets an overcurrent warning at 10 A. IOUT = VSENSE/(RSENSE × 0.001) where: VSENSE = (VSENSE+) − (VSENSE−). LSB25mV = 12.4 µV. IADC is the 12-bit ADC code. IOUT is the measured current value in amperes. RSENSE is the value of the sense resistor in milliohms. To convert an ADC code to a voltage, the following formula can be used: Example 2 The READ_IOUT command returns a direct format value of 3339 representing the current flowing through a sense resistor of 1 mΩ. To convert this value to the current flowing, use Equation 2, with m = 807 × 1. X = 1/807 × (3339 × 101 − 20,475) X = 16.00 A This means that when READ_IOUT returns a value of 3339, 16.00 A is flowing in the sense resistor. VOLTAGE AND CURRENT CONVERSION USING LSB VALUES VM = LSBxV × (VADC + 0.5) where: VM is the measured value in volts. VADC is the 12-bit ADC code. LSBxV values are based on the voltage range (see Table 10). Table 10. Voltage Ranges and LSB Values Voltage Range, LSBxV 0 V to 6 V 0 V to 20 V LSB Magnitude 1.488 mV 5.208 mV To convert a current in amperes to a 12-bit value, the following formula can be used (round the result to the nearest integer): VSENSE = IA × RSENSE × 0.001 The direct format voltage and current values returned by the READ_VIN, READ_VOUT, READ_IOUT commands, and the corresponding peak versions, are actually the data output directly by the ADM1275 ADC. As the voltages and currents are really a 12-bit ADC output code, they can also be converted to real-world values with knowledge of the size of the LSB on the ADC. The m, b, R coefficients defined for the PMBus conversion are required to be whole integers by the standard, and have therefore been rounded-off slightly. Using this alternative method, with the exact LSB values, can provide slightly more accurate numerical conversions. ICODE = 2048 + (VSENSE/LSB25mV) where: VSENSE = (VSENSE+) − (VSENSE−). IA is the current value in amperes. RSENSE is the value of the sense resistor in milliohms. ICODE is the 12-bit ADC code. LSB25mV = 12.4 µV. To convert a voltage to a 12-bit value, the following formula can be used (round the result to the nearest integer): VCODE = (VA/LSBxV) − 0.5 where: VCODE is the 12-bit ADC code. VA is the voltage value in volts. LSBxV values are based on the voltage range (see Table 10). Rev. E | Page 33 of 48 ADM1275 Data Sheet ADM1275 ALERT PIN BEHAVIOR The ADM1275 provides a very flexible alert system, whereby one or more fault/warning conditions can be indicated to an external device. FAULTS AND WARNINGS A PMBus fault on the ADM1275 is always generated due to an analog event and causes a change in state in the hot-swap output, turning it off. The three defined fault sources are as follows: • • • Undervoltage (UV) event detected on the UV pin Overvoltage (OV) event detected on the OV pin Overcurrent (OC) event that causes a hot-swap timeout Faults are continuously monitored, and, as long as power is applied to the device, they cannot be disabled. When a fault occurs, a corresponding status bit is set in one or more STATUS_xxx registers. A warning is less severe than a fault and never causes a change in the state of the hot-swap controller. The eight sources of a warning are defined as follows: • • • • • • Any one or more of the faults and warnings listed in the Faults and Warnings section can be enabled and cause an alert, making the corresponding GPOx/ALERTx pin active. By default, the active state of a GPOx/ALERTx pin is low. For example, to use GPO1/ALERT1/CONV to monitor the VOUT UV warning from the ADC, the followings steps must be performed: A value of 1 in a status register bit field always indicates a fault or warning condition. Fault and warning bits in the status registers are latched when set to 1. To clear a latched bit to 0— provided that the fault condition is no longer active—use the CLEAR_FAULTS command or use the OPERATION command to turn the hot-swap output off and then on again. • • By default at power-up, the open-drain GPOx/ALERTx outputs are high impedance, so the pins can be pulled high through resistors. No faults or warnings are enabled on the GPO1/ ALERT1/CONV pin at power-up; the user must explicitly enable the faults or warnings to be monitored. The FET health bad warning is active by default on the GPO2/ALERT2 pin at power-up. CML: a communications error occurred on the I2C bus HS timer was active (HSTA): the current regulation was active, but does not necessarily shut the system down IOUT OC warning from the ADC IOUT Warning 2 from the ADC VIN UV warning from the ADC VIN OV warning from the ADC VOUT UV warning from the ADC (ADM1275-1 and ADM1275-3 only) VOUT OV warning from the ADC (ADM1275-1 and ADM1275-3 only) 1. 2. If a VOUT sample is taken that is below the configured VOUT UV value, the GPO1/ALERT1/CONV pin is taken low, signaling an interrupt to a processor. HANDLING/CLEARING AN ALERT When faults/warnings are configured on the GPOx/ALERTx pins, the pins become active to signal an interrupt to the processor. (These pins are active low, unless inversion is enabled.) The GPOx/ALERTx signal functions as an SMBAlert. Note that the GPOx/ALERTx pins can become active independently of each other, but they are always made inactive together. A processor can respond to the interrupt in one of two basic ways: • GENERATING AN ALERT A host device can periodically poll the ADM1275 using the status commands to determine whether a fault/warning is active. However, this polling is very inefficient in terms of software and processor resources. The ADM1275 has GPOx/ALERTx output pins that can be used to generate interrupts to a host processor. • • • Set a threshold level with the VOUT_UV_WARN_LIMIT command. Start the power monitor sampling on VOUT. • ADM1275-1: GPO1/ALERT1/CONV and GPO2/ALERT2 ADM1275-2: GPO1/ALERT1/CONV ADM1275-3: GPO2/ALERT2 Rev. E | Page 34 of 48 If there is only one device on the bus, the processor can simply read the status bytes and issue a CLEAR_FAULTS command to clear all the status bits, which causes the deassertion of the GPOx/ALERTx line. If there is a persistent fault—for example, an undervoltage on the input—the status bits remain set after the CLEAR_FAULTS command is executed because the fault has not been removed. However, the GPOx/ALERTx line is not pulled low unless a new fault/ warning becomes active. If the cause of the SMBAlert is a power monitor generated warning and the power monitor is running continuously, the next sample generates a new SMBAlert after the CLEAR_FAULTS command is issued. If there are several devices on the bus, the processor can issue an SMBus alert response address command to find out which device asserted the SMBAlert line. The processor can read the status bytes from that device and issue a CLEAR_FAULTS command. Data Sheet ADM1275 SMBus ALERT RESPONSE ADDRESS The SMBus alert response address (ARA) is a special address that can be used by the bus host to locate any devices that need to talk to it. A host typically uses a hardware interrupt pin to monitor the SMBus ALERT pins of a number of devices. When the host interrupt occurs, the host issues a message on the bus using the SMBus receive byte or receive byte with PEC protocol. The special address used by the host is 0x0C. Any devices that have an SMBAlert signal return their own 7-bit address as the seven MSBs of the data byte. The LSB value is not used and can be either 1 or 0. The host reads the device address from the received data byte and proceeds to handle the alert condition. More than one device may have an active SMBAlert signal and attempt to communicate with the host. In this case, the device with the lowest address dominates the bus and succeeds in transmitting its address to the host. The device that succeeds disables its SMBus alert signal. If the host sees that the SMBus alert signal is still low, it continues to read addresses until all devices that need to talk to it have successfully transmitted their addresses. EXAMPLE USE OF SMBus ALERT RESPONSE ADDRESS The full sequence of steps that occurs when an SMBAlert is generated and cleared is as follows: 1. 2. 3. 4. 5. 6. Rev. E | Page 35 of 48 A fault or warning is enabled using the ALERT1_CONFIG command, and the corresponding status bit for the fault or warning goes from 0 to 1, indicating that the fault/warning has just become active. The GPOx/ALERTx pin becomes active (low) to signal that an SMBAlert is active. The host processor issues an SMBus alert response address to determine which device has an active alert. If there are no other active alerts from devices with lower I2C addresses, this device makes the GPOx/ALERTx pin inactive (high) during the NACK bit period after it sends its address to the host processor. If the GPOx/ALERTx pin stays low, the host processor must continue to issue SMBus alert response address commands to devices to find out the addresses of all devices whose status it must check. The ADM1275 continues to operate with the GPOx/ALERTx pin inactive and the contents of the status bytes unchanged until the host reads the status bytes and clears them, or until a new fault occurs. That is, if a status bit for a fault/warning that is enabled on the GPOx/ALERTx pin and that was not already active (equal to 1) goes from 0 to 1, a new alert is generated, causing the GPOx/ALERTx pin to become active again. ADM1275 Data Sheet PMBus COMMAND REFERENCE Register addresses are in hexadecimal format. Table 11. PMBus Command Summary Command Code 0x01 0x03 0x19 0x42 0x43 0x4A 0x57 0x58 0x78 0x79 0x7A 0x7B 0x7C 0x80 0x88 0x8B 0x8C 0x98 0x99 0x9A Command Name OPERATION CLEAR_FAULTS CAPABILITY VOUT_OV_WARN_LIMIT VOUT_UV_WARN_LIMIT IOUT_OC_WARN_LIMIT VIN_OV_WARN_LIMIT VIN_UV_WARN_LIMIT STATUS_BYTE STATUS_WORD STATUS_VOUT STATUS_IOUT STATUS_INPUT STATUS_MFR_SPECIFIC READ_VIN READ_VOUT READ_IOUT PMBUS_REVISION MFR_ID MFR_MODEL SMBus Transaction Type Read/write byte Send byte Read byte Read/write word Read/write word Read/write word Read/write word Read/write word Read byte Read word Read byte Read byte Read byte Read byte Read word Read word Read word Read byte Block read Block read Number of Data Bytes 1 0 1 2 2 2 2 2 1 2 1 1 1 1 2 2 2 1 1 (byte count) + 3 (data) 1 (byte count) + 9 (data) 0x9B 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 MFR_REVISION PEAK_IOUT PEAK_VIN PEAK_VOUT PMON_CONTROL PMON_CONFIG ALERT1_CONFIG ALERT2_CONFIG IOUT_WARN2_LIMIT DEVICE_CONFIG POWER_CYCLE Block read Read/write word Read/write word Read/write word Read/write byte Read/write byte Read/write word Read/write word Read/write word Read/write byte Send byte 1 (byte count) + 1 (data) 2 2 2 1 1 2 2 2 1 0 1 Default Value at Reset 0x80 Not applicable 0xB0 0x0FFF 0x0000 0x0FFF 0x0FFF 0x0000 0x00 0x0000 0x00 0x00 0x00 0x00 0x0000 0x0000 0x0000 0x11 0x03 + ASCII “ADI” 0x09 + ASCII “ADM1275x” 1 0x01 + ASCII “1” 0x0000 0x0000 0x0000 0x00 0x2C 0x0000 0x8000 0x0000 0x00 Not applicable The character “x” in the string is 1, 2, or 3, depending on the model of the ADM1275 that is being queried (ADM1275-1, ADM1275-2, or ADM1275-3). Rev. E | Page 36 of 48 Data Sheet ADM1275 OPERATION Code: 0x01, read/write byte. Value after reset: 0x80. Table 12. Bit Descriptions for OPERATION Command Bits 7 Bit Name ON [6:0] Reserved Settings 0 1 0000000 Description Hot-swap output is disabled. Default. Hot-swap output is enabled. Always reads as 0000000. CLEAR_FAULTS Code: 0x03, send byte, no data. CAPABILITY Code: 0x19, read byte. Value after reset: 0xB0. Table 13. Bit Descriptions for CAPABILITY Command Bits 7 [6:5] 4 [3:0] Bit Name Packet error checking Maximum bus speed SMBALERT# Reserved Settings 1 01 1 0000 Description Always reads as 1. Packet error checking (PEC) is supported. Always reads as 01. Maximum supported bus speed is 400 kHz. Always reads as 1. Device supports SMBAlert and alert response address (ARA). Always reads as 0000. VOUT_OV_WARN_LIMIT Code: 0x42, read/write word. Value after reset: 0x0FFF. This command is supported on the ADM1275-1 and the ADM1275-3. The ADM1275-2 does not have a VOUT pin. Table 14. Bit Descriptions for VOUT_OV_WARN_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved VOUT_OV_WARN_LIMIT Settings 0000 Description Always reads as 0000. Overvoltage threshold for the VOUT pin measurement, expressed in ADC codes. VOUT_UV_WARN_LIMIT Code: 0x43, read/write word. Value after reset: 0x0000. This command is supported on the ADM1275-1 and the ADM1275-3. The ADM1275-2 does not have a VOUT pin. Table 15. Bit Descriptions for VOUT_UV_WARN_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved VOUT_UV_WARN_LIMIT Settings 0000 Description Always reads as 0000. Undervoltage threshold for the VOUT pin measurement, expressed in ADC codes. IOUT_OC_WARN_LIMIT Code: 0x4A, read/write word. Value after reset: 0x0FFF. Table 16. Bit Descriptions for IOUT_OC_WARN_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved IOUT_OC_WARN_LIMIT Settings 0000 Description Always reads as 0000. Overcurrent threshold for the IOUT measurement through the sense resistor, expressed in ADC codes. Rev. E | Page 37 of 48 ADM1275 Data Sheet IOUT_WARN2_LIMIT Code: 0xD7, read/write word. Value after reset: 0x0000. Table 17. Bit Descriptions for IOUT_WARN2_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved IOUT_WARN2_LIMIT Settings 0000 Description Always reads as 0000. Threshold for the IOUT measurement through the sense resistor, expressed in ADC codes. This value can be either an undercurrent or an overcurrent, depending on the state of the IOUT_WARN2_SELECT bit set using the DEVICE_CONFIG command. VIN_OV_WARN_LIMIT Code: 0x57, read/write word. Value after reset: 0x0FFF. Table 18. Bit Descriptions for VIN_OV_WARN_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved VIN_OV_WARN_LIMIT Settings 0000 Description Always reads as 0000. Overvoltage threshold for the SENSE+ pin measurement, expressed in ADC codes. VIN_UV_WARN_LIMIT Code: 0x58, read/write word. Value after reset: 0x0000. Table 19. Bit Descriptions for VIN_UV_WARN_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved VIN_UV_WARN_LIMIT Settings 0000 Description Always reads as 0000. Undervoltage threshold for the SENSE+ pin measurement, expressed in ADC codes. STATUS_BYTE Code: 0x78, read byte. Value after reset: 0x00. Table 20. Bit Descriptions for STATUS_BYTE Command Bits 7 6 Bit Name Reserved HOTSWAP_OFF Behavior Live 5 4 Reserved IOUT_OC_FAULT Latched 3 VIN_UV_FAULT Latched 2 1 Reserved CML_ERROR Latched 0 NONE_OF_THE_ABOVE Live Settings 0 0 1 0 0 1 0 1 0 0 1 0 1 Description Always reads as 0. The hot-swap gate drive output is enabled. The hot-swap gate drive output is disabled, and the GATE pin is pulled down. This can be due to, for example, an overcurrent fault that causes the ADM1275 to latch off, an undervoltage condition on the UV pin, or the use of the OPERATION command to turn the output off. Always reads as 0. No overcurrent output fault detected. The hot-swap controller detected an overcurrent condition and the time limit set by the capacitor on the TIMER pin has elapsed, causing the hotswap gate drive to shut down. No undervoltage input fault detected on the UV pin. An undervoltage input fault was detected on the UV pin. Always reads as 0. No communications error detected on the I2C/PMBus interface. An error was detected on the I2C/PMBus interface. Errors detected are unsupported command, invalid PEC byte, and incorrectly structured message. No other active status bit to be reported by any other status command. Active status bits are waiting to be read by one or more status commands. Rev. E | Page 38 of 48 Data Sheet ADM1275 STATUS_WORD Code: 0x79, read word. Value after reset: 0x0000. Table 21. Bit Descriptions for STATUS_WORD Command Bits 15 Bit Name VOUT_STATUS Behavior Live 14 IOUT_STATUS Live 13 VIN_STATUS Live 12 MFR_STATUS Live 11 POWER_GOOD# Live Settings 0 1 0 1 0 1 0 1 0 1 [10:8] [7:0] Reserved STATUS_BYTE 000 Description There are no active status bits to be read by STATUS_VOUT. There are one or more active status bits to be read by STATUS_VOUT. There are no active status bits to be read by STATUS_IOUT. There are one or more active status bits to be read by STATUS_IOUT. There are no active status bits to be read by STATUS_INPUT. There are one or more active status bits to be read by STATUS_INPUT. There are no active status bits to be read by STATUS_MFR_SPECIFIC. There are one or more active status bits to be read by STATUS_MFR_SPECIFIC. The voltage on the FLB pin is above the required threshold, indicating that output power is considered good. This bit is the logical inversion of the PWRGD pin on the part. The voltage on the FLB pin is below the required threshold, indicating that output power is considered bad. Always reads as 000. This byte is the same as the byte returned by the STATUS_BYTE command. STATUS_VOUT Code: 0x7A, read byte. Value after reset: 0x00. This command is supported on the ADM1275-1 and the ADM1275-3. The ADM1275-2 does not have a VOUT pin. Table 22. Bit Descriptions for STATUS_VOUT Command Bits 7 6 Bit Name Reserved VOUT_OV_WARN Behavior Latched Settings 0 0 1 5 VOUT_UV_WARN Latched 0 1 [4:0] Reserved 00000 Description Always reads as 0. No overvoltage condition on the output supply detected by the power monitor. An overvoltage condition on the output supply was detected by the power monitor. No undervoltage condition on the output supply detected by the power monitor. An undervoltage condition on the output supply was detected by the power monitor. Always reads as 00000. STATUS_IOUT Code: 0x7B, read byte. Value after reset: 0x00. Table 23. Bit Descriptions for STATUS_IOUT Command Bits 7 Bit Name IOUT_OC_FAULT Behavior Latched 6 5 Reserved IOUT_OC_WARN Latched Settings 0 1 0 0 1 [4:0] Reserved 00000 Description No overcurrent output fault detected. The hot-swap controller detected an overcurrent condition and the time limit set by the capacitor on the TIMER pin has elapsed, causing the hotswap gate drive to shut down. Always reads as 0. No overcurrent condition on the output supply detected by the power monitor using the IOUT_OC_WARN_LIMIT command. An overcurrent condition was detected by the power monitor using the IOUT_OC_WARN_LIMIT command. Always reads as 00000. Rev. E | Page 39 of 48 ADM1275 Data Sheet STATUS_INPUT Code: 0x7C, read byte. Value after reset: 0x00. Table 24. Bit Descriptions for STATUS_INPUT Command Bits 7 Bit Name VIN_OV_FAULT Behavior Latched 6 VIN_OV_WARN Latched Settings 0 1 0 1 5 VIN_UV_WARN Latched 0 1 4 VIN_UV_FAULT [3:0] Reserved Latched 0 1 0000 Description No overvoltage detected on the OV pin. An overvoltage was detected on the OV pin. No overvoltage condition on the input supply detected by the power monitor. An overvoltage condition on the input supply was detected by the power monitor. No undervoltage condition on the input supply detected by the power monitor. An undervoltage condition on the input supply was detected by the power monitor. No undervoltage detected on the UV pin. An undervoltage was detected on the UV pin. Always reads as 0000. STATUS_MFR_SPECIFIC Code: 0x80, read byte. Value after reset: 0x00. Table 25. Bit Descriptions for STATUS_MFR_SPECIFIC Command Bits 7 Bit Name FET_HEALTH_BAD Behavior Latched 6 UV_CMP_OUT Live 5 OV_CMP_OUT Live 4 3 Reserved HS_INLIM Latched [2:1] HS_SHUTDOWN_CAUSE Latched 00 Latched 01 10 11 0 0 IOUT_WARN2 Settings 0 1 0 1 0 1 0 0 1 1 Description FET behavior appears to be as expected. FET behavior suggests that the FET may be shorted. Input voltage to UV pin is above threshold. Input voltage to UV pin is below threshold. Input voltage to OV pin is below threshold. Input voltage to OV pin is above threshold. Always reads as 0. The ADM1275 has not actively limited the current into the load. The ADM1275 has actively limited current into the load. This bit differs from the IOUT_OC_FAULT bit in that the HS_INLIM bit is set immediately, whereas the IOUT_OC_FAULT bit is not set unless the time limit set by the capacitor on the TIMER pin elapses. The ADM1275 is either enabled and working correctly, or has been shut down using the OPERATION command. An IOUT_OC_FAULT condition occurred that caused the ADM1275 to shut down. A VIN_UV_FAULT condition occurred that caused the ADM1275 to shut down. A VIN_OV_FAULT condition occurred that caused the ADM1275 to shut down. No overcurrent condition on the output supply detected by the power monitor using the IOUT_WARN2_LIMIT command. An undercurrent or overcurrent condition on the output supply was detected by the power monitor using the IOUT_WARN2_LIMIT command. The polarity of the threshold condition is set by the IOUT_WARN2_SELECT bit using the DEVICE_CONFIG command. READ_VIN Code: 0x88, read word. Value after reset: 0x0000. Table 26. Bit Descriptions for READ_VIN Command Bits [15:12] [11:0] Bit Name Reserved VIN Settings 0000 Description Always reads as 0000. Input voltage from the SENSE+ pin measurement, expressed in ADC codes. Rev. E | Page 40 of 48 Data Sheet ADM1275 READ_VOUT Code: 0x8B, read word. Value after reset: 0x0000. This command is supported on the ADM1275-1 and the ADM1275-3. The ADM1275-2 does not have a VOUT pin. Table 27. Bit Descriptions for READ_VOUT Command Bits [15:12] [11:0] Bit Name Reserved VOUT Settings 0000 Description Always reads as 0000. Output voltage from the VOUT pin measurement, expressed in ADC codes. READ_IOUT Code: 0x8C, read word. Value after reset: 0x0000. Table 28. Bit Descriptions for READ_IOUT Command Bits [15:12] [11:0] Bit Name Reserved IOUT Settings 0000 Description Always reads as 0000. Output current from the measurement through the sense resistor. PMBUS_REVISION Code: 0x98, read byte. Value after reset: 0x11. Table 29. Bit Descriptions for PMBUS_REVISION Command Bits [7:4] [3:0] Bit Name Part I Revision Part II Revision Settings 0001 0001 Description Always reads as 0001, PMBus Specification Part I, Revision 1.1. Always reads as 0001, PMBus Specification Part II, Revision 1.1. MFR_ID Code: 0x99, block read. Value after reset: 0x03 + ASCII “ADI”. Table 30. Bit Descriptions for MFR_ID Command Byte 0 Byte Name Byte count Value 0x03 1 2 3 Character 1 Character 2 Character 3 0x41 or “A” 0x44 or “D” 0x49 or “I” Description Always reads as 0x03, the number of data bytes that the block read command should expect to read. Always reads as 0x41. Always reads as 0x44. Always reads as 0x49. MFR_MODEL Code: 0x9A, block read. Value after reset: 0x09 + ASCII “ADM1275-x”. Table 31. Bit Descriptions for MFR_MODEL Command Byte 0 Byte Name Byte count Value 0x09 1 2 3 4 5 6 7 8 Character 1 Character 2 Character 3 Character 4 Character 5 Character 6 Character 7 Character 8 0x41 or “A” 0x44 or “D” 0x4D or “M” 0x31 or “1” 0x32 or “2” 0x37 or “7” 0x35 or “5” 0x2D or “-” Description Always reads as 0x09, the number of data bytes that the block read command should expect to read. Always reads as 0x41. Always reads as 0x44. Always reads as 0x4D. Always reads as 0x31. Always reads as 0x32. Always reads as 0x37. Always reads as 0x35. Always reads as 0x2D. Rev. E | Page 41 of 48 ADM1275 Byte 9 Byte Name Character 9 Data Sheet Value 0x31 or “1” 0x32 or “2” 0x33 or “3” Description Always reads as 0x31 on the ADM1275-1. Always reads as 0x32 on the ADM1275-2. Always reads as 0x33 on the ADM1275-3. MFR_REVISION Code: 0x9B, block read. Value after reset: 0x01 + ASCII “1”. Table 32. Bit Descriptions for MFR_REVISION Command Byte 0 Byte Name Byte count Value 0x01 1 Character 1 0x31 or “1” Description Always reads as 0x01, the number of data bytes that the block read command should expect to read. Always reads as 0x31, Revision 1 of the ADM1275. PEAK_IOUT Code: 0xD0, read/write word. Value after reset: 0x0000 (writing 0x0000 clears the peak value). Table 33. Bit Descriptions for PEAK_IOUT Command Bits [15:12] [11:0] Bit Name Reserved PEAK_IOUT Settings 0000 Description Always reads as 0000. Returns the peak IOUT current since the register was last cleared. PEAK_VIN Code: 0xD1, read/write word. Value after reset: 0x0000 (writing 0x0000 clears the peak value). Table 34. Bit Descriptions for PEAK_VIN Command Bits [15:12] [11:0] Bit Name Reserved PEAK_VIN Settings 0000 Description Always reads as 0000. Returns the peak VIN voltage since the register was last cleared. PEAK_VOUT Code: 0xD2, read/write word. Value after reset: 0x0000 (writing 0x0000 clears the peak value). This command is supported on the ADM1275-1 and the ADM1275-3. The ADM1275-2 does not have a VOUT pin. Table 35. Bit Descriptions for PEAK_VOUT Command Bits [15:12] [11:0] Bit Name Reserved PEAK_VOUT Settings 0000 Description Always reads as 0000. Returns the peak VOUT voltage since the register was last cleared. PMON_CONTROL Code: 0xD3, read/write byte. Value after reset: 0x00. Table 36. Bit Descriptions for PMON_CONTROL Command Bits [7:1] 0 Bit Name Reserved CONVERT Settings 0000000 0 1 Description Always reads as 0000000. Default. Power monitor is not running. Start the sampling of current and voltage with the power monitor. In single-shot mode, this bit clears itself after one complete cycle. In continuous mode, this bit must be written to 0 to stop sampling. Rev. E | Page 42 of 48 Data Sheet ADM1275 PMON_CONFIG Code: 0xD4, read/write byte. Value after reset: 0x2C. Modifying the power monitor settings while the power monitor is sampling is not supported. The power monitor must be stopped before any setting in Table 37 is changed to ensure correct operation and to prevent any potential spurious data and status alerts being generated. Table 37. Bit Descriptions for PMON_CONFIG Command Bits 7 Bit Name PMON_MODE 6 VIN_VOUT_SELECT 5 VRANGE 4 3 Reserved Reserved [2:0] AVERAGING Settings 0 1 0 1 0 1 0 1 000 001 010 011 100 101 110 111 Description Default. This setting selects single-shot sampling mode. This setting selects continuous sampling mode. Default. The power monitor will sample the input voltage on the SENSE+ pin. On the ADM1275-2, this bit should always be written as 0. The power monitor will sample the output voltage on the VOUT pin. Sets the voltage input range from 0 V to 6 V (low input voltage range). Default. Sets the voltage input range from 0 V to 20 V (high input voltage range). Reserved. This bit must always be written as 0. Default. This bit must be set to 1 for the power monitor current sense to operate correctly. Disables sample averaging for current and voltage. Sets sample averaging for current and voltage to 2 samples. Sets sample averaging for current and voltage to 4 samples. Sets sample averaging for current and voltage to 8 samples. Sets sample averaging for current and voltage to 16 samples. Sets sample averaging for current and voltage to 32 samples. Sets sample averaging for current and voltage to 64 samples. Sets sample averaging for current and voltage to 128 samples. ALERT1_CONFIG Code: 0xD5, read/write word. Value after reset: 0x0000. This command is supported on the ADM1275-1 and the ADM1275-2. The ADM1275-3 does not have a GPO1/ALERT1/CONV pin. Table 38. Bit Descriptions for ALERT1_CONFIG Command Bits 15 Bit Name FET_HEALTH_BAD_EN1 14 IOUT_OC_FAULT_EN1 13 VIN_OV_FAULT_EN1 12 VIN_UV_FAULT_EN1 11 CML_ERROR_EN1 10 IOUT_OC_WARN_EN1 9 IOUT_WARN2_EN1 8 VIN_OV_WARN_EN1 7 VIN_UV_WARN_EN1 6 VOUT_OV_WARN_EN1 Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Default. Disables generation of SMBAlert when the FET_HEALTH_BAD bit is set. Generate SMBAlert when the FET_HEALTH_BAD bit is set. Default. Disables generation of SMBAlert when the IOUT_OC_FAULT bit is set. Generate SMBAlert when the IOUT_OC_FAULT bit is set. Default. Disables generation of SMBAlert when the VIN_OV_FAULT bit is set. Generate SMBAlert when the VIN_OV_FAULT bit is set. Default. Disables generation of SMBAlert when the VIN_UV_FAULT bit is set. Generate SMBAlert when the VIN_UV_FAULT bit is set. Default. Disables generation of SMBAlert when the CML_ERROR bit is set. Generate SMBAlert when the CML_ERROR bit is set. Default. Disables generation of SMBAlert when the IOUT_OC_WARN bit is set. Generate SMBAlert when the IOUT_OC_WARN bit is set. Default. Disables generation of SMBAlert when the IOUT_WARN2 bit is set. Generate SMBAlert when the IOUT_WARN2 bit is set. Default. Disables generation of SMBAlert when the VIN_OV_WARN bit is set. Generate SMBAlert when the VIN_OV_WARN bit is set. Default. Disables generation of SMBAlert when the VIN_UV_WARN bit is set. Generate SMBAlert when the VIN_UV_WARN bit is set. Default. Disables generation of SMBAlert when the VOUT_OV_WARN bit is set. Generate SMBAlert when the VOUT_OV_WARN bit is set. Rev. E | Page 43 of 48 ADM1275 Bits 5 Bit Name VOUT_UV_WARN_EN1 4 HS_INLIM_EN1 3 INVERT_SMBALERT_1 2 CONVERT_EN 1 GPO1_EN Data Sheet Settings 0 1 0 1 0 1 0 1 0 1 0 GPO1_DATA 0 1 Description Default. Disables generation of SMBAlert when the VOUT_UV_WARN bit is set. Generate SMBAlert when the VOUT_UV_WARN bit is set. Default. Disables generation of SMBAlert when the HS_INLIM bit is set. Generate SMBAlert when the HS_INLIM bit is set. Default. SMBAlert is active low when a fault/warning bit that is enabled becomes set. SMBAlert is active high when a fault/warning bit that is enabled becomes set. Default. GPO1/ALERT1/CONV is configured as an output pin. GPO1/ALERT1/CONV is configured as an input pin. All other settings in ALERT1_CONFIG are ignored. Default. GPO1/ALERT1/CONV can be configured as either a power monitor convert input or an SMBAlert output. GPO1/ALERT1/CONV is configured as a general-purpose output unless CONVERT_EN is set to 1. Default. Sets GPO1/ALERT1/CONV low when configured as a general-purpose output. Sets GPO1/ALERT1/CONV high when configured as a general-purpose output. ALERT2_CONFIG Code: 0xD6, read/write word. Value after reset: 0x8000. This command is supported on the ADM1275-1 and the ADM1275-3. The ADM1275-2 does not have a GPO2/ALERT2 pin. Table 39. Bit Descriptions for ALERT2_CONFIG Command Bits 15 Bit Name FET_HEALTH_BAD_EN2 14 IOUT_OC_FAULT_EN2 13 VIN_OV_FAULT_EN2 12 VIN_UV_FAULT_EN2 11 CML_ERROR_EN2 10 IOUT_OC_WARN_EN2 9 IOUT_WARN2_EN2 8 VIN_OV_WARN_EN2 7 VIN_UV_WARN_EN2 6 VOUT_OV_WARN_EN2 5 VOUT_UV_WARN_EN2 4 HS_INLIM_EN2 3 INVERT_SMBALERT_2 2 Reserved Settings 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Description Disables generation of SMBAlert when the FET_HEALTH_BAD bit is set. Default. Generate SMBAlert when the FET_HEALTH_BAD bit is set. This bit is active from power-up so that a FET problem can be detected and flagged immediately without the need for software to set this bit. Default. Disables generation of SMBAlert when the IOUT_OC_FAULT bit is set. Generate SMBAlert when the IOUT_OC_FAULT bit is set. Default. Disables generation of SMBAlert when the VIN_OV_FAULT bit is set. Generate SMBAlert when the VIN_OV_FAULT bit is set. Default. Disables generation of SMBAlert when the VIN_UV_FAULT bit is set. Generate SMBAlert when the VIN_UV_FAULT bit is set. Default. Disables generation of SMBAlert when the CML_ERROR bit is set. Generate SMBAlert when the CML_ERROR bit is set. Default. Disables generation of SMBAlert when the IOUT_OC_WARN bit is set. Generate SMBAlert when the IOUT_OC_WARN bit is set. Default. Disables generation of SMBAlert when the IOUT_WARN2 bit is set. Generate SMBAlert when the IOUT_WARN2 bit is set. Default. Disables generation of SMBAlert when the VIN_OV_WARN bit is set. Generate SMBAlert when the VIN_OV_WARN bit is set. Default. Disables generation of SMBAlert when the VIN_UV_WARN bit is set. Generate SMBAlert when the VIN_UV_WARN bit is set. Default. Disables generation of SMBAlert when the VOUT_OV_WARN bit is set. Generate SMBAlert when the VOUT_OV_WARN bit is set. Default. Disables generation of SMBAlert when the VOUT_UV_WARN bit is set. Generate SMBAlert when the VOUT_UV_WARN bit is set. Default. Disables generation of SMBAlert when the HS_INLIM bit is set. Generate SMBAlert when the HS_INLIM bit is set. Default. SMBAlert is active low when a fault/warning bit that is enabled becomes set. SMBAlert is active high when a fault/warning bit that is enabled becomes set. Always reads as 0. Rev. E | Page 44 of 48 Data Sheet Bits 1 Bit Name GPO2_EN 0 GPO2_DATA ADM1275 Settings 0 1 0 1 Description Default. GPO/ALERT2 is configured as an SMBAlert output. GPO/ALERT2 is configured as a general-purpose output. Default. Sets GPO/ALERT2 low when configured as a general-purpose output. Sets GPO/ALERT2 high when configured as a general-purpose output. DEVICE_CONFIG Code: 0xD8, read/write byte. Value after reset: 0x00. Table 40. Bit Descriptions for DEVICE_CONFIG Command Bits 7 Bit Name OC_GLITCH_TIME Settings 0 6 FLB_DISABLE 1 0 1 5 OPERATION_CMD_EN 0 4 IOUT_WARN2_SELECT [3:0] Reserved 1 0 1 0000 Description Default. The long duration glitch filter is used when a severe overcurrent fault is detected. The short duration glitch filter is used when a severe overcurrent fault is detected. Default. Foldback is enabled and can affect the hot-swap current sense limit. Foldback is disabled and does not affect the hot-swap current sense limit. This setting can be useful if the sole purpose of the FLB pin is to act as a power-good input. Default. The OPERATION command is disabled, and the ADM1275 issues a NACK if the command is received. This setting provides some protection against a card accidentally turning itself off. The OPERATION command is enabled, and the ADM1275 responds to it. Default. Configures IOUT_WARN2_LIMIT as an undercurrent threshold. Configures IOUT_WARN2_LIMIT as an overcurrent threshold. Always reads as 0000. POWER_CYCLE Code: 0xD9, send byte, no data. Rev. E | Page 45 of 48 ADM1275 Data Sheet OUTLINE DIMENSIONS 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 1 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 8 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.025 (0.64) BSC SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8° 0° 0.020 (0.51) 0.010 (0.25) 0.050 (1.27) 0.016 (0.41) 0.041 (1.04) REF 01-28-2008-A COMPLIANT TO JEDEC STANDARDS MO-137-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 66. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 11 1 10 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.025 (0.64) BSC SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8° 0° 0.050 (1.27) 0.016 (0.41) COMPLIANT TO JEDEC STANDARDS MO-137-AD CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 67. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches and (millimeters) Rev. E | Page 46 of 48 0.020 (0.51) 0.010 (0.25) 0.041 (1.04) REF 08-19-2008-A 20 Data Sheet ADM1275 PIN 1 INDICATOR 5.10 5.00 SQ 4.90 0.35 0.28 0.23 0.65 BSC 20 16 15 PIN 1 INDICATOR 1 EXPOSED PAD 3.25 3.10 SQ 2.95 5 11 0.80 0.75 0.70 0.70 0.60 0.40 10 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHC. 111908-A TOP VIEW Figure 68. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-20-9) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADM1275-1ARQZ ADM1275-1ARQZ-R7 ADM1275-1ACPZ ADM1275-1ACPZ-R7 ADM1275-2ARQZ ADM1275-2ARQZ-R7 ADM1275-3ARQZ ADM1275-3ARQZ-R7 ADM1275-3ACPZ ADM1275-3ACPZ-R7 EVAL-ADM1275EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 20-Lead Shrink Small Outline Package [QSOP] 20-Lead Shrink Small Outline Package [QSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 20-Lead Shrink Small Outline Package [QSOP] 20-Lead Shrink Small Outline Package [QSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Z = RoHS Compliant Part. Rev. E | Page 47 of 48 Package Option RQ-20 RQ-20 CP-20-9 CP-20-9 RQ-16 RQ-16 RQ-20 RQ-20 CP-20-9 CP-20-9 ADM1275 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08931-0-5/19(E) Rev. E | Page 48 of 48