FEATURES
TYPICAL APPLICATION CIRCUIT
RSENSE
4.5V TO 20V
±0.3% accurate, 12-bit ADC for IOUT, VIN, VOUT, and temperature
320 ns response time to short circuit
Shutdown on detection of FET health fault
Constant power foldback for tighter FET SOA protection
Remote temperature sensing with programmable warning
and shutdown thresholds
Resistor-programmable 5 mV to 25 mV VSENSE current limit
Programmable start-up current limit
1% accurate UV, OV, and PWRGD thresholds
Split hot swap and power monitor inputs to allow additional
external ADC filtering
Reports power and energy consumption over time
Peak detect registers for current, voltage, and power
PROCHOT power throttling capability
PMBus fast mode compliant interface
5 mm × 5 mm, 32-lead LFCSP
HS+
MO+
VCC
VCAP
LDO
1.0V
ISET
PSET
ISTART
HS–
MO–
ADM1278-1
+ –
×50
UV
OV
Q1
+
–
–
1.0V +
REF
SELECT
1.0V
HS–
CHARGE
PUMP
ISENSE
VCP
GATE
DRIVE/
LOGIC
GATE
TEMP
TIMEOUT
+
–
+
–
CURRENTLIMIT
CONTROL
PWGIN
1.0V
VOUT
VCBOS
TIMER
IOUT
TIMER TIMEOUT
HS+
ISENSE
VOUT
TEMP
LOGIC
AND
PMBus
12-BIT
ADC
RETRY
APPLICATIONS
ANALOG
VOUT
Servers
Power monitoring and control/power budgeting
Telecommunication and data communication equipment
PGND
PWRGD
FAULT
ENABLE
GPO2/ALERT2
GPO1/ALERT1/CONV
SCL
SDA
ADR1
ADR2
CSOUT
GND
12198-001
Data Sheet
Hot Swap Controller and Digital Power and
Energy Monitor with PMBus Interface
ADM1278
Figure 1.
GENERAL DESCRIPTION
The ADM1278 is a hot swap controller that allows a circuit
board to be removed from or inserted into a live backplane. It also
features current, voltage, power, and temperature readback via an
integrated 12-bit analog-to-digital converter (ADC), accessed
using a PMBus™ interface. The load current is measured using an
internal current sense amplifier that measures the voltage across
a sense resistor in the power path via the HS+ and HS− pins. A
default current limit of 20 mV is set, but this limit can be
adjusted, if required.
The ADM1278 limits the current through the sense resistor by
controlling the gate voltage of an external N-channel FET in the
power path, via the GATE pin. The sense voltage, and therefore
the load current, is maintained below the preset maximum. The
ADM1278 protects the external FET by limiting the time that
the FET remains on while the current is at its maximum value.
This current-limit time is set by the choice of capacitor connected
to the TIMER pin. In addition, a constant power foldback scheme
is used to control the power dissipation in the MOSFET during
power-up and fault conditions. The level of this power, along
with the TIMER regulation time, can be set to ensure that the
MOSFET remains within safe operating area (SOA) limits.
Rev. C
In case of a short-circuit event, a fast internal overcurrent
detector responds within 320 ns and signals the gate to shut
down. A 1500 mA pull-down device ensures a fast FET response.
The ADM1278 features overvoltage (OV) and undervoltage (UV)
protection, programmed using external resistor dividers on the
UV and OV pins. A PWRGD signal can be used to detect when the
output supply is valid, using the PWGIN pin to accurately
monitor the output.
The ADM1278 is available in a 32-lead LFCSP with a RETRY pin
that can be configured for automatic retry or latch-off when an
overcurrent fault occurs.
Table 1. Model Options
Model
ADM1278-1AA
ADM1278-1A
ADM1278-1B
ADM1278-2A
ADM1278-3A
1
ADC Accuracy
±0.3%
±0.7%
±1.0%
±0.7%
±0.7%
SPI Interface
No
No
No
Yes
No
Enable Pin1
Active high
Active high
Active high
Active high
Active low
Active high relates to the ENABLE pin, and active low relates to the ENABLE pin.
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ADM1278
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
SMBus Protocol Usage .............................................................. 34
Applications ...................................................................................... 1
Packet Error Checking .............................................................. 34
Typical Application Circuit ............................................................ 1
Partial Transactions on I2C Bus ............................................... 35
General Description ......................................................................... 1
SMBus Message Formats .......................................................... 35
Revision History ............................................................................... 3
Group Commands ..................................................................... 37
Specifications .................................................................................... 4
Hot Swap Control Commands ................................................. 37
Power Monitoring Accuracy Specifications ............................. 8
ADM1278 Information Commands ....................................... 37
Serial Bus Timing Characteristics .............................................. 8
Status Commands ...................................................................... 38
SPI Timing Characteristics (ADM1278-2) ............................... 9
GPO and Alert Pin Setup Commands .................................... 38
Absolute Maximum Ratings ......................................................... 10
Power Monitor Commands ...................................................... 39
Thermal Characteristics ............................................................ 10
Warning Limit Setup Commands ........................................... 40
ESD Caution................................................................................ 10
PMBus Direct Format Conversion .......................................... 40
Pin Configurations and Function Descriptions ......................... 11
Voltage and Current Conversion Using LSB Values ............ 41
Typical Performance Characteristics ........................................... 17
Alert Pin Behavior .......................................................................... 42
Theory of Operation ...................................................................... 24
Faults and Warnings .................................................................. 42
Powering the ADM1278............................................................ 24
Generating an Alert ................................................................... 42
Hot Swap Current Sense Inputs ............................................... 24
Handling/Clearing an Alert ...................................................... 42
Power Monitor Current Sense Inputs ..................................... 25
SMBus Alert Response Address ............................................... 43
Current-Limit Reference ........................................................... 25
Example Use of SMBus ARA.................................................... 43
Setting the Current Limit (ISET) ............................................. 26
Digital Comparator Mode ........................................................ 43
Setting a Linear Output Voltage Ramp at Power-Up ........... 26
Typical Application Circuits .................................................... 43
Start-Up Current Limit ............................................................. 27
PMBus Command Reference ....................................................... 45
Constant Power Foldback ......................................................... 28
Register Details ............................................................................... 46
Timer ............................................................................................ 28
Operation Register ..................................................................... 46
Hot Swap Retry ........................................................................... 29
Clear Faults Register .................................................................. 46
FET Gate Drive Clamps ............................................................ 29
PMBus Capability Register ....................................................... 46
Fast Response to Severe Overcurrent ...................................... 29
VOUT OV Warning Limit Register ............................................ 46
Undervoltage and Overvoltage................................................. 29
VOUT UV Warning Limit Register ............................................ 47
Power Good ................................................................................ 29
IOUT OC Warning Limit Register.............................................. 47
FAULT Pin .................................................................................. 29
OT Fault Limit Register............................................................. 47
ENABLE/ENABLE Input .......................................................... 30
OT Warning Limit Register ...................................................... 47
Current Sense Output (CSOUT) ............................................. 30
VIN OV Warning Limit Register .............................................. 47
Remote Temperature Sensing .................................................. 30
VIN UV Warning Limit Register .............................................. 48
SPI Interface ................................................................................ 31
PIN OP Warning Limit Register ................................................ 48
VOUT Measurement ..................................................................... 32
Status Byte Register .................................................................... 48
FET Health .................................................................................. 32
Status Word Register ................................................................. 49
Power Throttling ........................................................................ 32
VOUT Status Register ................................................................... 50
Power Monitor ........................................................................... 32
IOUT Status Register ..................................................................... 50
PMBus Interface ............................................................................. 34
Input Status Register .................................................................. 50
Device Addressing...................................................................... 34
Temperature Status Register .................................................... 51
Rev. C | Page 2 of 61
Data Sheet
ADM1278
Manufacturer Specific Status Register .....................................51
Power Monitor Configuration Register................................... 55
Read EIN Register .........................................................................52
Alert 1 Configuration Register.................................................. 56
Read VIN Register ........................................................................52
Alert 2 Configuration Register.................................................. 57
Read VOUT Register ......................................................................53
Peak Temperature Register ....................................................... 57
Read IOUT Register .......................................................................53
Device Configuration Register .................................................. 57
Read Temperature 1 Register ....................................................53
Power Cycle Register .................................................................. 58
Read PIN Register .........................................................................53
Peak PIN Register ......................................................................... 59
PMBus Revision Register ...........................................................53
Read PIN (Extended) Register .................................................... 59
Manufacturer ID Register ..........................................................54
Read EIN (Extended) Register .................................................... 59
Manufacturer Model Register ...................................................54
Hysteresis Low Level Register ................................................... 59
Manufacturer Revision Register ...............................................54
Hysteresis High Level Register.................................................. 59
Manufacturer Date Register ......................................................54
Hysteresis Status Register .......................................................... 60
Peak IOUT Register ........................................................................54
Start-Up IOUT Limit Register ...................................................... 60
Peak VIN Register .........................................................................55
Outline Dimensions ....................................................................... 61
Peak VOUT Register ......................................................................55
Ordering Guide ........................................................................... 61
Power Monitor Control Register ..............................................55
REVISION HISTORY
3/2020—Rev. B to Rev. C
Change to Endnote 1, Table 6 .......................................................10
Changes to Figure 27 ......................................................................20
Changes to Figure 62 ......................................................................35
Changes to Table 12 ........................................................................41
Added Endnote 1, Table 13 ...........................................................45
Changes to Table 57 ........................................................................60
10/2018—Rev. A to Rev. B
Changes to Figure 4 and Figure 5 .................................................11
Changes to Figure 6 ........................................................................14
Updated Outline Dimensions .......................................................61
Changes to Ordering Guide...........................................................61
12/2014—Rev. 0 to Rev. A
Changes to Features Section, General Description Section,
and Applications Section ................................................................. 1
Added Table 1, Renumbered Sequentially .................................... 1
Changes to POWER_CYCLE Command Section ...................... 37
Change to Power Cycle Register Section ..................................... 58
6/2014—Revision 0: Initial Version
Rev. C | Page 3 of 61
ADM1278
Data Sheet
SPECIFICATIONS
VCC = 4.5 V to 20 V, VCC ≥ VHS+ and VMO+, VHS+ = 2 V to 20 V, VSENSE_HS = (VHS+ − VHS−) = 0 V, TA = −40°C to +85°C, unless otherwise
noted.
Table 2.
Parameter1
POWER SUPPLY
Operating Voltage Range
Undervoltage Lockout
Undervoltage Hysteresis
Quiescent Current
UV PIN
Input Current
UV Threshold
A Grade and AA Grade
B Grade Only
UV Threshold Hysteresis
UV Glitch Filter
UV Propagation Delay
OV PIN
Input Current
OV Threshold
A Grade and AA Grade
B Grade Only
OV Threshold Hysteresis
OV Glitch Filter
OV Propagation Delay
HS+ AND HS− PINS
Input Current
Input Imbalance
MO+ AND MO− PINS
Input Current
VCAP PIN
Internally Regulated Voltage
A Grade and AA Grade
B Grade Only
ISET PIN
Reference Select Threshold
Internal Reference
Gain of Current Sense
Amplifier
Recommended Maximum
Operating Range
Input Current
GATE PIN
GATE Drive Voltage
GATE Pull-Up Current
GATE Pull-Down Current
Regulation
Slow
Fast
Symbol
Min
VCC
UVLO
4.5
2.4
Typ
Max
Unit
20
2.7
120
5.5
V
V
mV
mA
GATE on and power monitor running
50
nA
UV ≤ 3.6 V
1.01
1.03
75
7
8
V
V
mV
μs
μs
UV falling
UV falling
50
nA
OV ≤ 3.6 V
1.01
1.03
75
3.5
4.0
V
V
mV
μs
μs
OV rising
OV rising
ISENSEx
IΔSENSE
150
5
μA
μA
Per individual pin; VHS+, VHS− = 20 V
IΔSENSE = (I+ − I−)
IMO±
25
nA
Per individual pin; VMO+, VMO− = 20 V
90
ICC
IUV
UVTH
UVHYST
UVGF
UVPD
0.99
0.97
45
2
1.0
1.0
60
5
IOV
OVTH
OVHYST
OVGF
OVPD
0.99
0.97
45
1.5
1.0
1.0
60
3.0
Test Conditions/Comments
VCC rising
50 mV overdrive
UV low to GATE pull-down active
50 mV overdrive
OV high to GATE pull-down active
VVCAP
2.68
2.66
2.7
2.7
2.72
2.74
V
V
0 μA ≤ IVCAP ≤ 100 μA; CVCAP = 1 μF
0 μA ≤ IVCAP ≤ 100 μA; CVCAP = 1 μF
VISETRSTH
VCLREF
AVCSAMP
1.35
1.5
1
50
1.65
V
V
V/V
If VISET > VISETRSTH, an internal 1 V reference (VCLREF) is used
Accuracies included in total sense voltage accuracies
Accuracies included in total sense voltage accuracies
VISET
0.25
1.25
V
5 mV to 25 mV VSENSE current limit
100
nA
IISET
10
8
7
−20
12
14
10
9
−30
V
V
V
μA
VISET ≤ VVCAP
Maximum voltage on the gate is always clamped to ≤31 V
ΔVGATE = VGATE − VOUT
20 V ≥ VCC ≥ 8 V; IGATE ≤ 5 μA
VHS+ = VCC = 5 V; IGATE ≤ 5 μA
VHS+ = VCC = 4.5 V; IGATE ≤ 1 μA
VGATE = 0 V
45
5
750
60
10
1500
75
15
2250
μA
mA
mA
VGATE ≥ 2 V; VISET = 1.0 V; (VHS+ − VHS−) = 30 mV
VGATE ≥ 2 V
VGATE ≥ 12 V; VCC ≥ 12 V
ΔVGATE
IGATEUP
IGATEDN
IGATEDN_REG
IGATEDN_SLOW
IGATEDN_FAST
Rev. C | Page 4 of 61
Data Sheet
Parameter1
GATE Holdoff Resistance
HOT SWAP SENSE VOLTAGE
Hot Swap Sense Voltage
Current Limit
A Grade and AA Grade
B Grade Only
Constant Power Inactive
A Grade and AA Grade
ADM1278
Symbol
Min
Typ
20
Max
Unit
Ω
Test Conditions/Comments
VCC = 0 V, VGATE = 2 V
19.75
19.6
20
20
20.25
20.4
mV
mV
24.75
19.75
14.75
24.6
19.6
14.6
25
20
15
25
20
15
25.25
20.25
15.25
25.4
20.4
15.4
mV
mV
mV
mV
mV
mV
9.25
4.65
1.7
9
4.6
1.4
10
5
2
10
5
2
10.75
5.35
2.3
11
5.4
2.6
mV
mV
mV
mV
mV
mV
VISET > 1.65 V; VGATE = (VHS+ + 3 V); IGATE = 0 μA
VISET > 1.65 V; VGATE = (VHS+ + 3 V); IGATE = 0 μA
VGATE = (VHS+ + 3 V); IGATE = 0 μA; VDS = (HS−) − VOUT
VISET = 1.25 V; VDS < 2 V
VISET = 1.0 V; VDS < 2 V
VISET = 0.75 V; VDS < 2 V
VISET = 1.25 V; VDS < 2 V
VISET = 1.0 V; VDS < 2 V
VISET = 0.75 V; VDS < 2V
FET power limit = (VPSET × 8)/(50 × RSENSE); constant power
active when VDS > (VPSET × 8)/ISET
VISET > 1.65 V; VPSET = 0.25 V; VDS = 4 V
VISET > 1.65 V; VPSET = 0.25 V; VDS = 8 V
VISET > 1.65 V; VPSET = 0.25 V; VDS = 20 V
VISET > 1.65 V; VPSET = 0.25 V; VDS = 4 V
VISET > 1.65 V; VPSET = 0.25 V; VDS = 8 V
VISET > 1.65 V; VPSET = 0.25 V; VDS = 20 V
4.7
3.7
4.5
3.5
5
4
5
4
5.3
4.3
5.5
4.5
mV
mV
mV
mV
STRT_UP_IOUT_LIM = 3; VISET > 1.65 V
VISTART = 0.2 V
STRT_UP_IOUT_LIM = 3; VISET > 1.65 V
VISTART = 0.2 V
1.6
1.4
0.6
2
2
0.88
2.4
2.6
1.12
mV
mV
mV
VISTART = 0 V or STRT_UP_IOUT_LIM = 0
VISTART = 0 V or STRT_UP_IOUT_LIM = 0
Circuit breaker trip voltage, VCB = VSENSECL − VCBOS
23
28
38
43
20
25
35
40
100
530
25
30
40
45
25
30
40
45
27
32
42
47
30
35
45
50
220
900
mV
mV
mV
mV
mV
mV
mV
mV
ns
ns
VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (125%)
VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (150%)
VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (200%)
VISET > 1.65 V; VPSET > 1.1 V; default at power-up (225%)
VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (125%)
VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (150%)
VISET > 1.65 V; VPSET > 1.1 V; optional select PMBus (200%)
VISET > 1.65 V; VPSET > 1.1 V; default at power-up (225%)
VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
320
1000
ns
ns
VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
VSENSE_HS step = 18 mV to (2 mV above VSENSEOC_MAX)
1.25
100
V
V/V
nA
Tie ISTART to VCAP to disable start-up current limit
Accuracies included in total sense voltage accuracies
VISTART ≤ VVCAP
−4
−63
μA
μA
Initial power-on reset; VTIMER = 0.5 V
Overcurrent fault; 0.2 V ≤ VTIMER ≤ 1 V
VSENSECL
B Grade Only
Constant Power Active
A Grade and AA Grade
B Grade Only
Start-Up Current Limit
A Grade and AA Grade
VISTARTCL
B Grade Only
Start-Up Current-Limit Clamp
A Grade and AA Grade
B Grade Only
Circuit Breaker Offset
SEVERE OVERCURRENT
Voltage Threshold
A Grade and AA Grade
VISTARTCL_CLAMP
VCBOS
VSENSEOC
B Grade Only
Short Glitch Filter Duration
Long Glitch Filter Duration
(Default)
Response Time
Short Glitch Filter
Long Glitch Filter
ISTART PIN
Active Range
Gain of Current Sense Amplifier
Input Current
TIMER PIN
TIMER Pull-Up Current
Power-On Reset (POR)
Overcurrent (OC) Fault
200
630
0.1
AVCSAMP
IISTART
ITIMERUPPOR
ITIMERUPFLT
50
−2
−57
−3
−60
Rev. C | Page 5 of 61
ADM1278
Parameter1
TIMER Pull-Down Current
Retry
Hold
TIMER High Threshold
TIMER Low Threshold
TIMER Glitch Filter
Minimum POR Duration
PSET PIN
Reference Select Threshold
Gain of Current Sense Amplifier
Input Current
VOUT PIN
Input Current
FAULT PIN
Output Low Voltage
Data Sheet
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
ITIMERDNRT
ITIMERDNHOLD
VTIMERH
VTIMERL
TIMERGF
1.7
2
100
1.0
0.2
10
27
2.3
μA
μA
V
V
μs
ms
After fault when GATE is off; VTIMER = 0.5 V
Holds TIMER at 0 V when inactive; VTIMER = 0.5 V
1.5
50
1.65
VPSETRSTH
AVCSAMP
IPSET
0.98
0.18
1.35
100
V
V/V
nA
Minimum initial insertion delay regardless of CTIMER value
FET power limit = (VPSET × 8)/(50 × RSENSE)
If VPSET > VPSETRSTH, constant power is disabled
Accuracies included in total sense voltage accuracies
VPSET ≤ VVCAP
40
μA
VOUT = 20 V
0.4
1.5
100
1
V
V
nA
μA
IFAULT = 1 mA
IFAULT = 5 mA
VFAULT ≤ 2 V; FAULT output high-Z
VFAULT = 20 V; FAULT output high-Z
0.8
1
V
V
μs
Latch off when high; internal pull-up sets this as default
10 second automatic retry when pin pulled low
1
8
V
V
μs
μA
V/V
%
%
mV
mA
CSOUT = VSENSE_HS × 350; VCC > CSOUT + 2 V
VSENSE_HS = 20 mV; ICSOUT ≤ 1 mA; CCSOUT = 1 nF
VSENSE_HS = 10 mV; ICSOUT ≤ 1 mA; CCSOUT = 1 nF
CSOUT short-circuit current
V
V
nA
μA
V
V
μs
IGPO1 = 1 mA
IGPO1 = 5 mA
VGPO1 ≤ 2 V; GPO1 output high-Z
VGPO1 = 20 V; GPO1 output high-Z
Configured as CONV
Configured as CONV
Configured as CONV
VOL_LATCH
Leakage Current
ENABLE PIN
Input High Voltage
Input Low Voltage
Glitch Filter
RETRY PIN
Input High Voltage
Input Low Voltage
Glitch Filter
Internal Pull-Up Current
CSOUT PIN
CSOUT Gain
Total Output Error
Output Swing to GND
Current Limiting
GPO1/ALERT1/CONV PIN
Output Low Voltage
VIH
VIL
VIH
VIL
1.1
1.1
0.8
350
−1.6
−3.0
+1.6
+3.0
40
5
VOL_GPO1
0.4
1.5
100
1
Leakage Current
Input High Voltage
Input Low Voltage
Glitch Filter
GPO2/ALERT2 PIN
Output Low Voltage
VIH
VIL
1.1
0.8
1
VOL_GPO2
0.4
1.5
100
1
V
V
nA
μA
IGPO2 = 1 mA
IGPO2 = 5 mA
VGPO2 ≤ 2 V; GPO2 output high-Z
VGPO2 = 20 V; GPO2 output high-Z
VOL_PWRGD
0.4
1.5
V
V
V
IPWRGD = 1 mA
IPWRGD = 5 mA
ISINK = 100 μA; VOL_PWRGD = 0.4 V
100
1
nA
μA
VPWRGD ≤ 2 V; PWRGD output high-Z
VPWRGD = 20 V; PWRGD output high-Z
Leakage Current
PWRGD PIN
Output Low Voltage
VCC That Guarantees Valid
Output
Leakage Current
1.02
0.22
1
Rev. C | Page 6 of 61
Data Sheet
Parameter1
PWGIN PIN
Input Current
PWGIN Threshold
A Grade and AA Grade
B Grade Only
PWGIN Threshold Hysteresis
Glitch Filter
CURRENT AND VOLTAGE
MONITORING
ADC Conversion Time
ADRx PINS
Address Set to 00
Input Current for Address Set
to 00
Address Set to 01
Address Set to 10
Address Set to 11
Input Current for Address Set
to 11
TEMP PIN
Operating Range
Accuracy
Resolution
Output Current Source2
Low Level
Medium Level
High Level
Maximum Series Resistance
for External Diode2
Maximum Parallel
Capacitance for External
Diode2
SPI DIGITAL INPUTS (SPI_SS,
MCLK, MDAT)
Input High Voltage
Input Low Voltage
Output Low Voltage
Leakage Current
Data Rate
SERIAL BUS DIGITAL INPUTS
(SDA, SCL)
Input High Voltage
Input Low Voltage
Output Low Voltage
Input Leakage
ADM1278
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
50
nA
PWGIN ≤ 3.6 V
1.0
1.0
60
1
1.01
1.03
70
V
V
mV
μs
PWGIN falling
PWGIN falling
144
165
μs
64
73
μs
64
73
μs
0.8
V
μA
Connect to GND
VADRx = 0 V to 0.8 V
150
165
+1
3
10
kΩ
μA
V
μA
°C
°C
°C
Resistor to GND
No connect state; maximum leakage current allowed
Connect to VCAP
VADRx = 2.0 V to VCAP; must not exceed the maximum
allowable current draw from VCAP
External transistor is 2N3904
Limited by external diode
TA = TDIODE = −40°C to +85°C
LSB size
For