FEATURES
FUNCTIONAL BLOCK DIAGRAMS
VDD1
VDD2
ADM2461E
DIGITAL ISOLATION
RS-485 TRANSCEIVER
RxD
R
DE
CABLE
INVERT
D
TxD
INV
GND1
Figure 1. ADM2461E Functional Block Diagram
VDD1
VDD2
ADM2463E
RE
DIGITAL ISOLATION
RS-485 TRANSCEIVER
R
RxD
CABLE
INVERT
D
TxD
DE
GND1
ISOLATION
BARRIER
GND2
A
B
Z
Y
21430-001
Heating, ventilation, and air conditioning (HVAC) networks
Industrial field buses
Building automation
Utility networks
A
GND2
ISOLATION
BARRIER
INVR
APPLICATIONS
B
21430-002
RE
IEC 61000-4-2 ESD PROTECTION
5.7 kV rms, signal isolated RS-485/RS-422 transceiver
Low radiated emissions, passes EN55032 Class B with margin
on a 2-layer PCB
Cable inversion smart feature
Correction for reversed cable connection on A, B, Y, and Z bus
pins while maintaining full receiver fail-safe
ESD protection on the RS-485 A, B, Y, and Z bus pins
≥±12 kV IEC61000-4-2 contact discharge
≥±15 kV IEC61000-4-2 air discharge
Low speed 500 kbps data rate for EMI control
Flexible power supply inputs
Primary VDD1 supply of 1.7 V to 5.5 V
Isolated VDD2 supply of 3.0 V to 5.5 V
Profibus® compliant for 5 V VDD2
Wide −40°C to +125°C operating temperature range
High common-mode transient immunity: >250 kV/μs
Short-circuit, open-circuit, and floating input receiver fail-safe
Supports 192 bus nodes (72 kΩ receiver input impedance)
Full hot swap support (glitch free power-up and power-down)
Safety and regulatory approvals (pending)
CSA Component Acceptance Notice 5A, DIN V VDE V 0884-11,
UL 1577, CQC11-471543-2012, IEC 61010-1
16-lead, wide body, SOIC_W package with >8.0 mm
creepage and clearance in standard pinout
IEC 61000-4-2 ESD PROTECTION
Data Sheet
500 kbps, 5.7 kV RMS, Signal Isolated
RS-485 Transceiver with ±15 kV IEC ESD
ADM2461E/ADM2463E
Figure 2. ADM2463E Functional Block Diagram
GENERAL DESCRIPTION
The ADM2461E/ADM2463E are 500 kbps, 5.7 kV rms, signal
isolated RS-485 transceivers that pass radiated emissions testing to
the EN55032 Class B standard with margin on a 2-layer printed
circuit board (PCB). The ADM2461E/ADM2463E isolation
barrier provides robust immunity to noise and system level EMC
events. The devices are protected against ≥±12 kV contact and ≥
±15 kV air IEC61000-4-2 electrostatic discharge (ESD) events
on the RS-485 A, B, Y, and Z pins. The devices feature cable invert
pins to allow quick correction of the reversed cable connection
on the A, B, Y, and Z bus pins while maintaining full receiver
fail-safe performance.
Rev. 0
These devices are optimized for low speed over long cable runs
and have a maximum data rate of 500 kbps. The high differential
output voltage makes these devices suitable for Profibus nodes
when powered with 5 V on the VDD2 supply. The VDD1 primary
supply and VDD2 isolated supply both support a wide range of
voltages (1.7 V to 5.5 V and 3 V to 5.5 V, respectively). Halfduplex and full duplex device options are available in the industry
standard 16-lead, wide-body, standard SOIC_W package with
>8.0 mm creepage and clearance.
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ADM2461E/ADM2463E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 16
Applications ...................................................................................... 1
Robust Low Power Digital Isolator.......................................... 16
Functional Block Diagrams............................................................. 1
High Driver Differential Output Voltage ............................... 16
General Description ......................................................................... 1
IEC61000-4-2 ESD Protection ................................................. 16
Revision History ............................................................................... 2
Truth Tables ................................................................................ 17
Specifications .................................................................................... 3
Receiver Fail-Safe ....................................................................... 17
Timing Specifications .................................................................. 4
Driver and Receiver Cable Inversion ...................................... 18
Package Characteristics ............................................................... 6
Hot Swap Inputs ......................................................................... 18
Regulatory Information............................................................... 6
192 Transceivers on the Bus ..................................................... 18
Insulation and Safety Related Specifications ............................ 6
Driver Output Protection ......................................................... 18
DIN V VDE 0884-11 (VDE 0884-11) Insulation Characteristics
(Pending) ........................................................................................ 7
Applications Information ............................................................. 19
Absolute Maximum Ratings ........................................................... 8
Maximum Data Rate vs. Ambient Temperature ................... 19
Thermal Resistance ...................................................................... 8
Isolated Profibus Solution......................................................... 19
Electrostatic Discharge (ESD) Ratings ...................................... 8
EMC, EFT, and Surge Protection ............................................ 19
ESD Caution.................................................................................. 8
Insulation Lifetime ..................................................................... 19
Pin Configurations and Function Descriptions ........................... 9
Outline Dimensions ....................................................................... 21
Typical Performance Characteristics ........................................... 11
Ordering Guide .......................................................................... 21
PCB Layout and Electromagnetic Interference (EMI) ......... 19
Test Circuits and Switching Characteristics ............................... 15
REVISION HISTORY
6/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 21
Data Sheet
ADM2461E/ADM2463E
SPECIFICATIONS
All voltages are relative to the respective ground, 1.7 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 5.5 V, TA = TMIN (−40°C) to TMAX (+125°C). All
minimum and maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical
specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V, unless otherwise noted.
Table 1.
Parameter
PRIMARY SIDE SUPPLY CURRENT
ISOLATED SIDE SUPPLY CURRENT
Symbol
IDD1 (Q)
IDD1
IDD2 (Q)
Min
Typ
0.6
2
5
5
6
6
58
Max
1
8
8
8
9
9
78
Unit
mA
mA
mA
mA
mA
mA
mA
100
145
mA
2.0
1.5
2.1
1.5
2.5
2.1
3.3
2.1
VDD2
VDD2
VDD2
VDD2
V
V
V
V
2.1
3.3
VDD2
0.2
V
V
1.5
3.0
0.2
+250
50
V
V
mA
μA
IDD2
ISOLATED SIDE DYNAMIC SUPPLY
CURRENT
DRIVER DIFFERENTIAL OUTPUTS
Differential Output Voltage, Loaded
IDD2 (DYN)
|VOD2|
Over Common-Mode Range
|VOD3|
Δ|VOD2| for Complementary Output
States
Common-Mode Output Voltage
Δ|VOC| for Complementary Output States
Short-Circuit Output Current
Output Leakage Current (Y, Z)1
Δ|VOD2|
VOC
Δ|VOC|
IOS
IO
Pin Capacitance (A, B, Y, Z)
RECEIVER DIFFERENTIAL INPUTS
Differential Input Threshold Voltage,
Noninverted
Differential Input Threshold Voltage,
Inverted
Input Voltage Hysteresis
Input Current (A, B)
VTH
+10
μA
28
pF
VIN = 0.4sin(10πt × 106)
1
CIN
−200
−125
−30
mV
−7 V < VCM < +12 V, INV or INVR = 0 V
30
125
200
mV
−7 V < VCM < +12 V, INV or INVR = VDD1
mV
μA
μA
pF
−7 V < VCM < +12 V
DE = 0 V, VDD2 = 0 V or 5.5 V, VIN = 12 V
DE = 0 V, VDD2 = 0 V or 5.5 V, VIN = −7 V
VIN = 0.4sin(10πt × 106)
V
DE, RE, TxD, INV, INVR
+2
+30
V
μA
μA
DE, RE, TxD, INV, INVR
DE, RE, TxD, VIN = 0 V or VDD1
INV, INVR, VIN = 0 V or VDD1
0.4
V
0.4
0.2
V
V
VDD1 = 3.6 V, output current (IOUT) = 2.0 mA,
differential input voltage (VID) ≤ −0.2 V
VDD1 = 2.7 V, IOUT = 1.0 mA, VID ≤ −0.2 V
VDD1 = 1.95 V, IOUT = 500 μA, VID ≤ −0.2 V
VHYS
II
25
167
−133
Pin Capacitance (A, B)
DIGITAL LOGIC INPUTS
Input Low Voltage
CIN
Input High Voltage
Input Current
VIH
II
RxD DIGITAL OUTPUT
Output Voltage Low
4
0.3 ×
VDD1
VIL
VOL
VDD2 ≥ 3.0 V, RL = 100 Ω, see Figure 31
VDD2 ≥ 3.0 V, RL = 54 Ω, see Figure 31
VDD2 ≥ 4.5 V, RL = 54 Ω, see Figure 31
VDD2 ≥ 3.0 V, −7 V ≤ common-mode voltage
(VCM) ≤ +12 V, see Figure 32
VDD2 ≥ 4.5 V, −7 V ≤ VCM ≤ +12 V, see Figure 32
RL = 54 Ω or 100 Ω, see Figure 31
RL = 54 Ω or 100 Ω, see Figure 31
RL = 54 Ω or 100 Ω, see Figure 31
−7 V < output voltage (VOUT) < +12 V
DE = RE = 0 V, VDD2 = 0 V or 5.5 V,
input voltage (VIN) = 12 V
DE = RE = 0 V, VDD2 = 0 V or 5.5 V, VIN = −7 V
−250
−50
Test Conditions/Comments
DE = 0 V
DE = VDD1
VDD2 ≤ 3.6 V, DE = 0 V
VDD2 ≥ 4.5 V, DE = 0 V
VDD2 ≤ 3.6 V, DE = VDD1
VDD2 ≥ 4.5 V, DE = VDD1
VDD2 ≤ 3.6 V, load resistance (RL) = 54 Ω, DE =
VDD1, data rate = 500 kbps
VDD2 ≥ 4.5 V, RL = 54 Ω, DE = VDD1, data rate =
500 kbps
0.7 × VDD1
−2
−2
+0.01
+10
Rev. 0 | Page 3 of 21
ADM2461E/ADM2463E
Data Sheet
Parameter
Output Voltage High
Short-Circuit Current
Three-State Output Leakage Current
Symbol
VOH
Min
2.4
2.0
VDD1 − 0.2
Typ
Max
IOZR
−1
+0.01
100
+1
COMMON-MODE TRANSIENT IMMUNITY
(CMTI)2
1
2
250
Unit
V
V
V
mA
μA
Test Conditions/Comments
VDD1 = 3.0 V, IOUT = −2.0 mA, VID ≥ −0.03 V
VDD1 = 2.3 V, IOUT = −1.0 mA, VID ≥ −0.03 V
VDD1 = 1.7 V, IOUT = −500 μA, VID ≥ −0.03 V
VOUT = GND1 or VDD1, RE = 0 V
RE = VDD1, RxD = 0 V or VDD1
kV/μs
VCM ≥ ±1 kV, transient magnitude measured
between 20% and 80% of VCM , see Figure 37
and Figure 38
ADM2463E only.
The CMTI is the maximum common-mode voltage slew rate that can be sustained while maintaining specification compliant operation. VCM is the common-mode
potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew
rates apply to rising and falling common-mode voltage edges.
TIMING SPECIFICATIONS
VDD1 = 1.7 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All typical specifications are at
TA = 25°C, VDD1 = VDD2 = 3.3 V, unless otherwise noted.
Table 2.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay
Output Skew
Rise Time and Fall Time
Enable Time
Disable Time
RECEIVER
Propagation Delay
Output Skew
Enable Time
Disable Time
RECEIVER CABLE INVERT (INVR, INV)
Propagation Delay
DRIVER CABLE INVERT (INV)
Propagation Delay
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
230
3
400
150
1700
400
100
800
1000
2200
kbps
ns
ns
ns
ns
ns
RL = 54 Ω, CL = 100 pF, see Figure 33 and Figure 3.
RL = 54 Ω, CL = 100 pF, see Figure 33 and Figure 3.
RL = 54 Ω, CL = 100 pF, see Figure 33 and Figure 3.
RL = 110 Ω, CL = 50 pF, see Figure 34 and Figure 5.
RL = 110 Ω, CL = 50 pF, see Figure 34 and Figure 5.
tRPLH, tRPHL
tSKEW
tZL, tZH
tLZ, tHZ
30
2.5
3
8
200
50
50
50
ns
ns
ns
ns
CL = 15 pF, see Figure 35 and Figure 4.
CL = 15 pF, see Figure 35 and Figure 4.
RL = 1 kΩ, CL = 15 pF, see Figure 36 and Figure 6.
RL = 1 kΩ, CL = 15 pF, see Figure 36 and Figure 6.
tINVRPHL, tINVRPLH
20
40
ns
VID ≥ −200 mV or VID ≤ +200 mV, see Figure 7.
tINVDPHL, tINVDPLH
230
400
ns
TxD = 0 V or TxD = VDD1, see Figure 8.
500
tDPLH, tDPHL
tSKEW
tDR, tDF
tZL, tZH
tLZ, tHZ
200
Rev. 0 | Page 4 of 21
Data Sheet
ADM2461E/ADM2463E
Timing Diagrams
VDD1
TxD
VDD1 /2
VDD1 /2
0V
tDPHL
VO/2
VDD1
tSKEW = │tDPLH – tDPHL │
RE
VO
VDD1 /2
Y
+VO
90% POINT
90% POINT
VDIFF = V(Y) – V(Z)
10% POINT
VDD1 /2
RxD
tZH
tDF
RxD
21430-012
tDR
NOTES
1. Y = A, Z = B FOR ADM2461E/ADM2463E
VOL + 0.5V
OUTPUT LOW
10% POINT
0V
tLZ
tZL
A–B
OR Y – B
–VO
VDD1 /2
OUTPUT HIGH
VOL
tHZ
VOH
VOH – 0.5V
VDD1 /2
21430-015
tDPLH
Z
0V
Figure 6. Receiver Enable or Disable Timing
Figure 3. Driver Propagation Delay, Rise and Fall Timing
VDD1
0V
VDD1 /2
0V
0V
tINVRPHL
tINVRPLH
VOH
tRPHL
tRPLH
VDD1 /2
VDD1 /2
VDD1 /2
RxD (V ID ≥ +200mV)
VOL
VOH
RxD (V ID ≤ –200mV)
tSKEW = |tRPLH – tRPHL |
VOL
VDD1/2
VDD1 /2
VOL
21430-016
VDD1 /2
21430-013
VDD1 /2
RxD
VOH
NOTES
1. INVR = INV FOR ADM2461E/ADM2463E
Figure 4. Receiver Propagation Delay
Figure 7. Receiver Cable Invert Timing Specification Measurement
V DD1
VDD1
DE
VDD1 /2
INV
VDD1 /2
VDD1 /2
0V
tZL
tINVDPLH
tLZ
Z
|VOD|
0.5 (VDD2 + VOL)
Y, Z
VOL+ 0.5V
Y
NOTES
1. Y = A, Z = B FOR ADM2461E/ADM2463E
1/2|VO|
|VOD|
VOH – 0.5V
TxD = 1
Z
21430-014
VOH/2
1/2|VO|
Y
tHZ
VOH
Y, Z
tINVDPHL
TxD = 0
VOL
tZH
VDD1 /2
NOTES
1. Y = A, Z = B FOR ADM2461E/ADM2463E
Figure 8. Driver Cable Invert Timing Specification Measurement
Figure 5. Driver Enable or Disable Timing
Rev. 0 | Page 5 of 21
21430-017
A–B
INVR
ADM2461E/ADM2463E
Data Sheet
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
1
2
Symbol
RI-O
CI-O
CI
Min
Typ
1013
2.2
3.0
Max
Unit
Ω
pF
pF
Test Conditions/Comments
Test frequency = 1 MHz
The device is considered a 2-terminal device. Short together Pin 1 through Pin 8 and short together Pin 9 through Pin 16 to set the device up as a 2-terminal device during testing.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
For additional information, see www.analog.com/icouplersafety.
Table 4. ADM2461E/ADM2463E Approvals
UL (Pending)
Recognized Under UL 1577
Component Recognition
Protection1
Single Protection, 5700 V rms
File (pending)
1
2
CSA (Pending)
Approved under CSA Component
Acceptance Notice 5A
VDE (Pending)
To be certified under
DIN V VDE 0884-112
CQC (Pending)
Certified under CQC11471543-2012
CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2
Basic insulation at 800 V rms (1131 V peak)
Basic insulation
GB4943.1-2011
Working voltage (VIOWM) = 875 V rms
Reinforced insulation at 400 V rms
(565 V peak)
CSA 62368-1-14, EN 62368-1:2014/A11:2017
and IEC 62368-1: 2014 second edition
Basic insulation at 800 V rms
(1131 V peak)
Reinforced insulation at 400 V rms
(565 V peak)
IEC 60601-1 Edition 3.1
1 means of patient protection
(1 MOPP), 400 V rms (565 V peak)
2 MOPP, 250 V rms (353 V peak)
1 MOPP or 2 MOPP, 400 V rms (565 V peak)
CSA 61010-1-12 and IEC 61010-1 third edition
Basic insulation at 300 V rms mains, 800 V rms
(1131 V peak) from secondary circuit
Reinforced insulation at 300 V rms mains,
400 V rms (565 V peak) from secondary circuit
File (pending)
Repetitive maximum voltage (VIORM) = 1237 V peak
Basic insulation at 800 V rms
(1131 V peak)
Reinforced insulation at
400 V rms (565 V peak)
Surge isolation voltage (VIOSM) = 10 kV peak
Highest allowable overvoltage (VIOTM) = 8000 V peak
Reinforced insulation
VIOWM = 750 V rms
VIORM = 1060 V peak
VIOSM = 6.25 kV peak
VIOTM = 8000 V peak
File (pending)
File (pending)
In accordance with UL 1577, each ADM2461E/ADM2463E is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec.
In accordance with DIN V VDE 0884-11, each ADM2461E/ADM2463E is proof tested by applying an insulation test voltage ≥ 2320 V peak for 1 sec (partial discharge
detection limit = 5 pC).
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 5. Critical Safety Related Dimensions and Material Properties
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
5700
8.3
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
8.3
mm
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
L (PCB)
8.1
mm
CTI
43
>600
I
μm min
V
Rev. 0 | Page 6 of 21
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals, shortest
distance through air
Measured from input terminals to output terminals, shortest
distance along body
Measured from input terminals to output terminals, shortest
distance through air, line of sight, in the PCB mounting plane
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110: 1989-01, Table 1)
Data Sheet
ADM2461E/ADM2463E
DIN V VDE 0884-11 (VDE 0884-11) INSULATION CHARACTERISTICS (PENDING)
The ADM2461E/ADM2463E are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety
data must be ensured by means of protective circuits.
Table 6.
Description
CLASSIFICATIONS
Installation Classification per DIN VDE 0110
for Rated Mains Voltage
≤600 V rms
≤750 V rms
≤875 V rms
Climatic Classification
Pollution Degree
VOLTAGE
Maximum Working Insulation Voltage
Test Conditions/Comments
Symbol
Reinforced insulation
Reinforced insulation
Basic insulation
Maximum DC Working Insulation Voltage
Input to Output Test Voltage
Method b1
Unit
I to IV
I to III
I to IV
40/125/21
2
DIN VDE 0110, see Table 1
Maximum Repetitive Peak Insulation Voltage
Characteristic
Basic insulation
Reinforced insulation
Basic insulation
Reinforced insulation
Basic insulation
Reinforced insulation
VIOWM
875
750
1237
1060
1237
1060
V rms
V rms
V peak
V peak
V dc
V dc
VIORM × 1.875 = VPR, 100% production tested,
tm = 1 sec, partial discharge < 5 pC
2320
V peak
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
Transient overvoltage, tTR = 10 sec
Peak voltage (VPEAK) = 10 kV, 1.2 μs rise time, 50 μs,
50% fall time
VPEAK = 10 kV, 1.2 μs rise time, 50 μs, 50% fall time
Maximum value allowed in the event of a failure
1856
V peak
1485
V peak
VIOTM
VIOSM
8000
10,000
V peak
V peak
VIOSM
6250
V peak
TS
PS
RS
150
1.95
>109
°C
W
Ω
VIORM
VIOWM (DC)
VPR
Method a
After Environmental Tests, Subgroup 1
After Input and/or Safety Test,
Subgroup 2/Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage, Basic
Surge Isolation Voltage, Reinforced
SAFETY-LIMITING VALUES
Case Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
VIO = 500 V
3.0
2.7
SAFE LIMITING POWER (W)
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0
0
50
100
AMBIENT TEMPERATURE (°C)
150
21430-003
0.3
Figure 9. Thermal Derating Curve for 16-Lead, Standard, Wide Body SOIC_W, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10
Rev. 0 | Page 7 of 21
ADM2461E/ADM2463E
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
the respective ground.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Table 7.
Parameter
VDD1 to GND1
VDD2 to GND2
Digital Input Voltage (DE, RE, TxD, INV,
and INVR)
Digital Output Voltage (RxD)
Driver Output/Receiver Input Voltage
(A, B, Y, and Z)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.5 V to +7 V
−0.5 V to +7 V
−0.3 V to VDD1 + 0.3 V
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
International Electrotechnical Commission (IEC) electromagnetic
compatibility: Part 4-2 (IEC) per IEC 61000-4-2.
ESD Ratings for ADM2461E/ADM2463E
−0.3 V to VDD1 + 0.3 V
−9 V to +14 V
Table 9. ADM2461E/ADM2463E, 16-Lead SOIC_W
ESD Model
HBM
CDM
IEC1
−40°C to +125°C
−55°C to +150°C
260°C
215°C
220°C
1
2
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Withstand Threshold (V)
±4000
±1250
≥±12,000 (contact discharge) to GND2
≥±15,000 (air discharge) to GND2
≥±8,000 (contact/air discharge) to GND1
Class
3A
C5
Level 4
Level 4
Level 42
Pin A, Pin B, Pin Y, and Pin Z only.
Limited by clearance across isolation barrier.
ESD CAUTION
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
Table 8. Thermal Resistance
Package Type
RW-161
1
θJA
63.9
Unit
°C/W
Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with no bias. See JEDEC JESD-51.
Table 10. Maximum Continuous Working Voltage1, 2
Parameter
AC Voltage (Bipolar)
Basic Insulation
Reinforced Insulation
AC Voltage (Unipolar)
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
2
Max
Unit
Reference Standard
1237
1060
V peak
V peak
50-year minimum lifetime
50-year minimum lifetime
2474
1355
V peak
V peak
50-year minimum lifetime
Lifetime limited by package creepage per
IEC60664-1
1237
830
V dc
V dc
50-year minimum lifetime
Lifetime limited by package creepage per
IEC60664-1
The maximum continuous working voltage refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Values are quoted for Material Group I, Pollution Degree II.
Rev. 0 | Page 8 of 21
Data Sheet
ADM2461E/ADM2463E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
16 VDD2
GND1 2
15 GND2
RE 4
DE 5
ADM2461E
14 NIC
13 B
TOP VIEW
(Not to Scale) 12 A
TxD 6
11 NIC
INV 7
10 NIC
GND1 8
9
GND2
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
21430-005
RxD 3
Figure 10. ADM2461E Half-Duplex Pin Configuration
Table 11. ADM2461E Pin Function Descriptions
Pin No.
1
Mnemonic
VDD1
2, 8
3
GND1
RxD
4
RE
5
DE
6
TxD
7
INV
9, 15
10, 11, 14
12
13
16
GND2
NIC
A
B
VDD2
Description
1.7 V to 5.5 V Flexible Primary Side Power Supply. Connect a 0.1 μF decoupling capacitor between Pin 1 and Pin 2
to decouple the two supplies. An additional 10 μF decoupling capacitor can be connected between Pin 1 and Pin
2 to improve noise immunity in noisy environments.
Ground 1, Logic Side.
Receiver Output Data. When the INV pin is logic low, this output is high when A – B ≥ −30 mV and low when A – B ≤
–200 mV. When the INV pin is logic high, this output is high when A – B ≤ 30 mV and low when A – B ≥ 200 mV.
When the RE pin is driven high, the receiver disables and this output is tristated.
Receiver Enable Input. This pin is an active low input. Drive this input low to enable the receiver. Drive this input
high to disable the receiver.
Driver Output Enable. A high level on this pin enables the driver differential outputs, A and B. A low level on this
pin places the outputs in a high impedance state.
Transmit Data Input. Data to be transmitted by the driver is applied to this input. When the INV pin is logic high,
the data applied to this input is inverted.
Cable Invert Input. This pin is an active high input. Drive this pin high to invert the TxD signal applied and invert
the A and B receiver inputs to correct for reversed cable installation. This pin is pulled internally to ground
through a high impedance. If the cable invert function is not used, connect this pin to GND1.
Isolated Ground 2 for the Integrated RS-485 Transceiver, Bus Side.
Not Internally Connected.
Driver Noninverting Output/Receiver Noninverting Input.
Driver Inverting Output/Receiver Inverting Input.
3.0 V to 5.5 V Isolated Side Power Supply. Connect a decoupling capacitor of 0.1 μF between Pin 16 and Pin 15 to
decouple the two supplies. An additional 10 μF decoupling capacitor can be connected between Pin 16 and Pin
15 to improve noise immunity in noisy environments.
Rev. 0 | Page 9 of 21
ADM2461E/ADM2463E
Data Sheet
VDD1 1
16 VDD2
GND1 2
15 GND2
RE 4
DE 5
TxD 6
INVR 7
GND1 8
ADM2463E
14 A
13 B
TOP VIEW
(Not to Scale) 12 Z
11 Y
10 NIC
9
GND2
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
21430-004
RxD 3
Figure 11. ADM2463E Full Duplex Pin Configuration
Table 12. ADM2463E Pin Function Descriptions
Pin No.
1
Mnemonic
VDD1
2, 8
3
GND1
RxD
4
RE
5
DE
6
7
TxD
INVR
9, 15
10
11
12
13
14
16
GND2
NIC
Y
Z
B
A
VDD2
Description
1.7 V to 5.5 V Flexible Primary Side Power Supply. Connect a 0.1 μF decoupling capacitor between Pin 1 and Pin 2
to decouple the two supplies. An additional 10 μF decoupling capacitor can be connected between Pin 1 and Pin
2 to improve noise immunity in noisy environments.
Ground 1, Logic Side.
Receiver Output Data. When the INVR pin is logic low, this output is high when the differential receiver input voltage
(A – B) ≥ −30 mV and low when A – B ≤ –200 mV. When the INVR pin is logic high, this output is high when A – B ≤
30 mV and low when A – B ≥ 200 mV. When the RE pin is driven high, the receiver disables and this output is tristated.
Receiver Enable Input. This pin is an active low input. Drive this input low to enable the receiver. Drive this input
high to disable the receiver.
Driver Output Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level on this
pin places the outputs in a high impedance state.
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Receiver Cable Invert Input. This pin is an active high input. Drive this pin high to invert the A and B receiver inputs
to correct for reversed cable installation. This pin is pulled internally to ground through a high impedance. If the
cable invert function is not used, connect this pin to GND1.
Isolated Ground 2 for the Integrated RS-485 Transceiver, Bus Side.
Not Internally Connected.
Driver Noninverting Output.
Driver Inverting Output.
Receiver Inverting Input.
Receiver Noninverting Input.
3.0 V to 5.5 V Isolated Side Power Supply. Connect a decoupling capacitor of 0.1 μF between Pin 16 and Pin 15 to
decouple the two supplies. An additional 10 μF decoupling capacitor can be connected between Pin 16 and Pin
15 to improve noise immunity in noisy environments.
Rev. 0 | Page 10 of 21
Data Sheet
ADM2461E/ADM2463E
TYPICAL PERFORMANCE CHARACTERISTICS
80
60
50
40
30
20
30
20
20
40
60
80
100
120
140
0
90
80
80
VDD2 SUPPLY CURRENT (mA)
90
50
40
30
20
–40
–20
0
20
40
60
80
100
120
140
250
300
350
400
450
500
VDD2 = 3.3V
VDD2 = 5V
70
60
50
40
30
20
0
0
50
100
150
200
250
300
350
400
450
500
DATA RATE (kbps)
Figure 13. VDD2 Supply Current vs. Temperature, Data Rate = 500 kbps, RL = 120 Ω
Figure 16. VDD2 Supply Current vs. Data Rate, TA = 25°C, RL = 120 Ω
120
140
120
VDD2 = 3.3V
VDD2 = 5V
VDD2 SUPPLY CURRENT (mA)
100
100
80
60
40
80
60
40
20
VDD2 = 3.3V
VDD2 = 5V
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
140
21430-051
0
–60
200
10
TEMPERATURE (°C)
20
150
Figure 14. VDD2 Supply Current vs. Temperature, Data Rate = 500 kbps, RL = 54 Ω
Rev. 0 | Page 11 of 21
0
0
50
100
150
200
250
300
350
400
450
500
DATA RATE (kbps)
Figure 17. VDD2 Supply Current vs. Data Rate, TA = 25°C, RL = 54 Ω
21430-048
0
–60
VDD2 = 3.3V
VDD2 = 5V
21430-050
10
100
Figure 15. VDD2 Supply Current vs. Data Rate, TA = 25°C, No Load
100
60
50
DATA RATE (kbps)
100
70
0
21430-046
0
Figure 12. VDD2 Supply Current vs. Temperature, Data Rate = 500 kbps, No Load
VDD2 SUPPLY CURRENT (mA)
40
21430-047
–20
21430-049
–40
TEMPERATURE (°C)
VDD2 SUPPLY CURRENT (mA)
50
10
10
0
–60
VDD2 = 3.3V
VDD2 = 5V
60
VDD2 SUPPLY CURRENT (mA)
70
VDD2 SUPPLY CURRENT (mA)
70
VDD2 = 3.3V
VDD2 = 5V
ADM2461E/ADM2463E
Data Sheet
5.7
0
VDD1
VDD1
VDD1
VDD1
5.3
5.1
–0.02
= 1.8V
= 2.5V
= 3.3V
= 5.0V
DRIVER OUTPUT CURRENT (A)
VDD1 SUPPLY CURRENT (mA)
5.5
4.9
4.7
4.5
4.3
VDD2 = 3.3V
VDD2 = 5.0V
–0.04
–0.06
–0.08
–0.10
1k
10k
100k
1M
10M
100M
DATA RATE (bps)
–0.12
–8
21430-024
3.9
2.6
0.12
DRIVER OUTPUT CURRENT (A)
0.14
2.5
2.4
RL = 100Ω, VDD2 = 3.3V
RL = 54Ω, VDD2 = 3.3V
2.2
2.1
2.0
–2
0
0.10
0.08
VDD2 = 3.3V
VDD2 = 5.0V
0.06
0.04
0.02
50
100
150
TEMPERATURE (°C)
0
VDD2 = 3.3V
VDD2 = 5.0V
80
60
40
2
3
4
5
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)
6
21430-025
20
DRIVER DIFFERENTIAL PROPAGATION DELAY (ns)
100
1
4
6
8
10
12
Figure 22. Driver Output Current vs. Driver Output Low Voltage
120
0
2
DRIVER OUTPUT LOW VOLTAGE (V)
Figure 19. Driver Differential Output Voltage vs. Temperature
0
0
Figure 20. Driver Output Current vs. Driver Differential Output Voltage
Rev. 0 | Page 12 of 21
250
240
tDPLH
tDPHL
230
220
210
200
190
180
–50
0
50
100
150
TEMPERATURE (°C)
Figure 23. Driver Differential Propagation Delay vs. Temperature
21430-029
0
21430-028
1.9
21430-026
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)
2.7
1.8
–50
DRIVER OUTPUT CURRENT (mA)
–4
Figure 21. Driver Output Current vs. Driver Output High Voltage
Figure 18. VDD1 Supply Current vs. Data Rate
2.3
–6
DRIVER OUTPUT HIGH VOLTAGE (V)
21430-027
4.1
Data Sheet
ADM2461E/ADM2463E
1.0
1
CHANNEL 2 (VOD2)
CH1 1.0V
CH2 1.0V
21430-030
2
2µs/DIV
0.6
0.5
0.4
0.3
0.2
0.1
5
10
15
RECEIVER OUTPUT CURRENT (mA)
Figure 26. Receiver Output Low Voltage vs. Receiver Output Current
3.5
3
2
1
–10
–5
RECEIVER OUTPUT CURRENT (mA)
0
3.0
2.5
2.0
1.5
VDD1 = 3.0V, –2mA LOAD
VDD1 = 2.3V, –1mA LOAD
VDD1 = 1.7V, –0.5mA LOAD
1.0
0.5
0
–50
0
50
100
TEMPERATURE (C)
Figure 25. Receiver Output High Voltage vs. Receiver Output Current
Rev. 0 | Page 13 of 21
Figure 27. Receiver Output High Voltage vs. Temperature
150
21430-033
RECEIVER OUTPUT HIGH VOLTAGE (V)
= 5.0V
= 3.3V
= 2.5V
= 1.8V
4
0
–15
0.7
0
21430-031
RECEIVER OUTPUT HIGH VOLTAGE (V)
5
VDD1
VDD1
VDD1
VDD1
V DD1 = 5.0V
V DD1 = 3.3V
V DD1 = 2.5V
V DD1 = 1.8V
0.8
0
Figure 24. Driver Switching at 500 kbps
6
0.9
21430-032
RECEIVER OUTPUT LOW VOLTAGE (V)
CHANNEL 1 (TxD)
ADM2461E/ADM2463E
Data Sheet
CHANNEL 1 (VID)
VDD1 = 3.6V, 2mA LOAD
VDD1 = 2.7V, 1mA LOAD
VDD1 = 1.95V, 0.5mA LOAD
100
1
80
60
CHANNEL 2 (RxD)
40
20
0
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
tDPLH
tDPHL
34
33
32
31
30
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
140
21430-035
RECEIVER PROPAGATION DELAY (ns)
36
29
–60
2µs/DIV
Figure 30. Receiver Switching at 500 kbps
Figure 28. Receiver Output Low Voltage vs. Temperature
35
CH1 1.0V
CH2 1.0V
Figure 29. Receiver Propagation Delay vs. Temperature
Rev. 0 | Page 14 of 21
21430-036
2
21430-034
RECEIVER OUTPUT LOW VOLTAGE (mV)
120
Data Sheet
ADM2461E/ADM2463E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
VOD2
RL
2
RE
VOC
Figure 36. Receiver Enable or Disable Time Measurement
(See Figure 6 for Timing Diagram)
VDD1
A OR Y
375Ω
RxD
375Ω
B OR Z
VCM
VDD1
GND1
Figure 32. Driver Voltage Measurement over
Common-Mode Range, |VOD3|
TxD
DD
GND1
GND1
120Ω
DE = VDD1
RE = GND1
21430-018
VCM ≥ 1kV
dv/dt ≥ 250kV/µs
CL
21430-008
B OR Z
Figure 37. CMTI Test Diagram, Half-Duplex
Figure 33. Driver Propagation Delay Measurement
(See Figure 3 for Timing Diagram)
B OR Z
RxD
R
15pF
GND1
VDD1
Figure 34. Driver Enable or Disable Time Measurement
(See Figure 5 for Timing Diagram)
TxD
500kbps
GND1
GND1
GND1
RE
VO
CL
21430-010
A
DD
ISOLATION
BARRIER
A
120Ω
B
Z
Y
GND2
DE = VDD1
RE = GND1
VCM ≥ 1kV
dv/dt ≥ 250kV/µs
Figure 38. CMTI Test Diagram, Full Duplex
Figure 35. Receiver Propagation Delay Time Measurement
(See Figure 4 for Timing Diagram)
Rev. 0 | Page 15 of 21
21430-019
S2
CL
50pF
VDD2
IEC 61000-4-2 ESD PROTECTION
VDD1
RL
110Ω
21430-009
S1
ADM2463E
VDD2
VOUT
A OR Y
B
B
GND2
ISOLATION
BARRIER
RL
TxD
A
CL
TxD
DE
R
15pF
GND1
500kbps
A OR Y
VDD2
ADM2461E
60Ω
21430-007
VOD3
S2
CL
RE
Figure 31. Driver Voltage Measurement, |VOD2|
TxD
RL
–1.5V
21430-006
B OR Z
VDD1
S1
21430-011
TxD
+1.5V
RL
2
IEC 61000-4-2 ESD PROTECTION
A OR Y
ADM2461E/ADM2463E
Data Sheet
THEORY OF OPERATION
ROBUST LOW POWER DIGITAL ISOLATOR
IEC61000-4-2 ESD PROTECTION
The ADM2461E/ADM2463E feature a low power, digital isolator
block to galvanically isolate the primary and secondary sides of the
device. The use of coplanar transformer coils with an on or off
keying modulation scheme allows high data throughput across
the isolation barrier while minimizing any radiated emissions.
This architecture provides a robust digital isolator with immunity
to common-mode transients >250 kV/μs across the full
temperature and supply range of the device. The digital isolator
circuitry features a flexible VDD1 power supply with an input
voltage range of 1.7 V to 5.5 V.
ESD is the sudden transfer of electrostatic charge between bodies
at different potentials, which is either caused by near contact or
induced by an electric field. ESD has the characteristics of a high
current in a short time period. The primary purpose of the
IEC61000-4-2 test is to determine system immunity to external
ESD events outside the system during operation. IEC61000-4-2
describes testing using two coupling methods: contact discharge
and air discharge. Contact discharge implies a direct contact
between the discharge gun and the equipment under test (EUT).
During air discharge testing, the charged electrode of the discharge
gun is moved toward the EUT until a discharge occurs as an arc
across the air gap. The discharge gun does not make direct contact
with the EUT during air discharge testing. Factors including
humidity, temperature, barometric pressure, distance, and rate
of approach to the EUT affect the results and repeatability of
the air discharge test. Air discharge testing is a more accurate
representation of an actual ESD event than the contact discharge
method but is not as repeatable. Therefore, contact discharge is
the preferred test method. During testing, the EUT data port is
subjected to at least 10 positive and 10 negative single discharges.
Test voltage selection depends on the system end environment.
Figure 40 shows the 8 kV contact discharge current waveform,
as described in the IEC61000-4-2 specification. Waveform
parameters include rise times of 250 kV/μs
Common-Mode Transients
IPEAK
30A
90%
HIGH DRIVER DIFFERENTIAL OUTPUT VOLTAGE
The ADM2461E/ADM2463E feature a proprietary transmitter
architecture with a low driver output impedance that results in
an increased differential output voltage. This architecture is useful
when operating the device at lower data rates over long cable
runs where the dc resistance of the transmission line dominates
the signal attenuation. In these applications, the increased
differential voltage extends the reach of the device to longer
cable lengths. When operated as a 5 V transceiver (VDD2 > 4.5 V),
the ADM2461E/ADM2463E meet or exceed the Profibus
requirement of a minimum 2.1 V differential output voltage.
I30ns 16A
I60ns
Rev. 0 | Page 16 of 21
8A
10%
30ns
60ns
tR = 0.7ns TO 1ns
Figure 40. IEC61000-4-2 ESD Waveform (8 kV)
TIME
21430-038
2
Data Sheet
ADM2461E/ADM2463E
Figure 41 shows the 8 kV contact discharge current waveform
from the IEC61000-4-2 standard compared to the HBM ESD 8 kV
waveform. Figure 41 shows that the two standards specify a
different waveform shape and peak current (IPEAK). The IPEAK
associated with an IEC61000-4-2 8 kV pulse is 30 A, whereas
the corresponding IPEAK for HBM ESD is more than five times
less at 5.33 A. The other key difference between the two standards
is the rise time of the initial voltage spike. The IEC61000-4-2
ESD waveform has a faster rise time of 1 ns compared to the
10 ns associated with the HBM ESD waveform. The amount of
power associated with an IEC ESD waveform is greater than that of
an HBM ESD waveform. The HBM ESD standard requires the
EUT to be subjected to at least three positive and three negative
discharge tests, whereas the IEC ESD standard requires the EUT to
be subjected to at least 10 positive and 10 negative discharge tests.
Table 14. Transmitting Truth Table
Supply Status
VDD1
VDD2
On
On
On
On
On
On
On
On
On
On
Off
On
X
Off
DE
H
H
H
H
L
X
X
Inputs
TxD
H
H
L
L
X
X
X
INV
L
H
L
H
X
X
X
Outputs
A or Y
B or Z
H
L
L
H
L
H
H
L
Z
Z
Z
Z
Z
Z
Table 15. Receiving Truth Table
Supply Status
VDD1
On
On
On
On
On
On
On
On
On
Off
The ADM2461E/ADM2463E are rated to ≥±12 kV contact ESD
protection and ≥±15 kV air ESD protection between the RS-485
bus pins (A, B, Y, and Z) and the GND2 pin according to the
IEC61000-4-2 standard. The isolation barrier provides ±8kV
contact protection between the bus pins and the GND1 pin. These
devices with IEC61000-4-2 ESD ratings are better suited for
operation in harsh environments when compared to other RS485 transceivers that state varying levels of HBM ESD protection.
VDD2
On
On
On
On
On
On
On
X
Off
X
Inputs
A−B
≥−0.03 V
≤0.03 V
≤−0.2 V
≥0.2 V
0.2 V < A – B < −0.03 V
0.03 V < A – B < 0.2 V
Inputs open or shorted
X
X
X
Outputs
INV or INVR
RE
L
H
L
H
L
H
L
X
X
X
L
L
L
L
L
L
L
H
L
X
RxD
H
H
L
L
I
I
H
Z
I
I
IPEAK
RECEIVER FAIL-SAFE
30A
90%
The ADM2461E/ADM2463E guarantee a logic high receiver
output when the receiver inputs are shorted, open, or connected to
a terminated transmission line with all drivers disabled. To achieve
a fail-safe logic high output when the receiver inversion feature
is disabled (INV or INVR = 0 V), the receiver input threshold is
set internally between −30 mV and −200 mV. If A – B ≥ −30 mV,
the RxD output is logic high. If A – B ≤ −200 mV, the RxD
output is logic low. To preserve the fail-safe feature when the
receiver inversion feature is enabled (INV or INVR = VDD1), the
inverted receiver input threshold is set internally between 30 mV
and 200 mV. In the case of a terminated bus with all transmitters
disabled, the termination resistor pulls the receiver differential
input voltage to 0 V, which results in a logic high RxD output
with a 30 mV minimum noise margin. This feature eliminates
the need for the external biasing components that are usually
required to implement the fail-safe feature.
IEC 61000-4-2 ESD 8kV
I30ns
16A
I60ns
8A
5.33A
HBM ESD 8kV
10ns
30ns
60ns
TIME
tR = 0.7ns TO 1ns
Figure 41. IEC61000-4-2 ESD 8 kV Waveform Compared to
HBM ESD 8 kV Waveform
TRUTH TABLES
Table 14 and Table 15 use the abbreviations defined in Table 13.
VDD1 supplies the DE, TxD, RE, RxD, INV, and INVR pins only.
Table 13. Truth Table Abbreviations
Letter
H
I
L
X
Z
Description
High level
Indeterminate
Low level
Any state
High impedance (off)
21430-039
10%
These features are fully compatible with external fail-safe
biasing configurations and can be used in applications with
legacy devices that lack fail-safe support and in applications
where additional noise margin is desired. See the AN-960
Application Note, RS-485/RS-422 Circuit Implementation
Guide, for details on external fail-safe biasing.
Rev. 0 | Page 17 of 21
ADM2461E/ADM2463E
Data Sheet
DRIVER AND RECEIVER CABLE INVERSION
HOT SWAP INPUTS
The ADM2461E/ADM2463E feature cable inversion
functionality to correct for errors during installation. This
adjustment can be implemented in the software on the controller
driving the RS-485 transceiver to avoid installation costs to fix
wiring errors. The ADM2463E full duplex transceiver features a
receiver cable invert pin, INVR, that can be used to correct
receiver functionality in cases where connections to the A and
B pins are made in reverse. The ADM2461E half-duplex
transceiver features a single cable invert logic input pin, INV, that
inverts the driver and receiver to correct for reversed connections
to the A and B pins. When the receiver is inverted, the device
maintains a Logic 1 receiver output with a 30 mV noise margin
when inputs are shorted together or open-circuit. Figure 42
shows the receiver output in inverted and noninverted cases.
When a circuit board is inserted into a powered (or hot)
backplane, parasitic coupling from supply and ground rails to
digital inputs can occur. The ADM2461E/ADM2463E contain
circuitry to ensure that the RS-485 driver outputs remain in a
high impedance state during power-up, and then default to the
correct states. For example, when VDD1 and VDD2 power up at the
same time and the RE pin is pulled low with the DE and TxD pins
pulled high, the A and B outputs remain in high impedance until
the outputs settle at an expected default high for the A pin and
expected default low for the B pin.
PHASE INVERTED RS-485
INVR = H
A–B
NONINVERTED
RS-485
INVR = L
0
+200mV
IN
+30mV
1
FAIL-SAFE
FAIL-SAFE
The standard RS-485 receiver input impedance is 12 kΩ (1 unit
load) and the standard driver can drive up to 32 unit loads.
The ADM2461E/ADM2463E transceivers have a 1/6 unit
load receiver input impedance (equivalent to 72 kΩ) that
allows up to 192 transceivers to be connected in parallel on one
communication line. Any combination of these devices and
other RS-485 transceivers with a total of 32 unit loads or fewer can
be connected to the line.
DRIVER OUTPUT PROTECTION
–30mV
1
21430-040
–200mV
0
192 TRANSCEIVERS ON THE BUS
Figure 42. Noninverted RS-485 and Phase Inverted RS-485 Comparison
The ADM2461E/ADM2463E have two methods to prevent
excessive output current and power dissipation caused either by
faults or by bus contention. Current-limit protection on the output
stage provides immediate protection against short circuits over the
entire common-mode voltage range. In addition, a thermal
shutdown circuit forces the driver outputs into a high impedance
state if the die temperature rises excessively. This circuitry disables
the driver outputs when a die temperature of 150°C is reached.
As the device cools, the drivers are re-enabled at a temperature
of 140°C.
Rev. 0 | Page 18 of 21
Data Sheet
ADM2461E/ADM2463E
APPLICATIONS INFORMATION
EMC, EFT, AND SURGE PROTECTION
MAXIMUM DATA RATE vs. AMBIENT
TEMPERATURE
Under a large current load, power dissipation within the
transceiver can limit the maximum ambient temperature
achievable while retaining a silicon junction temperature
below 150°C. This internal power dissipation is related to
application conditions including supply voltage configuration,
switching frequency, effective load on the RS-485 bus, and the
amount of time the transceiver is in transmit mode. Thermal
performance also depends on the PCB design and thermal
characteristics of a system.
For high temperature applications above 85°C with a fully
loaded RS-485 bus (equivalent to 54 Ω bus resistance) operating
with a VDD2 supply of 5 V ± 10%, limiting the transmitter data
rate to 300 kbps is recommended. The thermal resistance (θJA)
of the package can be used in conjunction with the typical
performance curves for the VDD2 supply current to calculate the
maximum data rate for a given ambient temperature.
ISOLATED PROFIBUS SOLUTION
The ADM2461E features a transceiver that meets the
requirements of an isolated Profibus node. When operating the
ADM2461E as a Profibus transceiver, ensure that the VDD2
power supply is a minimum of 4.5 V. The ADM2461E is
acceptable for use in Profibus applications as a result of the
following characteristics:
The output driver meets or exceeds the Profibus differential
output requirements. To ensure that the transmitter
differential output does not exceed 7 V p-p over all
conditions, place 10 Ω resistors in series with the A and
B transmitter outputs.
Low bus pin capacitance of 28 pF.
Class I (no loss of data) immunity to IEC61000-4-4 electrical
fast transients (EFTs) up to ±1 kV with respect to the GND2
pin can be achieved using a Profibus shielded cable. IEC
61000-4-4 Class I up to ±3 kV can be achieved with the
addition of a 470 pF capacitor connected between the
GND1 pin and the RxD output pin.
In applications where additional levels of protection against
IEC61000-4-5 EFT or IEC61000-4-4 surge events are required,
external protection circuits can be added to enhance the EMC
robustness of the device. See Figure 43 for a recommended EMC
protection circuit that uses a series of SM712 transient voltage
suppressors (TVS) and 10 Ω pulse proof resistors to achieve
Level 2 IEC61000-4-5 surge protection and an excess of Level 4
IEC61000-4-2 ESD and IEC61000-4-4 EFT protection. Table 16
and Table 17 list the recommended protection components and
protection levels for this circuit.
VDD1
VDD2
RECEIVER
RxD
DRIVER
TxD
D
GND2
GND1
A 10Ω
120Ω
B 10Ω
SM712
TVS
Z 10Ω
Y 10Ω
SM712
TVS
ISOLATION
BARRIER
21430-041
The ADM2461E/ADM2463E use a low power, on or off keying
encoding scheme for robust communication with minimal
radiated emissions. These devices can meet EN55032 and CISPR
32 Class B requirements with margin on a standard 2-layer PCB,
without the need for complex and area intensive layout techniques.
IEC 61000-4-2 ESD PROTECTION
PCB LAYOUT AND ELECTROMAGNETIC
INTERFERENCE (EMI)
Figure 43. Isolated RS-485 Solution with ESD, EFT, and Surge Protection
Table 16. Recommended Components for ESD, EFT, and
Surge Protection Solution
Recommended Components
TVS
10 Ω Pulse Proof Resistors
Part Number
CDSOT23-SM712
CRCW060310R0FKEAHP
Table 17. Protection Levels with Recommend Circuit
EMC Standard
ESD—Contact (IEC 61000-4-2)
ESD—Air (IEC 61000-4-2)
EFT (IEC 61000-4-4)
Surge (IEC 61000-4-5)
Protection Level (kV)
≥ ±30 (exceeds Level 4)
≥ ±30 (exceeds Level 4)
≥ ±4 (exceeds Level 4)
≥ ±1 (Level 2)
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period of time. The rate
of insulation degradation depends on the characteristics of the
voltage waveform applied across the insulation and on the
materials and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and is the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Rev. 0 | Page 19 of 21
ADM2461E/ADM2463E
Data Sheet
Calculation and Use of Parameters Example
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components to allow the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and can provide
adequate lifetime with smaller creepage. The minimum creepage
for a given working voltage and material group is in each system
level standard and is based on the total rms voltage across the
isolation, pollution degree, and material group. See Table 5 for
the material group and creepage information for the ADM2461E/
ADM2463E isolated RS-485 transceivers.
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation barrier is 240 V ac rms and that a 400 V dc bus voltage
is present on the other side of the isolation barrier. The isolator
material is polyimide. To establish the critical voltages in
determining the creepage, clearance, and lifetime of a device,
see Figure 44, Equation 3, and Equation 4, where VPEAK is the
peak voltage.
The lifetime of insulation caused by wear out is determined by
the insulation thickness, the material properties, and the voltage
stress applied across the insulation. Ensure that the product
lifetime is adequate at the application working voltage. The
working voltage supported by an isolator for wear out may not be
the same as the working voltage supported for tracking. The
working voltage applicable to tracking is specified in most
standards.
Testing and modeling show that the primary driver of long-term
degradation is displacement current in the polyimide insulation,
which causes incremental damage. The stress on the insulation
can be divided into broad categories such as dc stress and ac
component, time varying voltage stress. DC stress causes little
wear out because there is no displacement current. AC component,
time varying voltage stress causes wear out.
The ratings in certification documents are typically based on 60 Hz
sinusoidal stress to reflect isolation from the line voltage. However,
many practical applications have combinations of 60 Hz ac and
dc across the barrier, as shown in Equation 1. Because only the
ac portion of the stress causes wear out, the equation can be
rearranged to solve for the ac rms voltage, as shown in Equation 2.
For insulation wear out with the polyimide materials used in these
products, the ac rms voltage determines the product lifetime.
2
VRMS VAC RMS VDC
2
(1)
VPEAK
VRMS
VDC
TIME
Figure 44. Critical Voltage Example
For this example, the VRMS from Equation 1 is calculated as follows:
VRMS 240 2 400 2 = 466 V
(3)
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the creepage
required by a system standard.
To determine if the lifetime is adequate, obtain VAC RMS. To
calculate VAC RMS for this example, use Equation 2 as follows:
VAC RMS 466 2 400 2 = 240 V rms
(4)
In this case, VAC RMS is the line voltage of 240 V rms. This
calculation is more relevant when the waveform is not sinusoidal.
The VAC RMS value is compared to the limits for the working ac
voltage in Table 10 for the expected lifetime (which is less than
a 60 Hz sine wave) and is well within the limit for a 50-year
service life.
Note that the dc working voltage limit is set by the creepage of
the package, as specified in IEC60664-1. This dc value can
differ for specific system level standards.
or
VAC RMS VRMS 2 VDC2
VAC RMS
21430-042
Insulation Wear Out
ISOLATION VOLTAGE
Surface Tracking
(2)
where:
VRMS is the total rms working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
Rev. 0 | Page 20 of 21
Data Sheet
ADM2461E/ADM2463E
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
03-27-2007-B
1
Figure 45. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
ADM2461EBRWZ
ADM2461EBRWZ-R7
ADM2463EBRWZ
ADM2463EBRWZ-RL7
EVAL-ADM2461EEBZ
EVAL-ADM2463EEBZ
1
Data Rate (Mbps)
0.5
0.5
0.5
0.5
Duplex
Half
Half
Full
Full
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D21430-6/20(0)
Rev. 0 | Page 21 of 21
Package Description
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
Half-Duplex Evaluation Board
Full Duplex Evaluation Board
Package Option
RW-16
RW-16
RW-16
RW-16
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