ADM3052

Isolated CAN Transceiver with Integrated High Voltage, Bus-Side, Linear Regulator ADM3052 FEATURES 5 kV rms isolated CAN transceiver Integrated V+ linear regulator Bus side powered by V+ and V− 11 V to 25 V operation on V+ 5 V or 3.3 V operation on VDD1 Complies with ISO 11898 standard High speed data rates up to 1 Mbps Short-circuit protection on bus pins Integrated bus miswire protection Unpowered nodes do not disturb the bus 110 or more nodes on the bus Thermal shutdown protection High common-mode transient immunity: >25 kV/μs Safety and regulatory approvals UL recognition (pending) 5000 VRMS for 1 minute per UL 1577 VDE Certificates of Conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 846 V peak Industrial operating temperature range: −40°C to +85°C Wide body, 16-lead SOIC package GENERAL DESCRIPTION The ADM3052 is an isolated controller area network (CAN) physical layer transceiver with a V+ integrated linear regulator. The ADM3052 complies with the ISO 11898 standard. The device employs Analog Devices, Inc., iCoupler® technology to combine a 3-channel isolator, a CAN transceiver, and a linear regulator into a single package. The power is isolated between a single 3.3 V or 5 V supply on VDD1, the logic side, and a single 24 V supply provided on V+, the bus side. The ADM3052 creates an isolated interface between the CAN protocol controller and the physical layer bus. It is capable of running at data rates up to 1 Mbps. The device has integrated miswire protection on the bus pins, V+, V−, CANH, and CANL. The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where the bus may be shorted to ground or power terminals. The part is fully specified over the industrial temperature range and is available in a 16-lead, wide-body SOIC package. APPLICATIONS CAN data buses Industrial field networks DeviceNet applications FUNCTIONAL BLOCK DIAGRAM VDD1 ISOLATION BARRIER CINT LINEAR REGULATOR VDD2 BUS V+SENSE PROTECTION TxD ENCODE DECODE TxD DRIVER V+R V+SENSE DECODE ENCODE VDD2 V+ RxD RxD DECODE ENCODE VREF GND2 GND2 DIGITAL ISOLATION GND1 RECEIVER REFERENCE VOLTAGE CANH CANL VREF ADM3052 CAN TRANSCEIVER V– 09292-001 LOGIC SIDE BUS SIDE Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. ADM3052 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Timing Specifications .................................................................. 4  Regulatory Information ............................................................... 4  Insulation and Safety-Related Specifications ............................ 4  VDE 0884 Insulation Characteristics (Pending) ...................... 5  Absolute Maximum Ratings............................................................ 6  ESD Caution .................................................................................. 6  Pin Configuration and Function Descriptions ............................. 7  Typical Performance Characteristics ............................................. 8  Test Circuits ..................................................................................... 12  Switching Characteristics .............................................................. 13  Circuit Description......................................................................... 14  CAN Transceiver Operation ..................................................... 14  Electrical Isolation...................................................................... 14  Truth Tables................................................................................. 14  Thermal Shutdown .................................................................... 16  Linear Regulator ......................................................................... 16  Magnetic Field Immunity.......................................................... 16  Applications Information .............................................................. 17  Typical Applications ................................................................... 17  Outline Dimensions ....................................................................... 18  Ordering Guide .......................................................................... 18  REVISION HISTORY 6/11—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADM3052 SPECIFICATIONS All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 5.5 V, TA = −40°C to +85°C, V+ = 11 V to 25 V, unless otherwise noted. Table 1. Parameter SUPPLY CURRENT Power Supply Current Logic Side TxD/RxD Data Rate 1 Mbps Power Supply Current Bus Side Recessive State Dominant State TxD/RxD Data Rate 1 Mbps EXTERNAL RESISTOR Resistance Power Rating DRIVER Logic Inputs Input Voltage High Input Voltage Low CMOS Logic Input Currents Differential Outputs Recessive Bus Voltage CANH Output Voltage CANL Output Voltage Differential Output Voltage Short-Circuit Current, CANH Short-Circuit Current, CANL RECEIVER Differential Inputs Voltage Recessive Voltage Dominant Input Voltage Hysteresis CANH, CANL Input Resistance Differential Input Resistance Logic Outputs Output Low Voltage Output High Voltage Short-Circuit Current VOLTAGE REFERENCE Reference Output Voltage BUS VOLTAGE SENSE V+SENSE Output Voltage Low V+SENSE Output Voltage High Threshold Voltage COMMON-MODE TRANSIENT IMMUNITY1 1 Symbol Min Typ Max Unit Test Conditions IDD1 I+ I+ I+ RP 297 0.75 0.7 2 10 75 55 303 mA mA mA mA Ω W RL = 60 Ω, see Figure 26 RL = 60 Ω, see Figure 26 RL = 60 Ω, see Figure 26 64 48 300 VIH VIL IIH, IIL VCANL, VCANH VCANH VCANL VOD VOD ISCCANH ISCCANL 0.7 VDD1 V 0.25 VDD1 V 500 μA 3.0 4.5 2.0 3.0 +50 −200 −100 200 V V V V mV mA mA mA TxD TxD TxD VTxD = high, RL = ∞, see Figure 23 VTxD = low, see Figure 23 VTxD = low, see Figure 23 VTxD = low, RL = 45 Ω, see Figure 23 VTxD = high, RL = ∞, see Figure 23 VCANH = −5 V VCANH = −36 V VCANL = 36 V 2.0 2.75 0.5 1.5 −500 VIDR VIDD VHYS RIN RDIFF VOL VOH IOS VREF VOL VOH V+SENSETH −1.0 0.9 150 5 20 +0.5 5.0 V V mV kΩ kΩ V V mA V V V V kV/μs −7 V < VCANL, VCANH < 12 V, see Figure 24, CL = 15 pF −7 V < VCANL, VCANH < 12 V, see Figure 24, CL = 15 pF See Figure 24 25 100 0.2 0.4 VDD1 − 0.3 VDD1 − 0.2 7 85 2.025 3.025 IOUT = 1.5 mA IOUT = −1.5 mA VOUT = GND1 or VDD1 |IREF = 50 μA| IO+SENSE = 1.5 mA IO+SENSE = −1.5 mA VCM = 1 kV, transient magnitude = 800 V 0.2 0.4 VDD1 − 0.3 VDD1 − 0.2 7.0 10 25 CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. 0 | Page 3 of 20 ADM3052 TIMING SPECIFICATIONS All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 5.5 V, TA = −40°C to +85°C, V+ = 11 V to 25 V, unless otherwise noted. Table 2. Parameter DRIVER Maximum Data Rate Propagation Delay from TxD On to Bus Active Propagation Delay from TxD Off to Bus Inactive RECEIVER Propagation Delay from TxD On to Receiver Active Propagation Delay from TxD Off to Receiver Inactive POWER-UP Enable Time, V+ High to V+SENSE Low Disable Time, V+ Low to V+SENSE High Symbol Min 1 tonTxD toffTxD 90 120 Typ Max Unit Mbps ns ns Test Conditions See Figure 25 and Figure 27, RL = 60 Ω, CL = 100 pF See Figure 25 and Figure 27, RL = 60 Ω, CL = 100 pF See Figure 25 and Figure 27, RL = 60 Ω, CL = 100 pF See Figure 25 and Figure 27, RL = 60 Ω, CL = 100 pF See Figure 29 See Figure 29 tonRxD toffRxD 200 250 ns ns tSE tSD 300 10 μs ms REGULATORY INFORMATION The ADM3052 approval is pending by the organizations listed in Table 3. Table 3. Organization UL Approval Type Recognized under the component recognition program of Underwriters Laboratories, Inc. Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Notes In accordance with UL 1577, each ADM3052 is proof tested by applying an insulation test voltage ≥6000 V rms for 1 second (current leakage detection limit = 10 μA) In accordance with DIN V VDE V 0884-10, each ADM3052 is proof tested by applying an insulation test voltage ≥1590 V peak for 1 second (partial discharge detection limit = 5 pC) VDE INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 4. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value 5000 7.7 7.6 0.017 min >175 IIIa Unit V rms mm mm mm V Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance along body Insulation distance through insulation DIN IEC 112/VDE 0303-1 Material group (DIN VDE 0110) CTI Rev. 0 | Page 4 of 20 ADM3052 VDE 0884 INSULATION CHARACTERISTICS (PENDING) This isolator is suitable for reinforced electrical isolation within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits. Table 5. Description CLASSIFICATIONS Installation Classification per DIN VDE 0110 for Rated Mains Voltage ≤150 V rms ≤300 V rms ≤400 V rms Climatic Classification Pollution Degree VOLTAGE Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests, Subgroup 1 After Input and/or Safety Test, Subgroup 2/Subgroup 3 Highest Allowable Overvoltage SAFETY-LIMITING VALUES Case Temperature Input Current Output Current Insulation Resistance at TS Test Conditions Symbol Characteristic Unit DIN VDE 0110 VIORM VPR VPR VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC VTR TS IS, INPUT IS, OUTPUT RS I to IV I to III I to II 40/85/21 2 846 1590 1357 V peak V peak V peak VIORM × 1.875 = VPR, 100% production tested, tm = 1 sec, partial discharge < 5 pC 1018 6000 150 265 335 >109 V peak V peak °C mA mA Ω Rev. 0 | Page 5 of 20 ADM3052 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground. Table 6. Parameter VDD1 V+ V+R Digital Input Voltage TxD Digital Output Voltage RxD V+SENSE CANH, CANL VREF Operating Temperature Range Storage Temperature Range ESD (Human Body Model) Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) θJA, Thermal Impedance TJ, Junction Temperature Rating −0.5 V to +6 V −36 V to +36 V −36 V to +36 V −0.5 V to VDD1 + 0.5 V −0.5 V to VDD1 + 0.5 V −0.5 V to VDD1 + 0.5 V −36 V to +36 V −0.5 V to +6 V −40°C to +85°C −55°C to +150°C 3 kV 300°C 215°C 220°C 53°C/W 130°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 6 of 20 ADM3052 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 GND1 2 GND1 3 V+SENSE 4 RxD 5 TxD 6 VDD1 7 GND1 8 16 15 14 V– V+ V+R CINT CANH CANL VREF V– 09292-006 ADM3052 TOP VIEW (Not to Scale) 13 12 11 10 9 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 2. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic NC GND1 GND1 V+SENSE RxD TxD VDD1 GND1 V− VREF CANL CANH CINT V+R V+ V− Description No Connect. Do not connect to this pin. Ground (Logic Side). Ground (Logic Side). Bus Voltage Sense. A low level on V+SENSE indicates that there is power connected on the bus on V+ and V−. A high level on V+SENSE indicates that power is not connected on the bus on V+ and V−. Receiver Output Data. Driver Input Data. Power Supply (Logic Side). Decoupling capacitor to GND1 required; capacitor value should be between 0.01 μF and 0.1 μF. Ground (Logic Side). Ground (Bus Side). Reference Voltage Output. Low Level CAN Voltage Input/Output. High Level CAN Voltage Input/Output. A capacitor of 1 μF, 10 V is required on this pin. Connect a 300 Ω, 750 mW resistor between V+R and V+. It is recommended that a 10 μF capacitor be fitted between V+R and GND2. Bus Power Connection. Connect a 300 Ω, 750 mW resistor between V+R and V+. Ground (Bus Side). Rev. 0 | Page 7 of 20 ADM3052 TYPICAL PERFORMANCE CHARACTERISTICS 164 162 195 VDD1 = 3.3V, V+ = 25V VDD1 = 5V, V+ = 25V PROPAGATION DELAY TxD OFF TO RECEIVER INACTIVE, toffRxD (ns) VDD1 = 3.3V, TA = 25°C VDD1 = 5V, TA = 25°C 194 193 192 191 PROPAGATION DELAY TxD ON TO RECEIVER ACTIVE, tonRxD (ns) 160 158 156 154 152 150 148 –40 190 189 188 11 09292-023 –15 10 35 60 85 13 15 17 19 21 23 25 TEMPERATURE (°C) SUPPLY VOLTAGE, V+ (V) Figure 3. Propagation Delay from TxD On to Receiver Active vs. Temperature 157 Figure 6. Propagation Delay from TxD Off to Receiver Inactive vs. Supply Voltage, V+ 90 VDD1 = 3.3V, TA = 25°C VDD1 = 5V, TA = 25°C V+ = 25V PROPAGATION DELAY, toffTxD (ns) PROPAGATION DELAY TxD ON TO RECEIVER ACTIVE, tonRxD (ns) 156 85 VDD1 = 3.3V 80 VDD1 = 5V 155 154 75 153 70 152 65 09292-024 11 13 15 17 19 21 23 25 –15 10 35 60 85 SUPPLY VOLTAGE, V+ (V) TEMPERATURE (°C) Figure 4. Propagation Delay from TxD On to Receiver Active vs. Supply Voltage, V+ 250 Figure 7. Propagation Delay from TxD Off to Bus Inactive vs. Temperature 85 VDD1 = 3.3V, V+ = 25V VDD1 = 5V, V+ = 25V 84 VDD1 = 3.3V, TA = 25°C VDD1 = 5V, TA = 25°C PROPAGATION DELAY TxD OFF TO RECEIVER INACTIVE, toffRxD (ns) PROPAGATION DELAY TxD OFF TO BUS INACTIVE, toffTxD (ns) 200 83 82 81 80 79 78 77 76 150 100 50 09292-025 –15 10 35 60 85 13 15 17 19 21 23 25 TEMPERATURE (°C) SUPPLY VOLTAGE, V+ (V) Figure 5. Propagation Delay from TxD Off to Receiver Inactive vs. Temperature Figure 8. Propagation Delay from TxD Off to Bus Inactive vs. Supply Voltage, V+ Rev. 0 | Page 8 of 20 09292-029 0 –40 75 11 09292-015 151 60 –40 09292-026 ADM3052 51 50 VDD1 = 3.3V, V+ = 25V VDD1 = 5V, V+ = 25V 51 VDD1 = 3.3V, V+ = 25V VDD1 = 5V, V+ = 25V 50 PROPAGATION DELAY TxD ON TO BUS ACTIVE, tonTxD (ns) PROPAGATION DELAY TxD ON TO BUS ACTIVE, tonTxD (ns) 09292-023 49 49 48 47 46 45 48 47 46 45 44 –40 –15 10 35 60 85 –15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. Propagation Delay from TxD On to Bus Active vs. Temperature Figure 12. Propagation Delay from TxD On to Bus Active vs. Temperature 51 VDD1 = 3.3V, TA = 25°C VDD1 = 5V, TA = 25°C 50 48 46 SUPPLY CURRENT, I+ (mA) 50 V+ = 11V, V+ = 18V, V+ = 25V, VDD1 = 5V, VDD1 = 5V, VDD1 = 5V, TA = 25°C TA = 25°C TA = 25°C PROPAGATION DELAY TxD ON TO BUS ACTIVE, tonTxD (ns) 49 44 42 40 38 36 34 48 47 46 45 32 09292-022 13 15 17 19 21 23 25 1000 DATA RATE (kbps) SUPPLY VOLTAGE, V+ (V) Figure 10. Propagation Delay from TxD On to Bus Active vs. Supply Voltage, V+ 2.40 Figure 13. Supply Current (I+) vs. Data Rate (Across V+, VDD1 = 5 V) 1.2 VDD1 = 3.3V, TA = 25°C VDD1 = 5V, TA = 25°C DIFFERENTIAL OUTPUT VOLTAGE DOMINANT, VOD (V) VDD1 = 3.3V, V+ = 24V, TA = 25°C VDD1 = 5V, V+ = 24V, TA = 25°C 2.39 2.38 2.37 2.36 2.35 2.34 2.33 1.0 SUPPLY CURRENT, IDD1 (mA) 0.8 0.6 0.4 0.2 09292-028 13 15 17 19 21 23 25 1000 DATA RATE (kbps) SUPPLY VOLTAGE, V+ (V) Figure 11. Differential Output Voltage Dominant vs. Supply Voltage, V+ Figure 14. Supply Current (IDD1) vs. Data Rate (VDD1 = 3.3 V, 5 V; V+ = 24 V) Rev. 0 | Page 9 of 20 09292-020 2.32 11 0 100 09292-019 44 11 30 100 09292-021 44 –40 ADM3052 2.42 DIFFERENTIAL OUTPUT VOLTAGE DOMINANT, VOD (V) 2.40 2.38 2.36 2.34 2.32 2.30 2.28 2.26 –40 RECEIVER OUTPUT LOW VOLTAGE, VOL (mV) 09292-027 VDD1 = 3.3V, V+ = 25V VDD1 = 5V, V+ = 25V 120 100 80 60 40 20 –15 10 35 60 85 –15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Driver Differential Output Voltage Dominant vs. Temperature Figure 18. Receiver Output Low Voltage vs. Temperature 2.40 2.80 VDD1 = 3.3V, TA = 25°C VDD1 = 5V, TA = 25°C DIFFERENTIAL OUTPUT VOLTAGE DOMINANT, VOD (V) 2.39 2.38 2.37 2.36 2.35 2.34 2.33 2.32 11 2.75 REFERENCE VOLTAGE, VREF (V) VCC VCC VCC VCC = 5V, = 5V, = 5V, = 5V, IREF IREF IREF IREF = +50µA = –50µA = +5µA = –5µA 2.70 2.65 2.60 2.55 2.50 2.45 2.40 –40 09292-033 13 15 17 19 21 23 25 –15 10 35 60 85 SUPPLY VOLTAGE, V+ (V) TEMPERATURE (°C) Figure 16. Driver Differential Output Voltage Dominant vs. Supply Voltage, V+ Figure 19. VREF vs. Temperature 4.895 85 RECEIVER OUTPUT HIGH VOLTAGE, VOH (V) 4.890 4.885 4.880 4.875 4.870 4.865 4.860 4.855 –40 VCC = 5V IOUT = –1.5mA V+SENSE ENABLE TIME, tSE (µs) 80 VDD1 = 3.3V 75 VDD1 = 5V 70 65 –15 10 35 60 85 –15 10 35 60 85 TEMPERATURE TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Receiver Output High Voltage vs. Temperature Figure 20. Enable Time, V+ High to V+SENSE Low vs. Temperature Rev. 0 | Page 10 of 20 09292-016 09292-031 60 –40 09292-032 09292-030 0 –40 ADM3052 V+SENSE THRESHOLD VOLTAGE HIGH TO LOW (V) 680 VDD1 = 3.3V 670 8.56 8.54 8.52 8.50 8.48 8.46 8.44 8.42 8.40 –40 VDD1 = 3.3V VDD1 = 5V V+SENSE DISABLE, tSD (µs) 660 VDD1 = 5V 650 640 630 620 610 600 –40 09292-017 –15 10 35 60 85 –15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 21. Disable Time, V+ Low to V+SENSE High vs. Temperature Figure 22. Bus Voltage Sense Threshold Voltage High to Low vs. Temperature Rev. 0 | Page 11 of 20 09292-018 ADM3052 TEST CIRCUITS CANH TxD TxD VOD VCANH RL 2 RL 2 VCANL CANL RL CL VOC 09292-007 15pF Figure 23. Driver Voltage Measurements Figure 25. Switching Characteristics Measurements CANH 09292-008 VID CANL CL RxD Figure 24. Receiver Voltage Measurements 1µF VDD1 ISOLATION BARRIER CINT V+R 10µF RP BUS V+SENSE PROTECTION TxD ENCODE DECODE TxD DRIVER CANH CANL RxD DECODE ENCODE VREF GND2 GND2 DIGITAL ISOLATION GND1 RECEIVER REFERENCE VOLTAGE RL V+ VDD2 V+ LINEAR REGULATOR VDD2 09292-009 RxD 100nF V+SENSE DECODE ENCODE RxD VREF V– 09292-010 ADM3052 CAN TRANSCEIVER LOGIC SIDE BUS SIDE Figure 26. Supply Current Measurement Test Circuit Rev. 0 | Page 12 of 20 ADM3052 SWITCHING CHARACTERISTICS VDD1 0.7VDD1 VTxD 0V 0.25V DD1 VOD VDIFF = VCANH – VCANL VDIFF 0.9V 0.5V VOR tonTxD VDD1 toffTxD VDD1 – 0.3V VRxD 0V 0.4V tonRxD toffRxD Figure 27. Driver and Receiver Propagation Delay VRxD HIGH LOW VHYS 0.5 0.9 VID (V) Figure 28. Receiver Input Hysteresis 25V V+ V+SENSETH V+SENSETH 0V tSE tSD VDD1 V+SENSE 0.4V 0V VDD1 – 0.3 09292-005 Figure 29. V+SENSE Enable/Disable Time Rev. 0 | Page 13 of 20 09292-004 09292-002 ADM3052 CIRCUIT DESCRIPTION CAN TRANSCEIVER OPERATION A CAN bus has two states: dominant and recessive. A dominant state is present on the bus when the differential voltage between CANH and CANL is greater than 0.9 V. A recessive state is present on the bus when the differential voltage between CANH and CANL is less than 0.5 V. During a dominant bus state, the CANH pin is high and the CANL pin is low. During a recessive bus state, both the CANH and CANL pins are in the high impedance state. TRUTH TABLES The truth tables in this section use the abbreviations shown in Table 8. Table 8. Truth Table Abbreviations Letter H L I X Z NC Description High level Low level Indeterminate Don’t care High impedance (off) Disconnected ELECTRICAL ISOLATION In the ADM3052, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 30). The driver input signal, which is applied to the TxD pin and referenced to the logic ground (GND1), is coupled across an isolation barrier to appear at the transceiver section referenced to the isolated ground (V−). Similarly, the receiver input and V+, which are referenced to the isolated ground in the transceiver section, are coupled across the isolation barrier to appear at the RxD pin and V+SENSE referenced to the logic ground, respectively. Table 9. Transmitting Supply Status VDD1 V+ On On On On On On Off On On Off Input TxD L H Floating X L Bus State Dominant Recessive Recessive Recessive I Outputs CANH CANL H L Z Z Z Z Z Z I I V+SENSE L L L I H Table 10. Receiving Supply Status VDD1 V+ On On On On On On On On Off On On Off Inputs VID = CANH − CANL ≥ 0.9 V ≤ 0.5 V 0.5 V < VID < 0.9 V Inputs open X X Bus State Dominant Recessive I Recessive X X RxD L H I H I H Outputs V+SENSE L L L L I H iCoupler Technology The digital signals transmit across the isolation barrier using iCoupler technology. This technique uses chip scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are decoded into the binary value that was originally transmitted. Positive and negative logic transitions at the input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses, indicative of the correct input state, is sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the output is forced to a default state (see Table 9 and Table 10). Rev. 0 | Page 14 of 20 ADM3052 1µF VDD1 ISOLATION BARRIER CINT V+R 10µF RP BUS V+ VDD2 PROTECTION TxD ENCODE DECODE TxD DRIVER CANH CANL RxD DECODE ENCODE VREF GND2 GND2 DIGITAL ISOLATION GND1 RECEIVER REFERENCE VOLTAGE RL V+ LINEAR REGULATOR VDD2 100nF V+SENSE DECODE ENCODE V+SENSE RxD VREF V– 09292-010 ADM3052 CAN TRANSCEIVER LOGIC SIDE BUS SIDE Figure 30. Digital Isolation and Transceiver Sections Rev. 0 | Page 15 of 20 ADM3052 THERMAL SHUTDOWN MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGAUSS) 100 The ADM3052 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a junction temperature of 150°C is reached. As the device cools, the drivers reenable at a temperature of 140°C. 10 1 0.1 0.01 LINEAR REGULATOR The linear regulator takes the V+ bus power (ranging between 11 V to 25 V) and regulates this voltage to 5 V to provide power to the internal bus-side circuitry (iCoupler isolation, V+SENSE, and transceiver circuits). The linear regulator uses two regulation loops to share the power dissipation between the internal die and an external resistor. This reduces the internal heat dissipation in the package. The 300 Ω external resistor should be capable of dissipating 750 mW of power and have a tolerance of 1%. 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 31. Maximum Allowable External Magnetic Flux Density MAGNETIC FIELD IMMUNITY The limitation on the magnetic field immunity of the iCoupler is set by the condition in which an induced voltage in the receiving coil of the transformer is large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADM3052 is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1 V. The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by ⎛ − dβ ⎞ 2 V =⎜ ⎟∑ πrn ; n = 1, 2, . . . , N ⎝ dt ⎠ For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. Figure 32 shows the magnetic flux density values in terms of more familiar quantities, such as maximum allowable current flow at given distances away from the ADM3052 transformers. 1000 MAXIMUM ALLOWABLE CURRENT (kA) DISTANCE = 1m 100 DISTANCE = 5mm 10 DISTANCE = 100mm 1 where: β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field can be determined using Figure 31. 0.1 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 32. Maximum Allowable Current for Various Current-to-ADM3052 Spacings With combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. Rev. 0 | Page 16 of 20 09292-013 0.01 1k 09292-012 0.001 1k ADM3052 APPLICATIONS INFORMATION TYPICAL APPLICATIONS 3.3V/5V SUPPLY 1µF 100nF VDD1 ISOLATION BARRIER CINT LINEAR REGULATOR VDD2 V+SENSE BUS V+SENSE VDD2 CAN CONTROLLER TxD ENCODE DECODE TxD PROTECTION DRIVER CANH RxD RxD RECEIVER DECODE ENCODE VREF REFERENCE VOLTAGE GND2 VREF V– DIGITAL ISOLATION GND1 CAN TRANSCEIVER 09292-014 V+R 10µF V+ ADM3052 V+ RP 100nF DECODE ENCODE BUS CONNECTOR V+ CANH RL CANL V– CANL GND2 LOGIC SIDE BUS SIDE Figure 33. Typical Isolated CAN Node Using the ADM3052 Rev. 0 | Page 17 of 20 ADM3052 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 16 9 7.60 (0.2992) 7.40 (0.2913) 1 8 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 0.75 (0.0295) 45° 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) SEATING PLANE COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 34. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 ADM3052BRWZ ADM3052BRWZ-REEL7 EVAL-ADM3052EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 16-Lead SOIC_W 16-Lead SOIC_W Evaluation Board 03-27-2007-B Package Option RW-16 RW-16 Z = RoHS Compliant Part. Rev. 0 | Page 18 of 20 ADM3052 NOTES Rev. 0 | Page 19 of 20 ADM3052 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09292-0-6/11(0) Rev. 0 | Page 20 of 20