Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
3.0 V to 5.5 V, ±12 kV IEC ESD Protected, 500 kbps/50 Mbps RS-485 Transceivers
FEATURES
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FUNCTIONAL BLOCK DIAGRAMS
TIA/EIA RS-485 compliant over full supply range
3.0 V to 5.5 V operating voltage range on VCC
1.62 V to 5.5 V VIO logic supply option available
ESD protection on the bus pins
► IEC 61000-4-2 ≥ ±12 kV contact discharge
► IEC 61000-4-2 ≥ ±12 kV air discharge
► HBM ≥ ±30 kV
Full hot swap support (glitch free power-up/power-down)
High speed 50 Mbps data rate (ADM3065E/ADM3066E/
ADM3067E/ADM3068E)
Low speed 500 kbps data rate for long cables (ADM3061E/
ADM3062E/ADM3063E/ADM3064E)
Full receiver short-circuit, open circuit, and bus idle fail-safe
Extended temperature range up to 125°C
PROFIBUS compliant at VCC ≥ 4.5 V
Half-duplex and full duplex models available
Allows connection of up to 128 transceivers onto the bus
Space-saving package options
► 10-lead, 3 mm × 3 mm LFCSP
► 8-lead and 10-lead, 3 mm × 3 mm MSOP
► 8-lead and 14-lead, narrow-body SOIC
Figure 1. ADM3061E/ADM3065E Functional Block Diagram
Figure 2. ADM3063E/ADM3067E Functional Block Diagram
APPLICATIONS
Industrial fieldbuses
Process control
► Building automation
► PROFIBUS networks
► Motor control servo drives and encoders
►
►
Figure 3. ADM3062E/ADM3066E Functional Block Diagram
Figure 4. ADM3064E/ADM3068E Functional Block Diagram
Rev. H
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
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Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagrams....................................1
General Description...............................................3
Specifications........................................................ 4
Timing Specifications......................................... 5
Absolute Maximum Ratings...................................8
Thermal Resistance........................................... 8
ESD Caution.......................................................8
Pin Configurations and Function Descriptions.......9
Typical Performance Characteristics................... 13
Test Circuits......................................................... 17
Theory of Operation.............................................18
IEC ESD Protected RS-485............................. 18
High Driver Differential Output Voltage............ 18
IEC 61000-4-2 ESD Protection........................ 18
Truth Tables......................................................18
Receiver Fail-Safe............................................19
Hot Swap Capability......................................... 19
128 Transceivers on the Bus............................19
Driver Output Protection...................................19
Applications Information...................................... 20
Isolated High Speed RS-485 Node.................. 21
Outline Dimensions............................................. 22
Ordering Guide.................................................23
Evaluation Boards............................................ 24
REVISION HISTORY
3/2022—Rev. G to Rev. H
Changes to Figure 4........................................................................................................................................ 1
Changes to Isolated High Speed RS-485 Node Section and Figure 48........................................................ 21
Updated Outline Dimensions......................................................................................................................... 23
Changes to Ordering Guide........................................................................................................................... 23
analog.com
Rev. H | 2 of 25
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
Data Sheet
GENERAL DESCRIPTION
The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E are 3.0 V to 5.5 V, IEC electrostatic discharge (ESD) protected RS-485 transceivers, allowing the
devices to withstand ±12 kV contact discharges on the transceiver
bus pins without latch-up or damage. The ADM3062E/ADM3064E/
ADM3066E/ADM3068E feature a VIO logic supply pin that allows a
flexible digital interface capable of operating as low as 1.62 V.
The RS-485 transceivers are available in a number of space-saving packages, including the 10-lead, 3 mm × 3 mm lead frame
chip-scale package (LFCSP); the 8‑lead or 10-lead, 3 mm × 3 mm
mini small outline package (MSOP); and the 8-lead or 14-lead,
narrow-body standard small outline packages (SOIC_N). Models
with operating temperature ranges of −40°C to +125°C and −40°C
to +85°C are available.
The ADM3065E/ADM3066E/ADM3067E/ADM3068E are suitable
for high speed, 50 Mbps, bidirectional data communication on multipoint bus transmission lines. ADM3061E/ADM3062E/ADM3063E/
ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E feature a 1/4 unit load input impedance that allows up to 128
transceivers on a bus. The ADM3061E/ADM3062E/ADM3063E/
ADM3064E models offer all of the same features as the
ADM3065E/ADM3066E/ ADM3067E/ADM3068E models at a low
500 kbps data rate that is suitable for operation over long cable
runs.
Excessive power dissipation caused by bus contention or by output
shorting is prevented by a thermal shutdown circuit. If a significant
temperature increase is detected in the internal driver circuitry
during fault conditions, this feature forces the driver output into a
high impedance state.
The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E guarantee a logic high receiver
output when the receiver inputs are shorted, open, or connected to
a terminated transmission line with all drivers disabled.
The ADM3061E/ADM3062E/ADM3065E/ADM3066E are half-duplex RS-485 transceivers, fully compliant to the PROFIBUS® standard with increased 2.1 V bus differential voltage at VCC ≥ 4.5 V.
The ADM3063E/ADM3064E/ADM3067E/ADM3068E are full duplex
RS-485 transceiver options.
Table 2 presents an overview of
the ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E data rate capability across
temperature, power supply, and package options. Refer to the
Evaluation Boards section for model numbering.
Table 1. Generic Description Table
Device No.
Duplex
Maximum Data Rate
VIO Logic Supply Available
ADM3061E
ADM3062E
ADM3063E
ADM3064E
ADM3065E
ADM3066E
ADM3067E
ADM3068E
Half
Half
Full
Full
Half
Half
Full
Full
500 kbps1
500 kbps1
500 kbps1
500 kbps1
50 Mbps
50 Mbps
50 Mbps
50 Mbps
No
Yes
No
Yes
No
Yes
No
Yes
1
Temperature Range
A grade: −40°C to +85°C
B grade: −40°C to +125°C
Packages Available
8‑lead SOIC_N, 8-lead MSOP
10‑lead MSOP, 10-lead LFCSP
14-lead SOIC_N
14-lead SOIC_N
8‑lead SOIC_N, 8-lead MSOP
10‑lead MSOP, 10-lead LFCSP
14-lead SOIC_N
14-lead SOIC_N
Driver outputs are slew rate limited to minimize common-mode emissions over long cable runs.
Table 2. Summary of the ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Operating Conditions—Data Rate Capability
Across Temperature, Power Supply, and Package
Maximum Data Rate1
Maximum VCC (V)
Maximum Temperature
Package Description
50 Mbps
50 Mbps
50 Mbps
500 kbps
5.5
5.5
3.6
5.5
−40°C to +125°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
10-lead LFCSP
8-lead SOIC_N, 8‑lead MSOP, 10‑lead MSOP, and 14-lead SOIC_N
8-lead SOIC_N, 8‑lead MSOP, 10‑lead MSOP, and 14-lead SOIC_N
8-lead SOIC_N, 8‑lead MSOP, 10‑lead MSOP, 10-lead LFCSP, and 14-lead
SOIC_N
1
The ADM3065E/ADM3066E/ADM3067E/ADM3068E data input (DI) transmits 50 Mbps (or 500 kbps for the ADM3061E/ADM3062E/ADM3063E/ADM3064E) clock data,
and the ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E driver enable (DE) is enabled for 50% of the DI transmit time.
analog.com
Rev. H | 3 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
SPECIFICATIONS
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E/ADM3064E/ADM3066E/ADM3068E), TA = TMIN (−40°C) to TMAX (+125°C), unless
otherwise noted. All typical specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 3.
Parameter
Symbol
POWER SUPPLY
No Load Supply Current
ICC
ADM3065E/ADM3066E/ADM3067E/ADM3068E
Supply Current, Data Rate = 50 Mbps
ADM3061E/ADM3062E/ADM3063E/ADM3064E
Supply Current, Data Rate = 500 kbps
Supply Current in Shutdown Mode
VIO Shutdown Current2
DRIVER
Differential Outputs
Output Voltage, Loaded
Change in Differential Input Voltage for
Complementary Output States
Common-Mode Output Voltage
Change in Common-Mode Voltage for
Complementary Output States
Output Short-Circuit Current
Output Leakage (Y, Z)3
Min
Typ
Max
Unit
Test Conditions/Comments
ICC
3.5
3.5
3
107
7.5
7.5
4.5
172
mA
mA
mA
mA
ICC
67
100
75
165
mA
mA
DE = VIO1, RE = 0 V
DE = VIO, RE = VIO
DE = 0 V, RE = 0 V
Load resistance (RL) = 54 Ω, DE = VIO, RE = 0 V (VCC ≥
4.5 V)
RL = 54 Ω, DE = VIO, RE = 0 V (VCC = 3.0 V)
RL = 54 Ω, DE = VIO, RE = 0 V (VCC ≥ 4.5 V)
ISHDN
IIOSHDN
56
210
1
74
450
50
mA
µA
µA
RL = 54 Ω, DE = VIO, RE = 0 V (VCC = 3.0 V)
DE = 0 V, RE = VIO
DE = 0 V, RE = VIO
|VOD2|
|VOD2|
|VOD2|
|VOD2|
|VOD3|
2.0
1.5
2.1
2.1
1.5
2.5
2.1
3.5
3
2.1
VCC
VCC
VCC
VCC
VCC
V
V
V
V
V
|VOD3|
∆|VOD|
2.1
3
VCC
0.2
V
V
VCC ≥ 3.0 V, RL = 50 Ω, see Figure 38
VCC ≥ 3.0 V, RL = 27 Ω (RS-485), see Figure 38
VCC ≥ 4.5 V, RL = 50 Ω, see Figure 38
VCC ≥ 4.5 V, RL = 27 Ω (RS-485), see Figure 38
VCC ≥ 3.0 V, −7 V ≤ common-mode voltage (VCM) ≤ +12 V,
see Figure 39
VCC ≥ 4.5 V, −7 V ≤ VCM ≤ +12 V, see Figure 39
RL = 27 Ω or 50 Ω, see Figure 38
1.6
3.0
0.2
V
V
RL = 27 Ω or 50 Ω, see Figure 38
RL = 27 Ω or 50 Ω, see Figure 38
+250
+100
mA
µA
µA
−7 V < output voltage (VOUT) < +12 V
DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, input voltage (VIN)
= 12 V
DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V
V
V
µA
DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V
DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V
DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V, 0 V ≤ VIN ≤ VIO
mV
mV
mA
mA
kΩ
−7 V < VCM < +12 V
−7 V < VCM < +12 V
DE = 0 V, VCC = powered/unpowered, VIN = 12 V
DE = 0 V, VCC = powered/unpowered, VIN = −7 V
−7 V ≤ VCM ≤ +12 V
VOC
∆|VOC|
IOS
IO
−250
−100
Logic Inputs (DE, RE, DI)
Input Voltage
Low
High
Input Current
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Input Voltage Hysteresis
Input Current (A, B)
Line Input Resistance
Logic Outputs
Output Voltage
analog.com
VIL
VIH
II
VTH
VHYS
II
RIN
0.33 × VIO
0.67 × VIO
−2
−200
−0.20
48
+2
−125
30
0.1
−0.1
96
−30
0.25
Rev. H | 4 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
SPECIFICATIONS
Table 3.
Parameter
Low
High
Short-Circuit Current
Three-State Output Leakage
1
Symbol
Min
Typ
VOL
VOH
Max
Unit
Test Conditions/Comments
0.4
V
0.4
0.2
V
V
V
V
V
mA
µA
VIO = 3.6 V, output current (IOUT) = 2 mA,
VID4 ≤ −0.2 V
VIO = 2.7 V, IOUT = 1 mA, VID ≤ −0.2 V2
VIO = 1.95 V, IOUT = +500 µA, VID ≤ −0.2 V2
VIO = 3.0 V, IOUT = −2 mA, VID ≥ −0.03 V
VIO = 2.3 V, IOUT = −1 mA, VID ≥ −0.03 V2
VIO = 1.65 V, IOUT = −500 µA, VID ≥ −0.03 V2
VOUT = GND or VIO
RO pin = 0 V or VIO
2.4
2.0
VIO − 0.2
85
±2
IOZR
VIO = VCC for ADM3061E/ADM3063E/ADM3065E/ADM3067E.
2
ADM3062E/ADM3064E/ADM3066E/ADM3068E only.
3
ADM3063E/ADM3064E/ADM3067E/ADM3068E only.
4
VID is the receiver input differential voltage.
TIMING SPECIFICATIONS
ADM3061E/ADM3062E/ADM3063E/ADM3064E
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E/ADM3064E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All typical
specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 4.
Parameter
DRIVER
Maximum Data Rate1
Propagation Delay
Skew
Rise/Fall Times
Enable to Output High
Enable to Output Low
Disable Time from Low
Disable Time from High
Enable Time from Shutdown to High
Enable Time from Shutdown to Low
RECEIVER
Maximum Data Rate
Propagation Delay
Skew/Pulse Width Distortion
Enable to Output High
Symbol
Min
Typ
Max
Unit
500
tDPLH, tDPHL
220
800
kbps
ns
tDSKEW
tDR, tDF
tDZH
tDZL
tDLZ
tDHZ
tDZH(SHDN)2
tDZL(SHDN)2
5
300
100
100
350
600
550
550
100
800
1000
1000
2000
2000
2000
2000
ns
ns
ns
ns
ns
ns
ns
ns
kbps
ns
ns
ns
120
500
tRPLH, tRPHL
tRSKEW
tRZH
10
200
50
50
Enable to Output Low
tRZL
10
50
ns
Disable Time from Low
Disable Time from High
Enable from Shutdown to High
tRLZ
tRHZ
tRZH(SHDN)3
10
10
50
50
2000
ns
ns
ns
analog.com
Test Conditions/Comments
RLDIFF capacitor = 54 Ω, CL1 capacitor = CL2 capacitor = 100 pF,
see Figure 5 and Figure 40
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 40
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 40
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8 and
Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8 and
Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 43
Rev. H | 5 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
SPECIFICATIONS
Table 4.
Parameter
Enable from Shutdown to Low
TIME TO SHUTDOWN
Symbol
tRZL(SHDN)
tSHDN4
Min
Typ
3
Max
Unit
Test Conditions/Comments
2000
ns
ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 43
40
1
Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:0.5:1.
2
tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. RE = VCC for this condition.
3
tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when RE changes from VCC to 0 V. DE = 0 V for this condition.
4
Minimum time required to put the device into shutdown: DE and RE must be disabled for more than 40 ns for the device to go into shutdown.
ADM3065E/ADM3066E/ADM3067E/ADM3068E
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3066E/ADM3068E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All typical
specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 5.
Parameter
DRIVER
Maximum Data Rate1
Propagation Delay
Skew
Rise/Fall Times
Enable to Output High
Enable to Output Low
Disable Time from Low
Disable Time from High
Enable Time from Shutdown to High
Enable Time from Shutdown to Low
RECEIVER
Maximum Data Rate
Propagation Delay
Skew/Pulse Width Distortion
Enable to Output High
Enable to Output Low
Disable Time from Low
Disable Time from High
Enable from Shutdown to High
Enable from Shutdown to Low
TIME TO SHUTDOWN
1
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
9
1
4
10
10
10
10
550
550
15
2
6.7
30
30
30
30
2000
2000
Mbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 40
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 40
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 40
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
tRPLH, tRPHL
tRSKEW
tRZH
20
1
10
35
3
35
Mbps
ns
ns
ns
tRZL
10
35
ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8 and
Figure 44
tRLZ
tRHZ
tRZH(SHDN)3
tRZL(SHDN)3
tSHDN4
10
10
450
450
35
35
2000
2000
ns
ns
ns
ns
ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 43
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 43
50
tDPLH, tDPHL
tDSKEW
tDR, tDF
tDZH
tDZL
tDLZ
tDHZ
tDZH(SHDN)2
tDZL(SHDN)2
50
40
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8 and
Figure 44
Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:1:1.
2
tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. RE = VCC for this condition.
3
tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when RE changes from VCC to 0 V. DE = 0 V for this condition.
4
Minimum time required to put the device into shutdown: DE and RE must be disabled for more than 40 ns for the device to go into shutdown.
analog.com
Rev. H | 6 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
SPECIFICATIONS
Timing Diagrams
Figure 5. Driver Propagation Delay Rise and Fall Timing Diagram
Figure 6. Driver Enable and Disable Timing Diagram
Figure 7. Receiver Propagation Delay Timing Diagram
Figure 8. Receiver Enable and Disable Timing Diagram
analog.com
Rev. H | 7 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
Parameter
Rating
VCC to GND
VIO to GND
Digital Input and Output Voltage (DE, RE, DI, and RO)
Driver Output and Receiver Input Voltage
Operating Temperature Ranges
6V
−0.3 V to +6 V
−0.3 V to VIO1 + 0.3 V
−9 V to +14 V
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
Storage Temperature Range
Continuous Total Power Dissipation
8-Lead SOIC_N
8-Lead MSOP
10-Lead MSOP
10-Lead LFCSP
14-Lead SOIC_N
Maximum Junction Temperature (TJ)
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
ESD on the Bus Pins (A, B, Y, Z)
IEC 61000-4-2 Contact Discharge
IEC 61000-4-2 Air Discharge
10 Positive and 10 Negative Discharges
Three Positive or Three Negative Discharges
ESD Human Body Model (HBM)
On the Bus Pins (A, B, Y, Z)
All Other Pins
1
0.225 W
0.151 W
0.151 W
0.450 W
0.239 W
150°C
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to PCB
thermal design is required.
θJA is the natural convection junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure.
θJC is the junction to case thermal resistance.
Table 7. Thermal Resistance
Package Type
θJA1
θJC1
Unit
R-8
RM-8
RM-10
R-14
CP-10-9
110.88
165.69
165.69
104.5
55.65
58.63
49.61
49.61
42.90
33.22
°C/W
°C/W
°C/W
°C/W
°C/W
1
300°C
215°C
220°C
±12 kV
≥±12 kV
±15 kV
Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with no bias. See JEDEC JESD-51.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
≥±30 kV
±8 kV
VIO = VCC on the ADM3061E/ADM3063E/ADM3065E/ADM3067E.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
analog.com
Rev. H | 8 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 9. ADM3061E/ADM3065E 8-Lead Narrow Body SOIC_N Pin
Configuration
Figure 10. ADM3061E/ADM3065E 8-Lead MSOP Pin Configuration
Table 8. ADM3061E/ADM3065E Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RO
2
3
RE
DE
4
5
6
DI
GND
A
7
B
8
VCC
Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is tristated when the receiver
is disabled, that is, when RE is driven high.
Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high disables the receiver.
Driver Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places the driver output into a high
impedance state.
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Ground.
Noninverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is put into a high impedance
state to avoid overloading the bus.
Inverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put into a high impedance
state to avoid overloading the bus.
3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is recommended.
analog.com
Rev. H | 9 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 12. ADM3062E/ADM3066E 10-Lead MSOP Pin Configuration
Figure 11. ADM3062E/ADM3066E 10-Lead LFCSP Pin Configuration
Table 9. ADM3062E/ADM3066E Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
VIO
RO
3
DE
4
5
6
7
8
RE
DI
GND
NIC
A
9
B
10
VCC
EPAD
1.62 V to 5.5 V Logic Supply. Adding a 0.1 µF decoupling capacitor between the VIO pin and the GND pin is recommended.
Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is tristated when the receiver
is disabled; that is, when RE is driven high.
Driver Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places the driver output into a high
impedance state.
Receiver Enable Input. This is an active low input. Driving this input low enables the receiver, and driving it high disables the receiver.
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Ground.
No Internal Connection. This pin is not internally connected.
Noninverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is put into a high impedance
state to avoid overloading the bus.
Inverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put into a high impedance
state to avoid overloading the bus.
3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is recommended.
Exposed Pad. The exposed pad must be connected to ground.
analog.com
Rev. H | 10 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 13. ADM3063E/ADM3067E 14-Lead SOIC_N Pin Configuration
Table 10. ADM3063E/ADM3067E Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 8
2
NIC
RO
3
4
RE
DE
5
6, 7
9
DI
GND
Y
10
Z
11
12
13, 14
B
A
VCC
No Internal Connection. This pin is not internally connected.
Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is tristated when the receiver
is disabled, that is, when RE is driven high.
Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high disables the receiver.
Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver output into a high
impedance state.
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Ground.
Driver Noninverting Output. When the driver is disabled, or when VCC is powered down, Pin Y is put into a high impedance state to avoid
overloading the bus.
Driver Inverting Output. When the driver is disabled, or when VCC is powered down, Pin Z is put into a high impedance state to avoid
overloading the bus.
Inverting Receiver Input.
Noninverting Receiver Input.
3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is recommended.
analog.com
Rev. H | 11 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 14. ADM3064E/ADM3068E 14-Lead SOIC_N Pin Configuration
Table 11. ADM3064E/ADM3068E Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
VIO
RO
3
DE
4
5
6, 8
7, 13
9
RE
DI
GND
NIC
Y
10
Z
11
12
14
B
A
VCC
1.62 V to 5.5 V Logic Supply. Adding a 0.1 µF decoupling capacitor between the VIO pin and the GND pin is recommended.
Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is tristated when the receiver
is disabled, that is, when RE is driven high.
Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver output into a high
impedance state.
Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high disables the receiver.
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Ground.
No Internal Connection. This pin is not internally connected.
Driver Noninverting Output. When the driver is disabled, or when VCC is powered down, Pin Y is put into a high impedance state to avoid
overloading the bus.
Driver Inverting Output. When the driver is disabled, or when VCC is powered down, Pin Z is put into a high impedance state to avoid
overloading the bus.
Inverting Receiver Input.
Noninverting Receiver Input.
3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is recommended.
analog.com
Rev. H | 12 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 15. Shutdown Current (ISHDN) vs. Temperature
Figure 16. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps, 50
Mbps Models, VCC = 3.3 V
Figure 17. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps, 50
Mbps Models, VCC = 5.0 V
analog.com
Figure 18. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance, 50
Mbps Models
Figure 19. Supply Current (ICC) vs. Data Rate with No Load Resistance,
50 Mbps Models
Figure 20. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance and
No Load Resistance, 500 kbps Models
Rev. H | 13 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 21. Supply Current (ICC) vs. Temperature, Data Rate = 500 kbps, 500
kbps Models, VCC = 3.0 V
Figure 24. Receiver Propagation Delay (Oscilloscope Plot), Data Rate = 500
kbps, VID ≥ 1.5 V
Figure 22. Supply Current (ICC) vs. Temperature, Data Rate = 500 kbps, 500
kbps Models, VCC = 5.5 V
Figure 25. Driver Propagation Delay (Oscilloscope Plot), Data Rate = 500
kbps, 500 kbps Models
Figure 23. Driver Differential Propagation Delay vs. Temperature, 500 kbps
Models
Figure 26. Driver Differential Propagation Delay vs. Temperature, 50 Mbps
Models
analog.com
Rev. H | 14 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 27. Driver Propagation Delay (Oscilloscope Plot), Data Rate = 50
Mbps, 50 Mbps Models
Figure 30. Driver Output Current vs. Driver Output High Voltage
Figure 31. Driver Output Current vs. Driver Output Low Voltage
Figure 28. Driver Output Current vs. Driver Differential Output Voltage
Figure 29. Driver Differential Output Voltage vs. Temperature
analog.com
Figure 32. Receiver Propagation Delay (Oscilloscope Plot) at 50 Mbps, |VID| ≥
1.5 V
Rev. H | 15 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 33. Receiver Propagation Delay vs. Temperature, 50 Mbps
Figure 36. Receiver Output High Voltage vs. Temperature
Figure 34. Receiver Output Current vs. Receiver Output Low Voltage (VCC =
3.3 V)
Figure 37. Receiver Output Low Voltage vs. Temperature
Figure 35. Receiver Output Current vs. Receiver Output High Voltage (VCC =
3.3 V)
analog.com
Rev. H | 16 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
TEST CIRCUITS
Figure 38. Driver Voltage Measurements
Figure 42. Receiver Propagation Delay/Skew
Figure 39. Driver Voltage Measurements over Common-Mode Range
Figure 43. Receiver Enable/Disable from Shutdown
Figure 40. Driver Propagation Delay
Figure 41. Driver Enable/Disable
analog.com
Figure 44. Receiver Enable/Disable
Rev. H | 17 of 25
Data Sheet
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
THEORY OF OPERATION
IEC ESD PROTECTED RS-485
The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E are 3.0 V to 5.5 V, 50 Mbps
RS-485 transceivers with IEC 61000-4-2 Level 4 ESD protection
on the bus pins. These devices can withstand up to ±12 kV
contact discharge on transceiver bus pins (A, B, Y, and Z) without latch-up or damage. The ADM3061E/ADM3062E/ADM3063E/
ADM3064E have the same robust IEC 61000-4-2 ESD protection
as the ADM3065E/ADM3066E/ADM3067E/ADM3068E models, and
operate at a lower, 500 kbps data rate.
HIGH DRIVER DIFFERENTIAL OUTPUT
VOLTAGE
The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E have characteristics that are
optimized for use in PROFIBUS applications. When powered at
VCC ≥ 4.5 V, the ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E driver output differential voltage meets or exceeds the PROFIBUS requirements of 2.1
V with a 54 Ω load.
IEC 61000-4-2 ESD PROTECTION
ESD is the sudden transfer of electrostatic charge between bodies
at different potentials either caused by near contact or induced by
an electric field. It has the characteristics of high current in a short
time period. The primary purpose of the IEC 61000-4-2 test is to
determine the immunity of systems to external ESD events outside
the system during operation. IEC 61000-4-2 describes testing using
two coupling methods: contact discharge and air discharge. Contact
discharge implies a direct contact between the discharge gun and
the equipment under test (EUT). During air discharge testing, the
charged electrode of the discharge gun is moved toward the EUT
until a discharge occurs as an arc across the air gap. The discharge
gun does not make direct contact with the EUT. A number of
factors affect the results and repeatability of the air discharge test,
including humidity, temperature, barometric pressure, distance, and
rate of approach to the EUT. This method is a more accurate
representation of an actual ESD event but is not as repeatable.
Therefore, contact discharge is the preferred test method.
Figure 45. IEC 61000-4-2 ESD Waveform (8 kV)
Figure 46 shows the 8 kV contact discharge current waveform
from the IEC 61000-4-2 standard compared to the HBM ESD
8 kV waveform. Figure 46 shows that the two standards specify
a different waveform shape and peak current. The peak current
associated with an IEC 61000-4-2 8 kV pulse is 30 A, whereas
the corresponding peak current for HBM ESD is more than five
times less at 5.33 A. The other difference is the rise time of the
initial voltage spike, with the IEC 61000-4-2 ESD waveform having
a much faster rise time of 1 ns, compared to the 10 ns associated
with the HBM ESD waveform. The amount of power associated with
an IEC ESD waveform is much greater than that of an HBM ESD
waveform. The HBM ESD standard requires the EUT to be subjected to three positive and three negative discharges, whereas the
IEC ESD standard requires 10 positive and 10 negative discharge
tests.
The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E with IEC 61000-4-2 ESD ratings is better suited for operation in harsh environments compared
to other RS-485 transceivers that state varying levels of HBM ESD
protection.
During testing, the data port is subjected to at least 10 positive
and 10 negative single discharges. Selection of the test voltage is
dependent on the system end environment.
Figure 45 shows the 8 kV contact discharge current waveform as
described in the IEC 61000-4-2 specification. Some of the key
waveform parameters are rise times of less than 1 ns and pulse
widths of approximately 60 ns.
Figure 46. IEC 61000-4-2 ESD Waveform (8 kV) Compared to HBM ESD
Waveform (8 kV)
TRUTH TABLES
Table 13 and Table 14 use the abbreviations shown in Table 12.
analog.com
Rev. H | 18 of 25
ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E
Data Sheet
THEORY OF OPERATION
is pulled to 0 V, resulting in a logic high with a 30 mV minimum
noise margin.
Table 12. Truth Table Abbreviations
Letter
Description
H
I
L
X
Z
High level
Indeterminate
Low level
Any state
High impedance (off)
HOT SWAP CAPABILITY
Table 13. Transmitting Truth Table
Supply Status
Inputs
Outputs
VIO1
VCC
RE
DE
DI
A/Y
B/Z
On
On
On
Off
On
Off
On
On
On
On
Off
Off
X
X
X
X
X
X
H
H
L
X
X
X
H
L
X
X
X
X
H
L
Z
I
Z
Z
L
H
Z
I
Z
Z
1
The VIO pin is not applicable for the ADM3061E/ADM3063E/ADM3065E/
ADM3067E.
Table 14. Receiving Truth Table
Supply Status
Inputs
Outputs
VIO1
VCC
A−B
RE
DE
RO
On
On
On
On
On
On
On
Off
Off
On
On
On
On
On
Off
Off
On
Off
>−0.03 V
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