ADM3251E

Isolated, Single-Channel RS-232 Line Driver/Receiver ADM3251E FEATURES 2.5 kV fully isolated (power and data) RS-232 transceiver isoPower integrated, isolated dc-to-dc converter 460 kbps data rate 1 Tx and 1 Rx Meets EIA/TIA-232E specifications ESD protection on RIN and TOUT pins ±8 kV: contact discharge ±15 kV: air gap discharge 0.1 μF charge pump capacitors High common-mode transient immunity: >25 kV/μs Safety and regulatory approvals (pending) UL recognition 2500 V rms for 1 minute per UL 1577 VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak Operating temperature range: −40°C to +85°C Wide body, 20-lead SOIC package FUNCTIONAL BLOCK DIAGRAM C1 0.1µF 16V C3 0.1µF 10V 0.1µF C2 0.1µF 16V C4 0.1µF 16V C1+ C1– V+ VISO C2+ C2– V– ADM3251E VCC 0.1µF ROUT DECODE VOLTAGE DOUBLER VOLTAGE INVERTER OSC RECT REG ENCODE R RIN* TOUT TIN ENCODE DECODE T *5kΩ PULL-DOWN RESISTOR ON THE RS-232 INPUT. Figure 1. APPLICATIONS High noise data communications Industrial communications General-purpose RS-232 data links Industrial/telecommunications diagnostic ports Medical equipment GENERAL DESCRIPTION The ADM3251E is a high speed, 2.5 kV fully isolated, singlechannel RS-232/V.28 transceiver device that operates from a single 5 V power supply. Due to the high ESD protection on the RIN and TOUT pins, the device is ideally suited for operation in electrically harsh environments or where RS-232 cables are frequently being plugged and unplugged. The ADM3251E incorporates dual-channel digital isolators with isoPower™ integrated, isolated power. There is no requirement to use a separate isolated dc-to-dc converter. Chip-scale transformer iCoupler® technology from Analog Devices, Inc., is used both for the isolation of the logic signals as well as for the integrated dc-to-dc converter. The result is a total isolation solution. The ADM3251E conforms to the EIA/TIA-232E and ITU-T V. 28 specifications and operates at data rates up to 460 kbps. Four external 0.1 μF charge pump capacitors are used for the voltage doubler/inverter, permitting operation from a single 5 V supply. The ADM3251E is available in a 20-lead, wide body SOIC package and is specified over the −40°C to +85°C temperature range. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. 07388-001 GND GNDISO ADM3251E TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Package Characteristics ............................................................... 5 Regulatory Information (Pending) ............................................ 5 Insulation and Safety-Related Specifications ............................ 5 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics (Pending) ............................................................ 6 Absolute Maximum Ratings............................................................ 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions..............................8 Typical Performance Characteristics ..............................................9 Theory of Operation ...................................................................... 11 Isolation of Power and Data ...................................................... 11 Charge Pump Voltage Converter ............................................. 12 5.0 V Logic to EIA/TIA-232E Transmitter.............................. 12 EIA/TIA-232E to 5 V Logic Receiver ...................................... 12 High Baud Rate ........................................................................... 12 Thermal Analysis ....................................................................... 12 PCB Layout ................................................................................. 13 Insulation Lifetime ..................................................................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14 REVISION HISTORY 7/08—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADM3251E SPECIFICATIONS All voltages are relative to their respective ground; all minimum/maximum specifications apply over the entire recommended operating range; TA = 25°C and VCC = 5.0 V (dc-to-dc converter enabled), unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS VCC Operating Voltage Range DC-to-DC Converter Enable Threshold, VCC(ENABLE) 1 DC-to-DC Converter Disable Threshold, VCC(DISABLE)1 DC-to-DC Converter Enabled Input Supply Current, ICC(ENABLE) VISO Output 2 LOGIC Transmitter Input, TIN Logic Input Current, ITIN Logic Low Input Threshold, VTINL Logic High Input Threshold, VTINH Receiver Output, ROUT Logic High Output, VROUTH Logic Low Output, VROUTL RS-232 Receiver, RIN EIA-232 Input Voltage Range 3 EIA-232 Input Threshold Low EIA-232 Input Threshold High EIA-232 Input Hysteresis EIA-232 Input Resistance Transmitter, TOUT Output Voltage Swing (RS-232) Transmitter Output Resistance Output Short-Circuit Current (RS-232) TIMING CHARACTERISTICS Maximum Data Rate Receiver Propagation Delay tPHL tPLH Transmitter Propagation Delay Transmitter Skew Receiver Skew Transition Region Slew Rate3 AC SPECIFICATIONS Output Rise/Fall Time, tR/tF (10% to 90%) Common-Mode Transient Immunity at Logic High Output 4 Common-Mode Transient Immunity at Logic Low Output4 ESD PROTECTION (RIN And TOUT PINS) Min 4.5 4.5 Typ Max 5.5 3.7 110 145 5.0 Unit V V V mA mA V VCC = 5.5 V, no load VCC = 5.5 V, RL = 3 kΩ IISO = 0 μA Test Conditions/Comments −10 0.7 VCC VCC − 0.1 VCC − 0.5 +0.01 +10 0.3 VCC μA V V V V V V IROUTH = −20 μA IROUTH = −4 mA IROUTH = 20 μA IROUTH = 4 mA VCC VCC − 0.3 0.0 0.3 0.1 0.4 −30 0.6 +30 2.0 2.1 0.1 5 ±5.7 ±12 2.4 7 3 ±5 300 V V V V kΩ V Ω mA kbps RL = 3 kΩ to GND VISO = 0 V 460 190 135 650 80 70 10 RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF 5.5 30 μs μs μs ns ns V/μs RL = 3 kΩ, CL = 1000 pF +3 V to −3 V or −3 V to +3 V, VCC = +3.3 V, RL = +3 kΩ, CL = 1000 pF, TA = 25°C CL = 15 pF, CMOS signal levels VCM = 1 kV, transient magnitude = 800 V VCM = 1 kV, transient magnitude = 800 V Human body model air discharge Human body model contact discharge 2.3 25 25 ±15 ±8 ns kV/μs kV/μs kV kV 1 2 Enable/disable threshold is the VCC voltage at which the internal dc-to-dc converter is enabled/disabled. To maintain data sheet specifications, do not draw current from VISO. 3 Guaranteed by design. 4 CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. 0 | Page 3 of 16 ADM3251E All voltages are relative to their respective ground; all minimum/maximum specifications apply over the entire recommended operating range; TA = 25°C, VCC = 3.3 V (dc-to-dc converter disabled), and the secondary side is powered externally by VISO = 3.3 V, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS VCC Operating Voltage Range DC-to-DC Converter Disable Threshold, VCC(DISABLE) 1 DC-to-DC Converter Disabled VISO 2 Primary Side Supply Input Current, ICC(DISABLE) Secondary Side Supply Input Current, IISO(DISABLE) Secondary Side Supply Input Current, IISO(DISABLE) LOGIC Transmitter Input, TIN Logic Input Current, ITIN Logic Low Input Threshold, VTINL Logic High Input Threshold, VTINH Receiver Output, ROUT Logic High Output, VROUTH Logic Low Output, VROUTL RS-232 Receiver, RIN EIA-232 Input Voltage Range 3 EIA-232 Input Threshold Low EIA-232 Input Threshold High EIA-232 Input Hysteresis EIA-232 Input Resistance Transmitter, TOUT Output Voltage Swing (RS-232) Transmitter Output Resistance Output Short-Circuit Current (RS-232) TIMING CHARACTERISTICS Maximum Data Rate Receiver Propagation Delay tPHL tPLH Transmitter Propagation Delay Transmitter Skew Receiver Skew Transition Region Slew Rate3 AC SPECIFICATIONS Output Rise/Fall Time, tR/tF (10% to 90%) Common-Mode Transient Immunity at Logic High Output 4 Common-Mode Transient Immunity at Logic Low Output4 ESD PROTECTION (RIN AND TOUT PINS) Min 3.0 Typ Max 3.7 3.7 5.5 1.5 12 6.2 Unit V V V mA mA mA Test Conditions/Comments 3.0 No load VISO = 5.5 V, RL = 3 kΩ RL = 3 kΩ −10 0.7 VCC VCC − 0.1 VCC − 0.5 +0.01 +10 0.3 VCC μA V V V V V V IROUTH = −20 μA IROUTH = −4 mA IROUTH = 20 μA IROUTH = 4 mA VCC VCC − 0.3 0.0 0.3 0.1 0.4 −30 0.6 +30 1.3 1.6 0.3 5 ±5.7 ±11 2.4 7 3 ±5 300 V V V V kΩ V Ω mA kbps RL = 3 kΩ to GND VISO = 0 V 460 190 135 650 80 55 10 RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF 5.5 30 μs μs μs ns ns V/μs RL = 3 kΩ, CL = 1000 pF +3 V to −3 V or −3 V to +3 V, VCC = 3.3 V, RL = 3 kΩ, CL = 1000 pF, TA = 25°C CL = 15 pF, CMOS signal levels VCM = 1 kV, transient magnitude = 800 V VCM = 1 kV, transient magnitude = 800 V Human body model air discharge Human body model contact discharge 2.3 25 25 ±15 ±8 ns kV/μs kV/μs kV kV 1 2 3 Enable/disable threshold is the VCC voltage at which the internal dc-to-dc converter is enabled/disabled. To maintain data sheet specifications, do not draw current from VISO. Guaranteed by design. 4 CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. 0 | Page 4 of 16 ADM3251E PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input-Output) Capacitance (Input-Output) Input Capacitance IC Junction-to-Air Thermal Resistance Symbol RI-O CI-O CI θJA Min Typ 1012 2.2 4.0 47.05 Max Unit Ω pF pF °C/W Test Conditions f = 1 MHz REGULATORY INFORMATION (PENDING) Table 4. UL 1 1577 Component Recognition Program (Pending) Single/Basic Insulation, 2500 V rms Isolation Rating 1 2 VDE To be certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 2 Reinforced insulation, 560 V peak In accordance with UL 1577, each ADM3251E is proof-tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA). In accordance with DIN V VDE V 0884-10, each ADM3251E is proof-tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 5. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Maximum Working Voltage Compatible with 50-Year Service Life Symbol L(I01) L(I02) Value 2500 7.7 4.16 0.017 >175 IIIa 425 Unit V rms mm mm mm V V peak Conditions 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303 Part 1 Material group (DIN VDE 0110, 1/89, Table 1) Continuous peak voltage across the isolation barrier CTI VIORM Rev. 0 | Page 5 of 16 ADM3251E DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS (PENDING) This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. Table 6. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 1) Maximum Working Insulation Voltage Input-to-Output Test Voltage Method b1 Method a After Environmental Test Subgroup 1 After Input and/or Safety Subgroup 2/Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Supply Current Insulation Resistance at TS Conditions Symbol Characteristic I to IV I to III 40/105/21 2 424 795 Unit VIORM VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 sec Maximum value allowed in the event of a failure VPR V peak V peak VPR VP VTR 680 510 4000 V peak V peak V peak VIO = 500 V TS IS1 RS 150 531 >109 °C mA Ω Rev. 0 | Page 6 of 16 ADM3251E ABSOLUTE MAXIMUM RATINGS Table 7. Parameter VCC, VISO V+ V− Input Voltages TIN RIN Output Voltages TOUT ROUT Short-Circuit Duration TOUT Power Dissipation θJA, Thermal Impedance Operating Temperature Range Industrial Storage Temperature Range Pb-Free Temperature (Soldering, 30 sec) Rating −0.3 V to +6 V (VCC − 0.3 V) to +13 V –13 V to +0.3 V −0.3 V to (VCC + 0.3 V) ±30 V ±15 V −0.3 V to (VCC + 0.3 V) Continuous 47.05°C/W −40°C to +85°C −65°C to +150°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 7 of 16 ADM3251E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 VCC 2 VCC 3 GND 4 GND 5 GND 6 GND 7 ROUT 8 TIN 9 GND 10 20 19 18 VISO V+ C1+ C1– TOUT RIN C2+ C2– V– 07388-002 ADM3251E TOP VIEW (Not to Scale) 17 16 15 14 13 12 11 GNDISO NC = NO CONNECT Figure 2. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2, 3 Mnemonic NC VCC Description No Connect. This pin should always remain unconnected. Power Supply Input. A 0.1 μF decoupling capacitor is required between VCC and ground. When a voltage between 4.5 V and 5.5 V is applied to the VCC pin, the integrated dc-to-dc converter is enabled. If this voltage is lowered to between 3.0 V and 3.7 V, the integrated dc-to-dc converter is disabled. Ground Pin. Receiver Output. This pin outputs CMOS logic levels. Transmitter (Driver) Input. This pin accepts TTL/CMOS levels. Ground Reference for Isolator Primary Side. Internally Generated Negative Supply. Positive and Negative Connections for Charge Pump Capacitors. External Capacitor C2 is connected between these pins; a 0.1 μF capacitor is recommended, but larger capacitors up to 10 μF can be used. Receiver Input. This input accepts RS-232 signal levels. Transmitter (Driver) Output. This outputs RS-232 signal levels. Positive and Negative Connections for Charge Pump Capacitors. External Capacitor C1 is connected between these pins; a 0.1 μF capacitor is recommended, but larger capacitors up to 10 μF can be used. Internally Generated Positive Supply. Isolated Supply Voltage for Isolator Secondary Side. A 0.1 μF decoupling capacitor is required between VISO and ground. When the integrated dc-to-dc converter is enabled, the VISO pin should not be used to power external circuitry. If the integrated dc-to-dc converter is disabled, power the secondary side by applying a voltage in the range of 3.0 V to 5.5 V to this pin. 4, 5, 6, 7, 10 8 9 11 12 13, 14 15 16 17, 18 19 20 GND ROUT TIN GNDISO V− C2−, C2+ RIN TOUT C1−, C1+ V+ VISO Rev. 0 | Page 8 of 16 ADM3251E TYPICAL PERFORMANCE CHARACTERISTICS 12 Tx HIGH (VCC = 5V) 8 Tx HIGH (VISO = 3.3V) Tx OUTPUT (V) 12 10 8 6 4 2 0 –2 –4 –6 Tx OUTPUT LOW (VISO = 3.3V) Tx OUTPUT HIGH (VISO = 3.3V) Tx OUTPUT HIGH (VCC = 5V) 4 Tx OUTPUT (V) 0 –4 Tx LOW (VISO = 3.3V) –8 Tx LOW (VCC = 5V) 07388-004 –8 –10 Tx OUTPUT LOW (VCC = 5V) 0 1 2 LOAD CURRENT (mA) 3 4 07388-006 07388-008 07388-007 –12 0 200 400 600 LOAD CAPACITANCE (pF) 800 1000 –12 Figure 3. Transmitter Output Voltage High/Low vs. Load Capacitance @ 460 kbps 12 10 8 6 Tx OUTPUT HIGH Figure 6. Transmitter Output Voltage High/Low vs. Load Current 15 V+ (VCC = 5V) 10 Tx OUTPUT (V) 4 2 0 –2 –4 –6 –8 –10 4.5 4.7 Tx OUTPUT LOW 07388-005 5 V+, V– (V) V+ (VISO = 3.3V) 0 V– (VISO = 3.3V) –5 –10 V– (VCC = 5V) 4.9 VCC (V) 5.1 5.3 5.5 –15 0 1 2 LOAD CURRENT (mA) 3 4 Figure 4. Transmitter Output Voltage High/Low vs. VCC, RL = 3 kΩ 12 10 8 6 Tx OUTPUT HIGH CHARGE PUMP IMPEDANCE (Ω) Figure 7. Charge Pump V+, V− vs. Load Current 400 V– 350 300 250 V+ 200 150 100 50 0 4.50 Tx OUTPUT (V) 4 2 0 –2 –4 –6 –8 Tx OUTPUT LOW –10 07388-009 –12 3.0 3.5 4.0 VISO (V) 4.5 5.0 5.5 4.75 5.00 VCC (V) 5.25 5.50 Figure 5. Transmitter Output Voltage High/Low vs. VISO, RL = 3 kΩ Figure 8. Charge Pump Impedance vs. VCC Rev. 0 | Page 9 of 16 ADM3251E 400 350 CHARGE PUMP IMPEDANCE (Ω) V– 5V/DIV 300 250 200 150 100 50 07388-010 1 V+ 5V/DIV 2 3.25 3.50 3.75 4.00 4.25 4.50 VISO (V) 4.75 5.00 5.25 5.50 TIME (500ns/DIV) Figure 9. Charge Pump Impedance vs. VISO 200 180 TIN VOLTAGE THRESHOLD (V) Figure 11. 460 kpbs Data Transmission 5.0 4.5 160 SUPPLY CURRENT (mA) VCC = 5.5V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 LOW THRESHOLD HIGH THRESHOLD 140 120 100 80 60 40 20 07388-003 VCC = 5V VCC = 4.5V 0 46 92 138 184 230 276 322 DATA RATE (kbps) 368 414 460 4.75 5.00 VCC (V) 5.25 5.50 Figure 10. Primary Supply Current vs. Data Rate Figure 12. TIN Voltage Threshold vs. VCC Rev. 0 | Page 10 of 16 07388-011 0 0 4.50 07388-012 0 3.00 VCC = 5V LOAD = 3kΩ AND 1nF ADM3251E THEORY OF OPERATION The ADM3251E is a high speed, 2.5 kV fully isolated, singlechannel RS-232 transceiver device that operates from a single power supply. The internal circuitry consists of the following main sections: • • • • Isolation of power and data A charge pump voltage converter A 5.0 V logic to EIA/TIA-232E transmitter A EIA/TIA-232E to 5.0 V logic receiver C1 0.1µF 16V C3 0.1µF 10V 0.1µF C2 0.1µF 16V C4 0.1µF 16V The ADM3251E can be operated with the dc-to-dc converter enabled or disabled. The internal dc-to-dc converter state of the ADM3251E is controlled by the input VCC voltage. In normal operating mode, VCC is set between 4.5 V and 5.5 V and the internal dc-to-dc converter is enabled. When/if it is desired to disable the dc-to-dc converter, lower VCC to a value between 3.0 V and 3.7 V. In this mode, the user must externally supply isolated power to the VISO pin. An isolated secondary side voltage of between 3.0 V and 5.5 V and a secondary side input current, IISO, of 12 mA (maximum) is required on the VISO pin. The signal channels of the ADM3251E then continue to operate normally. The TIN pin accepts TTL/CMOS input levels. The driver input signal that is applied to the TIN pin is referenced to logic ground (GND). It is coupled across the isolation barrier, inverted, and then appears at the transceiver section, referenced to isolated ground (GNDISO). Similarly, the receiver input (RIN) accepts RS-232 signal levels that are referenced to isolated ground. The RIN input is inverted and coupled across the isolation barrier to appear at the ROUT pin, referenced to logic ground. The digital signals are transmitted across the isolation barrier using iCoupler technology. Chip-scale transformer windings couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer of the winding. At the secondary winding, the induced waveforms are decoded into the binary value that was originally transmitted. There is hysteresis in the VCC input voltage detect circuit. Once the dc-to-dc converter is active, the input voltage must be decreased below the turn-on threshold to disable the converter. This feature ensures that the converter does not go into oscillation due to noisy input power. C1+ C1– V+ VISO C2+ C2– V– ADM3251E VCC 0.1µF ROUT DECODE VOLTAGE DOUBLER VOLTAGE INVERTER OSC RECT REG ENCODE R RIN* TOUT TIN ENCODE DECODE T *5kΩ PULL-DOWN RESISTOR ON THE RS-232 INPUT. Figure 13. Functional Block Diagram ISOLATION OF POWER AND DATA The ADM3251E incorporates a dc-to-dc converter section, which works on principles that are common to most modern power supply designs. VCC power is supplied to an oscillating circuit that switches current into a chip-scale air core transformer. Power is transferred to the secondary side, where it is rectified to a high dc voltage. The power is then linearly regulated to about 5.0 V and supplied to the secondary side data section and to the VISO pin. The VISO pin should not be used to power external circuitry. Because the oscillator runs at a constant high frequency independent of the load, excess power is internally dissipated in the output voltage regulation process. Limited space for transformer coils and components also adds to internal power dissipation. This results in low power conversion efficiency. Rev. 0 | Page 11 of 16 07388-013 GND GNDISO ADM3251E 4.5V TO 5.5V VCC 0.1µF VISO V+ C3 + 0.1µF 10V + C1 0.1µF 16V EIA/TIA-232E OUTPUT EIA/TIA-232E INPUT + C2 0.1µF 16V C4 + 0.1µF 16V + VISO S1 + S2 C1 S3 + S4 C3 VISO 07388-016 V+ = 2VISO 0.1µF GND INTERNAL OSCILLATOR ADM3251E C1+ C1– CMOS OUTPUT CMOS INPUT ROUT TIN TOUT RIN C2+ C2– ISOLATION BARRIER V– Figure 16. Charge Pump Voltage Doubler V+ FROM VOLTAGE DOUBLER GNDISO 07388-014 S1 + S2 C2 S3 + S4 C4 GNDISO V– = –(V+) 07388-017 GND GNDISO INTERNAL OSCILLATOR Figure 14. Typical Operating Circuit with the DC-to-DC Converter Enabled (VCC = 4.5 V to 5.5 V) 3.0V TO 5.5V ISOLATED SUPPLY 3.0V TO 3.7V VCC 0.1µF VISO V+ C3 + 0.1µF 10V + C1 0.1µF 16V EIA/TIA-232E OUTPUT EIA/TIA-232E INPUT + C2 0.1µF 16V C4 + 0.1µF 16V + 0.1µF Figure 17. Charge Pump Voltage Inverter 5.0 V LOGIC TO EIA/TIA-232E TRANSMITTER The transmitter driver converts the 5.0 V logic input levels into RS-232 output levels. When driving an RS-232 load with VCC = 5.0 V, the output voltage swing is typically ±10 V. ADM3251E C1+ C1– EIA/TIA-232E TO 5 V LOGIC RECEIVER The receiver is an inverting level-shifter that accepts the RS-232 input level and translates it into a 5.0 V logic output level. The input has an internal 5 kΩ pull-down resistor to ground and is also protected against overvoltages of up to ±30 V. An unconnected input is pulled to 0 V by the internal 5 kΩ pull-down resistor. This, therefore, results in a Logic 1 output level for an unconnected input or for an input connected to GND. The receiver has a Schmitt-trigger input with a hysteresis level of 0.1 V. This ensures error-free reception for both a noisy input and for an input with slow transition times. CMOS OUTPUT CMOS INPUT ROUT TIN TOUT RIN C2+ C2– ISOLATION BARRIER V– GND GNDISO Figure 15. Typical Operating Circuit with the DC-to-DC Converter Disabled (VCC = 3.0 V to 3.7 V) CHARGE PUMP VOLTAGE CONVERTER The charge pump voltage converter consists of a 200 kHz oscillator and a switching matrix. The converter generates a ±10.0 V supply from the input 5.0 V level. This is done in two stages by using a switched capacitor technique as illustrated in Figure 16 and Figure 17. First, the 5.0 V input supply is doubled to 10.0 V by using C1 as the charge storage element. The +10.0 V level is then inverted to generate −10.0 V using C2 as the storage element. C3 is shown connected between V+ and VISO, but is equally effective if connected between V+ and GNDISO. Capacitors C3 and C4 are used to reduce the output ripple. Their values are not critical and can be increased, if desired. Larger capacitors (up to 10 μF) can be used in place of Capacitors C1, C2, C3, and C4. 07388-015 HIGH BAUD RATE The ADM3251E offers high slew rates, permitting data transmission at rates well in excess of the EIA/TIA-232E specifications. The RS-232 voltage levels are maintained at data rates up to 460 kbps. THERMAL ANALYSIS Each ADM3251E device consists of three internal die, attached to a split-paddle lead frame. For the purposes of thermal analysis, it is treated as a thermal unit with the highest junction temperature reflected in the θJA value from Table 7. The value of θJA is based on measurements taken with the part mounted on a JEDEC standard 4-layer PCB with fine-width traces in still air. Following the recommendations in the PCB Layout section decreases the thermal resistance to the PCB, allowing increased thermal margin at high ambient temperatures. Rev. 0 | Page 12 of 16 ADM3251E PCB LAYOUT The ADM3251E requires no external circuitry for its logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 18). The power supply section of the ADM3251E uses a 300 MHz oscillator frequency to pass power through its chip-scale transformers. In addition, the normal operation of the data section of the iCoupler introduces switching transients on the power supply pins. Low inductance capacitors are required to bypass noise generated at the switching frequency as well as 1 ns pulses generated by the data transfer and dc refresh circuitry. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. In cases where EMI emission is a concern, series inductance can be added to critical power and ground traces. Discrete inductors should be added to the line such that the high frequency bypass capacitors are between the inductor and the ADM3251E device pin. Inductance can be added in the form of discrete inductors or ferrite beads added to both power and ground traces. The recommended value corresponds to impedance between 50 Ω and 100 Ω at approximately 300 MHz. In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins to exceed the absolute maximum ratings of the device, thereby leading to latch-up and/or permanent damage. VIA TO GNDISO 0.1µF VISO C3 V+ Because it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipating into the PCB through the GND pins. If the device is used at high ambient temperatures, care should be taken to provide a thermal path from the GND pins to the PCB ground plane. The board layout in Figure 18 shows enlarged pads for Pin 4, Pin 5, Pin 6, Pin 7, Pin 10, and Pin 11. Multiple vias should be implemented from each of the pads to the ground plane, which significantly reduce the temperatures inside the chip. The dimensions of the expanded pads are left to the discretion of the designer and the available board space. INSULATION LIFETIME All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADM3251E. The insulation lifetime of the ADM3251E depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 19, Figure 20, and Figure 21 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. RATED PEAK VOLTAGE 0V 07388-019 NC VCC VCC 0.1µF GND GND GND GND Figure 19. Bipolar AC Waveform ADM3251E C1 C1+ C1– TOUT RIN C2+ C2 RATED PEAK VOLTAGE 07388-020 07388-021 0V Figure 20. Unipolar AC Waveform ROUT TIN C4 GND RATED PEAK VOLTAGE C2– V– 0V GNDISO 07388-018 Figure 21. DC Waveform Outline Dimensions NC = NO CONNECT Figure 18. Recommended Printed Circuit Board Layout Rev. 0 | Page 13 of 16 ADM3251E OUTLINE DIMENSIONS 13.00 (0.5118) 12.60 (0.4961) 20 11 7.60 (0.2992) 7.40 (0.2913) 1 10 10.65 (0.4193) 10.00 (0.3937) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 0.75 (0.0295) 0.25 (0.0098) 8° 0° 45° SEATING PLANE 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 22. 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-20) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADM3251EARWZ 1 ADM3251EARWZ-REEL1 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 20-Lead Standard Small Outline Package [SOIC_W] 20-Lead Standard Small Outline Package [SOIC_W] Z = RoHS Compliant Part. Rev. 0 | Page 14 of 16 060706-A Package Option RW-20 RW-20 ADM3251E NOTES Rev. 0 | Page 15 of 16 ADM3251E NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07388-0-7/08(0) Rev. 0 | Page 16 of 16