ADM3485EARZ

±15 kV ESD-Protected, 3.3 V,12 Mbps, EIA RS-485/RS-422 Transceiver ADM3485E FEATURES TIA/EIA RS-485/RS-422 compliant ±15 kV ESD protection on RS-485 input/output pins 12 Mbps data rate Half-duplex transceiver Up to 32 nodes on the bus Receiver open-circuit, fail-safe design Low power shutdown current Outputs high-Z when disabled or powered off Common-mode input range: −7 V to +12 V Thermal shutdown and short-circuit protection Industry-standard 75176 pinout 8-lead narrow SOIC package FUNCTIONAL BLOCK DIAGRAM ADM3485E RO R B RE A DE DI D Power/energy metering Telecommunications EMI-sensitive systems Industrial control Local area networks 03338-001 APPLICATIONS Figure 1. GENERAL DESCRIPTION The ADM3485E is a 3.3 V, low power data transceiver with ±15 kV ESD protection, suitable for half-duplex communication on multipoint bus transmission lines. The ADM3485E is designed for balanced data transmission and complies with TIA/EIA standards RS­485 and RS-422. The ADM3485E is a half-duplex transceiver that shares differential lines and has separate enable inputs for the driver and the receiver. The devices have a 12 kΩ receiver input impedance, which allows up to 32 transceivers on a bus. Because only one driver should be enabled at any time, the output of a disabled or powered-down driver is tristated to avoid overloading the bus. The receiver has a fail-safe feature that ensures a logic high output when the inputs are floating. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. The part is fully specified over the industrial temperature range and is available in an 8-lead narrow SOIC package. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000-2010 Analog Devices, Inc. All rights reserved. ADM3485E TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits and Switching Characteristics...................................7 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................9 Functional Block Diagram .............................................................. 1 Standards and Testing .................................................................... 11 General Description ......................................................................... 1 ESD Testing ................................................................................. 11 Revision History ............................................................................... 2 Applications Information .............................................................. 12 Specifications..................................................................................... 3 Differential Data Transmission ................................................ 12 Timing Specifications....................................................................... 4 Cable and Data Rate ................................................................... 12 Absolute Maximum Ratings............................................................ 5 Receiver Open-Circuit Fail-Safe............................................... 12 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 13 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 13 Pin Configuration and Pin Function Descriptions ...................... 6 REVISION HISTORY 8/10—Rev. C to Rev. D Changes to Table 1, Driver, Logic Inputs ...................................... 3 12/06—Rev. B to Rev. C Updated Format .................................................................. Universal Removed PDIP Model ....................................................... Universal Changes to Features, Applications, and General Description .... 1 Changes to Specifications ................................................................ 3 Changes to Timing Specifications .................................................. 4 Changes to Absolute Maximum Ratings ....................................... 5 Reorganized Test Circuits and Switching Characteristics Section..................................................................... 7 Replaced Figure 3 to Figure 11 ....................................................... 7 Deleted Figure 12 to Figure 14 ........................................................ 8 Changes to Figure 15 to Figure 20 .................................................. 9 Changes to Figure 21 and Figure 22 ............................................. 10 Changes to Table 9 .......................................................................... 11 Deleted Figure 24 ............................................................................ 11 Removed Fast Transient Burst Immunity (IEC1000-4-4) Section ................................................................... 12 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 10/04—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Power-Supply Current, Table 1 .................................. 3 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 5/00—Rev. 0 to Rev. A Rev. D | Page 2 of 16 ADM3485E SPECIFICATIONS VCC = +3.3 V ± 0.3 V. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter DRIVER Differential Outputs Differential Output Voltage ∆|VOD| for Complementary Output States 1 Common-Mode Output Voltage ∆|VOC| for Complementary Output States1 Short-Circuit Output Current Symbol Min VOD 2.0 1.5 1.5 ∆VOD VOC ∆VOC IOSD Typ Max Unit Test Conditions/Comments V V V V V V mA mA RL = 100 Ω (RS-422) (see Figure 3) RL = 54 Ω (RS-485) (see Figure 3) RL = 60 Ω (RS-485) (see Figure 4) RL = 54 Ω or 100 Ω (see Figure 3) RL = 54 Ω or 100 Ω ( see Figure 3) RL = 54 Ω or 100 Ω (see Figure 3) VOUT = –7 V VOUT = 12 V V V µA DE, DI, RE DE, DI, RE DE, DI, RE V mV kΩ mA mA –7 V < VCM < +12 V VCM = 0 V –7 V < VCM < +12 V DE = 0 V, VCC = 0 V or 3.6 V, VIN = 12 V DE = 0 V, VCC = 0 V or 3.6 V, VIN = –7 V 0.4 ±60 ±1 V V mA µA IOUT = –1.5 mA, VID = 200 mV (see Figure 5) IOUT = 2.5 mA, VID = 200 mV (see Figure 5) 0 V < VRO < VCC VCC = 3.6 V, 0 V < VOUT < VCC 1.1 3.6 2.2 V mA 0.95 1.9 mA 0.002 1 µA No load, DI = 0 V or VCC, DE = VCC, RE = 0 V or VCC No load, DI = 0 V or VCC, DE = 0 V, RE = 0 V DE = 0 V, RE = VCC, DI = 0 V or VCC kV kV Human body model Human body model 0.2 3 0.2 –250 250 Logic Inputs Input Low Voltage Input High Voltage Logic Input Current RECEIVER Differential Inputs Differential Input Threshold Voltage Input Voltage Hysteresis Input Resistance (A, B) Input Current (A, B) VIL VIH IIN1 VTH ∆VTH RIN IIN2 0.8 2.0 ±2 –0.2 +0.2 50 12 1.0 –0.8 RO Logic Output Output Voltage High Output Voltage Low Short-Circuit Output Current Tristate Output Leakage Current POWER SUPPLY CURRENT Voltage Range Supply Current Shutdown Current ESD PROTECTION A, B Pins All Pins Except A, B 1 VOH VOL IOSR IOZR VCC – 0.4 V VCC ICC 3.0 ISHDN ±8 ±15 ±4 Δ|VOD| and Δ|VOC| are the changes in VOD and VOC, respectively, when DI input changes state. Rev. D | Page 3 of 16 ADM3485E TIMING SPECIFICATIONS VCC = 3.3 V, TA = 25°C. Table 2. Parameter DRIVER Maximum Data Rate Differential Output Delay Differential Output Transition Time Propagation Delay From Low to High Level From High to Low Level |tPLH − tPHL| Propagation Delay Skew Enable/Disable Timing Enable Time to Low Level Enable Time to High Level Disable Time from Low Level Disable Time from High Level Enable Time from Shutdown to Low Level Enable Time from Shutdown to High Level RECEIVER Propagation Delay From Low to High Level From High to Low Level |tRPLH − tRPHL| Propagation Delay Skew Enable/Disable Timing Enable Time to Low Level Enable Time to High Level Disable Time from Low Level Disable Time from High Level Enable Time from Shutdown to Low Level Enable Time from Shutdown to High Level Time to Shutdown1 1 Symbol Min Typ Max Unit Test Conditions/Comments tDD tTD 12 1 3 15 22 11 35 25 ns ns RL = 60 Ω, CL1 = CL2 = 15 pF (see Figure 6) RL = 60 Ω, CL1 = CL2 = 15 pF (see Figure 6) 7 7 23 23 –1.4 35 35 ±8 ns ns ns RL = 27 Ω (see Figure 7) RL = 27 Ω (see Figure 7) RL = 27 Ω (see Figure 7) 42 42 35 35 650 650 90 90 80 80 900 900 ns ns ns ns ns ns RL = 110 Ω (see Figure 9) RL = 110 Ω (see Figure 8) RL = 110 Ω (see Figure 9) RL = 110 Ω (see Figure 8) RL = 110 Ω (see Figure 9) RL = 110 Ω (see Figure 8) 62 62 6 90 90 ±10 ns ns ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 10) VID = 0 V to 3.0 V, CL = 15 pF (see Figure 10) VID = 0 V to 3.0 V, CL = 15 pF (see Figure 10) 25 25 25 25 720 720 190 50 50 45 45 1400 1400 300 ns ns ns ns ns ns ns CL = 15 pF (see Figure 11) CL = 15 pF (see Figure 11) CL = 15 pF (see Figure 11) CL = 15 pF (see Figure 11) CL = 15 pF (see Figure 11) CL = 15 pF (see Figure 11) tPLH tPHL tPDS tPZL tPZH tPLZ tPHZ tPSL tPSH tRPLH tRPHL tRPDS tRPZL tRPZH tRPLZ tRPHZ tRPSL tRPSH tSHDN 25 25 80 The transceivers are put into shutdown mode by bringing the RE high and the DE low. If the inputs are in this state for less than 80 ns, the parts are guaranteed not to enter shutdown. If the parts are in this state for 300 ns or more, the parts are guaranteed to enter shutdown. Rev. D | Page 4 of 16 ADM3485E ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter VCC to GND Digital Input/Output Voltage (DE, RE, DI) Receiver Output Voltage (RO) Driver Output (A, B)/ Receiver Input (A, B) Voltage Driver Output Current Power Dissipation (8-Lead SOIC_N) Operating Temperature Range Storage Temperature Range Lead Temperature, Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) ESD Rating Human Body Model (A, B) Values –0.3 V to +6 V –0.3 V to +6 V –0.3 V to (VCC + 0.3 V) −8 V to +13 V ±250 mA 650 mW –40°C to +85°C –65°C to +150°C 300°C 215°C 220°C Table 4. Thermal Resistance Package Type 8-Lead SOIC_N ESD CAUTION ±15 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. D | Page 5 of 16 θJA 158 Unit °C/W ADM3485E 8 VCC RE 2 ADM3485E 7 B DE 3 TOP VIEW (Not to Scale) 6 A 5 GND RO 1 DI 4 03338-002 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS Figure 2. SOIC_N Pin Configuration (R-8) Table 5. Pin Function Descriptions Mnemonic RO RE Pin Number 1 2 DE 3 DI 4 GND A B VCC 5 6 7 8 Description Receiver Output. When enabled, if A > B by 200 mV, then RO = high. If A < B by 200 mV, then RO = low. Receiver Output Enable. With RE low, the receiver output (RO) is enabled. With RE high, the output goes into a high impedance state. If RE is high and DE is low, the ADM3485E enters a shutdown state. Driver Output Enable. A high level enables the driver differential outputs A and B. A low level places it in a high impedance state. Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, while a logic high on DI forces A high and B low. Ground Connection, 0 V. Noninverting Receiver Input A/Driver Output A. Inverting Receiver Input B/Driver Output B. Power Supply, 3.3 V ± 0.3 V. Rev. D | Page 6 of 16 ADM3485E TEST CIRCUITS AND SWITCHING CHARACTERISTICS VOM A RL = 27Ω RL/2 S1 VOD B OUT D 03338-037 VOC RL/2 GENERATOR1 CL = 15pF2 50Ω VCC Figure 3. Driver Differential Output Voltage and Common-Mode Output Voltage VOM = VOH + VOL 2 ≈ 1.5V 375Ω 1PPR = 250kHz, 50% DUTY CYCLE, t ≤ 6.0ns, Z = 50Ω. O R 2C INCLUDES PROBE AND STRAY CAPACITANCE. L VCM = –7V TO +12V RL VOD VCC 3V 03338-038 D 375Ω IN 1.5V 1.5V 0V Figure 4. Driver Differential Output Voltage with Varying Common-Mode Voltage tPLH tPHL VOH A OUT VOM VOM VOL VID tPHL R tPLH VOH IOH (–) (+) 03338-039 IOL VOL B OUT VOM VOM VOL Figure 7. Driver Propagation Delays Figure 5. Receiver Output Voltage High and Output Voltage Low S1 CL 0V OR 3V RL = OUT 60Ω D GENERATOR1 03338-041 VOH 0 OUT D CL = 50pF2 RL = 110Ω 50Ω VCC GENERATOR1 CL = 15pF2 50Ω VOM = 1PPR = 250kHz, 50% DUTY CYCLE, t ≤ 6.0ns, Z = 50Ω. R O 2C INCLUDES PROBE AND STRAY CAPACITANCE. L VOH + VOL 2 ≈ 1.5V 1PPR = 250kHz, 50% DUTY CYCLE, t ≤ 6.0ns, Z = 50Ω. R O 2C INCLUDES PROBE AND STRAY CAPACITANCE. L +3V +1.5V +1.5V 3V 0V 90% tTD 1.5V 90% 0V ≈ +2V 50% 10% tTD ≈ –2V tPZH OUT 03338-040 50% 10% 1.5V tDD tDD OUT IN tPHZ 0.25V VOH VOM 0V Figure 6. Driver Differential Output Delay and Transition Times Figure 8. Driver Enable and Disable Times (tPZH, tPSH, tPHZ) Rev. D | Page 7 of 16 03338-042 IN ADM3485E VCC RL = 110Ω S1 0V OR 3V OUT D VID GENERATOR1 CL = 50pF2 OUT 50Ω CL = 15pF2 50Ω 1.5V VOM = 0V 1PPR = 250kHz, 50% DUTY CYCLE, t ≤ 6.0ns, Z = 50Ω. R O 2C INCLUDES PROBE AND STRAY CAPACITANCE. L 1.5V 3V 1.5V 1.5V IN 1.5V 0V 0V tPLZ tPSL tRPLH VCC OUT tRPHL VCC 0.25V 03338-043 VOM VOL VOM OUT Figure 10. Receiver Propagation Delays S1 S3 +1.5V VOM 0V Figure 9. Driver Enable and Disable Times (tPZL, tPSL, tPLZ) VID –1.5V VCC 1kΩ R S2 CL2 GENERATOR1 50Ω 1PPR = 250kHz, 50% DUTY CYCLE, t ≤ 6.0ns, Z = 50Ω. R O 2C INCLUDES PROBE AND STRAY CAPACITANCE. L +3V +1.5V IN 0V tRPZH tRPSH OUT S1 OPEN S2 CLOSED S3 = +1.5V +3V IN +1.5V VOH +1.5V VOL +3V +3V 0V S1 CLOSED S2 OPEN S3 = –1.5V VCC OUT +1.5V +1.5V S1 OPEN S2 CLOSED S3 = +1.5V +1.5V IN 0V tRPHZ S1 CLOSED S2 OPEN S3 = –1.5V tRPLZ VCC VOH OUT 0V tRPZL tRPSL 0V IN VOL 0V +0.25V Figure 11. Receiver Enable and Disable Times Rev. D | Page 8 of 16 03338-045 OUT +0.25V 2 1PPR = 250kHz, 50% DUTY CYCLE, t ≤ 6.0ns, Z = 50Ω. R O 2C INCLUDES PROBE AND STRAY CAPACITANCE. L 3V IN VCC 03338-044 GENERATOR1 R ADM3485E TYPICAL PERFORMANCE CHARACTERISTICS 25 0.8 IRO = 2.5mA 0.7 OUTPUT LOW VOLTAGE (V) OUTPUT CURRENT (mA) 20 15 10 5 0.6 0.5 0.4 0.3 0.2 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 OUTPUT LOW VOLTAGE (V) 0 –40 03338-051 0 Figure 12. Output Current vs. Receiver Output Low Voltage –18 100 –16 90 85 80 OUTPUT CURRENT (mA) –12 –10 –8 –6 –4 70 60 50 40 30 20 –2 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 OUTPUT HIGH VOLTAGE (V) 0 03338-052 0 0 0.5 1.0 1.5 2.0 2.5 3.0 Figure 13. Output Current vs. Receiver Output High Voltage Figure 16. Driver Output Current vs. Differential Output Voltage 2.6 3.30 3.5 DIFFERENTIAL OUTPUT VOLTAGE (V) 03338-055 10 RL = 54Ω DIFFERENTIAL OUTPUT VOLTAGE (V) IRO = –1.5mA 3.25 3.20 3.15 3.10 3.05 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 –25 0 25 50 75 TEMPERATURE (°C) 1.6 –50 03338-053 3.00 –50 –25 0 25 50 75 TEMPERATURE (°C) Figure 14. Receiver Output High Voltage vs. Temperature Figure 17. Driver Differential Output Voltage vs. Temperature Rev. D | Page 9 of 16 03338-056 OUTPUT CURRENT (mA) 60 Figure 15. Receiver Output Low Voltage vs. Temperature –14 OUTPUT HIGH VOLTAGE (V) 10 TEMPERATURE (°C) 03338-054 0.1 ADM3485E 0.9 120 0.8 0.7 SHUTDOWN CURRENT (µA) OUTPUT CURRENT (mA) 100 80 60 40 0.6 0.5 0.4 0.3 0.2 20 0 2 4 6 8 10 12 OUTPUT LOW VOLTAGE (V) 0 –50 03338-057 0 –25 0 25 50 03338-060 0.1 75 TEMPERATURE (°C) Figure 18. Output Current vs. Driver Output Low Voltage Figure 21. Shutdown Current vs. Temperature 120 DI 80 3 60 A 40 20 –6 –5 –4 –3 –2 –1 0 1 2 3 4 OUTPUT HIGH VOLTAGE (V) B CH1 1.0V Ω CH3 2.0V Ω 03338-058 0 –7 CH1 CH2 Figure 19. Output Current vs. Driver Output High Voltage CH2 1.0V Ω IT 400ps/pt A CH3 M20ns 1.25GS/s 1.44V 03338-061 OUTPUT CURRENT (mA) 100 Figure 22. Driver Propagation Delay 1.2 V A – VB 1.0 M1 0.9 0.8 0.7 RO 0.6 –10 20 50 TEMPERATURE (°C) 80 Figure 20. Supply Current vs. Temperature CH3 2.0V Ω M200ns 250MS/s MATH1 2.01V 200ns 4ns/pt A CH2 Figure 23. Receiver Propagation Delay, Driven by External RS-485 Device Rev. D | Page 10 of 16 1.24V 03338-062 3 0.5 –40 03338-059 SUPPLY CURRENT (mA) 1.1 ADM3485E STANDARDS AND TESTING Table 6 compares RS-422 and RS-485 interface standards, and Table 7 and Table 8 show transmitting and receiving truth tables. Table 6. Specification Transmission Type Maximum Data Rate Maximum Cable Length Minimum Driver Output Voltage Driver Load Impedance Receiver Input Resistance Receiver Input Sensitivity Receiver Input Voltage Range Number of Drivers/Receivers per Line RS-422 Differential 10 Mbps 4000 ft ±2 V 100 Ω 4 kΩ min ±200 mV −7 V to +7 V 1/10 RS-485 Differential 10 Mbps 4000 ft ±1.5 V 54 Ω 12 kΩ min ±200 mV −7 V to +12 V 32/32 Table 7. Transmitting Truth Table RE X1 X1 0 1 1 2 Transmitting Inputs DE DI 1 1 0 0 1 0 X1 X1 B Transmitting Outputs A 0 1 High-Z2 High-Z2 1 0 High-Z2 High-Z2 1 2 X1 X1 X1 X1 ESD Test Method Human Body Model Receiving Outputs A–B RO > +0.2 V < –0.2 V Inputs open X1 1 0 1 High-Z2 I/O Pins ±15 kV 100% 90% IPEAK 0 0 0 1 I/O lines are particularly vulnerable to ESD damage. Simply touching or plugging in an I/O cable can result in a static discharge that can damage or completely destroy the interface product connected to the I/O port. It is extremely important, therefore, to have high levels of ESD protection on the I/O lines. Table 9. ESD Test Results Table 8. Receiving Truth Table RE Although very little energy is contained within an ESD pulse, the extremely fast rise time, coupled with high voltages, can cause failures in unprotected semiconductors. Catastrophic destruction can occur immediately as a result of arcing or heating. Even if catastrophic failure does not occur immediately, the device can suffer from parametric degradation, which can result in degraded performance. The cumulative effects of continuous exposure can eventually lead to complete failure. The ESD discharge could induce latch-up in the device under test, so it is important that ESD testing on the I/O pins be carried out while device power is applied. This type of testing is more representative of a real-world I/O discharge, where the equipment is operating normally when the discharge occurs. X = don't care. High-Z = high impedance. Receiving Inputs DE influenced by humidity, temperature, barometric pressure, distance, and rate of closure of the discharge gun. The contact discharge method, while less realistic, is more repeatable and is gaining acceptance and preference over the air-gap method. X = don't care. High-Z = high impedance. ESD TESTING Rev. D | Page 11 of 16 36.8% 10% tRL tDL TIME t Figure 24. Human Body Model Current Waveform 03338-023 Two coupling methods are used for ESD testing, contact discharge and air-gap discharge. Contact discharge calls for a direct connection to the unit being tested. Air-gap discharge uses a higher test voltage but does not make direct contact with the unit under test. With air-gap discharge, the discharge gun is moved toward the unit under test, developing an arc across the air gap, hence the term air-gap discharge. This method is ADM3485E APPLICATIONS INFORMATION DIFFERENTIAL DATA TRANSMISSION Differential data transmission is used to reliably transmit data at high rates over long distances and through noisy environments. Differential transmission nullifies the effects of ground shifts and noise signals that appear as common-mode voltages on the line. Two main standards that specify the electrical characteristics of transceivers used in differential data transmission are approved by the Electronics Industries Association (EIA). The RS-422 standard specifies data rates up to 10 Mbps and line lengths up to 4000 feet. A single driver can drive a transmission line with up to 10 receivers. The RS-485 standard was defined to cater to true multipoint communications. This standard meets or exceeds all the requirements of RS-422 but also allows multiple drivers and receivers to be connected to a single bus. An extended common-mode range of −7 V to +12 V is defined. The most significant difference between RS-422 and RS-485 is the fact that under the RS-485 standard the drivers may be disabled, thereby allowing more than one to be connected to a single line. Only one driver should be enabled at a time, but the RS-485 standard contains additional specifications to guarantee device safety in the event of line contention. CABLE AND DATA RATE The transmission line of choice for RS-485 communications is a twisted pair. Twisted-pair cable tends to cancel common-mode noise and also causes cancellation of the magnetic fields generated by the current flowing through each wire, thereby reducing the effective inductance of the pair. The ADM3485E is designed for bidirectional data communications on multipoint transmission lines. A typical application showing a multipoint transmission network is illustrated in Figure 25. Only one driver can transmit at a particular time, but multiple receivers may be enabled simultaneously. As with any transmission line, it is important that reflections are minimized. This can be achieved by terminating the extreme ends of the line using resistors equal to the characteristic impedance of the line. Stub lengths off the main line must also be kept as short as possible. A properly terminated transmission line appears purely resistive to the driver. RECEIVER OPEN-CIRCUIT FAIL-SAFE The receiver input includes a fail-safe feature that guarantees a logic high on the receiver when the inputs are open circuit or floating. Table 10. RS-422 and RS-485 Interface Standards Specification Transmission Type Maximum Cable Length Minimum Driver Output Voltage Driver Load Impedance Receiver Input Resistance Receiver Input Sensitivity Receiver Input Voltage Range R A A R RO RE RE DE DE D B B A A B ADM3485E R R D RE DI B ADM3485E RO D DE D RO DI RE DE MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 50 Figure 25. Multipoint Transmission Network Rev. D | Page 12 of 16 DI 03338-027 DI RS-485 Differential 4000 ft ±1.5 V 54 Ω 12 kΩ min ±200 mV −7 V to +12 V ADM3485E ADM3485E RO RS-422 Differential 4000 ft ±2 V 100 Ω 4 kΩ min ±200 mV −7 V to +7 V ADM3485E OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 26. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 ADM3485EAR ADM3485EAR-REEL7 ADM3485EAR-REEL ADM3485EARZ ADM3485EARZ-REEL7 ADM3485EARZ-REEL 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Z = RoHS Compliant Part. Rev. D | Page 13 of 16 Package Option R-8 R-8 R-8 R-8 R-8 R-8 ADM3485E NOTES Rev. D | Page 14 of 16 ADM3485E NOTES Rev. D | Page 15 of 16 ADM3485E NOTES ©2000-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03338-0-8/10(D) Rev. D | Page 16 of 16