5 V, Slew-Rate Limited, Half-Duplex and
Full-Duplex RS-485/RS-422 Transceivers
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
VCC
EIA RS-485-/RS-422-compliant
Data rate options
ADM4850/ADM4854: 115 kbps
ADM4851/ADM4855: 500 kbps
ADM4852/ADM4856: 2.5 Mbps
ADM4853/ADM4857: 10 Mbps
Half- and full-duplex options
Reduced slew rates for low EMI
True fail-safe receiver inputs
5 µA (maximum) supply current in shutdown mode
Up to 256 transceivers on one bus
Outputs high-Z when disabled or powered off
−7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with the MAX308x
Specified over the −40°C to +85°C temperature range
Available in 8-lead SOIC, LFCSP, and MSOP packages
ADM4850/ADM4851/
ADM4852/ADM4853
RO
R
A
RE
B
DE
04931-001
D
DI
GND
Figure 1.
VCC
ADM4854/ADM4855/
ADM4856/ADM4857
A
RO
APPLICATIONS
R
B
Low power RS-485 applications
EMI-sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
Z
DI
D
GND
04931-028
Y
Figure 2.
GENERAL DESCRIPTION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 are differential line transceivers
suitable for high speed half- and full-duplex data communication on
multipoint bus transmission lines. They are designed for balanced
data transmission and comply with EIA Standards RS-485 and
RS-422. The ADM4850/ADM4851/ADM4852/ADM4853 are halfduplex transceivers that share differential lines and have separate
enable inputs for the driver and receiver. The full-duplex
ADM4854/ADM4855/ADM4856/ADM4857 transceivers have
dedicated differential line driver outputs and receiver inputs.
The parts have a 1/8-unit-load receiver input impedance, which
allows up to 256 transceivers on one bus. Because only one driver
should be enabled at any time, the output of a disabled or powered-down driver is three-stated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which ensures
a logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
before communication begins and when communication ends.
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by
output shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the commercial and industrial
temperature ranges and are available in 8-lead SOIC, LFCSP
(ADM4850/ADM4851/ADM4852/ADM4853), and MSOP
(ADM4850 only) packages.
Table 1. Selection Table
Part No.
ADM4850
ADM4851
ADM4852
ADM4853
ADM4854
ADM4855
ADM4856
ADM4857
Half-/Full-Duplex
Half
Half
Half
Half
Full
Full
Full
Full
Data Rate
115 kbps
500 kbps
2.5 Mbps
10 Mbps
115 kbps
500 kbps
2.5 Mbps
10 Mbps
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits..................................................................................... 10
Applications ....................................................................................... 1
Switching Characteristics .............................................................. 11
Functional Block Diagrams ............................................................. 1
Circuit Description......................................................................... 12
General Description ......................................................................... 1
Slew-Rate Control ...................................................................... 12
Revision History ............................................................................... 2
Receiver Input Filtering ............................................................. 12
Specifications..................................................................................... 3
Half-/Full-Duplex Operation ................................................... 12
ADM4850/ADM4854 Timing Specifications ........................... 4
High Receiver Input Impedance .............................................. 13
ADM4851/ADM4855 Timing Specifications ........................... 4
Three-State Bus Connection ..................................................... 13
ADM4852/ADM4856 Timing Specifications ........................... 5
Shutdown Mode ......................................................................... 13
ADM4853/ADM4857 Timing Specifications ........................... 5
Fail-Safe Operation .................................................................... 13
Absolute Maximum Ratings ............................................................ 6
Current Limit and Thermal Shutdown ................................... 13
ESD Caution .................................................................................. 6
Outline Dimensions ....................................................................... 14
Pin Configurations and Function Descriptions ........................... 7
Ordering Guide .......................................................................... 15
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
1/11—Rev. B to Rev. C
Change to Table 8, Pin 3 Description ............................................ 7
Changes to Figure 29 ...................................................................... 12
Changes to Ordering Guide .......................................................... 15
7/09—Rev. A to Rev. B
Added MSOP Package .................................................. Throughout
Changes to Table 2 ............................................................................ 3
Changes to Table 7 ............................................................................ 6
Added Figure 4; Renumbered Figures Sequentially..................... 7
Moved Typical Performance Characteristics Section .................. 8
Changes to Figure 24, Figure 27 ................................................... 11
Changes to Figure 29 ...................................................................... 12
Change to Shutdown Mode Section ............................................. 13
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
4/09—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 15
10/04—Revision 0: Initial Version
Rev. C | Page 2 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
DRIVER
Differential Output Voltage, VOD
|VOD3|
∆|VOD| for Complementary Output States
Common-Mode Output Voltage, VOC
∆|VOC| for Complementary Output States
Output Short-Circuit Current, VOUT = High
Output Short-Circuit Current, VOUT = Low
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low
CMOS Input Logic Threshold High
CMOS Logic Input Current (DI)
DE Input Resistance to GND
RECEIVER
Differential Input Threshold Voltage, VTH
Input Hysteresis
Input Resistance (A, B)
Input Current (A, B)
CMOS Logic Input Current (RE)
CMOS Output Voltage Low
CMOS Output Voltage High
Output Short-Circuit Current
Three-State Output Leakage Current
POWER SUPPLY CURRENT
115 kbps Options (ADM4850/ADM4854)
Min
Typ
2.0
1.5
1.5
−200
−200
Unit
Test Conditions/Comments
VCC
5
5
5
0.2
3
0.2
+200
+200
V
V
V
V
V
V
V
mA
mA
R = ∞, see Figure 18 1
R = 50 Ω (RS-422), see Figure 18
R = 27 Ω (RS-485), see Figure 18
VTST = −7 V to 12 V, see Figure 19
R = 27 Ω or 50 Ω, see Figure 18
R = 27 Ω or 50 Ω, see Figure 18
R = 27 Ω or 50 Ω, see Figure 18
−7 V < VOUT < +12 V
−7 V < VOUT < +12 V
0.8
V
V
µA
kΩ
2.0
±1
220
−200
96
−125
20
150
−30
−7 V < VOC < +12 V
−7 V < VOC < +12 V
−7 V < VOC < +12 V
VIN = +12 V
VIN = −7 V
85
±2
mV
mV
kΩ
mA
mA
µA
V
V
mA
µA
5
60
160
5
120
200
5
400
500
5
400
500
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
DE = 0 V, RE = VCC (shutdown)
DE = 0 V, RE = 0 V
DE = VCC
DE = 0 V, RE = VCC (shutdown)
DE = 0 V, RE = 0 V
DE = VCC
DE = 0 V, RE = VCC (shutdown)
DE = 0 V, RE = 0 V
DE = VCC
DE = 0 V, RE = VCC (shutdown)
DE = 0 V, RE = 0 V
DE = VCC
0.125
−0.1
±1
0.4
4.0
7
36
100
500 kbps Options (ADM4851/ADM4855)
80
120
2.5 Mbps Options (ADM4852/ADM4856)
250
320
10 Mbps Options (ADM4853/ADM4857)
250
320
1
Max
Guaranteed by design.
Rev. C | Page 3 of 16
IOUT = +4 mA
IOUT = −4 mA
VOUT = GND or VCC
0.4 V ≤ VOUT ≤ 2.4 V
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ADM4850/ADM4854 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay, tPLH, tPHL
Skew, tSKEW
Rise/Fall Times, tR, tF
Enable Time, tZH
Disable Time, tZL
Enable Time from Shutdown
RECEIVER
Propagation Delay, tPLH, tPHL
Differential Skew, tSKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shutdown
1
Min
Typ
115
600
600
Max
Unit
Test Conditions/Comments
2500
70
2400
2000
2000
kbps
ns
ns
ns
ns
ns
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850
RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4850
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850
ns
ns
ns
ns
ns
ns
CL = 15 pF, see Figure 22
CL = 15 pF, see Figure 22
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
ADM48501
4000
400
50
5
20
4000
330
1000
255
50
50
3000
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4851/ADM4855 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay, tPLH, tPHL
Skew, tSKEW
Rise/Fall Times, tR, tF
Enable Time, tZH
Disable Time, tZL
Enable Time from Shutdown
RECEIVER
Propagation Delay, tPLH, tPHL
Differential Skew, tSKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shutdown
1
Min
Typ
500
250
200
Max
Unit
Test Conditions/Comments
600
40
600
1000
1000
kbps
ns
ns
ns
ns
ns
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851
RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4851
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851
ns
ns
ns
ns
ns
ns
CL = 15 pF, see Figure 22
CL = 15 pF, see Figure 22
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
ADM48511
4000
400
50
5
20
4000
330
1000
250
50
50
3000
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
Rev. C | Page 4 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ADM4852/ADM4856 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay, tPLH, tPHL
Skew, tSKEW
Rise/Fall Times, tR, tF
Enable Time, tZH
Disable Time, tZL
Enable Time from Shutdown
RECEIVER
Propagation Delay, tPLH, tPHL
Differential Skew, tSKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shutdown
1
Min
Typ
2.5
50
Max
Unit
Test Conditions/Comments
180
50
140
180
180
Mbps
ns
ns
ns
ns
ns
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852
RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4852
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852
ns
ns
ns
ns
ns
ns
CL = 15 pF, see Figure 22
CL = 15 pF, see Figure 22
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
ADM48521
4000
55
50
5
20
4000
330
190
50
50
50
3000
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4853/ADM4857 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 6.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay, tPLH, tPHL
Skew, tSKEW
Rise/Fall Times, tR, tF
Enable Time, tZH
Disable Time, tZL
Enable Time from Shutdown
RECEIVER
Propagation Delay, tPLH, tPHL
Differential Skew, tSKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shutdown
1
Min
Typ
10
0
Max
Unit
Test Conditions/Comments
30
10
30
35
35
Mbps
ns
ns
ns
ns
ns
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853
RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4853
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853
ns
ns
ns
ns
ns
ns
CL = 15 pF, see Figure 22
CL = 15 pF, see Figure 22
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
ADM48531
4000
55
50
5
20
4000
330
190
30
50
50
3000
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
Rev. C | Page 5 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
VCC to GND
Digital I/O Voltage (DE, RE, DI, RO)
Driver Output/Receiver Input Voltage
Operating Temperature Range
Storage Temperature Range
θJA Thermal Impedance
SOIC
LFCSP
MSOP
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
6V
−0.3 V to VCC + 0.3 V
−9 V to +14 V
−40°C to +85°C
−65°C to +125°C
110°C/W
62°C/W
133.1°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
300°C
215°C
220°C
Rev. C | Page 6 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADM4850/ADM4851/
ADM4852/ADM4853
RE
2
DE 3
ADM4850/
ADM4851/
ADM4852/
ADM4853
8
VCC
7
B
6
A
TOP VIEW
DI 4 (Not to Scale) 5 GND
RE 2
DE 3
DI 4
04931-002
RO 1
PIN 1
INDICATOR
8 VCC
7 B
TOP VIEW
(Not to Scale)
6 A
5 GND
NOTES
1. THE EXPOSED PADDLE ON THE UNDERSIDE
OF THE PACKAGE SHOULD BE SOLDERED
TO THE GROUND PLANE TO INCREASE THE
RELIABILITY OF THE SOLDER JOINTS AND
TO MAXIMIZE THE THERMAL CAPABILITY OF
THE PACKAGE.
Figure 3. ADM4850/ADM4851/ADM4852/ADM4853 Pin Configuration,
SOIC and MSOP
04931-029
RO 1
Figure 4. ADM4850/ADM4851/ADM4852/ADM4853 Pin Configuration, LFCSP
Table 8. ADM4850/ADM4851/ADM4852/ADM4853 Pin Descriptions
Mnemonic
RO
RE
3
DE
4
DI
5
6
7
8
GND
A
B
VCC
Description
Receiver Output. When RO is enabled, if (A − B) ≥ −30 mV, RO = high; if (A − B) ≤ −200 mV, RO = low.
Receiver Output Enable. A low level on this pin enables the receiver output, RO. A high level places RO
into a high impedance state.
Driver Output Enable. A high level on this pin enables the driver differential outputs, A and B. A low level
places them into a high impedance state.
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, whereas a logic high
on DI forces A high and B low.
Ground.
Noninverting Receiver Input A/Noninverting Driver Output A.
Inverting Receiver Input B/Inverting Driver Output B.
5 V Power Supply.
VCC 1
RO 2
ADM4854/
ADM4855/
ADM4856/
ADM4857
8
A
7
B
Z
TOP VIEW
GND 4 (Not to Scale) 5 Y
DI 3
6
04931-003
Pin No.
1
2
Figure 5. ADM4854/ADM4855/ADM4856/ADM4857 Pin Configuration, SOIC
Table 9. ADM4854/ADM4855/ADM4856/ADM4857 Pin Descriptions
Pin No.
1
2
3
Mnemonic
VCC
RO
DI
4
5
6
7
8
GND
Y
Z
B
A
Description
5 V Power Supply.
Receiver Output. When RO is enabled, if (A − B) ≥ −30 mV, RO = high; if (A − B) ≤ −200 mV, RO = low.
Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, whereas a logic high
on DI forces Y high and Z low.
Ground.
Noninverting Driver Output.
Inverting Driver Output.
Inverting Receiver Input.
Noninverting Receiver Input.
Rev. C | Page 7 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
TYPICAL PERFORMANCE CHARACTERISTICS
400
0.40
ADM4853: DE = V CC
ADM4853: DE = GND
250
200
ADM4850: DE = V CC
150
100
ADM4850: DE = GND
50
0
–50
–25
0
25
50
75
100
0.30
0.25
0.20
0.15
–50
125
04931-017
OUTPUT LOW VOLTAGE (V)
0.35
300
04931-014
UNLOADED SUPPLY CURRENT (A)
350
–25
0
TEMPERATURE (°C)
25
50
TEMPERATURE (°C)
75
100
125
Figure 9. Receiver Output Low Voltage vs. Temperature
Figure 6. Unloaded Supply Current vs. Temperature
4.6
50
4.5
OUTPUT HIGH VOLTAGE (V)
40
35
30
25
20
15
10
4.4
4.3
4.2
5
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
RECEIVER OUTPUT LOW VOLTAGE (V)
1.8
4.0
–50
2.0
04931-018
4.1
04931-015
RECEIVER OUTPUT CURRENT (mA)
45
–25
0
25
50
TEMPERATURE (°C)
75
100
125
Figure 10. Receiver Output High Voltage vs. Temperature
Figure 7. Receiver Output Current vs. Receiver Output Low Voltage
5
0
–5
–10
–15
–20
3.5
4.0
4.5
5.0
RECEIVER OUTPUT HIGH VOLTAGE (V)
70
60
50
40
30
20
04931-019
DRIVER OUTPUT CURRENT (mA)
80
04931-016
RECEIVER OUTPUT CURRENT (mA)
90
10
0
5.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
DIFFERENTIAL OUTPUT VOLTAGE (V)
4.5
5.0
Figure 11. Driver Output Current vs. Differential Output Voltage
Figure 8. Receiver Output Current vs. Receiver Output High Voltage
Rev. C | Page 8 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
800
120
700
ADM4855
600
PROPAGATION DELAY (ns)
80
60
40
500
400
300
200
ADM4853
20
04931-020
0
100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (V)
4.0
4.5
0
5.0
04931-023
OUTPUT CURRENT (mA)
100
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 15. Receiver Propagation Delay vs. Temperature
Figure 12. Output Current vs. Driver Output Low Voltage
–30
3
–50
–70
–90
04931-021
–110
2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (V)
4.0
4.5
04931-024
OUTPUT CURRENT (mA)
–10
4
CH1 1.00V ΩBW
CH3 2.00VΩBW
5.0
Figure 13. Output Current vs. Driver Output High Voltage
CH2 1.00V ΩBW
CH4 5.00VΩ
M 400ns
CH3
2.00V
Figure 16. Driver/Receiver Propagation Delay (ADM4855, 500 kbps)
450
350
1
ADM4855
300
250
200
150
100
0
ADM4853
–50
–25
0
25
50
75
100
04931-025
2
50
4
04931-022
PROPAGATION DELAY (ns)
400
CH1 2.00VΩ BW
CH3 1.00VΩBW
125
TEMPERATURE (°C)
Figure 14. Driver Propagation Delay vs. Temperature
CH2 1.00VΩ
CH4 5.00VΩ
M 50.0ns
CH1
480mV
Figure 17. Driver/Receiver Propagation Delay (ADM4857, 4 Mbps)
Rev. C | Page 9 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
TEST CIRCUITS
VCC
A
VOD
0V OR 3V
VOC
04931-004
R
DE
CL
S2
VOUT
Figure 21. Driver Enable/Disable
3�7
5&
�
!
A
B
3�7
5&
�
!
Figure 19. Driver Voltage Measurement over Common-Mode Voltage Range
VOUT
RE
04931-008
�T�S
V
T
�
0�4�9�3�1
5
-0
�
6�
�&
0
!
B
DE IN
Figure 18. Driver Voltage Measurement
�O�D
V
3
�
RL
S1
04931-007
R
CL
Figure 22. Receiver Propagation Delay
+1.5V
VCC
RL
–1.5V
CL2
RE
04931-006
RLDIFF
B
S1
CL1
CL
VOUT
RE IN
Figure 20. Driver Propagation Delay
Figure 23. Receiver Enable/Disable
Rev. C | Page 10 of 16
S2
04931-009
A
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
SWITCHING CHARACTERISTICS
3V
3V
1.5V
0V
1.5V
0V
tPHL
tPLH
1.5V
tLZ
tZL
1/2VOD
VOD
2.3V
A, B
VOL + 0.5V
A
VOL
tSKEW = |tPLH – tPHL|
5V
tZH
VOH
90% POINT
90% POINT
A, B
10% POINT
10% POINT
tR
tF
VOH – 0.5V
2.3V
04931-010
0V
tHZ
0V
Figure 24. Driver Propagation Delay, Rise/Fall Timing
04931-012
B
DE
1.5V
Figure 26. Driver Enable/Disable Timing
3V
RE
0V
0V
tPLH
tPHL
1.5V
0V
tLZ
tZL
1.5V
RO
tSKEW = |tPLH – tPHL|
1.5V
VOL
04931-011
1.5V
RO
VOL
tHZ
tZH
RO
VOL + 0.5V
OUTPUT LOW
VOH
OUTPUT HIGH
1.5V
VOH
VOH – 0.5V
0V
Figure 27. Receiver Enable/Disable Timing
Figure 25. Receiver Propagation Delay
Rev. C | Page 11 of 16
04931-013
A, B
1.5V
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
CIRCUIT DESCRIPTION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 are high speed RS-485/
RS-422 transceivers offering enhanced performance over
industry-standard devices. All devices in the family contain
one driver and one receiver, but offer a choice of performance
options. The devices feature true fail-safe operation, which
means that a logic high receiver output is guaranteed when
the receiver inputs are open-circuit or short-circuit, or when
they are connected to a terminated transmission line with all
drivers disabled (see the Fail-Safe Operation section).
SLEW-RATE CONTROL
The ADM4850 and ADM4854 feature a controlled slew-rate
driver that minimizes electromagnetic interference (EMI) and
reduces reflections caused by incorrectly terminated cables,
allowing error-free data transmission rates up to 115 kbps. The
ADM4851 and ADM4855 offer a higher limit on driver output
slew rate, allowing data transmission rates up to 500 kbps. The
driver slew rates of the ADM4852 and ADM4856 and the
ADM4853 and ADM4857 are not limited, offering data
transmission rates up to 2.5 Mbps and 10 Mbps, respectively.
RECEIVER INPUT FILTERING
The receivers of all the devices incorporate input hysteresis. In
addition, the receivers of the 115 kbps ADM4850 and ADM4854
and the 500 kbps ADM4851 and ADM4855 incorporate input
filtering. This enhances noise immunity with differential signals
that have very slow rise and fall times. However, it causes the
propagation delay to increase by 20%.
HALF-/FULL-DUPLEX OPERATION
Half-duplex operation implies that the transceiver can transmit
and receive, but it can do only one of these at any given time. However, with full-duplex operation, the transceiver can transmit and
receive simultaneously. The ADM4850/ADM4851/ADM4852/
ADM4853 are half-duplex devices in which the driver and the
receiver share differential bus terminals. The ADM4854/
ADM4855/ADM4856/ADM4857 are full-duplex devices that
have dedicated driver output and receiver input pins. Figure 28
and Figure 29 show typical half- and full-duplex topologies.
ADM4850/ADM4851/
ADM4852/ADM4853
RO
R
ADM4850/ADM4851/
ADM4852/ADM4853
A
A
R
RO
RE
RE
DE
B
R
D
RO RE DE
DI
A
D
R
D
RO RE DE
DI
MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 256
Figure 28. Typical Half-Duplex RS-485 Network Topology
VCC
RO
DI
A
Y
B
Z
Z
B
Y
A
ADM4854/ADM4855/
ADM4856/ADM4857
D
R
R
D
GND
GND
Figure 29. Typical Full-Duplex Point-to-Point RS-485 Network Topology
Rev. C | Page 12 of 16
DI
RO
04931-027
VCC
ADM4854/ADM4855/
ADM4856/ADM4857
DI
B
04931-026
A
ADM4850/ADM4851/
ADM4852/ADM4853
D
B
ADM4850/ADM4851/
ADM4852/ADM4853
DI
DE
B
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
HIGH RECEIVER INPUT IMPEDANCE
FAIL-SAFE OPERATION
The input impedance of the ADM4850/ADM4851/ADM4852/
ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 receivers
is 96 kΩ, which is eight times higher than the standard RS-485
unit load of 12 kΩ. This 96 kΩ impedance enables a standard
driver to drive 32 unit loads or to be connected to 256 ADM4850/
ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/
ADM4856/ADM4857 receivers. An RS-485 bus, driven by a
single standard driver, can be connected to a combination of
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 devices and standard unit
load receivers, up to an equivalent of 32 standard unit loads.
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 offer true fail-safe operation
while remaining fully compliant with the ±200 mV EIA/TIA-485
standard. A logic high receiver output is generated when the
receiver inputs are shorted together or open circuit, or when
they are connected to a terminated transmission line with all
drivers disabled. This is done by setting the receiver threshold
between −30 mV and −200 mV. If the differential receiver input
voltage (A − B) is greater than or equal to −30 mV, RO is logic
high. If (A − B) is less than or equal to −200 mV, RO is logic low.
In the case of a terminated bus with all transmitters disabled,
the differential input voltage of the receiver is pulled to 0 V by
the internal circuitry of the ADM4850/ADM4851/ADM4852/
ADM4853/ADM4854/ADM4855/ADM4856/ADM4857, which
results in a logic high with 30 mV minimum noise margin.
THREE-STATE BUS CONNECTION
The half-duplex parts (ADM4850/ADM4851/ADM4852/
ADM4853) have a driver enable (DE) pin that enables the
driver outputs when taken high, or puts the driver outputs
into a high impedance state when taken low. Similarly, the
half-duplex devices have an active low receiver enable (RE) pin.
Taking this pin low enables the receiver, whereas taking it high
puts the receiver outputs into a high impedance state. This
allows several driver outputs to be connected to an RS-485 bus.
Note that only one driver should be enabled at a time, but that
many receivers can be enabled.
SHUTDOWN MODE
The ADM4850/ADM4851/ADM4852/ADM4853 have a low
power shutdown mode, which is enabled by taking RE high and
DE low. If shutdown mode is not used, the fact that DE is active
high and RE is active low offers a convenient way of switching the
device between transmit and receive by tying DE and RE together.
CURRENT LIMIT AND THERMAL SHUTDOWN
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 incorporate two protection
mechanisms to guard the drivers against short circuits, bus contention, or other fault conditions. The first is a current limiting
output stage, which protects the driver against short circuits over
the entire common-mode voltage range by limiting the output
current to approximately 70 mA. Under extreme fault conditions
where the current limit is not effective, a thermal shutdown circuit
puts the driver outputs into a high impedance state if the die
temperature exceeds 150°C, and does not turn them back on
until the temperature falls to 130°C.
If DE is driven low and RE is driven high for less than 50 ns,
the devices are guaranteed not to enter shutdown mode. If DE
is driven low and RE is driven high for at least 3000 ns, the
devices are guaranteed to enter shutdown mode.
Rev. C | Page 13 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
8
3.20
3.00
2.80
0.50 (0.0196)
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
45°
1
4
PIN 1
IDENTIFIER
8°
0°
0.51 (0.0201)
0.31 (0.0122)
5.15
4.90
4.65
5
0.65 BSC
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
0.95
0.85
0.75
0.15
0.05
COPLANARITY
0.10
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
15° MAX
1.10 MAX
0.23
0.09
6°
0°
0.40
0.25
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 31. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Figure 30. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
0.60 MAX
5
TOP
VIEW
PIN 1
INDICATOR
2.95
2.75 SQ
2.55
8
12° MAX
(BOTTOM VIEW)
SEATING
PLANE
0.50
0.40
0.30
0.70 MAX
0.65 TYP
0.05 MAX
0.01 NOM
0.30
0.23
0.18
0.20 REF
1.60
1.45
1.30
EXPOSED
PAD
4
0.90 MAX
0.85 NOM
0.50
BSC
0.60 MAX
1
1.89
1.74
1.59
PIN 1
INDICATOR
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 32. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
Rev. C | Page 14 of 16
090308-B
3.25
3.00 SQ
2.75
0.80
0.55
0.40
10-07-2009-B
8
4.00 (0.1574)
3.80 (0.1497)
3.20
3.00
2.80
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ORDERING GUIDE
Model1
ADM4850ACPZ-REEL7
ADM4850AR
ADM4850ARZ
ADM4850ARZ-REEL7
ADM4850ARMZ
ADM4850ARMZ-REEL7
ADM4851AR
ADM4851AR-REEL7
ADM4851ARZ
ADM4851ARZ-REEL7
ADM4852ACPZ-REEL7
ADM4852AR
ADM4852AR-REEL7
ADM4852ARZ
ADM4852ARZ-REEL7
ADM4853ACPZ-REEL7
ADM4853AR
ADM4853AR-REEL7
ADM4853ARZ
ADM4853ARZ-REEL7
ADM4854AR
ADM4854AR-REEL7
ADM4854ARZ
ADM4855AR
ADM4855AR-REEL7
ADM4855ARZ
ADM4856AR
ADM4856AR-REEL7
ADM4856ARZ
ADM4856ARZ-REEL7
ADM4857AR
ADM4857AR-REEL7
ADM4857ARZ
ADM4857ARZ-REEL7
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead LFCSP_VD
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead LFCSP_VD
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead LFCSP_VD
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Z = RoHS Compliant Part.
Rev. C | Page 15 of 16
Package Option
CP-8-2
R-8
R-8
R-8
RM-8
RM-8
R-8
R-8
R-8
R-8
CP-8-2
R-8
R-8
R-8
R-8
CP-8-2
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
Branding
M8Q
M8Q
M8Q
M9M
F0B
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
NOTES
©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04931-0-1/11(C)
Rev. C | Page 16 of 16
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