ADM699AQ

a FEATURES Superior Upgrade for MAX698/MAX699 Guaranteed RESET Assertion with VCC = 1 V Low 0.6 mA Supply Current Precision 4.65 V Voltage Monitor Power OK/Reset Time Delay Watchdog Timer Minimum Component Count Performance Specified over Temperature APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Automotive Systems Critical P Power Monitoring VCC Microprocessor Supervisory Circuits ADM698/ADM699 FUNCTIONAL BLOCK DIAGRAM ADM698/ ADM699 RESET GENERATOR 4.65V RESET* RESET WATCHDOG INPUT WDI* WATCHDOG TRANSITION DETECTOR (1 sec) WATCHDOG OUTPUT WDO* *WDI (ADM699 ONLY) RESET (SOIC ONLY) WDO (ADM699 SOIC ONLY) TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION +5V The ADM698/ADM699 supervisory circuits provide power supply monitoring and watchdog timing for microprocessor systems. The ADM698 monitors the 5 V VCC power supply and generates a RESET pulse during power up, power down and during low voltage “Brown Out” conditions. The RESET output is guaranteed to be functional (logic low) with VCC as low as 1 V. The ADM699 features an identical monitoring circuit as in the ADM698 plus an additional watchdog timer input to monitor microprocessor activity. The RESET output is forced low if the watchdog input is not toggled within the 1 second watchdog timeout period. Both parts are available in 8-pin plastic DIP and 16-lead SOIC packages. The 16-lead SOIC contains additional outputs RESET (without inversion) and Watchdog Output WDO (ADM699 only). VCC RESET µP POWER µP RESET ADM698/ ADM699 WDI* GND µP SYSTEM I/O LINE *ADM699 ONLY R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 ADM698/ADM699–SPECIFICATIONS (V Parameter Min Typ CC = +5 V Max 10%, TA = TMIN to TMAX unless otherwise noted) Units Test Conditions/Comments VCC Operating Voltage Range Supply Current Power-Down Reset Assertion Power-Up Reset Deassertion Reset Threshold Hysteresis Reset Active Time Watchdog Timeout Period (ADM699) Minimum WDI Input Pulse Width RESET Output Voltage RESET Output Voltage (VCC = 1 V) 3.0 0.6 4.5 4.65 40 200 1.6 5.5 1.95 4.73 4.73 280 2.25 0.4 200 0.4 V mA V V mV ms s ns V mV V V V mA V V µA µA 140 1.0 50 TA = +25°C, VCC = +5 V TA = +25°C, VCC = +5 V VIL = 0.4, VIH = 3.5 V ISINK = 1.6 mA, Vcc = 4.4 V ISINK = 10 µA, VCC = 1.0 V ISOURCE = 1 µA, VCC = 5 V ISINK = 1.6 mA, VCC = 5 V ISOURCE = 1 µA, VCC = 4.4 V Output Sink Current 4 3.5 RESET and WDO Output Voltage 3.5 RESET Output Short Circuit Current WDI Input Threshold (ADM699) Logic Low Logic High WDI Input Current Specifications subject to change without notice. 25 0.8 3.5 –50 20 –20 50 WDI = VCC, TA = +25°C WDI = 0 V, TA = +25°C ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) ORDERING GUIDE Temperature Range Package Option VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V All Other Inputs . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Power Dissipation 8-Pin DIP . . . . . . . . . . . . . . . . . . . . 500 mW θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . +120°C/W Power Dissipation 16-Pin SOIC . . . . . . . . . . . . . . . . . 375 mW θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . +110°C/W Power Dissipation 8-Pin Cerdip . . . . . . . . . . . . . . . . . . 500 mW θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . +125°C/W Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C *Stresses above those listed under “Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability. Model ADM698AN ADM698AR ADM698AQ ADM698SQ ADM699AN ADM699AR ADM699AQ ADM699SQ –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C N-8 R-16 Q-8 Q-8 N-8 R-16 Q-8 Q-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM698/ADM699 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –2– REV. 0 ADM698/ADM699 PIN CONFIGURATION (DIP) PIN FUNCTION DESCRIPTION Mnemonic Function VCC VCC GND GND 1 2 3 4 8 7 6 5 GND RESET NC (WDI)* NC VCC GND RESET WDI RESET WDO +5 V Power Supply Input. 0 V. Ground reference for all signals. Logic Output. RESET goes low whenever VCC falls below the reset voltage threshold (4.65 V typ). RESET remains low for a minimum of 140 ms after VCC returns to 5 V. RESET also goes low for a minimum of 140 ms if the watchdog timer is enabled but not serviced within its timeout period. Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog timer may be disabled if WDI is left floating or is driven to midsupply. (SOIC packages only) Logic Output. RESET is an active high output. It is the inverse of RESET. (SOIC ADM699 only) Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply, the watchdog timer is disabled and WDO remains high. 215 ADM698/ ADM699 O TOP VIEW (Not to Scale) *( ) ADM699 ONLY PIN CONFIGURATION (SOIC) GND 1 VCC 2 VCC 3 GND 4 16 RESET 13 NC TOP VIEW NC 5 (Not to Scale) 12 NC NC 6 NC 7 NC 8 11 NC (WDI)* 10 NC 9 GND O ADM698/ TOP VIEW ADM699 (Not to Scale) 15 RESET 14 NC (WDO)* *( ) ADM699 ONLY TYPICAL PERFORMANCE CURVES RESET ACTIVE TIME – ms A4 100 90 VCC = +5V 210 3.36 V 205 200 10 0% 1V 1V 500ms 195 20 40 60 80 100 120 TEMPERATURE – °C Figure 1. RESET Output Voltage vs. VCC 4.70 VCC = +5V 4.68 Figure 2. RESET Active Time vs. Temperature RESET VOLTAGE THRESHOLD – V POWER UP 4.66 4.64 POWER DOWN 4.62 20 40 60 80 TEMPERATURE – °C 100 120 Figure 3. RESET Voltage Threshold vs. Temperature REV. 0 –3– ADM698/ADM699 CIRCUIT INFORMATION Power Fail RESET Watchdog Timer (ADM699 Only) On power up, an internal monostable holds RESET low for 140 ms after VCC rises above the reset threshold. This allows the power supply to stabilize on power up and also prevents repeated toggling of RESET even if the 5 V power drops out and recovers with each power line cycle. In order to prevent mistriggering due to transient voltage spikes, it is recommended that a 0.1 µF capacitor be connected at the VCC pin. The RESET output is guaranteed to remain low with VCC as low as 1 V. This holds the microprocessor in a stable shutdown condition as the power supply comes up. On the 16-lead SOIC package, an active high RESET output is also provided. This is the complement of RESET and is intended for microprocessors requiring an active high signal. The WDI input is a three level input and will recognize a low to- high or a high-to-low transition on its input. The watchdog timer is reset by each WDI transition and then begins its timeout period. If the WDI pin remains either high or low, reset pulses will be issued every 1.6 seconds typically. If the watchdog timer is not needed, the WDI input should be left floating. The Watchdog Output (WDO) (SOIC package Only) provides watchdog status information. It is driven low if WDI is not toggled within the watchdog timeout period. It goes high at the next WDI transition. It is also set high when VCC falls below the reset threshold. WDI VCC V2 V1 V2 V1 WDO t2 RESET t2 t1 t1 RESET V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + THRESHOLD HYSTERESIS t1 = RESET TIME t1 t1 t1 t1 = RESET TIME t2 = WATCHDOG TIME OUT PERIOD Figure 4. Watchdog Timeout Period vs. Temperature Figure 5. Watchdog Timeout Period and Reset Active Time OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Pin Plastic DIP (N-8) 8-Pin Cerdip (Q-8) 16-Lead SOIC (R-16) 8 PIN 1 1 0.420 (10.67) MAX 0.200 (5.08) MAX 5 4 0.299 (7.60) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.419 (10.65) 1 8 SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.320 (8.13) 0.290 (7.37) 0.413 (10.50) 0.012 (0.3) 0.104 (2.65) 0.05 (1.27) REF 0.030 (0.75) 0.013 (0.32) 0.042 (1.07) 0.019 (0.49) 0.070 (1.78) 0.30 (0.76) 0.015 (0.381) 0.008 (0.204) –4– REV. 0 PRINTED IN U.S.A. 0.310 (7.87) 0.220 (5.59) 16 9 C1784–18–4/93 A precision voltage detector monitors VCC and generates a RESET output to hold the microprocessor’s Reset line low when VCC falls below the reset threshold (4.65 V) (see Figure 4). The reset voltage threshold is set to accommodate a 5% variation on VCC. The voltage detector has 40 mV hysteresis to ensure that glitches on VCC do not activate the RESET output. The watchdog timer input (WDI) monitors an I/O line from the µP system. The µP must toggle this input once every 1.6 seconds to verify correct software execution. Failure to toggle the line indicates that the µP system is not correctly executing its program and may be tied up in an endless loop. If this happens, a reset pulse is generated to initialize the processor.