ADM707ARM

a FEATURES Guaranteed RESET Valid with VCC = 1 V 190 A Quiescent Current Precision Supply-Voltage Monitor 4.65 V (ADM705/ADM707) 4.40 V (ADM706/ADM708) 200 ms Reset Pulsewidth Debounced TTL/CMOS Manual Reset Input ( MR) Independent Watchdog Timer—1.6 sec Timeout (ADM705/ADM706) Active High Reset Output (ADM707/ADM708) Voltage Monitor for Power-Fail or Low Battery Warning Superior Upgrade for MAX705–MAX708 Also Available in MicroSOIC Packages APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Critical P Monitoring Automotive Systems Critical P Power Monitoring GENERAL DESCRIPTION WATCHDOG INPUT (WDI) Low Cost P Supervisory Circuits ADM705–ADM708 FUNCTIONAL BLOCK DIAGRAMS WATCHDOG TRANSITION DETECTOR VCC 250 A MR VCC 4.65V* POWER-FAIL INPUT (PFI) 1.25V RESET GENERATOR RESET WATCHDOG TIMER WATCHDOG OUTPUT (WDO) RESET & WATCHDOG TIMEBASE ADM705/ ADM706 POWER-FAIL OUTPUT (PFO) *VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706) VCC 250 A MR VCC 4.65V* POWER-FAIL INPUT (PFI) 1.25V RESET GENERATOR RESET RESET The ADM705–ADM708 are low cost µP supervisory circuits. They are suitable for monitoring the 5 V power supply/battery and can also monitor microprocessor activity. The ADM705/ADM706 provide the following functions: 1. Power-On Reset output during power-up, power-down and brownout conditions. The RESET output remains operational with VCC as low as 1 V. 2. Independent watchdog timeout, WDO, that goes low if the watchdog input has not been toggled within 1.6 seconds. 3. A 1.25 V threshold detector for power-fail warning, low battery detection or to monitor a power supply other than 5 V. 4. An active low debounced manual reset input (MR). The ADM707/ADM708 differ in that: 1. A watchdog timer function is not available. 2. An active high reset output in addition to the active low output is available. ADM707/ ADM708 POWER-FAIL OUTPUT (PFO) *VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708) Two supply-voltage monitor levels are available. The ADM705/ ADM707 generate a reset when the supply voltage falls below 4.65 V, while the ADM706/ADM708 require that the supply fall below 4.40 V before a reset is issued. All parts are available in 8-lead DIP and SOIC packages. The ADM707 and ADM708 are also available in space-saving microSOIC packages. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 ADM705–ADM708–SPECIFICATIONS (V Parameter VCC Operating Voltage Range Supply Current Reset Threshold Reset Threshold Hysteresis Reset Pulsewidth RESET Output Voltage Min 1.0 190 4.5 4.25 160 VCC – 1.5 4.65 4.40 40 200 Typ Max 5.5 250 4.75 4.50 280 0.4 0.3 0.3 RESET Output Voltage Watchdog Timeout Period (tWD) WDI Pulsewidth (tWP) WDI Input Threshold Logic Low Logic High WDI Input Current WDO Output Voltage MR Pull-Up Current MR Pulsewidth MR Input Threshold MR to Reset Output Delay PFI Input Threshold PFI Input Current PFO Output Voltage Specifications subject to change without notice. CC = 4.75 V to 5.5 V, TA = TMIN to TMAX unless otherwise noted.) Unit V µA V V mV ms V V V V V V sec ns V V µA µA V V µA ns V V ns V nA V V ADM705, ADM707 ADM706, ADM708 ISOURCE = 800 µA ISINK = 3.2 mA VCC = 1 V, ISINK = 50 µA VCC = 1.2 V, ISINK = 100 µA ADM707, ADM708, ISOURCE = 800 µA ADM707, ADM708, ISINK = 1.2 mA VIL = 0.4 V, VIH = VCC × 0.8 Test Conditions/Comments VCC – 1.5 0.4 1.00 50 1.60 2.25 0.8 3.5 –150 VCC – 1.5 100 150 2.0 250 1.2 –25 VCC – 1.5 1.25 0.01 1.3 25 0.4 50 –50 150 0.4 250 600 0.8 WDI = VCC WDI = 0 V ISOURCE = 800 µA ISINK = 1.2 mA MR = 0 V ISOURCE = 800 µA ISINK = 3.2 mA ABSOLUTE MAXIMUM RATINGS * (TA = 25°C unless otherwise noted) ORDERING GUIDE VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Input Current VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 727 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . . 470 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >5 kV *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability Model ADM705AN ADM705AR ADM706AN ADM706AR ADM707AN ADM707AR ADM707ARM ADM708AN ADM708AR ADM708ARM Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Option N-8 SO-8 N-8 SO-8 N-8 SO-8 RM-8 N-8 SO-8 RM-8 –2– REV. B ADM705–ADM708 PIN FUNCTION DESCRIPTION Pin No. ADM705 ADM706 DIP, SOIC 1 ADM707 ADM708 DIP, SPOC MicroSOIC 1 3 Mnemonic MR Function Manual Reset Input. When taken below 0.8 V, a RESET is generated. MR can be driven from TTL, CMOS logic or from a manual reset switch as it is internally debounced. An internal 250 µA pull-up current holds the input high when floating. 5 V Power Supply Input. 0 V. Ground reference for all signals. Power-Fail Input. PFI is the noninverting input to the Power-Fail Comparator. When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected to GND or VCC. Power-Fail Output. PFO is the output from the Power-Fail Comparator. It goes low when PFI is less than 1.25 V. Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period, the watchdog output WDO goes low. The timer resets with each transition at the WDI input. Either a high-to-low or a low-to-high transition will clear the counter. The internal timer is also cleared whenever reset is asserted. The watchdog timer is disabled when WDI is left floating or connected to a three-state buffer. VCC GND PFI 2 3 4 2 3 4 4 5 6 PFO WDI 5 6 5 N/A 7 N/A NC RESET N/A 7 6 7 8 1 No Connect. Logic Output. RESET goes low for 200 ms when triggered. It can be triggered either by VCC being below the reset threshold or by a low signal on the manual reset (MR) input. RESET will remain low whenever VCC is below the reset threshold (4.65 V in ADM705, 4.4 V in ADM706). It remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog timeout will not trigger RESET unless WDO is connected to MR. Logic Output. The Watchdog Output, WDO, goes low if the internal watchdog timer times out as a result of inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes low during low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As soon as VCC goes above the reset threshold, WDO goes high immediately. Logic Output. RESET is an active high output suitable for systems that use active high RESET logic. It is the inverse of RESET. PIN CONFIGURATION DIP, SOIC WDO 8 N/A N/A RESET N/A 8 2 DIP, SOIC MicroSOIC MR 1 VCC 2 GND 3 PFI 4 8 WDO MR 1 VCC 2 GND 3 PFI 4 8 RESET RESET 1 8 NC ADM705/ ADM706 TOP VIEW (Not to Scale) 7 RESET 6 WDI 5 PFO ADM707/ ADM708 TOP VIEW (Not to Scale) 7 RESET 6 NC 5 PFO RESET 2 ADM707/ 7 PFO MR 3 VCC 4 ADM708 TOP VIEW (Not to Scale) 6 PFI 5 GND NC = NO CONNECT NC = NO CONNECT REV. B –3– ADM705–ADM708 Manual Reset (ADM707/ADM708) WATCHDOG INPUT (WDI) WATCHDOG TRANSITION DETECTOR VCC 250 A MR VCC 4.65V* POWER-FAIL INPUT (PFI) 1.25V RESET GENERATOR RESET WATCHDOG TIMER WATCHDOG OUTPUT (WDO) RESET & WATCHDOG TIMEBASE The manual reset input (MR) allows other reset sources, such as a manual reset switch, to generate a processor reset. The input is effectively debounced by the timeout period (200 ms typical). The MR input is TTL/CMOS compatible, so it may also be driven by any logic reset output. VCC VRT VRT tRS tRS ADM705/ ADM706 RESET POWER-FAIL OUTPUT (PFO) MR MR EXTERNALLY DRIVEN LOW *VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706) Figure 1. ADM705/ADM706 Functional Block Diagram WDO VCC 250 A MR VCC 4.65V* POWER-FAIL INPUT (PFI) 1.25V RESET GENERATOR RESET RESET Figure 3. RESET, MR, and WDO Timing Watchdog Timer (ADM705/ADM706) ADM707/ ADM708 POWER-FAIL OUTPUT (PFO) *VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708) Figure 2. ADM707/ADM708 Functional Block Diagram CIRCUIT INFORMATION Power-Fail RESET Output The watchdog timer circuit may be used to monitor the activity of the microprocessor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the Watchdog Input (WDI) line. If this line is not toggled within the timeout period (1.6 sec), the watchdog output (WDO) goes low. The WDO output may be connected to a nonmaskable interrupt (NMI) on the processor; therefore, if the watchdog timer times out, an interrupt is generated. The interrupt service routine should then be used to rectify the problem. If a RESET signal is required when a timeout occurs, the WDO output should be connected to the manual reset input (MR). The watchdog timer is cleared by either a high-to-low or by a low-to-high transition on WDI. It is also cleared by RESET going low; therefore, the watchdog timeout period begins after RESET goes high. When VCC falls below the reset threshold, WDO is forced low whether or not the watchdog timer has timed out. Normally, this would generate an interrupt, but it is overridden by RESET going low. The watchdog monitor can be deactivated by floating the Watchdog Input (WDI). The WDO output can now be used as a low-line output since it will only go low when VCC falls below the reset threshold. tWP WDI RESET is an active low output that provides a RESET signal to the Microprocessor whenever the VCC input is below the reset threshold. An internal timer holds RESET low for 200 ms after the voltage on VCC rises above the threshold. This is intended as a power-on RESET signal for the microprocessor. It allows time for both the power supply and the microprocessor to stabilize after power-up. The RESET output is guaranteed to remain valid (low) with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition as the power supply voltage ramps up. In addition to RESET, an active high RESET output is also available on the ADM707/ADM708. This is the complement of RESET and is useful for processors requiring an active high RESET signal. tWD tWD tWD WDO RESET RESET EXTERNALLY TRIGGERED BY MR tRS Figure 4. Watchdog Timing –4– REV. B ADM705–ADM708 Power-Fail Comparator The power-fail comparator is an independent comparator that may be used to monitor the input power supply. The comparator’s inverting input is internally connected to a 1.25 V reference voltage. The noninverting input is available at the PFI input. This input may be used to monitor the input power supply via a resistive divider network. When the voltage on the PFI input drops below 1.25 V, the comparator output (PFO) goes low, indicating a power failure. For early warning of power failure, the comparator may be used to monitor the preregulator input simply by choosing an appropriate resistive divider network. The PFO output can be used to interrupt the processor so that a shutdown procedure is implemented before the power is lost. INPUT POWER R1 1.25V POWER-FAIL PFI INPUT PFO POWER-FAIL OUTPUT  R2 + R 3  VH = 1.25 1 +   R1]  R2 × R 3  [  1.25 VCC – 1.25  – VL = 1.25 + R1    R2  RE  R1 + R2  VMID = 1.25    R2  Valid RESET Below 1 V VCC The ADM70x family of products is guaranteed to provide a valid reset level with VCC as low as 1 V; please refer to the Typical Performance Characteristics. As VCC drops below 1 V, the internal transistor will not have sufficient drive to hold it ON so the voltage on RESET will no longer be held at 0 V. A pull-down resistor as shown in Figure 7 may be connected externally to hold the line low if it is required. ADM70x R2 ADM70x Figure 5. Power-Fail Comparator Adding Hysteresis to the Power-Fail Comparator RESET GND R1 For increased noise immunity, hysteresis may be added to the power-fail comparator. Since the comparator circuit is noninverting, hysteresis can be added simply by connecting a resistor between the PFO output and the PFI input as shown in Figure 6. When PFO is low, resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, resistor R3 sources current into the PFI summing junction. This results in differing trip levels for the comparator. Further noise immunity may be achieved by connecting a capacitor between PFI and GND. 7V TO 15V INPUT POWER R1 1.25V PFI R2 ADM663 5V Figure 7. RESET Valid Below 1 V VCC PFO TO P NMI ADM70x R3 5V PFO 0V 0V VL VIN VH Figure 6. Adding Hysteresis to the Power-Fail Comparator REV. B –5– ADM705–ADM708–Typical Performance Characteristics VCC = 5V TA = 25 C A! VCC 100 90 4.50V 1.3V PFI 1.2V 4.4V 10 RESET 0% PFO 1V 1V 500msHo 0V 500ns/DIV Figure 8. RESET Output Voltage vs. Supply Voltage Figure 11. PFI Comparator Deassertion Response Time A1 VCC RESET 100 90 4.50V 5V VCC = VRT TA = 25 C RESET RESET 5V 10 0% 1V 1V 500msHo 0V 0V 100ns/DIV Figure 9. ADM707/ADM708 RESET Output Voltage vs. Supply Voltage Figure 12. RESET, RESET Assertion VCC = 5V TA = 25 C 1.3V PFI 1.2V 5V RESET VCC = VRT TA = 25 C 5V RESET 5V PFO 0V 0V 0V 500ns/DIV 100ns/DIV Figure 10. PFI Comparator Assertion Response Time Figure 13. RESET, RESET Deassertion –6– REV. B ADM705–ADM708 TA = 25 C 5V VCC 5V 4V If, in the event of inactivity on the WDI line, a system reset is required, then the WDO output should be connected to the MR input as shown in Figure 16. RESET RESET ADM705/ ADM706 WDI RESET P I/O LINE MR GND WDO 0V Figure 16. RESET from WDO Monitoring Additional Supply Levels 2 s/DIV Figure 14. ADM705/ADM707 RESET Response Time APPLICATIONS A Typical Operating Circuit is shown in Figure 15. The unregulated dc input supply is monitored using the PFI input via the resistive divider network. Resistors R1 and R2 should be selected so that when the supply voltage drops below the desired level (e.g., 8 V), the voltage on PFI drops below the 1.25 V threshold thereby generating an interrupt to the µP. Monitoring the preregulator input gives additional time to execute an orderly shutdown procedure before power is lost. ADM666 IN UNREGULATED DC GND OUT 5V It is possible to use the power-fail comparator to monitor a second supply as shown in Figure 17. The two sensing resistors, R1 and R2, are selected so that the voltage on PFI drops below 1.25 V at the minimum acceptable input supply. The PFO output may be connected to the MR input so that a RESET is generated when the supply drops out of tolerance. In this case, if either supply drops out of tolerance, a RESET will be generated. VX 5V VCC RESET R1 RESET ADM705/ ADM706 PFI MR GND PFO P R2 Figure 17. Monitoring 5 V and an Additional Supply, VX VCC R1 RESET WDI RESET I/O LINE VCC Ps With Bidirectional RESET ADM705/ ADM706 PFI MR WDO GND PFO NMI P INTERRUPT R2 MANUAL RESET In order to prevent contention for microprocessors with a bidirectional reset line, a current limiting resistor should be inserted between the ADM70x RESET output pin and the µP reset pin. This will limit the current to a safe level if there are conflicting output reset levels. A suitable resistor value is 4.7 kΩ. If the reset output is required for other uses, it should be buffered as shown in Figure 18. 5V BUFFERED RESET Figure 15. Typical Application Circuit Microprocessor activity is monitored using the WDI input. This is driven using an output line from the processor. The software routines should toggle this line at least once every 1.6 seconds. If a problem occurs and this line is not toggled, WDO goes low and a nonmaskable interrupt is generated. This interrupt routine may be used to clear the problem. VCC ADM70x RESET GND RESET P GND Figure 18. Bidirectional I-O RESET REV. B –7– ADM705–ADM708 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) C00088a–0–8/00 (rev. B) 0.39 (9.91) MAX 8 5 0.25 0.31 (6.35) (7.87) 1 4 PIN 1 0.165 ± 0.01 (4.19 ± 0.25) 0.125 (3.18) MIN 0.018 ± 0.003 (0.46 ± 0.08) 0.035 ± 0.01 (0.89 ± 0.25) 0.18 ± 0.03 (4.57 ± 0.76) 0.30 (7.62) REF 0.033 (0.84) NOM 0.10 (2.54) TYP SEATING PLANE 0° - 15° 0.011 ± 0.003 (4.57 ± 0.76) 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 0.1574 (4.00) 0.1497 (3.80) 1 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45° 0.0099 (0.25) 0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) 8-Lead MicroSOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.122 (3.10) 0.114 (2.90) 1 0.199 (5.05) 0.187 (4.75) 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.027 (0.68) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33° 27° 0.027 (0.68) 0.015 (0.38) –8– REV. B PRINTED IN U.S.A.