Low Cost Microprocessor
Supervisory Circuits
ADM705/ADM706/ADM707/ADM708
Data Sheet
FUNCTIONAL BLOCK DIAGRAMS
Guaranteed RESET valid with VCC = 1 V
190 μA quiescent current
Precision supply voltage monitor
4.65 V (ADM705/ADM707)
4.40 V (ADM706/ADM708)
200 ms reset pulse width
Debounced TTL/CMOS manual reset input (MR)
Independent watchdog timer (ADM705/ADM706)
1.60 sec timeout (ADM705/ADM706)
Active high reset output (ADM707/ADM708)
Voltage monitor for power fail or low battery warning
Superior upgrade for MAX705 to MAX708
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION
DETECTOR
VCC
250μA
MR
WATCHDOG
TIMER
RESET AND
WATCHDOG
TIMEBASE
RESET
GENERATOR
VCC
4.65V*
ADM705/
ADM706
POWER-FAIL
INPUT (PFI)
WATCHDOG
OUTPUT (WDO)
1.25V
RESET
POWER-FAIL
OUTPUT (PFO)
* VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706)
APPLICATIONS
00088-001
FEATURES
Figure 1. ADM705/ADM706
Microprocessor systems
Computers
Controllers
Intelligent instruments
Critical microprocessor supply monitoring
VCC
250μA
RESET
RESET
GENERATOR
VCC
4.65V*
POWER-FAIL
INPUT (PFI)
RESET
ADM707/
ADM708
POWER-FAIL
OUTPUT (PFO)
1.25V
* VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)
00088-002
MR
Figure 2. ADM707/ADM708
GENERAL DESCRIPTION
The ADM705/ADM706/ADM707/ADM708 microprocessor
supervisory circuits are suitable for monitoring 5 V power
supplies/batteries and microprocessor activity.
The ADM705/ADM706 provide power-supply monitoring
circuitry that generate a reset output during power-up, powerdown, and brownout conditions. The reset output remains
operational with VCC as low as 1 V. Independent watchdog
monitoring circuitry is also provided. This is activated if the
watchdog input has not been toggled within 1.60 sec.
In addition, there is a 1.25 V threshold detector to warn of
power failures, to detect low battery conditions, or to monitor an
additional power supply. An active low, debounced manual reset
input (MR) is also included.
Rev. H
The ADM705 and ADM706 are identical except for the reset
threshold monitor levels, which are 4.65 V and 4.40 V, respectively.
The ADM707 and ADM708 provide a similar functionality to
the ADM705 and ADM706 and only differ in that a watchdog
timer function is not available. Instead, an active high reset
output (RESET) is available as well as the active low reset output
(RESET). The ADM707 and ADM708 are identical except for
the reset threshold monitor levels, which are 4.65 V and 4.40 V,
respectively.
All devices are available in narrow 8-lead PDIP and 8-lead SOIC
packages.
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ADM705/ADM706/ADM707/ADM708
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power Fail RESET Output ............................................................8
Applications ....................................................................................... 1
Manual Reset..................................................................................8
Functional Block Diagrams ............................................................. 1
Watchdog Timer (ADM705/ADM706) .....................................8
General Description ......................................................................... 1
Power Fail Comparator.................................................................8
Revision History ............................................................................... 2
Valid RESET Below 1 V VCC ........................................................9
Specifications..................................................................................... 3
Applications Information .............................................................. 10
Absolute Maximum Ratings ............................................................ 4
Monitoring Additional Supply Levels...................................... 10
ESD Caution .................................................................................. 4
Microprocessor with Bidirectional RESET ............................. 10
Pin Configurations and Function Descriptions ........................... 5
Outline Dimensions ....................................................................... 11
Typical Performance Characteristics ............................................. 6
Ordering Guide .......................................................................... 12
Circuit Information .......................................................................... 8
REVISION HISTORY
1/16—Rev. G to Rev. H
Changes to Table 3 ............................................................................ 5
Changes to Power Fail Comparator Section and Figure 15 ........ 8
Changes to Figure 16 ........................................................................ 9
Changes to Figure 18 and Figure 20............................................. 10
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
3/08—Rev. F to Rev. G
Changes to Applications .................................................................. 1
Changes to Table 2 ............................................................................ 4
Changes to Figure 9 .......................................................................... 6
Changes to Figure 10, Figure 11, and Figure 12 ........................... 7
Changes to Figure 14 ........................................................................ 8
Changes to Ordering Guide .......................................................... 12
7/06—Rev. D to Rev. E
Added RM-8 (MSOP) Package ......................................... Universal
Changes to Table 2.............................................................................4
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
11/05—Rev. C to Rev. D
Updated Format .................................................................. Universal
Deleted Figure 2.................................................................................4
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 12
8/02—Rev. B to Rev. C
Removed RM-8 (µSOIC) Package .................................... Universal
Updated N-8 and R-8 Packages .......................................................8
2/07—Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to Watchdog Timeout Period .......................................... 3
Replaced Pin Configurations and Function Descriptions Section .. 5
Rev. H | Page 2 of 12
Data Sheet
ADM705/ADM706/ADM707/ADM708
SPECIFICATIONS
VCC = 4.75 V to 5.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
190
5.5
250
V
µA
4.75
4.50
V
V
mV
ms
V
V
V
V
V
V
sec
ns
Test Conditions/Comments
POWER SUPPLY
VCC Operating Voltage Range
Supply Current
1.0
LOGIC OUTPUT
Reset Threshold
Reset Threshold Hysteresis
RESET PULSE WIDTH
RESET OUTPUT VOLTAGE
4.5
4.25
160
VCC − 1.5
4.65
4.40
40
200
280
0.4
0.3
0.3
RESET OUTPUT VOLTAGE
VCC − 1.5
WATCHDOG TIMEOUT PERIOD (tWD)
WDI Pulse Width (tWP)
1.00
50
1.60
0.4
2.25
ADM705/ADM707
ADM706/ADM708
ISOURCE = 800 µA
ISINK = 3.2 mA
VCC = 1 V, ISINK = 50 µA
VCC = 1.2 V, ISINK = 100 µA
ADM707/ADM708, ISOURCE = 800 µA
ADM707/ADM708, ISINK = 1.2 mA
VIL = 0.4 V, VIH = VCC × 0.8, WDI = VCC
WATCHDOG INPUT
WDI Input Threshold
Logic Low
Logic High
WDI Input Current
WDO OUTPUT VOLTAGE
0.8
3.5
−150
VCC − 1.5
50
−50
150
0.4
V
V
µA
µA
V
V
WDI = 0 V
WDI = 0 V
ISOURCE = 800 µA
ISINK = 1.2 mA
MANUAL RESET INPUT
MR Pull-Up Current
MR Pulse Width
100
150
250
600
µA
ns
0.8
V
V
ns
MR = 0 V
MR INPUT THRESHOLD
Logic Low
Logic High
2.0
MR TO RESET OUTPUT DELAY
POWER FAIL INPUT
PFI Input Threshold
PFI Input Current
PFO OUTPUT VOLTAGE
250
1.2
−25
VCC − 1.5
1.25
+0.01
1.3
+25
0.4
Rev. H | Page 3 of 12
V
nA
V
V
ISOURCE = 800 µA
ISINK = 3.2 mA
ADM705/ADM706/ADM707/ADM708
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
VCC
All Other Inputs
Input Current
VCC
GND
Digital Output Current
Power Dissipation, N-8 PDIP
θJA Thermal Impedance
Power Dissipation, R-8 SOIC
θJA Thermal Impedance
Power Dissipation, RM-8 MSOP
θJA Thermal Impedance
Operating Temperature Range
Industrial (Version A)
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Storage Temperature Range
ESD Rating
Rating
−0.3 V to +6 V
−0.3 V to VCC + 0.3 V
20 mA
20 mA
20 mA
727 mW
135°C/W
470 mW
110°C/W
900 mW
206°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−40°C to +85°C
300°C
215°C
220°C
−65°C to +150°C
>4.5 kV
Rev. H | Page 4 of 12
Data Sheet
ADM705/ADM706/ADM707/ADM708
MR 1
ADM705/
ADM706
VCC 2
GND 3
8
WDO
7
RESET
6 WDI
TOP VIEW
PFI 4 (Not to Scale) 5 PFO
00088-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. ADM705/ADM706 PDIP/SOIC
Pin Configuration
MR 1
ADM707/
ADM708
VCC 2
8
RESET
7
RESET
6 NC
TOP VIEW
PFI 4 (Not to Scale) 5 PFO
NC = NO CONNECT
00088-004
GND 3
Figure 4. ADM707/ADM708 PDIP/SOIC
Pin Configuration
RESET 2
ADM708
8
NC
7 PFO
6 PFI
MR 3
TOP VIEW
VCC 4 (Not to Scale) 5 GND
NC = NO CONNECT
00088-005
RESET 1
Figure 5. ADM708 MSOP
Pin Configuration
Table 3. Pin Function Descriptions
Pin Number
ADM705/ ADM707/
ADM706
ADM708
ADM708
Mnemonic (PDIP, SOIC) (PDIP, SOIC) (MSOP)
1
1
3
MR
VCC
GND
PFI
2
3
4
2
3
4
PFO
5
5
WDI
6
Not
applicable
NC
6
RESET
Not
applicable
7
Description
Manual Reset Input. When this pin is taken below 0.8 V, a reset is generated. MR can be
driven from TTL, CMOS logic, or from a manual reset switch as it is internally debounced.
An internal 250 μA pull-up current holds the input high when floating.
4
5 V Power Supply Input. Place a 0.1 μF decoupling capacitor between the VCC and GND pins.
5
0 V Ground Reference for All Signals.
6
Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is
less than 1.25 V, PFO goes low. If unused, PFI must be connected to GND.
7
Power Fail Output. PFO is the output from the power fail comparator. It goes low when
PFI is less than 1.25 V.
Not
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer
applicable than the watchdog timeout period, the watchdog output (WDO) goes low. The timer
resets with each transition at the WDI input. Either a high to low or a low to high transition
clears the counter. The internal timer is also cleared whenever reset is asserted. The
watchdog timer is disabled when WDI is left floating or connected to a three-state buffer.
8
No Connect.
7
1
WDO
8
Not
applicable
RESET
Not
applicable
8
Logic Output. RESET goes low for 200 ms when triggered. It can be triggered either by
VCC being below the reset threshold or by a low signal on the manual reset input (MR).
RESET remains low whenever VCC is below the reset threshold (4.65 V in ADM705/ADM707,
4.40 V in ADM706/ADM708). It remains low for 200 ms after VCC goes above the reset
threshold or MR goes from low to high. A watchdog timeout does not trigger RESET unless
WDO is connected to MR.
Not
Watchdog Output. WDO remains low until the watchdog timer is cleared. WDO also
applicable goes low during low line conditions. Whenever VCC is below the reset threshold, WDO
goes low if the internal WDO remains low. As soon as VCC goes above the reset threshold,
WDO goes high.
2
Logic Output. RESET is an active high output suitable for systems that use active high
reset logic. It is the inverse of RESET.
Rev. H | Page 5 of 12
ADM705/ADM706/ADM707/ADM708
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
A1
VCC
VCC = 5V
TA = 25°C
4.50V
1.3V
100
90
PFI
1.2V
4.4V
PFO
10
0%
RESET
500msH O
0V
00088-015
1V
00088-012
1V
500ns/DIV
Figure 6. RESET Output Voltage vs. Supply Voltage
A1
VCC
Figure 9. PFI Comparator Deassertion Response Time
4.50V
5V
5V
RESET
RESET
100
90
RESET
VCC = VRT
TA = 25°C
10
0V
1V
500msH O
00088-016
1V
0V
00088-013
0%
100ns/DIV
Figure 7. ADM707/ADM708 RESET Output Voltage vs. Supply Voltage
VCC = 5V
TA = 25°C
Figure 10. RESET, RESET Assertion
5V
5V
RESET
1.3V
PFI
RESET
VCC = VRT
TA = 25°C
1.2V
5V
PFO
0V
0V
500ns/DIV
00088-017
00088-014
0V
100ns/DIV
Figure 8. PFI Comparator Assertion Response Time
Figure 11. RESET, RESET Deassertion
Rev. H | Page 6 of 12
Data Sheet
ADM705/ADM706/ADM707/ADM708
TA = 25°C
5V
VCC
4V
5V
0V
00088-018
RESET
2μs/DIV
Figure 12. ADM705/ADM707 RESET Response Time
Rev. H | Page 7 of 12
ADM705/ADM706/ADM707/ADM708
Data Sheet
CIRCUIT INFORMATION
POWER FAIL RESET OUTPUT
RESET is an active low output that provides a reset signal to
the microprocessor whenever the VCC input is below the reset
threshold. An internal timer holds RESET low for 200 ms after
the voltage on VCC rises above the threshold. This functions as a
power-on reset signal for the microprocessor. It allows time for
both the power supply and the microprocessor to stabilize after
power-up. The RESET output is guaranteed to remain valid (low)
with VCC as low as 1 V. This ensures that the microprocessor is
held in a stable shutdown condition as the power supply voltage
ramps up.
In addition to RESET, an active high RESET output is also available
on the ADM707/ADM708. This is the complement of RESET
and is useful for processors requiring an active high reset signal.
The watchdog timer is cleared by either a high to low or a low to
high transition on WDI. It is also cleared by RESET going low;
therefore, the watchdog timeout period begins after RESET
goes high.
When VCC falls below the reset threshold, WDO is forced low,
whether or not the watchdog timer has timed out. Normally, this
generates an interrupt, but it is overridden by RESET going low.
The watchdog monitor can be deactivated by floating the WDI.
The WDO can then be used as a low line output because it goes
low only when VCC falls below the reset threshold.
tWP
tWD
tWD
tWD
WDI
WDO
VCC
VRT
VRT
tRS
tRS
RESET
MR EXTERNALLY
DRIVEN LOW
00088-007
MR
WDO
Figure 13. RESET, MR, and WDO Timing
WATCHDOG TIMER (ADM705/ADM706)
The watchdog timer circuit can monitor the activity of the microprocessor to check that it is not stalled in an indefinite loop. An
output line on the processor toggles the watchdog input (WDI)
line. If this line is not toggled within the timeout period (1.60 sec),
then the watchdog output (WDO) goes low. The WDO can be
connected to a nonmaskable interrupt (NMI) on the processor;
therefore, if the watchdog timer times out, an interrupt is generated. The interrupt service routine then rectifies the problem.
RESET EXTERNALLY
TRIGGERED BY MR
RESET
tRS
Figure 14. Watchdog Timing
POWER FAIL COMPARATOR
The power fail comparator is an independent comparator that
can monitor the input power supply. The comparator inverting
input is internally connected to a 1.25 V reference voltage. The
noninverting input is available at the PFI input. This input can
monitor the input power supply via a resistive divider network.
When the voltage on the PFI input drops below 1.25 V, the
comparator output (PFO) goes low, indicating a power failure. For
early warning of power failure, the comparator monitors the
preregulator input by choosing an appropriate resistive divider
network. The PFO output can interrupt the processor so a
shutdown procedure is implemented before power is lost.
As the voltage on the PFI pin is limited to VCC + 0.3 V, it is
recommended to connect the PFI pin with a Schottky diode to
the RESET pin as shown in Figure 15. This helps clamping the
PFI pin voltage during device power up and operation.
INPUT
POWER
If a RESET signal is required when a timeout occurs, the WDO
must connect to the manual reset input (MR).
R1
R2
1.25V
POWER-FAIL PFI
INPUT
PFO
RESET
ADM705/ADM706/
ADM707/ADM708
Figure 15. Power Fail Comparator
Rev. H | Page 8 of 12
POWER-FAIL
OUTPUT
RESET
OUTPUT
00088-009
The manual reset input (MR) allows other reset sources, such as
a manual reset switch, to generate a processor reset. The input is
effectively debounced by the timeout period (200 ms typically).
The MR input is TTL-/CMOS-compatible, so it can also be driven
by any logic reset output.
00088-008
MANUAL RESET
Data Sheet
ADM705/ADM706/ADM707/ADM708
Adding Hysteresis to the Power Fail Comparator
When PFO is low, Resistor R3 sinks current from the summing
junction at the PFI pin. When PFO is high, Resistor R3 sources
current into the PFI summing junction. This results in differing
trip levels for the comparator. Further noise immunity can be
achieved by connecting a capacitor between PFI and GND. The
equations calculate the hysteresis are as follows:
For increased noise immunity, hysteresis can be added to the
power fail comparator. Because the comparator circuit is
noninverting, hysteresis can be added by connecting a resistor
between the PFO output and the PFI input as shown in Figure 16.
7V TO 15V
INPUT
POWER
5V
ADP3367
VCC
R1
1.25V
–
PFO
R2 R3
VH 1.251
R1
R2 R3
TO
MICROPROCESSOR
NMI
1.25 VCC 1.25
VL 1.25 R1
R3
R2
+
PFI
R2
RESET
ADM705/ADM706/
ADM707/ADM708
TO
MICROPROCESSOR
RESET
R1 R2
V MID 1.25
R2
R3
VALID RESET BELOW 1 V VCC
5V
VH
0V VL
VIN
Figure 16. Adding Hysteresis to the Power Fail Comparator
ADM705/ADM706/
ADM707/ADM708
RESET
GND
R1
Figure 17. RESET Valid Below 1 V
Rev. H | Page 9 of 12
00088-011
0V
00088-010
PFO
The ADM705/ADM706/ADM707/ADM708 are guaranteed to
provide a valid reset level with VCC as low as 1 V (see the Typical
Performance Characteristics section). As VCC drops below 1 V,
the internal transistor does not have sufficient drive to hold the
voltage RESET at 0 V. A pull-down resistor can connect externally,
as shown in Figure 17, to hold the line low if required.
ADM705/ADM706/ADM707/ADM708
Data Sheet
APPLICATIONS INFORMATION
A typical application circuit is shown in Figure 18. The unregulated dc input supply is monitored using PFI via the resistive
divider network. Resistor R1 and Resistor R2 must be selected
so when the supply voltage drops below the desired level (such
as 8 V), the voltage on PFI drops below the 1.25 V threshold,
thereby generating an interrupt to the microprocessor. Monitoring
the preregulator input provides additional time to execute an
orderly shutdown procedure before power is lost.
7V TO 15V
INPUT
POWER
MONITORING ADDITIONAL SUPPLY LEVELS
It is possible to use the power fail comparator to monitor a
second supply as shown in Figure 20. The two sensing resistors,
R1 and R2, are selected so the voltage on PFI drops below 1.25 V at
the minimum acceptable input supply. PFO can connect to MR so
a reset is generated when the supply drops out of tolerance. In
this case, if either supply drops out of tolerance, a reset is generated.
VX
5V
ADP3367
5V
VCC
RESET
VCC
R1
1.25V
–
MICROPROCESSOR
PFO
INTERRUPT
+
PFI
R2
ADM705/
ADM706
R1
RESET
RESET
MICROPROCESSOR
PFI
RESET
MR
R2
GND
PFO
00088-020
00088-022
ADM705/ADM706/
ADM707/ADM708
Figure 20. Monitoring 5 V and an Additional Supply, VX
Figure 18. Typical Application Circuit
Microprocessor activity is monitored using WDI. This is driven
using an output line from the processor. The software routines
toggle this line at least once every 1.60 seconds. If a problem occurs
and this line is not toggled, WDO goes low and a nonmaskable
interrupt is generated. This interrupt routine can clear the problem.
If, in the event of inactivity on the WDI line, a system reset is
required, WDO must connect to MR as shown in Figure 19.
WDI
5V
BUFFERED
RESET
MICROPROCESSOR
I/O LINE
VCC
WDO
GND
ADM70x
00088-021
MR
RESET
To prevent contention for microprocessors with a bidirectional
reset line, a current limiting resistor must be inserted between
the ADM705/ADM706/ADM707/ADM708 RESET output pin
and the microprocessor RESET pin. This limits the current to a
safe level if there are conflicting output reset levels. A suitable
resistor value is 4.7 kΩ. If the reset output is required for other
uses, it must be buffered, as shown in Figure 21.
RESET
Figure 19. RESET From WDO
GND
MICROPROCESSOR
RESET
GND
Figure 21. Bidirectional Input/Output RESET
Rev. H | Page 10 of 12
00088-023
RESET
ADM705/
ADM706
MICROPROCESSOR WITH BIDIRECTIONAL RESET
Data Sheet
ADM705/ADM706/ADM707/ADM708
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
1
PIN 1
0.210
(5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-BA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 22. 8-Lead Plastic Dual-in-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497) 1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
0.50 (0.0196)
× 45°
0.25 (0.0099)
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 23. 8-Lead Standard Small Outline Package [SOIC_N]
(R-8)
Dimensions shown in millimeters and (inches)
Rev. H | Page 11 of 12
ADM705/ADM706/ADM707/ADM708
Data Sheet
3.20
3.00
2.80
3.20
3.00
2.80
8
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
15° MAX
1.10 MAX
0.15
0.05
COPLANARITY
0.10
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
10-07-2009-B
0.95
0.85
0.75
Figure 24. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADM705AN
ADM705ANZ
ADM705AR
ADM705AR–REEL
ADM705AR–REEL7
ADM705ARZ
ADM705ARZ–REEL
ADM705ARZ–REEL7
ADM706ANZ
ADM706AR
ADM706AR-REEL
ADM706AR-REEL7
ADM706ARZ
ADM706ARZ-REEL
ADM706ARZ-REEL7
ADM707ANZ
ADM707AR
ADM707AR-REEL
ADM707ARZ
ADM707ARZ-REEL
ADM708ANZ
ADM708AR
ADM708AR-REEL
ADM708ARZ
ADM708ARZ-REEL
ADM708ARMZ
ADM708ARMZ-REEL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead Plastic Dual-in-Line Package [PDIP]
8-Lead Plastic Dual-in-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Plastic Dual-in-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Plastic Dual-in-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Plastic Dual-in-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
Z = RoHS Compliant Part.
©2002–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00088-0-1/16(H)
Rev. H | Page 12 of 12
Package Option
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
N-8
R-8
R-8
R-8
R-8
N-8
R-8
R-8
R-8
R-8
RM-8
RM-8
Branding
M8F
M8F
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