ADM708SARZ-REEL

3 V, Voltage Monitoring Microprocessor Supervisory Circuits ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T FUNCTIONAL BLOCK DIAGRAMS Precision supply voltage monitor 2.63 V (ADM706P, ADM706R, ADM708R) 2.93 V (ADM706S, ADM708S) 3.08 V (ADM706T, ADM708T) 100 µA quiescent current 200 ms reset pulse width Debounced manual reset input (MR) Independent watchdog timer 1.6 sec timeout (ADM706P, ADM706R, ADM706S, ADM706T) Reset output Active high (ADM706P) Active low (ADM706R, ADM706S, ADM706T) Both active high and active low (ADM708R, ADM708S, ADM708T) Voltage monitor for power fail or low battery warning Guaranteed RESET valid with VCC = 1 V Superior upgrade for MAX706P/R/S/T, MAX708R/S/T WATCHDOG INPUT (WDI) WATCHDOG TRANSITION DETECTOR VCC 70μA MR VREF* 1.25V RESET, (P = RESET) POWER-FAIL OUTPUT (PFO) * VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T) Figure 1. ADM706P/ADM706R/ADM706S/ADM706T VCC 70μA MR POWER-FAIL INPUT (PFI) RESET RESET GENERATOR VREF * Microprocessor systems Computers Controllers Intelligent instruments Critical microprocessor monitoring Battery operated systems Portable instruments ADM706P/ADM706R/ ADM706S/ADM706T POWER-FAIL INPUT (PFI) WATCHDOG OUTPUT (WDO) RESET AND WATCHDOG TIMEBASE RESET GENERATOR VCC VCC APPLICATIONS WATCHDOG TIMER 06435-001 FEATURES ADM708R/ADM708S/ ADM708T 1.25V RESET POWER-FAIL OUTPUT (PFO) * VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T) 06435-002 Data Sheet Figure 2. ADM708R/ADM708S/ADM708T GENERAL DESCRIPTION The ADM706P/ADM706R/ADM706S/ADM706T and the ADM708R/ADM708S/ADM708T microprocessor supervisory circuits are suitable for monitoring either 3 V or 3.3 V power supplies. The ADM706P/ADM706R/ADM706S/ADM706T provide power supply monitoring circuitry that generate a reset output during power-up, power-down, and brownout conditions. The reset output remains operational with VCC as low as 1 V. Independent watchdog monitoring circuitry is also provided. This activates if the watchdog input does not toggle within 1.6 sec. In addition, there is a 1.25 V threshold detector for a power fail warning, low battery detection, or to monitor an additional power supply. An active low debounced MR input is also included. Rev. E The ADM706R, ADM706S, and ADM706T are identical except for the reset threshold monitor levels, which are 2.63 V, 2.93 V, and 3.08 V, respectively. The ADM706P is identical to the ADM706R in that the reset threshold is 2.63 V. It differs only in that it has an active high reset output. The ADM708R/ADM708S/ADM708T provide similar functionality as the ADM706R/ADM706S/ADM706T and only differ in that a watchdog timer function is not available. Instead, an active high reset output (RESET) is provided in addition to the active low (RESET) output. All devices are available in narrow 8-lead PDIP and 8-lead SOIC packages. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Manual Reset............................................................................... 10  Applications ....................................................................................... 1  Functional Block Diagrams ............................................................. 1  Watchdog Timer (ADM706P/ADM706R/ ADM706S/ADM706T) .............................................................. 10  General Description ......................................................................... 1  Power Fail Comparator.............................................................. 11  Revision History ............................................................................... 2  Adding Hysteresis to the Power Fail Comparator ................. 11  Specifications..................................................................................... 3  Valid RESET Below 1 V VCC ..................................................... 11  Absolute Maximum Ratings............................................................ 5  Applications Information .............................................................. 12  ESD Caution .................................................................................. 5  Monitoring Additional Supply Levels...................................... 12  Pin Configurations and Function Descriptions ........................... 6  Microprocessors with Bidirectional RESET ........................... 12  Typical Performance Characteristics ............................................. 8  Outline Dimensions ....................................................................... 13  Circuit Information ........................................................................ 10  Ordering Guide .......................................................................... 14  Power Fail Reset .......................................................................... 10  REVISION HISTORY 1/16—Rev. D to Rev. E Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 7 Changes to Power Fail Comparator Section, Figure 17, and Figure 18 ................................................................................... 10 Changes to Figure 20 and Figure 22 ............................................. 12 Changes to Ordering Guide .......................................................... 14 10/14—Rev. C to Rev. D Changes to Pin 4 Description; Table 3 ........................................... 6 Changes to Pin 4 Description; Table 4 ........................................... 7 Changes to Ordering Guide .......................................................... 14 5/08—Rev. B to Rev. C Changes to Applications Section .....................................................1 Changes to Table 2.............................................................................5 Changes to Table 3.............................................................................6 Changes to Figure 8 ...........................................................................7 Changes to Figure 16.........................................................................9 2/07—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Table 1.............................................................................3 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 13 Rev. E | Page 2 of 16 Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T SPECIFICATIONS VCC = 2.70 V to 5.5 V (ADM706P/ADM706R/ADM708R), VCC = 3.00 V to 5.5 V (ADM70xS), VCC = 3.15 V to 5.5 V (ADM70xT), TA = TMIN to TMAX unless otherwise noted. Table 1. Parameter POWER SUPPLY VCC Operating Voltage Range Supply Current LOGIC OUTPUT Reset Threshold (VRST) Reset Threshold Hysteresis RESET PULSE WIDTH Min Typ Max Unit Test Conditions/Comments 100 150 5.5 200 350 V μA μA VCC < 3.6 V VCC < 5.5 V 2.70 3.00 3.15 V V V mV ms ms 1.0 2.55 2.85 3.00 2.63 2.93 3.08 20 200 200 160 160 280 280 ms ADM706P/ADM706R/ADM708R, VCC = 3 V ADM706S/ADM708S/ADM706T/ADM708T, VCC = 3.3 V VCC = 5.0 V V V V V V VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA VCC = 1 V, ISINK = 100 μA V V V V VRST (max) < VCC < 3.6 V, ISOURCE = 215 μA VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA 0.4 V V V V VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA VRST (max) < VCC < 3.6 V, ISINK = 500 μA 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA 4.5 V < VCC < 5.5 V, ISINK = 1.2 mA 2.25 sec ns ns ADM706P/ADM706R: VCC = 3 V; ADM706S/ADM706T: VCC = 3.3 V; VIL = 0.4 V, VIH = VCC × 0.8 V VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V V V V V μA VRST (max) < VCC < 3.6 V VRST (max) < VCC < 3.6 V VCC = 5.0 V VCC = 5.0 V WDI = 0 V or VCC 200 RESET OUTPUT VOLTAGE (ADM706R/ADM708R/ ADM706S/ADM708S/ADM706T/ADM708T) VOH VOL VOH VOL VOL RESET OUTPUT VOLTAGE (ADM706P) VOH VOL VOH VOL RESET OUTPUT VOLTAGE (ADM708R/ADM708S/ADM708T) VOH VOL VOH VOL WATCHDOG INPUT (ADM706P/ADM706R/ ADM706S/ADM706T) Watchdog Timeout Period WDI Pulse Width WDI Input Threshold VIL VIH VIL VIH WDI Input Current 0.8 × VCC 0.3 VCC − 1.5 V 0.4 0.3 VCC − 0.6 V 0.3 VCC − 1.5 V 0.4 0.8 × VCC 0.3 VCC − 1.5 V 1.00 1.60 100 50 0.6 0.7 × VCC 0.8 3.5 −1.0 +0.02 ADM706P/ADM706R/ADM708R ADM706S/ADM708S ADM706T/ADM708T +1.0 Rev. E | Page 3 of 16 ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Parameter WDO OUTPUT VOLTAGE VOH Min Typ MANUAL RESET INPUT MR Pull-Up Current (MR = 0 V) MR Pulse Width MR INPUT THRESHOLD VIL VIH VIL VIH MR TO RESET OUTPUT DELAY POWER FAIL INPUT PFI Input Threshold PFI Input Current PFO OUTPUT VOLTAGE VOH VOL VOH VOL Max Unit Test Conditions/Comments 0.3 0.4 V V V V VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA VRST (max) < VCC < 3.6 V, ISINK = 500 μA 4.5 V < VCC < 5.5 V, ISINK = 1.2 mA 250 600 μA μA ns ns VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V 0.6 750 250 V V V V ns ns VRST (max) < VCC < 3.6 V VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V 4.5 V < VCC < 5.5 V VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V ADM706P/ADM706R/ADM708R, VCC = 3 V ADM706S/ADM708S/ADM706T/ADM708T, VCC = 3.3 V, PFI falling 0.8 × VCC VCC − 1.5 V VOL 25 100 500 150 70 250 Data Sheet 0.7 × VCC 0.8 2.0 1.2 1.25 1.3 V −25 +0.01 +25 nA 0.8 × VCC 0.3 VCC − 1.5 V 0.4 Rev. E | Page 4 of 16 V V V V VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Table 2. Parameter VCC All Other Inputs Input Current VCC GND Digital Output Current Power Dissipation, N-8 (PDIP) θJA Thermal Impedance Power Dissipation, R-8 (SOIC) θJA Thermal Impedance Operating Temperature Range Industrial (Version A) Lead Temperature (Soldering, 10 sec) Vapor Phase (60 sec) Infrared (15 sec) Storage Temperature Range ESD Rating Rating −0.3 V to +6 V −0.3 V to VCC + 0.3 V 20 mA 20 mA 20 mA 727 mW 135°C/W 470 mW 110°C/W Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION −40°C to +85°C 300°C 215°C 220°C −65°C to +150°C >4.5 kV Rev. E | Page 5 of 16 ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADM706P 8 WDO 7 RESET MR 1 VCC 2 GND 3 GND 3 PFI 4 06435-003 6 WDI TOP VIEW PFI 4 (Not to Scale) 5 PFO Figure 3. ADM706P ADM706R/ ADM706S/ ADM706T 8 WDO 7 RESET WDI TOP VIEW 5 PFO (Not to Scale) 6 06435-004 MR 1 VCC 2 Figure 4. ADM706R/ADM706S/ADM706T Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T Pin No. 1 Mnemonic MR 2 3 4 VCC GND PFI 5 PFO 6 WDI 7 (ADM706R/ADM706S/ ADM706T Only) RESET 7 (ADM706P Only) RESET 8 WDO Description Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds the input high when floating. Power Supply Input. Place a 0.1 µF decoupling capacitor between the VCC and GND pins. Ground. Ground reference for all signals (0 V). Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is less than 1.25 V, PFO goes low. If unused, PFI connects to GND. Power Fail Output. PFO is the output from the power fail comparator. It goes low when PFI is less than 1.25 V. Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the watchdog output, WDO, goes low. The timer resets with each transition at the WDI input. Either a high to low or a low to high transition clears the counter. The internal timer is also cleared whenever reset is asserted. Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being below the reset threshold or by a low signal on the MR input. RESET remains low whenever VCC is below the reset threshold. It remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is connected to MR. Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the inverse of RESET. Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes low during low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As soon as VCC goes above the reset threshold, WDO goes high immediately. Rev. E | Page 6 of 16 ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T MR 1 VCC 2 GND 3 PFI 4 ADM708R/ ADM708S/ ADM708T 8 RESET 7 RESET 6 NC TOP VIEW 5 PFO (Not to Scale) NC = NO CONNECT 06435-005 Data Sheet Figure 5. ADM708R/ADM708S/ADM708T Table 4. Pin Function Descriptions ADM708R/ADM708S/ADM708T Pin No. 1 Mnemonic MR 2 3 4 VCC GND PFI 5 6 7 PFO NC RESET 8 RESET Description Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds the input high when floating. Power Supply Input. Place a 0.1 µF decoupling capacitor between the VCC and GND pins. Ground. Ground reference for all signals (0 V). Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is less than 1.25 V, PFO goes low. If unused, PFI must connect to GND. Power Fail Output. PFO is the output from the power fail comparator. It goes low when PFI is less than 1.25 V. No Connect. Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being below the reset threshold or by a low signal on the MR input. RESET remains low whenever VCC is below the reset threshold. It remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is connected to MR. Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the inverse of RESET. Rev. E | Page 7 of 16 ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VCC = 3.3V TA = 25°C 1.3V PFI VCC 1.2V 3V PFO RESET 400ms/DIV 06435-016 06435-013 0V 500ns/DIV Figure 6. ADM706R/ADM706S/ADM706T and the ADM708R/ADM708S/ADM708T RESET Output Voltage vs. Supply Voltage Figure 9. PFI Deassertion Response Time VCC = VRT TA = 25°C 3V VCC RESET 3V 0V 06435-017 0V 06435-014 RESET RESET 100ns/DIV 400ms/DIV Figure 10. RESET, RESET Assertion Figure 7. RESET Output Voltage vs. Supply Voltage VCC = VRT TA = 25°C VCC = 3.3V TA = 25°C 1.3V PFI 3V 1.2V 3V RESET RESET 3V PFO 0V 0V 100ns/DIV Figure 11. RESET, RESET Deassertion Figure 8. PFI Assertion Response Time Rev. E | Page 8 of 16 06435-018 500ns/DIV 06435-015 0V Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T TA = 25°C 3V VCC 2V 3V RESET 2µs/DIV 06435-019 0V Figure 12. ADM706R/ADM706S/ADM706T and the ADM708R/ADM708S/ADM708T RESET Response Time Rev. E | Page 9 of 16 ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet CIRCUIT INFORMATION WATCHDOG TRANSITION DETECTOR VCC 70μA MR MANUAL RESET WATCHDOG TIMER RESET AND WATCHDOG TIMEBASE RESET GENERATOR VCC VREF* ADM706P/ADM706R/ ADM706S/ADM706T POWER-FAIL INPUT (PFI) The MR input allows other reset sources, such as a manual reset switch, to generate a processor reset. The input is effectively debounced by the timeout period (200 ms typical). The MR input is TTL-/CMOS-compatible; it can also be driven by any logic reset output. If unused, the MR input can be tied high or left floating. WATCHDOG OUTPUT (WDO) 1.25V RESET, (P = RESET) VCC * VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T) Figure 13. ADM706P/ADM706R/ADM706S/ADM706T Functional Block Diagram tRS RESET MR EXTERNALLY DRIVEN LOW MR VCC VCC VREF * ADM708R/ADM708S/ ADM708T 1.25V NOTES RESET = COMPLEMENT OF RESET RESET Figure 15. RESET, MR, and WDO Timing WATCHDOG TIMER (ADM706P/ADM706R/ ADM706S/ADM706T) POWER-FAIL OUTPUT (PFO) * VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T) Figure 14. ADM708R/ADM708S/ADM708T Functional Block Diagram POWER FAIL RESET The reset output provides a reset (RESET or RESET) output signal to the microprocessor whenever the VCC input is below the reset threshold. The actual reset threshold voltage is dependent on whether a P, R, S, or T suffix device is used. An internal timer holds the reset output active for 200 ms after the voltage on VCC rises above the threshold. This is intended as a power-on reset signal for the microprocessor. It allows time for both the power supply and the microprocessor to stabilize after power-up. If a power supply brownout or interruption occurs, the reset line is similarly activated and remains active for 200 ms after the supply recovers. If another interruption occurs during an active reset period, the reset timeout period continues for an additional 200 ms. The reset output is guaranteed to remain valid with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition as the power supply starts up. The ADM706P provides an active high RESET signal; the ADM706R/ADM706S/ADM706T provide an active low RESET signal; and the ADM708R/ADM706S/ADM706T provide both RESET and RESET. The watchdog timer circuit monitors the activity of the microprocessor to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the watchdog input (WDI) line. If this line is not toggled within the timeout period (1.6 sec), the watchdog output (WDO) is driven low. The WDO output is connected to a nonmaskable interrupt (NMI) on the processor. Therefore, if the watchdog timer times out, an interrupt is generated. The interrupt service routine is used to rectify the problem. The watchdog timer is cleared either by a high to low or by a low to high transition on WDI. Pulses as narrow as 50 ns are detected. The timer is also cleared by RESET/RESET going active. Therefore, the watchdog timeout period begins after reset goes inactive. When VCC falls below the reset threshold, WDO is forced low whether or not the watchdog timer has timed out. Normally, this generates an interrupt, but it is overridden by RESET/RESET going active. tWP tWD tWD tWD WDI WDO RESET RESET EXTERNALLY TRIGGERED BY MR Figure 16. Watchdog Timing Rev. E | Page 10 of 16 tRS 06435-009 RESET GENERATOR 06435-007 MR RESET 06435-008 WDO 70μA POWER-FAIL INPUT (PFI) VRT VRT tRS POWER-FAIL OUTPUT (PFO) 06435-006 WATCHDOG INPUT (WDI) ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T The power fail comparator is an independent comparator that monitors the input power supply. The inverting input of the comparator internally connects to a 1.25 V reference voltage. The noninverting input is available at the PFI input. This input monitors the input power supply via a resistive divider network. When the voltage on the PFI input drops below 1.25 V, the comparator output (PFO) goes low, indicating a power failure. For early warning of power failure, the comparator monitors the preregulator input by choosing an appropriate resistive divider network. The PFO output interrupts the processor to implement a shutdown procedure before the power is lost. INPUT POWER VCC 1.25V R1 R2 POWER-FAIL PFI INPUT PFO PFO RESET TO µP NMI TO µP RESET ADM706R/ADM706S/ ADM706T/ADM708R/ ADM708S/ADM708T R3 3.3V PFO POWER-FAIL OUTPUT 0V VL VIN VH Figure 18. Adding Hysteresis to the Power Fail Comparator RESET   R2 + R3    R1 VH = 1.25 1 +    R2 × R3   RESET OUTPUT  1.25 VCC − 1.25  VL = 1.25 + R1  −  R3  R2  06435-010 ADM706R/ADM706S/ ADM706T/ADM708R/ ADM708S/ADM708T – + PFI R2 0V 1.25V 3.3V R1 As the voltage on the PFI pin is limited to VCC + 0.3 V, it is recommended to connect the PFI pin with a Schottky diode to the RESET pin, as shown in Figure 17. This helps with clamping the PFI pin voltage during device power up and operation. INPUT POWER ADM663A 06435-011 POWER FAIL COMPARATOR Figure 17. Power Fail Comparator  R1 + R2  VMID = 1.25    R2  ADDING HYSTERESIS TO THE POWER FAIL COMPARATOR For increased noise immunity, hysteresis can be added to the power fail comparator. Because the comparator circuit is noninverting, hysteresis is added simply by connecting a resistor between the PFO output and the PFI input as shown in Figure 18. When PFO is low, Resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, Resistor R3 sources current into the PFI summing junction. This results in differing trip levels for the comparator. Further noise immunity is achieved by connecting a capacitor between PFI and GND. VALID RESET BELOW 1 V VCC The ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ ADM708T are guaranteed to provide a valid reset level with VCC as low as 1 V. Refer to the Typical Performance Characteristics section. As VCC drops below 1 V, the internal transistor does not have sufficient drive to hold it on so the voltage on RESET is no longer held at 0 V. A pull-down resistor, as shown in Figure 19, can connect externally to hold the line low if it is required. ADM706R/ADM706S/ ADM706T/ADM708R/ ADM708S/ADM708T RESET GND R1 Figure 19. RESET Valid Below 1 V Rev. E | Page 11 of 16 06435-012 Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet APPLICATIONS INFORMATION A typical operating circuit is shown in Figure 20. The unregulated dc input supply is monitored using the PFI input via the resistive divider network. Resistor R1 and Resistor R2 are to be selected so that when the supply voltage drops below the desired level (for example, 5 V), the voltage on PFI drops below the 1.25 V threshold, thereby generating an interrupt to the microprocessor. Monitoring the preregulator input gives additional time to execute an orderly shutdown procedure before power is lost. It is possible to use the power fail comparator to monitor a second supply as shown in Figure 22. The two sensing resistors, R1 and R2, are selected such that the voltage on PFI drops below 1.25 V at the minimum acceptable input supply. The PFO output can connect to the MR input so a reset generates when the supply drops out of tolerance. In this case, if either supply drops out of tolerance, a reset is generated. ADM666A IN VX OUT GND +3V/+3.3V 3.3V VCC VCC WDI ADM706R/ ADM706S/ ADM706T MANUAL RESET PFI PFO RESET NMI MICROPROCESSORS WITH BIDIRECTIONAL RESET To prevent contention for microprocessors with a bidirectional reset line, a current limiting resistor is to be inserted between the ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ ADM708T RESET output pin and the microprocessor reset pin. This limits the current to a safe level if there are conflicting output reset levels. A suitable resistor value is 4.7 kΩ. If the reset output is required for other uses, it must be buffered as shown in Figure 23. RESET VCC RESET I/O LINE GND MICROPROCESSOR GND BUFFERED RESET +3V/+3.3V ADM706R/ADM706S/ ADM706T/ADM708R/ ADM708S/ADM708T 06435-021 MR WDO PFO GND Figure 22. Monitoring 3 V/3.3 V and an Additional Supply, VX If, in the event of inactivity on the WDI line, a system reset is required, the WDO output is to be connected to the input as shown in Figure 21. ADM706R/ ADM706S/ WDI ADM706T MICROPROCESSOR GND Microprocessor activity is monitored using the WDI input. This is driven using an output line from the processor. The software routines toggle this line at least once every 1.6 sec. If a problem occurs and this line is not toggled, WDO goes low and a nonmaskable interrupt is generated. This interrupt routine is to be used to clear the problem. PFI RESET RESET Figure 20. Typical Application Circuit RESET MR R2 INTERRUPT 06435-020 GND ADM706R/ WDI ADM706S/ PFI ADM706T I/O LINE MICROPROCESSOR WDO RESET 06435-022 MR R1 VCC MICROPROCESSOR RESET GND Figure 23. Bidirectional Input/Output RESET Figure 21. RESET from WDO Rev. E | Page 12 of 16 06435-023 UNREGULATED DC MONITORING ADDITIONAL SUPPLY LEVELS ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070606-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 24. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimension shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 25. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. E | Page 13 of 16 012407-A Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet ORDERING GUIDE Model 1 ADM706PANZ ADM706PARZ ADM706PARZ-REEL ADM706RANZ ADM706RAR ADM706RARZ ADM706RARZ-REEL ADM706RARZ-REEL7 ADM706SANZ ADM706SAR ADM706SAR-REEL ADM706SARZ ADM706SARZ-REEL ADM706TANZ ADM706TAR ADM706TAR-REEL ADM706TARZ ADM706TARZ-REEL ADM708RANZ ADM708RAR ADM708RAR-REEL ADM708RARZ ADM708RARZ-REEL ADM708SANZ ADM708SAR ADM708SAR-REEL ADM708SARZ ADM708SARZ-REEL ADM708TANZ ADM708TAR ADM708TARZ ADM708TARZ-REEL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] 8-Lead Small Outline Package [SOIC_N] Z = RoHS Compliant Part. Rev. E | Page 14 of 16 Package Option N-8 R-8 R-8 N-8 R-8 R-8 R-8 R-8 N-8 R-8 R-8 R-8 R-8 N-8 R-8 R-8 R-8 R-8 N-8 R-8 R-8 R-8 R-8 N-8 R-8 R-8 R-8 R-8 N-8 R-8 R-8 R-8 Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T NOTES Rev. E | Page 15 of 16 ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T NOTES ©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00089-0-1/16(E) Rev. E | Page 16 of 16 Data Sheet