600 mA, Ultralow Noise,
High PSRR, RF Linear Regulator
ADM7154
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
Input voltage range: 2.3 V to 5.5 V
Maximum load current: 600 mA
Low noise
0.9 µV rms total integrated noise from 100 Hz to 100 kHz
1.6 µV rms total integrated noise from 10 Hz to 100 kHz
Noise spectral density: 1.5 nV/√Hz from 10 kHz to 1 MHz
PSRR of 90 dB from 200 Hz to 200 kHz; 58 dB at 1 MHz,
VOUT = 3.3 V, VIN = 3.8 V
Dropout voltage: 120 mV typical at VOUT = 3.3 V, IOUT = 600 mA
Initial accuracy: ±0.5%
Accuracy over line, load, and temperature: −2.0% (minimum),
+1.5% (maximum), from −40°C to +85°C
Quiescent current, IGND = 4 mA at no load
Low shutdown current: 0.2 μA
Stable with a 10 µF ceramic output capacitor
Adjustable and fixed output voltage options: 1.2 V, 1.8 V, 2.5 V,
2.8 V, 3.0 V, 3.3 V (16 standard voltages between 1.2 V and
3.3 V available)
8-lead LFCSP and 8-lead SOIC packages
Precision enable
Supported by ADIsimPower tool
ADM7154
VIN = 3.8V
VOUT
VIN
CIN
10µF
VOUT = 3.3V
COUT
10µF
ON
EN
REF
CREF
1µF
OFF
BYP
CBYP
1µF
REF_SENSE
12324-001
VREG
CREG
10µF
GND
Figure 1. Regulated 3.3 V Output from 3.8 V Input
APPLICATIONS
Regulation to noise sensitive applications: PLLs, VCOs, and
PLLs with integrated VCOs
Communications and infrastructure
Backhaul and microwave links
NOISE FLOOR
1.0µF
3.3µF
10µF
33µF
100µF
330µF
1000µF
1k
100
10
1
0.1
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
12324-046
NOISE SPECTRAL DENSITY (nV/√Hz)
10k
Figure 2. Noise Spectral Density for Different Values of CBYP
GENERAL DESCRIPTION
The ADM7154 is a linear regulator that operates from 2.3 V to
5.5 V and provides up to 600 mA of load current. Using an
advanced proprietary architecture, it provides high power
supply rejection and ultralow noise, achieving excellent line and
load transient response with only a 10 µF ceramic output capacitor.
The ADM7154 is available in 8-lead, 3 mm × 3 mm LFCSP and
8-lead SOIC packages, making it not only a very compact
solution, but also providing excellent thermal performance for
applications requiring up to 600 mA of load current in a small,
low profile footprint.
There are 16 standard output voltages for the ADM7154. The
following voltages are available in stock: 1.2 V, 1.8 V, 2.5 V, 2.8 V,
3.0 V, and 3.3 V. Additional voltages are available by special
order: 1.3 V, 1.5 V, 1.6 V, 2.0 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V, 3.1 V,
and 3.2 V.
Table 1. Related Devices
The ADM7154 regulator typical output noise is 0.9 μV rms from
100 Hz to 100 kHz for fixed output voltage options and
1.5 nV/√Hz for noise spectral density from 10 kHz to 1 MHz.
Model
ADM7150ACP
ADM7150ARD
ADM7151ACP
ADM7151ARD
ADM7155ACP
ADM7155ARD
1
Rev. B
Input
Voltage
4.5 V to 16 V
4.5 V to 16 V
4.5 V to 16 V
4.5 V to 16 V
2.3 V to 5.5 V
2.3 V to 5.5 V
Output
Current
800 mA
800 mA
800 mA
800 mA
600 mA
600 mA
Fixed/
Adj 1
Fixed
Fixed
Adj
Adj
Adj
Adj
Package
8-Lead LFCSP
8-Lead SOIC
8-Lead LFCSP
8-Lead SOIC
8-Lead LFCSP
8-Lead SOIC
Adj means adjustable.
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ADM7154
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 15
Applications ....................................................................................... 1
ADIsimPower Design Tool ....................................................... 15
Typical Application Circuit ............................................................. 1
Capacitor Selection .................................................................... 15
General Description ......................................................................... 1
Undervoltage Lockout (UVLO) ............................................... 16
Revision History ............................................................................... 2
Programmable Precision Enable .............................................. 17
Specifications..................................................................................... 3
Start-Up Time ............................................................................. 17
Absolute Maximum Ratings ............................................................ 5
REF, BYP, and VREG Pins......................................................... 18
Thermal Data ................................................................................ 5
Current-Limit and Thermal Overload Protection ................. 18
Thermal Resistance ...................................................................... 5
Thermal Considerations............................................................ 18
ESD Caution .................................................................................. 5
PCB Layout Considerations .......................................................... 21
Pin Configurations and Function Descriptions ........................... 6
Outline Dimensions ....................................................................... 22
Typical Performance Characteristics ............................................. 7
Ordering Guide .......................................................................... 23
Theory of Operation ...................................................................... 14
REVISION HISTORY
8/2016—Rev. A to Rev. B
Changes to Programmable Precision Enable Section and
Figure 52 .......................................................................................... 17
12/2014—Rev. 0 to Rev. A
Changes to Figure 35 to Figure 40 ................................................ 12
Changes to Figure 44 ...................................................................... 15
10/2014—Revision 0: Initial Version
Rev. B | Page 2 of 23
Data Sheet
ADM7154
SPECIFICATIONS
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater; EN = VIN; ILOAD = 10 mA; CIN = COUT = CREG = 10 µF; CREF = CBYP = 1 µF; TA = 25°C for
typical specifications; TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE RANGE
LOAD CURRENT
OPERATING SUPPLY CURRENT
Symbol
VIN
ILOAD
IGND
SHUTDOWN CURRENT
NOISE
Output Noise
IIN_SD
Noise Spectral Density
POWER SUPPLY REJECTION RATIO
OUTNSD
PSRR
OUTNOISE
OUTPUT VOLTAGE ACCURACY
Initial Accuracy
VOUT
REGULATION
Line
∆VOUT/∆VIN
Load 1
CURRENT-LIMIT THRESHOLD 2
VREF
VOUT
DROPOUT VOLTAGE 3
PULL-DOWN RESISTANCE
VOUT
REG
REF
BYP
START-UP TIME 4
VOUT
VREG
VREF
THERMAL SHUTDOWN
Threshold
Hysteresis
UNDERVOLTAGE THRESHOLDS
Input Voltage
Rising
Falling
Hysteresis
∆VOUT/∆IOUT
ILIMIT
Test Conditions/Comments
Min
2.3
Typ
Max
5.5
600
7.0
10
2
Unit
V
mA
mA
mA
µA
ILOAD = 0 µA
ILOAD = 600 mA
EN = GND
4.0
6.5
0.2
10 Hz to 100 kHz, VOUT = 1.2 V to 3.3 V
100 Hz to 100 kHz, VOUT = 1.2 V to 3.3 V
10 kHz to 1 MHz, VOUT = 1.2 V to 3.3 V
200 Hz to 200 kHz, VIN = 3.8 V, VOUT = 3.3 V,
ILOAD = 400 mA
1 MHz, VIN = 3.8 V, VOUT = 3.3 V, ILOAD = 400 mA
200 Hz to 200 kHz, VIN = 2.3 V, VOUT = 1.8 V,
ILOAD = 400 mA
1 MHz, VIN = 2.3 V, VOUT = 1.8 V, ILOAD = 400 mA
VOUT = VREF
ILOAD = 10 mA, TJ = +25°C
1 mA < ILOAD < 600 mA, TJ = −40°C to +85°C
1 mA < ILOAD < 600 mA
1.6
0.9
1.5
90
µV rms
µV rms
nV/√Hz
dB
58
90
dB
dB
63
dB
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater,
to 5.5 V
IOUT = 1 mA to 600 mA
−0.5
−2.0
−2.0
+0.5
+1.5
+2.0
%
%
%
−0.02
+0.02
%/V
0.3
1.6
%/A
1200
130
210
mA
mA
mV
mV
VDROPOUT
IOUT = 400 mA, VOUT = 3.3 V
IOUT = 600 mA, VOUT = 3.3 V
22
960
80
120
VOUT_PULL
VREG_PULL
VREF_PULL
VBYP_PULL
EN = 0 V, VOUT = 1 V, VIN = 5.5 V
EN = 0 V, VREG = 1 V, VIN = 5.5 V
EN = 0 V, VREF = 1 V, VIN = 5.5 V
EN = 0 V, VBYP = 1 V, VIN = 5.5 V
550
33
620
400
Ω
kΩ
Ω
Ω
tSTARTUP
tREG_STARTUP
tREF_STARTUP
VOUT = 3.3 V
VOUT = 3.3 V
VOUT = 3.3 V
1.2
0.55
0.44
ms
ms
ms
TSSD
TSSD_HYS
TJ rising
150
15
°C
°C
700
UVLORISE
UVLOFALL
UVLOHYS
2.29
1.95
200
Rev. B | Page 3 of 23
V
V
mV
ADM7154
Parameter
VREG THRESHOLDS 5
Rising
Falling
Hysteresis
PRECISION EN INPUT
Logic High
Logic Low
Logic Hysteresis
Leakage Current
Data Sheet
Symbol
Test Conditions/Comments
VREG_UVLORISE
VREG_UVLOFALL
VREG_UVLOHYS
Min
Typ
Max
Unit
1.94
V
V
mV
1.31
1.22
V
V
mV
µA
1.60
185
2.3 V ≤ VIN ≤ 5.5 V
ENHIGH
ENLOW
ENHYS
IEN_LKG
1.13
1.05
EN = VIN or GND
1.22
1.13
90
0.01
1
Based on an endpoint calculation using 1 mA and 600 mA loads.
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
3
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output
voltages above 2.3 V.
4
Start-up time is defined as the time between the rising edge of VEN to VOUT, VREG, or VREF being at 90% of the nominal value.
5
The output voltage is disabled until the VREG UVLO rise threshold is crossed. The VREG output is disabled until the input voltage UVLO rising threshold is crossed.
1
2
Table 3. Input and Output Capacitors, Recommended Specifications
Parameter
MINIMUM CAPACITANCE
Input 1
Regulator1
Output1
Bypass
Reference
CAPACITOR ESR
CREG, COUT, CIN, CREF
CBYP
1
Symbol
Test Conditions/Comments
Min
CIN
CREG
COUT
CBYP
CREF
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
7.0
7.0
7.0
0.1
0.7
RESR
RESR
TA = −40°C to +125°C
TA = −40°C to +125°C
0.001
0.001
Typ
Max
Unit
µF
µF
µF
µF
µF
0.2
2.0
Ω
Ω
The minimum input, regulator, and output capacitances must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions
in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are
recommended; Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. B | Page 4 of 23
Data Sheet
ADM7154
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VIN to GND
VREG to GND
VOUT to GND
BYP to VOUT
EN to GND
BYP to GND
REF to GND
REF_SENSE to GND
Storage Temperature Range
Junction Temperature
Operating Ambient Temperature
Range
Soldering Conditions
Rating
−0.3 V to +7 V
−0.3 V to VIN, or +4 V
(whichever is less)
−0.3 V to VREG, or +4 V
(whichever is less)
±0.3 V
−0.3 V to +7 V
−0.3 V to VREG, or +4 V
(whichever is less)
−0.3 V to VREG, or +4 V
(whichever is less)
−0.3 V to +4 V
−65°C to +150°C
150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer PCB. The
junction-to-ambient thermal resistance is highly dependent on
the application and PCB layout. In applications where high
maximum power dissipation exists, close attention to thermal
PCB design is required. The value of θJA can vary, depending on
PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information on
the board construction.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer PCB. JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than a single
path as in thermal resistance, θJB. Therefore, ΨJB thermal paths
include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Maximum junction temperature (TJ)
is calculated from the PCB temperature (TB) and power
dissipation (PD) using the formula
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL DATA
THERMAL RESISTANCE
Absolute maximum ratings apply individually only, not in
combination. The ADM7154 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature may need to be derated.
θJA, θJC, and ΨJB are specified for the worst case conditions, that
is, a device soldered in a circuit board for surface-mount
packages.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit provided
that the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA).
Table 5. Thermal Resistance
Package Type
8-Lead LFCSP
8-Lead SOIC
ESD CAUTION
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
following formula:
TJ = TA + (PD × θJA)
Rev. B | Page 5 of 23
θJA
36.7
36.9
θJC
23.5
27.1
ΨJB
13.3
18.6
Unit
°C/W
°C/W
ADM7154
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
8 VIN
VOUT 2
ADM7154
7 EN
BYP 3
TOP VIEW
(Not to Scale)
6 REF
VREG
VOUT
BYP
GND
5 REF_SENSE
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES
THERMAL PERFORMANCE, AND IT IS ELECTRICALLY
CONNECTED TO GND INSIDE THE PACKAGE. CONNECT
THE EP TO THE GROUND PLANE ON THE BOARD TO
ENSURE PROPER OPERATION.
8
2
ADM7154
3
TOP VIEW
(Not to Scale) 6
4
5
7
VIN
EN
REF
REF_SENSE
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES
THERMAL PERFORMANCE, AND IT IS ELECTRICALLY
CONNECTED TO GND INSIDE THE PACKAGE. CONNECT
THE EP TO THE GROUND PLANE ON THE BOARD TO
ENSURE PROPER OPERATION.
12324-003
GND 4
1
Figure 3. 8-Lead LFCSP Pin Configuration
12324-004
VREG 1
Figure 4. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
VREG
2
3
VOUT
BYP
4
5
6
GND
REF_SENSE
REF
7
EN
8
VIN
EP
Description
Regulated Input Supply Voltage to LDO Amplifier. Bypass VREG to GND with a 10 µF or greater
capacitor.
Regulated Output Voltage. Bypass VOUT to GND with a 10 µF or greater capacitor.
Low Noise Bypass Capacitor. Connect a 1 µF capacitor from the BYP pin to GND to reduce noise. Do not
connect a load to ground.
Ground Connection.
Reference Sense. Connect Pin 5 to the REF pin. Do not connect Pin 5 to VOUT or GND.
Low Noise Reference Voltage Output. Bypass REF to GND with a 1 µF capacitor. Short REF_SENSE to REF
for fixed output voltages. Do not connect a load to ground.
Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
Regulator Input Supply Voltage. Bypass VIN to GND with a 10 µF or greater capacitor.
Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances
thermal performance, and it is electrically connected to GND inside the package. Connect the EP to the
ground plane on the board to ensure proper operation.
Rev. B | Page 6 of 23
Data Sheet
ADM7154
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VOUT + 0.5 V, or VIN = 2.3 V, whichever is greater; VEN = VIN; IOUT = 10 mA; CIN = COUT = CREG = 10 µF; CREF = CBYP = 1 µF; TA = 25°C,
unless otherwise noted.
1.0
0.9
0.7
3.32
3.31
0.6
VOUT (V)
0.5
0.4
3.30
3.29
0.3
0.2
3.28
0.1
–25
0
25
50
75
100
125
TEMPERATURE (°C)
3.27
3.5
12324-005
0
–50
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
= 1mA
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
4.0
4.5
5.0
5.5
VIN (V)
12324-008
SHUTDOWN CURRENT (µA)
0.8
3.33
VIN = 2.3V
VIN = 2.4V
VIN = 2.6V
VIN = 3.0V
VIN = 4.0V
VIN = 5.5V
Figure 8. Output Voltage (VOUT) vs. Input Voltage (VIN) at Various Loads,
VOUT = 3.3 V
Figure 5. Shutdown Current vs. Temperature at
Various Input Voltages, VOUT = 1.8 V
10
3.33
9
3.32
GROUND CURRENT (mA)
8
3.30
3.29
3.27
–40
= 1mA
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
–5
6
5
4
3
2
1
25
85
0
12324-006
3.28
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
7
125
JUNCTION TEMPERATURE (°C)
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
–40
= 1mA
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
–5
25
85
12324-009
VOUT (V)
3.31
125
JUNCTION TEMPERATURE (°C)
Figure 6. Output Voltage (VOUT) vs. Junction Temperature at Various Loads,
VOUT = 3.3 V
Figure 9. Ground Current vs. Junction Temperature (TJ) at Various Loads,
VOUT = 3.3 V
3.33
10
9
3.32
GROUND CURRENT (mA)
8
VOUT (V)
3.31
3.30
3.29
7
6
5
4
3
2
3.28
10
100
1000
ILOAD (mA)
Figure 7. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
0
1
10
100
1000
ILOAD (mA)
Figure 10. Ground Current vs. Load Current (ILOAD), VOUT = 3.3 V
Rev. B | Page 7 of 23
12324-010
1
12324-007
1
3.27
Data Sheet
10
10
9
9
8
8
7
6
5
4
0
3.5
= 1mA
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
3
4.0
4.5
5.0
5.5
0
3.1
1.815
120
1.810
100
1.805
VOUT (V)
140
80
1.795
40
1.790
20
1.785
1000
ILOAD (mA)
Figure 12. Dropout Voltage vs. Load Current (ILOAD), VOUT = 3.3 V
–40
3.5
3.6
3.7
3.8
= 1mA
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
–5
25
85
125
JUNCTION TEMPERATURE (°C)
Figure 15. Output Voltage (VOUT) vs. Junction Temperature (TJ) at Various
Loads, VOUT = 1.8 V
1.820
3.35
1.815
3.30
1.810
3.25
1.805
VOUT (V)
3.40
3.20
1.800
1.795
3.15
3.05
3.2
3.3
3.4
3.5
3.6
= 5mA
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
3.7
1.790
1.785
3.8
VIN (V)
12324-013
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
3.10
3.00
3.1
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
1.780
12324-012
100
3.4
1.800
60
10
3.3
Figure 14. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 3.3 V
1.820
0
3.2
= 5mA
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
VIN (V)
160
1
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
1
Figure 11. Ground Current vs. Input Voltage (VIN) at Various Loads,
VOUT = 3.3 V
DROPOUT (mV)
4
2
VIN (V)
VOUT (V)
5
12324-015
1
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
6
Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,
VOUT = 3.3 V
1.780
1
10
100
1000
ILOAD (mA)
Figure 16. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 1.8 V
Rev. B | Page 8 of 23
12324-016
2
12324-011
3
7
12324-014
GROUND CURRENT (µA)
GROUND CURRENT (mA)
ADM7154
Data Sheet
ADM7154
1.820
8
1.810
7
1.800
1.795
1.790
1.785
4
3
2
1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
0
2.0
12324-017
3.5
4.0
4.5
5.0
5.5
0
ILOAD
ILOAD
ILOAD
ILOAD
9
–20
8
GROUND CURRENT (mA)
3.0
2.5
Figure 20. Ground Current vs. Input Voltage (VIN) at Different Loads,
VOUT = 1.8 V
10
= 100mA
= 200mA
= 400mA
= 600mA
–40
7
PSRR (dB)
6
5
4
3
1
0
–40
–5
25
85
125
JUNCTION TEMPERATURE (°C)
–60
–80
–100
= 1mA
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
–120
–140
12324-018
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
2
1
6
–20
5
–40
PSRR (dB)
0
4
3
1
–120
ILOAD (mA)
Figure 19. Ground Current vs. Load Current (ILOAD), VOUT = 1.8 V
100k
1M
10M
800mV
600mV
500mV
400mV
300mV
250mV
200mV
150mV
–140
12324-019
1000
10k
–80
–100
100
1k
–60
2
10
100
Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various
Loads, VOUT = 3.3 V, VIN = 4.1 V
7
0
10
FREQUENCY (Hz)
Figure 18. Ground Current vs. Junction Temperature (TJ) at Various Loads,
VOUT = 1.8 V
GROUND CURRENT (mA)
= 1mA
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
VIN (V)
Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN) at Various Loads,
VOUT = 1.8 V
1
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
12324-021
1.780
2.0
5
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
12324-022
VOUT (V)
1.805
6
12324-020
1.815
= 1mA
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
GROUND CURRENT (mA)
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various
Headroom Voltages, VOUT = 3.3 V, 400 mA Load
Rev. B | Page 9 of 23
Data Sheet
0
–20
–20
–40
–40
PSRR (dB)
0
–60
–80
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
–120
–140
0
0.1
100kHz
1MHz
10MHz
0.65
0.75
–60
–80
–100
–120
0.2
0.4
0.3
0.5
0.6
0.7
0.8
HEADROOM (V)
Figure 23. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage at
Different Frequencies, VOUT = 3.3 V, 400 mA Load
–140
0.25
0.35
0.45
0.55
HEADROOM (V)
Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
Different Frequencies, VOUT = 1.8 V, 400 mA Load
0
0
ILOAD
ILOAD
ILOAD
ILOAD
–20
= 100mA
= 200mA
= 400mA
= 600mA
1µF
10µF
100µF
1000µF
–20
–40
–60
–80
–60
–80
–100
–100
–120
–120
–140
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–140
Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various
Loads, VOUT = 1.8 V, VIN = 2.6 V
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
12324-027
PSRR (dB)
–40
12324-024
PSRR (dB)
10Hz
100Hz
1kHz
10kHz
12324-026
–100
12324-023
PSRR (dB)
ADM7154
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency, Different CBYP,
VOUT = 3.3 V, 400 mA Load, 500 mV Headroom
2.0
0
10Hz TO 100kHz
100Hz TO 100kHz
1.8
–20
OUTPUT NOISE (µV rms)
1.6
–60
–80
800mV
600mV
500mV
400mV
300mV
250mV
–120
–140
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Figure 25. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various
Headroom Voltages, VOUT = 1.8 V, 400 mA Load
Rev. B | Page 10 of 23
0
10
100
LOAD CURRENT (mA)
Figure 28. RMS Output Noise vs. Load Current
1000
12324-028
–100
12324-025
PSRR (dB)
–40
Data Sheet
ADM7154
10k
1.8
OUTPUT NOISE SPECTRAL DENSITY (nV/√Hz)
10Hz TO 100kHz
100Hz TO 100kHz
1.4
1.2
1.0
0.8
0.6
0.4
0
1.0
1.5
2.5
2.0
3.0
3.5
OUTPUT VOLTAGE (V)
Figure 29. RMS Output Noise vs. Output Voltage
10
100
1k
10k
100k
1M
10M
1
100
1k
10k
100k
1M
10M
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
1k
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
100
10
1
0.1
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 30. Output Noise Spectral Density,
10 Hz to 10 MHz, ILOAD = 100 mA
12324-070
OUTPUT NOISE SPECTRAL DENSITY (nV/√Hz)
10
12324-029
OUTPUT NOISE SPECTRAL DENSITY (nV/√Hz)
1
10k
FREQUENCY (Hz)
Figure 33. Output Noise Spectral Density at Various Loads,
0.1 Hz to 1 MHz
10k
OUTPUT NOISE SPECTRAL DENSITY (nV/√Hz)
1k
1k
100
10
1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
12324-030
OUTPUT NOISE SPECTRAL DENSITY (nV/√Hz)
1
Figure 32. Output Noise Spectral Density, 0.1 Hz to 10 MHz, ILOAD = 100 mA
100
0.1
0.1
10
FREQUENCY (Hz)
1k
0.1
10
100
0.1
0.1
12324-034
0.2
1k
Figure 31. Output Noise Spectral Density,
0.1 Hz to 1 MHz, ILOAD = 10 mA
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
100
= 10mA
= 100mA
= 200mA
= 400mA
= 600mA
10
1
0.1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 34. Output Noise Spectral Density at Various Loads,
10 Hz to 10 MHz
Rev. B | Page 11 of 23
12324-031
OUTPUT NOISE (µV rms)
1.6
12324-002
2.0
ADM7154
Data Sheet
T
T
1
1
2
B
W
M4.0µs
A CH1
T 10.2%
212mA
CH1 200mA Ω BW CH2 5mV
Figure 35. Load Transient Response, ILOAD = 10 mA to 510 mA,
VOUT = 3.3 V, VIN = 3.8 V, CH1 = IOUT, CH2 = VOUT
B
W
M4µs A CH1
T 10.6%
532mA
12324-138
CH1 200mA Ω BW CH2 5mV
12324-135
2
Figure 38. Load Transient Response, ILOAD = 100 mA to 600 mA,
VOUT = 1.8 V, VIN = 2.3 V, CH1 = IOUT, CH2 = VOUT
T
T
1
2
2
B
W M4.0µs
A CH1
212mA
T 10.2%
CH1 1V BW
Figure 36. Load Transient Response, ILOAD = 100 mA to 600 mA,
VOUT = 3.3 V, VIN = 3.8 V, CH1 = IOUT, CH2 = VOUT
CH2 1mV
B
W
M400ns
T 10.4%
A CH1
4.38V
12324-139
CH1 200mA Ω BW CH2 5mV
12324-136
1
Figure 39. Line Transient Response, 1 V Input Step, ILOAD = 600 mA,
VOUT = 3.3 V, VIN = 3.9 V, CH1 = VIN, CH2 = VOUT
T
T
1
2
B
W
M4.0µs
A CH1
T 10.4%
204mA
CH1 1V BW
CH2 1mV
B
W
M400ns
T 11.4%
A CH1
3.5V
12324-140
CH1 200mA Ω BW CH2 5mV
12324-137
1
2
Figure 40. Line Transient Response, 1 V Input Step, ILOAD = 600 mA,
VOUT = 1.8 V, VIN = 2.4 V, CH1 = VIN, CH2 = VOUT
Figure 37. Load Transient Response, ILOAD = 10 mA to 510 mA,
VOUT = 1.8 V, VIN = 2.3 V, CH1 = IOUT, CH2 = VOUT
Rev. B | Page 12 of 23
Data Sheet
ADM7154
3.5
ENABLE (VEN)
1.2V
1.8V
3.3V
3.0
VOUT (V)
2.5
2.0
1.5
1.0
0
0
1
2
3
4
5
TIME (ms)
6
7
8
9
10
12324-141
0.5
Figure 41. VOUT Start-Up Time After VEN Rising, Different Output Voltages,
VIN = 5 V
Rev. B | Page 13 of 23
ADM7154
Data Sheet
THEORY OF OPERATION
The ADM7154 is an ultralow noise, high power supply rejection
ratio (PSRR) linear regulator targeting radio frequency (RF)
applications. The input voltage range is 2.3 V to 5.5 V, and it can
deliver up to 600 mA of load current. Typical shutdown current
consumption is 0.2 µA at room temperature.
Optimized for use with 10 µF ceramic capacitors, the ADM7154
provides excellent transient performance.
VIN
ACTIVE
RIPPLE
FILTER
VREG
VOUT
CURRENT-LIMIT,
THERMAL
PROTECT
To maintain very high PSRR over a wide frequency range, the
ADM7154 architecture uses an internal active ripple filter. This
stage isolates the low output noise LDO from noise on the VIN
pin. The result is that the PSRR of the ADM7154 is significantly
higher over a wider frequency range than any single stage LDO.
The ADM7154 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. When EN is high,
VOUT turns on, and when EN is low, VOUT turns off. For
automatic startup, tie EN to VIN.
GND
BYP
REFERENCE
By heavily filtering the reference voltage, the ADM7154 is able
to achieve 1.5 nV/√Hz output typical from 10 kHz to 1 MHz.
Because the error amplifier is always in unity gain, the output
noise is independent of the output voltage.
OTA
VIN
7V
REF
EN
VREG
4V
REF
Figure 42. Simplified Internal Block Diagram
REF_SENSE
Internally, the ADM7154 consists of a reference, an error
amplifier, and a P-channel MOSFET pass transistor. Output
current is delivered via the PMOS pass device, which is
controlled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower
than the reference voltage, the gate of the PMOS device is
pulled lower, allowing more current to pass and increasing the
output voltage. If the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
allowing less current to pass and decreasing the output voltage.
4V
BYP
4V
VOUT
EN
7V
4V
4V
4V
4V
4V
GND
7V
12324-043
SHUTDOWN
12324-042
REF_SENSE
Figure 43. Simplified ESD Protection Block Diagram
The ESD protection devices are shown in the block diagram as
Zener diodes (see Figure 43).
Rev. B | Page 14 of 23
Data Sheet
ADM7154
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
Input and VREG Capacitor
The ADM7154 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic, bill of materials,
and calculate performance within minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and device count,
taking into consideration the operating conditions and
limitations of the IC and all real external components. For more
information about, and to obtain ADIsimPower design tools,
visit www.analog.com/ADIsimPower.
Connecting a 10 µF capacitor from VIN to GND reduces the
circuit sensitivity to PCB layout, especially when long input
traces or high source impedance are encountered.
Multilayer ceramic capacitors (MLCCs) combine small size, low
ESR, low ESL, and wide operating temperature range, making
them an ideal choice for bypass capacitors. They are not without
faults, however. Depending on the dielectric material, the
capacitance can vary dramatically with temperature, dc bias,
and ac signal level. Therefore, selecting the proper capacitor
results in the best circuit performance.
Output Capacitor
The ADM7154 is designed for operation with ceramic
capacitors but functions with most commonly used capacitors
when care is taken with regard to the effective series resistance
(ESR) value. The ESR of the output capacitor affects the stability
of the LDO control loop. A minimum of 10 µF capacitance with
an ESR of 0.2 Ω or less is recommended to ensure the stability
of the ADM7154. Output capacitance also affects transient
response to changes in load current. Using a larger value of
output capacitance improves the transient response of the
ADM7154 to large changes in load current. Figure 44 shows the
transient responses for an output capacitance value of 10 µF.
T
REF Capacitor
The REF capacitor, CREF, is necessary to stabilize the reference
amplifier. Connect at least a 1 µF capacitor between REF and GND.
BYP Capacitor
The BYP capacitor, CBYP, is necessary to filter the reference
buffer. A 1 µF capacitor is typically connected between BYP and
GND. Capacitors as small as 0.1 µF can be used; however, the
output noise voltage of the LDO increases as a result.
In addition, the BYP capacitor value can be increased to reduce
the noise below 1 kHz at the expense of increasing the start-up
time of the LDO. Very large values of CBYP significantly reduce
the noise below 10 Hz. Tantalum capacitors are recommended
for capacitors larger than approximately 33 µF because solid
tantalum capacitors are less prone to microphonic noise issues.
A 1 μF ceramic capacitor in parallel with the larger tantalum
capacitor is recommended to ensure good noise performance at
higher frequencies.
2.0
10Hz TO 100kHz
100Hz TO 100kHz
1.8
1.6
OUTPUT NOISE (µV rms)
CAPACITOR SELECTION
To maintain the best possible stability and PSRR performance,
connect a 10 µF capacitor from VREG to GND. When more
than 10 µF of output capacitance is required, increase the input
and the VREG capacitors, CREG, to match it.
1.4
1.2
1.0
0.8
0.6
0.4
1
0
1
2
10
100
CBYP (µF)
CH1 200mA Ω BW CH2 5mV
B
W
M4µs A CH1
T 10.2%
212mA
12324-144
Figure 45. RMS Noise vs. CBYP
Figure 44. Output Transient Response, VOUT = 3.3 V, COUT = 10 µF,
CH1 = Load Current, CH2 = VOUT
Rev. B | Page 15 of 23
1000
12324-045
0.2
ADM7154
Data Sheet
Use Equation 1 to determine the worst case capacitance
accounting for capacitor variation over temperature,
component tolerance, and voltage.
NOISE FLOOR
1.0µF
3.3µF
10µF
33µF
100µF
330µF
1000µF
100
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
10
1
0.1
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
(1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
Figure 46. Noise Spectral Density vs. Frequency at
Different Capacitances (CBYP)
In this example, the worst case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and CBIAS is 9.72 µF at 5 V, as shown in Figure 47.
Substituting these values in Equation 1 yields
CEFF = 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF
Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADM7154 if they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured
with a variety of dielectrics, each with different behavior over
temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over
the necessary temperature range and dc bias conditions. X5R
or X7R dielectrics with a voltage rating of 6.3 V to 50 V
are recommended. However, Y5V and Z5U dielectrics are
not recommended because of their poor temperature and dc
bias characteristics.
Figure 47 depicts the capacitance vs. dc bias voltage of a 1206,
10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is
strongly influenced by the capacitor size and voltage rating. In
general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is ~±15% over the −40°C to +85°C temperature range
and is not a function of package or voltage rating.
12
10
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADM7154, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT (UVLO)
The ADM7154 also incorporates an internal UVLO circuit to
disable the output voltage when the input voltage is less than the
minimum input voltage rating of the regulator. The upper and
lower thresholds are internally fixed with about 200 mV of
hysteresis.
2.5
+125°C
+25°C
–40°C
2.0
OUTPUT VOLTAGE (V)
1k
12324-046
NOISE SPECTRAL DENSITY (nV/√Hz)
10k
1.5
1.0
0
1.90
6
1.95
2.00
2.05
2.10
2.15
INPUT VOLTAGE (V)
2.20
2.25
2.30
12324-048
8
Figure 48. Typical UVLO Behavior at Different Temperatures, VOUT = 3.3 V
4
2
0
0
2
4
6
8
DC BIAS VOLTAGE (V)
10
12324-047
CAPACITANCE (µF)
0.5
Figure 48 shows the typical hysteresis of the UVLO function.
This hysteresis prevents on/off oscillations that can occur when
caused by noise on the input voltage as it passes through the
threshold points.
Figure 47. Capacitance vs. DC Bias Voltage
Rev. B | Page 16 of 23
Data Sheet
ADM7154
PROGRAMMABLE PRECISION ENABLE
The ADM7154 uses the EN pin to enable and disable the
VOUT pin under normal operating conditions. As shown in
Figure 49, when a rising voltage on EN crosses the upper threshold,
nominally 1.22 V, VOUT turns on. When a falling voltage on EN
crosses the lower threshold, nominally 1.13 V, VOUT turns off.
The hysteresis of the EN threshold is approximately 90 mV.
3.5
+125°C
+85°C
+25°C
–5°C
–40°C
3.0
The upper and lower thresholds are user programmable and can
be set higher than the nominal 1.22 V threshold by using two
resistors. The resistance values, REN1 and REN2, can be
determined from
REN1 = REN2 × (VIN − 1.22 V)/1.22 V
where:
REN2 typically ranges from 10 kΩ to 100 kΩ.
VIN is the desired turn-on voltage.
The hysteresis voltage increases by the factor
(REN1 + REN2)/REN2
For the example shown in Figure 52, the EN threshold is 2.44 V
with a hysteresis of 200 mV.
2.0
1.5
REN1
100kΩ
ON
0.5
OFF
1.1
1.2
1.3
EN PIN VOLTAGE (V)
3.5
ENABLE (VEN)
VOUT
REF
CREF
1µF
VREG
CREG
10µF
Figure 49. Typical VOUT Response to EN Pin Operation
COUT
10µF
REF_SENSE
BYP
CBYP
1µF
VOUT = 1.8V
VOUT
EN
REN2
100kΩ
12324-049
0
1.0
VIN
CIN
10µF
1.0
GND
Figure 52. Typical EN Pin Voltage Divider
3.0
Figure 52 shows the typical hysteresis of the EN pin. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
2.5
VOUT (V)
ADM7154
VIN = 2.3V
12324-052
VOUT (V)
2.5
START-UP TIME
2.0
The ADM7154 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for a 3.3 V output is
approximately 1.2 ms from the time the EN active threshold is
crossed to when the output reaches 90% of the final value.
1.5
1.0
0
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
TIME (ms)
12324-050
0.5
Figure 50. Typical VOUT Response to EN Pin Operation (VEN),
VOUT = 3.3 V, VIN = 5 V, CBYP = 1 µF
The rise time in seconds of the output voltage (10% to 90%) is
approximately
0.0012 × CBYP
where CBYP is in microfarads.
3.5
1.250
3.0
2.5
1.200
2.0
1.5
1.150
1.0
1.125
0.5
1.100
2.5
ENABLE (VEN)
CBYP = 1µF
CBYP = 3.3µF
CBYP = 10µF
0
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
0
5
10
15
20
25
30
35
40
TIME (ms)
Figure 53. Typical Start-Up Behavior with CBYP = 1 µF to 10 µF
Figure 51. Typical EN Threshold vs. Input Voltages (VIN) for Different
Temperatures
Rev. B | Page 17 of 23
12324-053
1.175
VOUT (V)
–40°C RISING
+25°C RISING
+125°C RISING
–40°C FALLING
+25°C FALLING
+125°C FALLING
12324-051
EN RISE THRESHOLD (V)
1.225
ADM7154
Data Sheet
2.5
Current-limit and thermal limit protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation must be externally
limited so that the junction temperature does not exceed 150°C.
2.0
THERMAL CONSIDERATIONS
3.5
In applications with a low input to output voltage differential,
the ADM7154 does not dissipate much heat. However, in
applications with high ambient temperature and/or high input
voltage, the heat dissipated in the package can become large
enough that it causes the junction temperature of the die to
exceed the maximum junction temperature of 150°C.
1.5
1.0
ENABLE (VEN)
CBYP = 10µF
CBYP = 33µF
CBYP = 100µF
CBYP = 330µF
0.5
0
0
20
40
60
80
100
120
140
160
180
200
TIME (ms)
12324-054
VOUT (V)
3.0
Figure 54. Typical Start-Up Behavior with CBYP = 10 µF to 330 µF
REF, BYP, AND VREG PINS
REF, BYP, and VREG generate voltages internally (VREF, VBYP,
and VREG) that require external bypass capacitors for proper
operation. Do not, under any circumstances, connect any loads
to these pins, because doing so compromises the noise and
PSRR performance of the ADM7154. Using larger values of
CBYP, CREF, and CREG is acceptable but can increase the start-up
time, as described in the Start-Up Time section.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADM7154 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADM7154 is designed to current limit when the
output load reaches 960 mA (typical). When the output load
exceeds 960 mA, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C. Under extreme
conditions (that is, high ambient temperature and/or high
power dissipation), when the junction temperature starts to rise
above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C, the output is turned on again, and the output current is
restored to the operating value.
Consider the case where a hard short from VOUT to GND
occurs. At first, the ADM7154 current limits, so that only
960 mA is conducted into the short. If self heating of the
junction is great enough to cause the temperature to rise above
150°C, thermal shutdown activates, turning off the output and
reducing the output current to zero. As the junction temperature cools and drops below 135°C, the output turns on and
conducts 900 mA into the short, again causing the junction
temperature to rise above 150°C. This thermal oscillation
between 135°C and 150°C causes a current oscillation between
900 mA and 0 mA that continues for as long as the short
remains at the output.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature decreases below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the
ambient temperature of the environment and the temperature
rise of the package due to the power dissipation, as shown in
Equation 2.
To guarantee reliable operation, the junction temperature of the
ADM7154 must not exceed 150°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The θJA number is dependent
on the package assembly compounds that are used and the
amount of copper used to solder the package GND pin and
exposed pad to the PCB.
Table 7 shows typical θJA values of the 8-lead SOIC and 8-lead
LFCSP packages for various PCB copper sizes.
Table 8 shows the typical ΨJB values of the 8-lead SOIC and
8-lead LFCSP.
Table 7. Typical θJA Values
Copper Size (mm2)
251
100
500
1000
6400
1
θJA (°C/W)
8-Lead LFCSP
8-Lead SOIC
165.1
165
125.8
126.4
68.1
69.8
56.4
57.8
42.1
43.6
Device soldered to minimum size pin traces.
Table 8. Typical ΨJB Values
Package
8-Lead LFCSP
8-Lead SOIC
Rev. B | Page 18 of 23
ΨJB (°C/W)
15.1
17.9
Data Sheet
ADM7154
The junction temperature of the ADM7154 is calculated from
the following equation:
PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND)
(3)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
130
120
110
100
90
80
6400mm 2
500mm 2
25mm 2
TJ MAX
70
60
50
0
Power dissipation caused by ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to the following:
TJ = TA + (((VIN − VOUT) × ILOAD) × θJA)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Figure 56. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 50°C
155
145
JUNCTION TEMPERATURE (°C)
The heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins and
exposed pad of the ADM7154. Adding thermal planes
underneath the package also improves thermal performance.
However, as shown in Table 7, a point of diminishing returns is
eventually reached, beyond which an increase in the copper
area does not yield significant reduction in the junction to
ambient thermal resistance.
0.4
TOTAL POWER DISSIPATION (W)
(4)
As shown in Equation 4, for a given ambient temperature, input
to output voltage differential, and continuous load current,
there exists a minimum copper size requirement for the PCB to
ensure that the junction temperature does not rise above 150°C.
0.2
12324-056
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
140
135
125
115
105
95
85
6400mm 2
500mm 2
25mm 2
TJ MAX
75
65
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
TOTAL POWER DISSIPATION (W)
Figure 55 to Figure 60 show junction temperature calculations
for different ambient temperatures, power dissipation, and areas
of PCB copper.
12324-057
(2)
150
JUNCTION TEMPERATURE (°C)
TJ = TA + (PD × θJA)
160
Figure 57. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 85°C
155
155
145
125
115
105
95
85
75
65
55
6400mm 2
45
500mm 2
25mm 2
TJ MAX
35
25
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
TOTAL POWER DISSIPATION (W)
135
125
115
105
95
85
6400mm 2
500mm 2
25mm 2
TJ MAX
75
65
0
12324-055
JUNCTION TEMPERATURE (°C)
135
Figure 55. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 25°C
Rev. B | Page 19 of 23
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
TOTAL POWER DISSIPATION (W)
Figure 58. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 25°C
12324-057
JUNCTION TEMPERATURE (°C)
145
Data Sheet
160
Thermal Characterization Parameter (ΨJB)
150
When board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction
temperature rise (see Figure 61 and Figure 62). Maximum
junction temperature (TJ) is calculated from the board
temperature (TB) and power dissipation (PD) using the following
formula:
140
130
120
110
100
90
TJ = TB + (PD × ΨJB)
80
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
TOTAL POWER DISSIPATION (W)
160
Figure 59. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 50°C
155
145
135
125
115
120
100
80
60
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
40
20
105
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0
95
TOTAL POWER DISSIPATION (W)
85
Figure 61. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP
6400mm 2
500mm 2
25mm 2
TJ MAX
65
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TOTAL POWER DISSIPATION (W)
Figure 60. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 85°C
160
140
JUNCTION TEMPERATURE (°C)
75
12324-060
JUNCTION TEMPERATURE (°C)
140
12324-061
0
120
100
80
60
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
40
20
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
TOTAL POWER DISSIPATION (W)
Figure 62. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC
Rev. B | Page 20 of 23
12324-062
50
JUNCTION TEMPERATURE (°C)
60
(5)
The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP
package and 17.9°C/W for the 8-lead SOIC package.
6400mm 2
500mm 2
25mm 2
TJ MAX
70
12324-059
JUNCTION TEMPERATURE (°C)
ADM7154
Data Sheet
ADM7154
PCB LAYOUT CONSIDERATIONS
12324-064
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Place the bypass capacitors (CREG, CREF,
and CBYP) for VREG, VREF, and VBYP close to the respective pins
(VREG, REF, and BYP) and GND. Use of an 0805, 0603, or
0402 size capacitor achieves the smallest possible footprint
solution on boards where area is limited.
12324-063
Figure 64. Example 8-Lead SOIC PCB Layout
Figure 63. Example 8-Lead LFCSP PCB Layout
Rev. B | Page 21 of 23
ADM7154
Data Sheet
OUTLINE DIMENSIONS
2.54
2.44
2.34
3.10
3.00 SQ
2.90
0.50 BSC
8
5
1.70
1.60
1.50
EXPOSED
PAD
0.50
0.40
0.30
4
TOP VIEW
0.80
0.75
0.70
PKG-004371
1
0.05 MAX
0.02 NOM
0.30
0.25
0.20
SEATING
PLANE
0.20 MIN
PIN 1
INDICATOR
(R 0.20)
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.203 REF
12-03-2013-A
PIN 1 INDEX
AREA
Figure 65. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-21)
Dimensions shown in millimeters
5.00
4.90
4.80
2.29
0.356
5
1
4
6.20
6.00
5.80
4.00
3.90
3.80
2.29
0.457
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
1.27 BSC
3.81 REF
TOP VIEW
1.65
1.25
1.75
1.35
SEATING
PLANE
0.51
0.31
0.50
0.25
0.10 MAX
0.05 NOM
COPLANARITY
0.10
8°
0°
45°
0.25
0.17
1.04 REF
1.27
0.40
COMPLIANT TO JEDEC STANDARDS MS-012-A A
Figure 66. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
Rev. B | Page 22 of 23
06-02-2011-B
8
Data Sheet
ADM7154
ORDERING GUIDE
Model 1
ADM7154ACPZ-1.2-R7
ADM7154ACPZ-1.8-R7
ADM7154ACPZ-2.5-R7
ADM7154ACPZ-2.8-R7
ADM7154ACPZ-3.0-R7
ADM7154ACPZ-3.3-R7
ADM7154ARDZ-1.2-R7
ADM7154ARDZ-1.8-R7
ADM7154ARDZ-2.5-R7
ADM7154ARDZ-2.8-R7
ADM7154ARDZ-3.0-R7
ADM7154ARDZ-3.3-R7
ADM7154CP-3.3EVALZ
ADM7154RD-1.8EVALZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage (V)
1.2
1.8
2.5
2.8
3.0
3.3
1.2
1.8
2.5
2.8
3.0
3.3
Z = RoHS Compliant Part.
©2014–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12324-0-8/16(B)
Rev. B | Page 23 of 23
Package Description
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
Evaluation Board
Evaluation Board
Package Option
CP-8-21
CP-8-21
CP-8-21
CP-8-21
CP-8-21
CP-8-21
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
Branding
LQS
LQT
LQU
LQ6
LRF
LQ7
工商网监
湘ICP备2023018690号
