FEATURES
TYPICAL APPLICATION CIRCUIT
APPLICATIONS
Regulation to noise sensitive applications: ADC and DAC
circuits, precision amplifiers, PLLs/VCOs, and clocking ICs
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
CIN
4.7µF
VIN
VIN
VOUT
VOUT
SENSE
EN
SS
VOUT = 3.3V
COUT
4.7µF
ON
OFF
GND
CSS
1nF
Figure 1. ADM7170 with Fixed Output Voltage, 3.3 V
Inrush current can be controlled by adjusting the start-up time
via the soft start pin. The typical start-up time with a 1 nF soft
start capacitor is about 1.0 ms.
The ADM7170 regulator output noise is 5 μV rms independent
of the output voltage. The ADM7170 is available in an 8-lead,
3 mm × 3 mm LFCSP, making it not only a very compact
solution, but also providing excellent thermal performance for
applications requiring up to 500 mA of output current in a
small, low profile footprint.
T
1
The ADM7170 is a CMOS, low dropout linear regulator (LDO)
that operates from 2.3 V to 6.5 V and provides up to 500 mA of
output current. This high output current LDO is ideal for
regulation of high performance analog and mixed signal circuits
operating from 6 V down to 1.2 V rails. Using an advanced
proprietary architecture, the device provides high power supply
rejection and low noise, and achieves excellent line and load
transient response with just a small 4.7 µF ceramic output
capacitor. Load transient response is typically 1.5 μs for a 1 mA
to 500 mA load step.
The ADM7170 is available in 17 fixed output voltage options.
The following voltages are available from stock: 1.3 V, 1.8 V,
2.5 V, 3.0 V, 3.3 V, 4.2 V, and 5.0 V. Additional voltages that are
available by special order are: 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.7 V,
2.75 V, 2.8 V, 2.85 V, 3.8 V, and 4.6 V. An adjustable version is
also available that allows output voltages that range from 1.2 V
to VIN − VDO with an external feedback divider.
Rev. D
ADM7170
VIN = 5V
12297-001
Input voltage range: 2.3 V to 6.5 V
Maximum load current: 500 mA
Low noise: 5 µV rms independent of output voltage at
100 Hz to 100 kHz
Fast transient response: 1.5 μs for 1 mA to 500 mA load step
60 dB PSRR at 100 kHz
Low dropout voltage: 42 mV at 500 mA load, VOUT = 3 V
Initial accuracy: ±0.75%
Accuracy over line, load, and temperature: ±1.25%
Quiescent current, IGND = 0.7 mA at no load
Low shutdown current: 0.25 μA at VIN = 5 V
Stable with small 4.7 µF ceramic output capacitor
Adjustable and fixed output voltage options: 1.2 V to 5.0 V
Adjustable output from 1.2 V to VIN − VDO
Precision enable
Adjustable soft start
8-lead, 3 mm × 3 mm LFCSP package
Supported by ADIsimPower tool
2
CH1 200mA Ω BW CH2 10mV
B
W
M400ns
T 0.4%
A CH3
100mV
12297-002
Data Sheet
6.5 V, 500 mA, Ultralow Noise, High PSRR,
Fast Transient Response CMOS LDO
ADM7170
Figure 2. Transient Response (Trace 2), 1 mA to 500 mA Load Step in 400 ns
(Trace 1)
Table 1. Related Devices
Device
ADM7171
ADM7172
Input Voltage
2.3 V to 6.5 V
2.3 V to 6.5 V
Output Current
1A
2A
Package
8-lead LFCSP
8-lead LFCSP
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ADM7170
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 17
Applications ....................................................................................... 1
ADIsimPower Design Tool ....................................................... 17
General Description ......................................................................... 1
Capacitor Selection .................................................................... 17
Typical Application Circuit ............................................................. 1
Programmable Precision Enable .............................................. 18
Revision History ............................................................................... 2
Undervoltage Lockout ............................................................... 18
Specifications..................................................................................... 3
Soft Start ...................................................................................... 18
Input and Output Capacitor, Recommended Specifications .. 4
Noise Reduction of the ADM7170 in Adjustable Mode ....... 19
Absolute Maximum Ratings ............................................................ 5
Effect of Noise Reduction on Start-Up Time ......................... 19
Thermal Data ................................................................................ 5
Current-Limit and Thermal Overload Protection ................. 19
Thermal Resistance ...................................................................... 5
Thermal Considerations............................................................ 20
ESD Caution .................................................................................. 5
Typical Applications Circuits .................................................... 21
Pin Configuration and Function Descriptions ............................. 6
Printed Circuit Board Layout Considerations ............................ 22
Typical Performance Characteristics ............................................. 7
Outline Dimensions ....................................................................... 23
Theory of Operation ...................................................................... 16
Ordering Guide .......................................................................... 23
REVISION HISTORY
9/2019—Rev. C to Rev. D
Change to Figure 33 Caption ........................................................ 11
Change to Figure 34 Caption, Figure 38 Caption, and Figure 39
Caption ............................................................................................. 12
Changes to Figure 49 and Figure 51............................................. 14
Changes to Figure 54 ...................................................................... 16
Changes to Figure 56 ...................................................................... 17
Updated Outline Dimensions ....................................................... 23
8/2015—Rev. B to Rev. C
Changes to Soft Start Section ........................................................ 19
Added Effect of Noise Reduction on Start-Up Time Section ... 19
12/2014—Rev. A to Rev. B
Changes to Figure 2 ...........................................................................1
Changes to Figure 48 to Figure 51................................................ 14
Changes to Figure 52 to Figure 53................................................ 15
Changes to Figure 56...................................................................... 17
Changes to Ordering Guide .......................................................... 23
8/2014—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 23
7/2014—Revision 0: Initial Version
Rev. D | Page 2 of 23
Data Sheet
ADM7170
SPECIFICATIONS
VIN = (VOUT + 0.5 V) or 2.3 V (whichever is greater), EN = VIN, ILOAD = 10 mA, CIN = COUT = 4.7 µF, TA = 25°C for typical specifications,
TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE RANGE
LOAD CURRENT
OPERATING SUPPLY CURRENT
Symbol
VIN
ILOAD
IGND
SHUTDOWN CURRENT
OUTPUT VOLTAGE ACCURACY
Fixed Output Voltage Accuracy
IGND-SD
Adjustable Output Voltage
Accuracy
REGULATION
Line
Load
SENSE INPUT BIAS CURRENT
DROPOUT VOLTAGE 1
OUTPUT NOISE
VOUT
VSENSE
∆VOUT/∆VIN
∆VOUT/∆ILOAD
SENSEI-BIAS
VDROPOUT
OUTNOISE
Noise Spectral Density
POWER SUPPLY REJECTION RATIO
PSRR
TRANSIENT LOAD RESPONSE
tTR-REC
VDEV
VSETTLE
START-UP TIME 2
tSTART-UP
SOFT START CURRENT
CURRENT-LIMIT THRESHOLD 3
VOUT PULL-DOWN RESISTANCE
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
UNDERVOLTAGE THRESHOLDS
Input Voltage Rising
Input Voltage Falling
Hysteresis
ISS
ILIMIT
VOUT-PULL
TSSD
TSSD-HYS
Test Conditions/Comments
Min
2.3
ILOAD = 0 µA
ILOAD = 500 mA
EN = GND, VIN = 5 V
ILOAD = 10 mA, TJ = 25°C
100 μA< ILOAD < 500 mA, VIN = (VOUT + 0.5 V) to 6.5 V
ILOAD = 10 mA
−0.75
−1.25
1.191
10 mA < ILOAD < 2 A, VIN = (VOUT + 0.5 V) to 6.5 V
1.185
VIN = (VOUT + 0.5 V) to 6.5 V
ILOAD = 100 μA to 500 mA
100 μA< ILOAD < 500 mA, VIN = (VOUT + 0.5 V) to 6.5 V
ILOAD = 500 mA, VOUT = 3 V
10 Hz to 100 kHz, all fixed output voltages
100 Hz to 100 kHz, all fixed output voltages
100 Hz, all fixed output voltages
1 kHz, all fixed output voltages
10 kHz, all fixed output voltages
100 kHz, all fixed output voltages
100 kHz, VIN = 4.0 V, VOUT = 3 V, ILOAD = 500 mA, CSS = 0 nF
100 kHz, VIN = 3.5 V, VOUT = 3 V, ILOAD = 500 mA, CSS = 0 nF
100 kHz, VIN = 3.3 V, VOUT = 3 V, ILOAD = 500 mA, CSS = 0 nF
1 MHz, VIN = 4.0 V, VOUT = 3 V, ILOAD = 500 mA, CSS = 0 nF
1 MHz, VIN = 3.5 V, VOUT = 3 V, ILOAD = 500 mA, CSS = 0 nF
1 MHz, VIN = 3.3 V, VOUT = 3 V, ILOAD = 500 mA, CSS = 0 nF
Time for output voltage to settle within ±VSETTLE from
VDEV for a 1 mA to 500 mA load step, load step rise
time = 400 ns
Output voltage deviation due to 1 mA to 500 mA load
step
Output voltage deviation after transient load response
time (tTR-REC) has passed, VOUT = 5 V, COUT = 4.7 µF
VOUT = 5 V, CSS = 0 nF
VOUT = 5 V, CSS = 1 nF
VIN = 5 V
−0.1
Typ
0.7
3.0
0.25
Max
6.5
500
2.0
5.1
3.8
Unit
V
mA
mA
mA
µA
1.200
+0.75
+1.25
1.209
%
%
V
1.215
V
+0.1
0.6
%/V
%/A
nA
mV
µV rms
µV rms
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
dB
dB
dB
dB
dB
dB
μs
0.1
1
42
6
5
110
40
20
12
60
53
42
31
30
20
1.5
0.5
0.7
EN = 0 V, VOUT = 1 V
TJ rising
70
35
mV
0.1
%
380
1.0
1
1.3
11
µs
ms
µA
A
kΩ
1.5
1.8
150
15
UVLORISE
UVLOFALL
UVLOHYS
°C
°C
2.28
1.94
200
Rev. D | Page 3 of 23
V
V
mV
ADM7170
Parameter
EN INPUT STANDBY
EN Input Logic High
EN Input Logic Low
EN Input Logic Hysteresis
EN INPUT PRECISION
EN Input Logic High
EN Input Logic Low
EN Input Logic Hysteresis
EN Input Leakage Current
EN Input Delay Time
Data Sheet
Symbol
Test Conditions/Comments
2.3 V ≤ VIN ≤ 6.5 V
ENSTBY-HIGH
ENSTBY-LOW
ENSTBY-HYS
Min
Typ
Max
Unit
0.4
V
V
mV
1.1
80
2.3 V ≤ VIN ≤ 6.5 V
ENHIGH
ENLOW
ENHYS
IEN-LKG
TIEN-DLY
1.11
1.01
EN = VIN or GND
From EN rising from 0 V to VIN to 0.1 V × VOUT
1.2
1.1
100
0.1
130
1.27
1.16
1.0
V
V
mV
µA
μs
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output
voltages greater than 2.3 V.
2
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
3
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V.
1
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 3.
Parameter
MINIMUM INPUT AND OUTPUT CAPACITANCE 1
CAPACITOR ESR
1
Symbol
CMIN
RESR
Test Conditions/Comments
TA = −40°C to +125°C
TA = −40°C to +125°C
Min
3.3
0.001
Typ
Max
0.05
Unit
µF
Ω
Ensure that the minimum input and output capacitance is greater than 3.3 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. D | Page 4 of 23
Data Sheet
ADM7170
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VIN to GND
VOUT to GND
EN to GND
SS to GND
SENSE to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +7 V
−0.3 V to VIN
−0.3 V to +7 V
−0.3 V to VIN
−0.3 V to +7 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADM7170 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit provided
that the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA).
PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information on
the board construction. For additional information, see the
AN-617 Application Note, Wafer Level Chip Scale Package,
available at www.analog.com.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than a single
path as in thermal resistance, θJB. Therefore, ΨJB thermal paths
include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and power
dissipation (PD) using the formula
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst-case conditions, that
is, a device soldered in a circuit board for surface-mount
packages.
Table 5. Thermal Resistance
Package Type
8-Lead LFCSP
ESD CAUTION
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
Rev. D | Page 5 of 23
θJA
36.4
θJC
23.5
ΨJB
13.3
Unit
°C/W
ADM7170
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VOUT 1
SENSE 3
SS 4
8 VIN
ADM7170
TOP VIEW
(Not to Scale)
7 VIN
6 GND
5 EN
NOTES
1. THE EXPOSED PAD ENHANCES THERMAL PERFORMANCE
AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE
PACKAGE. CONNECT THE EXPOSED PAD TO THE GROUND
PLANE ON THE BOARD TO ENSURE PROPER OPERATION.
12297-003
VOUT 2
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
VOUT
VOUT
SENSE
4
5
SS
EN
6
7
8
GND
VIN
VIN
EP
Description
Regulated Output Voltage. Bypass this pin to GND with a 4.7 µF or greater capacitor.
Regulated Output Voltage. This pin is internally connected to Pin 1.
Sense Input. Connect this pin as close as possible to the load for best load regulation. Use an external
resistor divider to set the output voltage higher than the fixed output voltage.
Soft Start. A 1 nF external capacitor connected to SS results in a 1.0 ms start-up time.
Regulator Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For
automatic startup, connect EN to VIN (Pin 7 or Pin 8).
Ground.
Regulator Input Supply. Bypass this pin to GND with a 4.7 µF or greater capacitor.
Regulator Input Supply. This pin is internally connected to Pin 7.
Exposed Pad. The exposed pad is on the bottom of the package. The exposed pad enhances thermal
performance and is electrically connected to GND inside the package. Connect the exposed pad to the
ground plane on the board to ensure proper operation.
Rev. D | Page 6 of 23
Data Sheet
ADM7170
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5.5 V, VOUT = 5 V, ILOAD = 10 mA, CIN = COUT = 4.7 µF, TA = 25°C, unless otherwise noted.
5.10
7
ILOAD
ILOAD
ILOAD
ILOAD
5.08
6
GROUND CURRENT (mA)
5.06
5.02
5.00
4.98
4.96
ILOAD
ILOAD
ILOAD
ILOAD
4.92
4.90
4
3
2
= 100µA
= 10mA
= 100mA
= 500mA
–40
–5
1
25
85
0
12297-004
4.94
5
125
JUNCTION TEMPERATURE (°C)
–40
–5
25
85
12297-007
VOUT (V)
5.04
= 100µA
= 10mA
= 100mA
= 500mA
125
JUNCTION TEMPERATURE (°C)
Figure 7. Ground Current vs. Junction Temperature
Figure 4. Output Voltage (VOUT) vs. Junction Temperature
7
5.05
5.04
6
GROUND CURRENT (mA)
5.03
VOUT (V)
5.02
5.01
5.00
4.99
4.98
5
4
3
2
4.97
1
10
100
1000
ILOAD (mA)
0
0.1
1
10
100
Figure 8. Ground Current vs. Load Current (ILOAD)
Figure 5. Output Voltage (VOUT) vs. Load Current (ILOAD)
7
5.05
ILOAD = 100µA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 500mA
5.04
6
GROUND CURRENT (mA)
5.03
5.01
5.00
4.99
4.98
4.96
4.95
5.4
ILOAD
ILOAD
ILOAD
ILOAD
5.6
= 100µA
= 10mA
= 100mA
= 500mA
5.8
5
4
3
2
1
6.0
6.2
6.4
VIN (V)
6.6
12297-006
VOUT (V)
5.02
4.97
1000
ILOAD (mA)
0
5.5
5.7
5.9
6.1
6.3
VIN (V)
Figure 9. Ground Current vs. Input Voltage (VIN)
Figure 6. Output Voltage (VOUT) vs. Input Voltage (VIN)
Rev. D | Page 7 of 23
6.5
12297-009
1
12297-005
4.95
0.1
12297-008
4.96
ADM7170
Data Sheet
1.8
1.2
30
1.0
0.8
0.6
0.4
25
20
15
10
5
0.2
–25
0
25
50
75
100
0
4.7
12297-010
0
–50
125
TEMPERATURE (°C)
4.8
4.9
5.0
5.1
5.2
5.3
5.4
VIN (V)
Figure 10. Shutdown Current vs. Temperature at Various Input Voltages
Figure 13. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 5 V
140
3.05
3.04
120
3.03
100
ILOAD
ILOAD
ILOAD
ILOAD
= 100µA
= 10mA
= 100mA
= 500mA
3.02
80
VOUT (V)
DROPOUT VOLTAGE (mV)
= 5mA
= 10mA
= 100mA
= 500mA
12297-013
1.4
ILOAD
ILOAD
ILOAD
ILOAD
35
GROUND CURRENT (mA)
SHUTDOWN CURRENT (µA)
1.6
40
VIN = 2.3V
VIN = 2.5V
VIN = 3.5V
VIN = 4.0V
VIN = 5.0V
VIN = 6.5V
60
3.01
3.00
2.99
2.98
40
2.97
20
2.96
10
100
1000
ILOAD (mA)
Figure 11. Dropout Voltage vs. Load Current (ILOAD), VOUT = 5 V
–40
25
85
125
Figure 14. Output Voltage (VOUT) vs. Junction Temperature, VOUT = 3 V
5.10
3.05
5.05
3.04
5.00
3.03
4.95
3.02
4.90
3.01
4.85
4.80
4.75
3.00
2.99
2.98
ILOAD = 5mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 500mA
4.8
4.9
5.0
5.1
VIN (V)
5.2
5.3
2.96
5.4
Figure 12. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = 5 V
Rev. D | Page 8 of 23
2.95
0.1
1
10
100
1000
ILOAD (mA)
Figure 15. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3 V
12297-015
4.65
2.97
12297-012
4.70
4.60
4.7
–5
JUNCTION TEMPERATURE (°C)
VOUT (V)
VOUT (V)
2.95
12297-014
1
12297-011
0
Data Sheet
ADM7170
3.05
3.03
= 100µA
= 10mA
= 100mA
= 500mA
3.02
VOUT (V)
ILOAD
ILOAD
ILOAD
ILOAD
6
GROUND CURRENT (mA)
3.04
7
ILOAD
ILOAD
ILOAD
ILOAD
3.01
3.00
2.99
2.98
= 100µA
= 10mA
= 100mA
= 500mA
5
4
3
2
2.97
1
3.8
4.2
4.6
5.0
5.4
5.8
6.2
6.6
VIN (V)
0
3.4
12297-016
4.2
4.6
5.0
5.4
5.8
6.2
6.6
VIN (V)
Figure 16. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 3 V
Figure 19. Ground Current vs. Input Voltage (VIN), VOUT = 3 V
180
7
ILOAD
ILOAD
ILOAD
ILOAD
= 100µA
= 10mA
= 100mA
= 500mA
160
DROPOUT VOLTAGE (mV)
6
GROUND CURRENT (mA)
3.8
5
4
3
2
1
140
120
100
80
60
40
20
–40
–5
25
85
0
12297-017
0
125
JUNCTION TEMPERATURE (°C)
1
10
100
1000
ILOAD (mA)
Figure 17. Ground Current vs. Junction Temperature, VOUT = 3 V
12297-020
2.95
3.4
12297-019
2.96
Figure 20. Dropout Voltage vs. Load Current (ILOAD), VOUT = 3 V
7
3.05
3.00
6
2.90
5
2.85
VOUT (V)
4
3
2.80
2.75
2.70
2
2.65
2.60
ILOAD = 5mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 500mA
2.55
0
0.1
1
10
100
1000
ILOAD (mA)
Figure 18. Ground Current vs. Load Current (ILOAD), VOUT = 3 V
2.50
2.7
2.8
2.9
3.0
3.1
VIN (V)
3.2
3.3
3.4
12297-021
1
12297-018
GROUND CURRENT (mA)
2.95
Figure 21. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = 3 V
Rev. D | Page 9 of 23
Data Sheet
16
1.24
14
1.23
12
1.22
10
1.21
VOUT (V)
8
6
4
ILOAD
ILOAD
ILOAD
ILOAD
1.17
2.9
3.0
3.1
3.2
3.3
3.4
1.16
2.0
12297-022
2.8
Figure 22. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 3 V
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VIN (V)
Figure 25. Output Voltage (VOUT) vs. Input Voltage (VIN), Adjustable Version,
VOUT = 1.2 V
1.24
5.0
ILOAD
ILOAD
ILOAD
ILOAD
= 100µA
= 10mA
= 100mA
= 500mA
ILOAD
ILOAD
ILOAD
ILOAD
4.5
4.0
GROUND CURRENT (mA)
1.22
1.21
VOUT (V)
1.20
1.18
VIN (V)
1.23
= 100µA
= 10mA
= 100mA
= 500mA
1.19
= 5mA
= 10mA
= 100mA
= 500mA
2
0
2.7
ILOAD
ILOAD
ILOAD
ILOAD
12297-025
GROUND CURRENT (mA)
ADM7170
1.20
1.19
1.18
= 100µA
= 10mA
= 100mA
= 500mA
3.5
3.0
2.5
2.0
1.5
1.0
1.17
0.5
–5
25
85
125
0
JUNCTION TEMPERATURE (°C)
–40
85
125
Figure 26. Ground Current vs. Junction Temperature, Adjustable Version,
VOUT = 1.2 V
1.24
4.5
1.23
4.0
3.5
GROUND CURRENT (mA)
1.22
1.21
1.20
1.19
1.18
3.0
2.5
2.0
1.5
1.0
1.17
0.5
10
ILOAD (mA)
100
1000
0
0.1
12297-024
1
Figure 24. Output Voltage (VOUT) vs. Load Current (ILOAD), Adjustable Version,
VOUT = 1.2 V
1
10
ILOAD (mA)
100
1000
12297-027
VOUT (V)
25
JUNCTION TEMPERATURE (°C)
Figure 23. Output Voltage (VOUT) vs. Junction Temperature, Adjustable
Version, VOUT = 1.2 V
1.16
0.1
–5
12297-026
–40
12297-023
1.16
Figure 27. Ground Current vs. Load Current (ILOAD), Adjustable Version,
VOUT = 1.2 V
Rev. D | Page 10 of 23
Data Sheet
ADM7170
4.5
ILOAD
ILOAD
ILOAD
ILOAD
4.0
GROUND CURRENT (mA)
3.5
0
= 100µA
= 10mA
= 100mA
= 500mA
–20
2.5
2.0
–40
–60
1.5
1.0
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
–80
0.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VIN (V)
–100
12297-028
0
2.0
Figure 28. Ground Current vs. Input Voltage (VIN), Adjustable Version,
VOUT = 1.2 V
0
0.3
0.4
0.5
0.6
0.7
0.8
Figure 31. Power Supply Rejection Ratio (PSRR) vs. Headroom, VOUT = 3 V,
500 mA Load Current, Different Frequencies
0
VIN = 3.0V
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 6.5V
ILOAD
ILOAD
ILOAD
ILOAD
–20
PSRR (dB)
SS CURRENT (µA)
0.2
HEADROOM (V)
1.2
1.1
0.1
12297-031
PSRR (dB)
3.0
1.0
= 10mA
= 100mA
= 200mA
= 500mA
–40
–60
0.9
–40
–5
25
85
–100
12297-029
0.8
125
TEMPERATURE (°C)
1
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 29. Soft Start (SS) Current vs. Temperature, Different Input Voltages,
VOUT = 5 V
Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency,
800 mV Headroom, VOUT = 3 V
0
0
–20
–40
–40
PSRR (dB)
–20
800mV
700mV
600mV
500mV
400mV
300mV
200mV
160mV
100mV
–80
–100
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
ILOAD
ILOAD
ILOAD
ILOAD
= 10mA
= 100mA
= 200mA
= 500mA
–60
–80
Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 3 V,
500 mA Load Current, Various Headroom Voltages
Rev. D | Page 11 of 23
–100
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 33. Power Supply Rejection Ratio (PSRR) vs. Frequency,
500 mV Headroom, VOUT = 3 V
12297-033
–60
12297-030
PSRR (dB)
10
12297-032
–80
ADM7170
0
ILOAD
ILOAD
ILOAD
ILOAD
–20
0
= 10mA
= 100mA
= 200mA
= 500mA
–40
–60
–60
–80
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–100
12297-034
–100
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency,
400 mV Headroom, VOUT = 3 V
Figure 37. Power Supply Rejection Ratio (PSRR) vs. Frequency,
800 mV Headroom, VOUT = 5 V
0
0
–20
–40
–40
PSRR (dB)
–20
–60
800mV
700mV
600mV
500mV
400mV
300mV
200mV
150mV
–100
1
10
ILOAD = 100mA
ILOAD = 200mA
ILOAD = 500mA
–60
–80
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–100
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 5 V,
500 mA Load Current, Various Headroom Voltages
12297-038
–80
12297-035
Figure 38. Power Supply Rejection Ratio (PSRR) vs. Frequency,
500 mV Headroom, VOUT = 5 V
0
0
–20
–40
–40
PSRR (dB)
–20
–60
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
–100
0
0.1
–60
–80
0.2
0.3
0.4
0.5
HEADROOM (V)
0.6
0.7
0.8
12297-036
–80
ILOAD = 100mA
ILOAD = 200mA
ILOAD = 500mA
Figure 36. Power Supply Rejection Ratio (PSRR) vs. Headroom, VOUT = 5 V,
500 mA Load Current, Different Frequencies
Rev. D | Page 12 of 23
–100
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 39. Power Supply Rejection Ratio (PSRR) vs. Frequency,
400 mV Headroom, VOUT = 5 V
12297-039
PSRR (dB)
–40
12297-037
–80
PSRR (dB)
ILOAD = 100mA
ILOAD = 200mA
ILOAD = 500mA
–20
PSRR (dB)
PSRR (dB)
Data Sheet
Data Sheet
ADM7170
10
10
8
7
7
NOISE (µV rms)
8
6
5
4
6
5
4
3
3
2
2
1
1
0
1
10
100
1000
10000
ILOAD (mA)
0
1.0
1.4
1.8
2.2
2.6
3.0
3.4
3.8
4.2
4.6
5.0
OUTPUT VOLTAGE (V)
Figure 43. RMS Output Noise vs. Output Voltage (VOUT),
Load Current = 100 mA
Figure 40. RMS Output Noise vs. Load Current (ILOAD), Adjustable Version,
VOUT = 1.2 V
100k
10
10Hz TO 100kHz
100Hz TO 100kHz
NOISE SPECTRAL DENSITY (nV/√Hz)
9
8
7
NOISE (µV rms)
10Hz TO 100kHz
100Hz TO 100kHz
9
12297-040
NOISE (µV rms)
9
12297-043
10Hz TO 100kHz
100Hz TO 100kHz
6
5
4
3
2
ILOAD
ILOAD
ILOAD
ILOAD
10k
= 1mA
= 10mA
= 100mA
= 500mA
1k
100
10
1
10
100
1000
10000
ILOAD (mA)
1
12297-041
0
Figure 41. RMS Output Noise vs. Load Current (ILOAD), VOUT = 3 V
1
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 44. Output Noise Spectral Density, Adjustable Version, VOUT = 1.2 V
10
100k
10Hz TO 100kHz
100Hz TO 100kHz
NOISE SPECTRAL DENSITY (nV/√Hz)
9
8
7
6
5
4
3
2
ILOAD
ILOAD
ILOAD
ILOAD
10k
= 1mA
= 10mA
= 100mA
= 500mA
1k
100
10
0
1
10
100
1000
10000
ILOAD (mA)
Figure 42. RMS Output Noise vs. Load Current (ILOAD), VOUT = 5 V
1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 45. Output Noise Spectral Density, VOUT = 3 V
Rev. D | Page 13 of 23
10M
12297-045
1
12297-042
NOISE (µV rms)
10
12297-044
1
ADM7170
Data Sheet
ILOAD
ILOAD
ILOAD
ILOAD
10k
T
= 1mA
= 10mA
= 100mA
= 500mA
1
1k
2
100
1
10
100
1k
10k
100k
1M
12297-046
1
10M
FREQUENCY (Hz)
CH1 50mA Ω BW CH2 2mV
M2.0µs
T 10.4%
A CH1
40mA
5.0V
3.0V
1.2V
T
10k
1
1k
100
2
10
1
10
100
1k
10k
100k
1M
12297-047
1
10M
FREQUENCY (Hz)
Figure 47. Output Noise Spectral Density, Different Output Voltages,
Load Current = 100 mA
CH1 200mA Ω BW CH2 10mV
B
W M4.0µs
A CH1
124mA
T 10.6%
12297-050
NOISE SPECTRAL DENSITY (nV/√Hz)
W
Figure 49. Load Transient Response, ILOAD = 10 mA to 110 mA,
VOUT = 5 V, VIN = 5.5 V, CH1 = ILOAD, CH2 = VOUT
Figure 46. Output Noise Spectral Density, VOUT = 5 V
100k
B
12297-049
10
Figure 50. Load Transient Response, ILOAD = 10 mA to 510 mA,
Adjustable Version, VOUT = 1.2 V, VIN = 2.5 V, CH1 = ILOAD, CH2 = VOUT
T
T
1
1
2
2
B
W
M2.0µs
T 9.8%
A CH1
160mA
CH1 50mA Ω BW CH2 2mV
12297-048
CH1 200mA Ω BW CH2 10mV
B
W
M2.0µs
T 10.6%
A CH1
63mA
12297-051
NOISE SPECTRAL DENSITY (nV/√Hz)
100k
Figure 51. Load Transient Response, ILOAD = 10 mA to 110 mA,
Adjustable Version, VOUT = 1.2 V, VIN = 2.5 V, CH1 = ILOAD, CH2 = VOUT
Figure 48. Load Transient Response, ILOAD = 10 mA to 510 mA,
VOUT = 5 V, VIN = 5.5 V, CH1 = ILOAD, CH2 = VOUT
Rev. D | Page 14 of 23
Data Sheet
ADM7170
T
T
1
2
2
CH2 2.0mV
B
W M4.0µs
T 9.8%
A CH3
–300mV
CH1 500mV BW
CH2 2.0mV
B
W
M4.0µs
T 9.8%
A CH3
360mV
12297-054
CH1 500mV BW
12297-052
1
Figure 53. Line Transient Response, 2.5 V to 3 V, ILOAD = 500 mA,
Adjustable Version, VOUT = 1.2 V, CH1 = VIN, CH2 = VOUT
Figure 52. Line Transient Response, 6 V to 6.5 V, ILOAD = 500 mA,
VOUT = 5 V, CH1 = VIN, CH2 = VOUT
Rev. D | Page 15 of 23
ADM7170
Data Sheet
THEORY OF OPERATION
The ADM7170 is a low quiescent current, low dropout linear
regulator that operates from 2.3 V to 6.5 V and provides up to
500 mA of load current. Drawing a low 3.0 mA of quiescent
current (typical) at full load makes the ADM7170 ideal for
portable equipment. Typical shutdown current consumption is
0.25 μA at room temperature.
The ADM7170 is available in 17 fixed output voltage options,
ranging from 1.2 V to 5 V. The ADM7170 architecture allows
any fixed output voltage to be set to a higher voltage with an
external voltage divider. For example, a fixed 5 V output
ADM7170 can be set to a 6 V output according to the following
equation:
Optimized for use with small 4.7 µF ceramic capacitors, the
ADM7170 provides excellent transient performance.
SENSE
CURRENT-LIMIT,
THERMAL
PROTECT
VOUT
VOUT
SENSE
VOUT = 6.0V
R1
2kΩ
COUT
4.7µF
R2
10kΩ
EN
SOFT START
OFF
SS
GND
SS
CSS
1nF
12297-057
ON
12297-056
SHUTDOWN
VIN
VIN
CIN
4.7µF
REFERENCE
EN
ADM7170
VIN = 6.5V
VOUT
VIN
GND
VOUT = 5 V(1 + R1/R2)
Figure 55. Typical Adjustable Output Voltage Application Schematic
Figure 54. Internal Block Diagram
Internally, the ADM7170 consists of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass
transistor. Output current is delivered via the PMOS pass
device, which is controlled by the error amplifier. The error
amplifier compares the reference voltage with the feedback
voltage from the output and amplifies the difference. When the
feedback voltage is lower than the reference voltage, the gate
of the PMOS device is pulled lower, allowing more current to
pass and increasing the output voltage. When the feedback
voltage is higher than the reference voltage, the gate of the
PMOS device is pulled higher, allowing less current to pass and
decreasing the output voltage.
Use a value of less than 200 kΩ for R2 to minimize errors in the
output voltage caused by the SENSE pin input current. For
example, when R1 and R2 each equal 200 kΩ and the default
output voltage is 1.2 V, the adjusted output voltage is 2.4 V. The
output voltage error introduced by the SENSE pin input current is
0.1 mV or 0.004%, assuming a typical SENSE pin input bias
current of 1 nA at 25°C.
The ADM7170 uses the EN pin to enable and disable the VOUT
pins under normal operating conditions. When EN is high, VOUT
turns on; when EN is low, VOUT turns off. For automatic startup,
tie EN to VIN (Pin 7 or Pin 8).
Rev. D | Page 16 of 23
Data Sheet
ADM7170
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
Input Bypass Capacitor
The ADM7170 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic, bill of materials,
and calculate performance in minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and parts count,
taking into consideration the operating conditions and
limitations of the IC and all real external components. For more
information about, and to obtain ADIsimPower design tools,
visit www.analog.com/ADIsimPower.
Connecting a 4.7 µF capacitor from VIN to GND reduces the
circuit sensitivity to PCB layout, especially when long input
traces or a high source impedance is encountered. If greater
than 4.7 µF of output capacitance is required, increase the input
capacitor to match it.
Multilayer ceramic capacitors (MLCC) combine small size, low
effective series resistance (ESR), low ESL, and wide operating
temperature range, making them an ideal choice for bypass
capacitors. They are not without limitations, however.
Depending on the dielectric material, the capacitance can vary
dramatically with temperature, dc bias, and ac signal level.
Therefore, selecting the proper capacitor results in the best
circuit performance.
Output Capacitor
The ADM7170 is designed for operation with small, spacesaving ceramic capacitors but functions with most commonly
used capacitors as long as care is taken with regard to the ESR
value. The ESR of the output capacitor affects the stability of the
LDO control loop. A minimum of 4.7 µF capacitance with an
ESR of 0.05 Ω or less is recommended to ensure the stability of the
ADM7170. Transient response to changes in load current is also
affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADM7170 to
large changes in load current. Figure 56 shows the transient
responses for an output capacitance value of 4.7 µF.
Any good quality ceramic capacitors can be used with the
ADM7170 if they meet the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors require a
dielectric adequate to ensure the minimum capacitance over
the necessary temperature range and dc bias conditions. X5R
or X7R dielectrics with a voltage rating of 6.3 V to 100 V are
recommended. Y5V and Z5U dielectrics are not recommended,
due to their poor temperature and dc bias characteristics.
Figure 57 depicts the capacitance vs. dc bias voltage of a 0805,
4.7 µF, 16 V, X5R capacitor. The voltage stability of a capacitor is
strongly influenced by the capacitor size and voltage rating. In
general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is ~±15% over the −40°C to +85°C temperature range
and is not a function of package or voltage rating.
5.0
4.5
4.0
CAPACITANCE (µF)
CAPACITOR SELECTION
Input and Output Capacitor Properties
3.5
3.0
2.5
2.0
1.5
T
1.0
0
0
1
2
4
6
8
10
12
14
16
DC BIAS VOLTAGE (V)
18
20
12297-059
0.5
Figure 57. Capacitance vs. DC Bias Voltage
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance,
and voltage.
2
CH1 200mA Ω BW CH2 10mV
B
W
M2.0µs
T 9.8%
A CH1
160mA
12297-058
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
Figure 56. Output Transient Response, VOUT = 5 V, COUT = 4.7 µF
(1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
Rev. D | Page 17 of 23
ADM7170
Data Sheet
CEFF = 4.35 μF × (1 − 0.15) × (1 − 0.1) = 3.33 μF
ON
The ADM7170 uses the EN pin to enable and disable the VOUT
pins under normal operating conditions. As shown in Figure 58,
when a rising voltage on EN crosses the upper threshold,
typically 1.2 V, VOUT turns on. When a falling voltage on EN
crosses the lower threshold, typically 1.1 V, VOUT turns off. The
hysteresis of the EN threshold is approximately 100 mV.
3.0
VOUT = 5.0V
VOUT
VOUT
SENSE
COUT
4.7µF
EN
REN2
100kΩ
GND
Figure 59. Typical EN Pin Voltage Divider
Figure 58 shows the typical hysteresis of the EN pin. This
prevents on/off oscillations that can occur due to noise
on the EN pin as it passes through the threshold points.
UNDERVOLTAGE LOCKOUT
The ADM7170 also incorporates an internal undervoltage
lockout circuit to disable the output voltage when the input
voltage is less than the minimum input voltage rating of the
regulator. The upper and lower thresholds are internally fixed
with about 200 mV of hysteresis. This hysteresis prevents on/off
oscillations that can occur when caused by noise on the input
voltage as it passes through the threshold points.
SOFT START
2.5
The ADM7170 uses an internal soft start (SS pin open) to limit the
inrush current when the output is enabled. The start-up time for
the 5.0 V option is approximately 380 μs from the time the EN
active threshold is crossed to when the output reaches 90% of its
final value. As shown in Figure 60, the start-up time is nearly
independent of the output voltage setting.
2.0
1.5
1.0
5.0
0.5
VEN
2.5V
3.0V
5.0V
4.5
4.0
1.10
1.15
1.20
1.25
1.30
VEN (V)
Figure 58. Typical VOUT Response to EN Pin Operation
The upper and lower thresholds are user programmable and can
be set higher than the nominal 1.2 V threshold by using two
resistors. The resistance values, REN1 and REN2, can be
determined from
3.5
VOUT (V)
1.05
12297-060
0
1.00
REN1 = REN2 × (VIN − 1.2 V)/1.2 V
3.0
2.5
2.0
1.5
1.0
0.5
0
where:
REN2 is nominally 10 kΩ to 100 kΩ.
VIN is the desired turn-on voltage.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
TIME (ms)
Figure 60. Typical Start-Up Behavior
The hysteresis voltage increases by the factor
(REN1 + REN2)/REN1
For the example shown in Figure 59, the enable threshold is
3.6 V with a hysteresis of 300 mV.
Rev. D | Page 18 of 23
0.9
1.0
12297-062
VOUT (V)
REN1
200kΩ
OFF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage of 3.0 V.
PROGRAMMABLE PRECISION ENABLE
VIN
VIN
CIN
4.7µF
Substituting these values in Equation 1 yields
To guarantee the performance of the ADM7170, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
ADM7170
VIN = 6.0V
12297-061
The tolerance of the capacitor (TOL) is assumed to be 10%, and
CBIAS is 4.35 μF at 3.0 V, as shown in Figure 57.
Data Sheet
ADM7170
SSTIME (sec) = tSTART-UP at 0 nF + (0.6 × CSS)/ISS
CNR is chosen by setting the reactance of CNR equal to RFB1 −
RNR at a frequency between 0.5 Hz and 10 Hz. This sets the
frequency where the ac gain of the error amplifier is 3 dB
less than its dc gain.
ADM7170
VIN = 6.5V
VIN
VIN
CIN
4.7µF
where:
tSTART-UP at 0 nF is the start-up time at CSS = 0 nF (typically 380 μs).
CSS is the soft start capacitor (F).
ISS is the soft start current (typically 1 μA).
RFB1
200kΩ
SS
RFB2
CSS 50kΩ
1nF
ON
EN
OFF
VOUT = 6.0V
VOUT
VOUT
SENSE
GND
RNR
5kΩ
CNR
1µF
COUT
4.7µF
3.5
12297-064
An external capacitor connected to the SS pin determines the
soft-start time. The SS pin can be left open for a typical 380 μs
start-up time. Do not ground this pin. When an external soft
start capacitor is used, the soft start time is determined by the
following equation:
Figure 62. Noise Reduction Modification
3.0
Assuming the noise of a fixed output LDO is approximately
5 μV, identify the noise of the adjustable LDO by using the
following formula:
2.0
Noise = 5 μV × (RPAR + RFB2)/RFB2
where RPAR is the parallel combination of RFB1 and RNR.
1.5
1.0
Based on the component values shown in Figure 62, the
ADM7170 has the following characteristics:
VEN
NO CSS
1nF
4.7nF
10nF
0.5
0
0
1
2
3
4
5
6
7
8
9
TIME (ms)
10
12297-063
VOUT (V)
2.5
Figure 61. Typical Soft Start Behavior, Different CSS Values
NOISE REDUCTION OF THE ADM7170 IN
ADJUSTABLE MODE
•
•
•
•
•
•
The ultralow output noise of the ADM7170 is achieved by
keeping the LDO error amplifier in unity gain and setting the
reference voltage equal to the output voltage. This architecture
does not work for an adjustable output voltage LDO in the
conventional sense. However, the ADM7170 architecture allows
any fixed output voltage to be set to a higher voltage with an
external voltage divider. For example, the adjustable (1.2 V in
unity gain) output ADM7170 can be set to a 6 V output
according to the following equation:
VOUT = 1.2 V(1 + R1/R2)
The disadvantage of using the ADM7170 in this manner is that
the output voltage noise is proportional to the output voltage.
Therefore, it is best to choose a fixed output voltage that is close
to the target voltage to minimize the increase in output noise.
The adjustable LDO circuit can be modified to reduce the
output voltage noise to levels close to that of the fixed output
ADM7170. The circuit shown in Figure 62 adds two additional
components to the output voltage setting resistor divider. CNR
and RNR are added in parallel with RFB1 to reduce the ac gain of
the error amplifier. RNR is chosen to be small with respect to
RFB2. If RNR is 1% to 10% of the value of RFB2, the minimum ac
gain of the error amplifier is approximately 0.1 dB to 0.8 dB.
The actual gain is determined by the parallel combination of
RNR and RFB1. This ensures that the error amplifier always
operates at slightly greater than unity gain.
DC gain of 5 (14 dB)
3 dB roll-off frequency of 0.8 Hz
High frequency ac gain of 1.09 (0.75 dB)
Noise reduction factor of 4.42 (12.91 dB)
RMS noise of the adjustable LDO without noise reduction
of 25 µV rms
RMS noise of the adjustable LDO with noise reduction
(assuming 5 µV rms for fixed voltage option) of 5.5 µV rms
EFFECT OF NOISE REDUCTION ON START-UP TIME
The start-up time of the ADM7170 is affected by the noise
reduction network and must be considered in applications
wherein power supply sequencing is critical.
The noise reduction circuit adds a pole in the feedback loop
that slows down the start-up time. The start-up time for an
adjustable model with a noise reduction network can be
approximated using the following equation:
SSNRTIME (sec) = 5.5 × CNR × (RNR + RFB1)
For a CNR, RNR, and RFB1 combination of 1 µF, 5 kΩ, and 200 kΩ,
respectively, as shown in Figure 62, the start-up time is
approximately 1.1 seconds. When SSNRTIME is greater than
SSTIME, it dictates the length of the start-up time instead of the
soft start capacitor.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADM7170 is protected against damage due to excessive
power dissipation by current-limit and thermal overload
protection circuits. The ADM7170 is designed to current limit
when the output load reaches 3 A (typical). When the output
load exceeds 3 A, the output voltage is reduced to maintain a
constant current limit.
Rev. D | Page 19 of 23
ADM7170
Data Sheet
Current-limit and thermal limit protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation must be externally
limited so that the junction temperature does not exceed 125°C.
THERMAL CONSIDERATIONS
In applications with low input-to-output voltage differential, the
ADM7170 does not dissipate much heat. However, in applications
with high ambient temperature and/or high input voltage, the heat
dissipated in the package may become large enough that it
causes the junction temperature of the die to exceed the
maximum junction temperature of 125°C.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown
in Equation 2.
To guarantee reliable operation, the junction temperature of
the ADM7170 must not exceed 125°C. To ensure that the
junction temperature stays below this maximum value, the
user must be aware of the parameters that contribute to
junction temperature changes. These parameters include
ambient temperature, power dissipation in the power device,
and thermal resistances between the junction and ambient air
(θJA). The θJA number is dependent on the package assembly
compounds that are used and the amount of copper used to
solder the package GND pin to the PCB.
Copper Size (mm2)
251
100
500
1000
6400
1
θJA (°C/W) of LFCSP
165.1
125.8
68.1
56.4
42.1
Device soldered to minimum size pin traces.
The junction temperature of the ADM7170 is calculated from
the following equation:
TJ = TA + (PD × θJA)
(2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND)
(3)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are the input and output voltages, respectively.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to the following:
TJ = TA + (((VIN − VOUT) × ILOAD) × θJA)
(4)
As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current, a
minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 63
to Figure 65 show junction temperature calculations for different ambient temperatures, power dissipation, and areas of PCB
copper.
155
145
135
Table 7 shows typical θJA values of the 8-lead LFCSP package for
various PCB copper sizes. The typical value of ΨJB is 15.1°C/W for
the 8-lead LFCSP package.
Rev. D | Page 20 of 23
125
115
105
95
85
75
65
55
6400mm 2
500mm 2
25mm 2
TJ MAX
45
35
25
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
TOTAL POWER DISSIPATION (W)
Figure 63. LFCSP, TA = 25°C
12297-065
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADM7170 current limits, so that only 3 A is
conducted into the short. If self heating of the junction is great
enough to cause its temperature to rise above 150°C, thermal
shutdown activates, turning off the output and reducing the output
current to zero. As the junction temperature cools and drops
below 135°C, the output turns on and conducts 3 A into the
short, again causing the junction temperature to rise above
150°C. This thermal oscillation between 135°C and 150°C
causes a current oscillation between 3 A and 0 mA that
continues for as long as the short remains at the output.
Table 7. Typical θJA Values
JUNCTION TEMPERATURE (°C)
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and/or
high power dissipation) when the junction temperature starts to
rise above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C, the output is turned on again, and the output current is
restored to its operating value.
Data Sheet
ADM7170
160
160
140
130
120
110
100
90
80
6400mm 2
500mm 2
25mm 2
TJ MAX
70
60
50
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
TOTAL POWER DISSIPATION (W)
120
100
80
60
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
40
20
0
0
1
2
3
4
5
6
7
8
TOTAL POWER DISSIPATION (W)
Figure 64. LFCSP, TA = 50°C
9
12297-068
JUNCTION TEMPERATURE (°C)
140
12297-066
JUNCTION TEMPERATURE (°C)
150
Figure 66. LFCSP Power Dissipation for Various Board Temperatures
TYPICAL APPLICATIONS CIRCUITS
155
4V TO 6.5V
125
ADM7170
6.5V, 500mA
LDO
3.3V
HIGH
SPEED
CLOCK
DRIVER
115
12297-070
135
105
Figure 67. Clock Driver
95
4V TO 6.5V
6400mm 2
500mm 2
25mm 2
TJ MAX
75
65
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
TOTAL POWER DISSIPATION (W)
Figure 65. LFCSP, TA = 85°C
3.3V
ADM7170
6.5V, 500mA
LDO
3.3V
VVCO
DVDD
AVDD
Figure 68. RF PLL/VCO Power
In the case where the board temperature is known, use the
thermal characterization parameter, ΨJB, to estimate the
junction temperature rise. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and power
dissipation (PD) using the following formula:
TJ = TB + (PD × ΨJB)
ADM7170
6.5V, 500mA
LDO
(5)
Rev. D | Page 21 of 23
ADF4350
12297-071
85
12297-067
JUNCTION TEMPERATURE (°C)
145
ADM7170
Data Sheet
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADM7170.
However, as listed in Table 7, a point of diminishing returns
is eventually reached, beyond which an increase in the copper
size does not yield significant heat dissipation benefits.
12297-069
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0805 or 1206 size capacitors and
resistors achieves the smallest possible footprint solution on
boards where area is limited.
Figure 69. Example LFCSP PCB Layout
Rev. D | Page 22 of 23
Data Sheet
ADM7170
OUTLINE DIMENSIONS
2.54
2.44
2.34
3.10
3.00 SQ
2.90
DETAIL A
(JEDEC 95)
0.50 BSC
8
PIN 1 INDEX
AREA
1.70
1.60
1.50
EXPOSED
PAD
0.50
0.40
0.30
4
1
BOTTOM VIEW
TOP VIEW
PKG-004371
0.80
0.75
0.70
SIDE VIEW
0.30
0.25
0.20
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 MIN
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET
0.203 REF
08-17-2018-A
5
Figure 70. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-21)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADM7170ACPZ-1.3-R7
ADM7170ACPZ-1.8-R7
ADM7170ACPZ-2.5-R7
ADM7170ACPZ-3.0-R7
ADM7170ACPZ-3.3-R7
ADM7170ACPZ-4.2-R7
ADM7170ACPZ-5.0-R7
ADM7170ACPZ-R7
ADM7170ACPZ-R2
ADM7170CP-EVALZ
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage (V) 2, 3
1.3
1.8
2.5
3.0
3.3
4.2
5.0
Adjustable (1.2 V)
Adjustable (1.2 V)
Evaluation Board
Package Description
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
Z = RoHS Compliant Part.
For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.
3
The evaluation boards are preconfigured with an adjustable voltage (1.2 V) preset to a 3.0 V ADM7170.
1
2
©2014–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12297-0-9/19(D)
Rev. D | Page 23 of 23
Package Option
CP-8-21
CP-8-21
CP-8-21
CP-8-21
CP-8-21
CP-8-21
CP-8-21
CP-8-21
CP-8-21
Marking Code
LPR
LPS
LR2
LPT
LPU
LQW
LPV
LPW
LPW
工商网监
湘ICP备2023018690号
