ADM8830ARUZ

Charge Pump Regulator for Color TFT Panel ADM8830 FEATURES 3 Output Voltages (+5.1 V, +15.3 V, –10.2 V) from One 3 V Input Supply Power Efficiency Optimized for Use with TFT in Mobile Phones Low Quiescent Current Low Shutdown Current ( 2.7 V Blanking Period VCC = 3 V, IL = 5 mA (Scanning) VCC = 3 V, IL = 200 µA (Blanking) 8 mA Load IL Stepped from 10 µA to 8 mA 14.4 15.3 50 1 50 15.6 100 10 V µA µA mV p-p IL = 1 µA to 100 µA Scanning Period Blanking Period IL = 100 µA –10.4 –100 –10 –10.2 –50 –1 50 –9.6 V µA µA mV p-p IL = –1 µA to –100 µA Scanning Period Blanking Period IL = –100 µA % % Relative to 5.1 V Output, IL = 100 µA (Scanning) Relative to 5.1 V Output, IL =10 µA (Blanking) kHz Scanning Period SUPPLY CURRENT, ICC +5.1 V OUTPUT Output Voltage Output Current Power Efficiency Output Ripple Transient Response +15.3 V OUTPUT Output Voltage Output Current Output Ripple –10.2 V OUTPUT Output Voltage Output Current Output Ripple POWER EFFICIENCY (+15.3 V and –10.2 V Outputs) CHARGE PUMP FREQUENCY 90 80 60 100 140 B SO CONTROL PINS SHDN Input Voltage, VSHDN Typ Digital Input Current Digital Input Capacitance* SCAN/BLANK Input Voltage O Digital Input Current Digital Input Capacitance* LDO_ON/OFF Input Voltage Digital Input Current Digital Input Capacitance* CLKIN Minimum Frequency Input Voltage VIL VIH Digital Input Current Digital Input Capacitance* 0.3 VCC 0.7 VCC ±1 10 0.3 VCC 0.7 VCC ±1 10 0.3 VCC 0.7 VCC 0.9 0.7 VCC Test Conditions TE Min LE Parameter (VCC = 2.6 V to 3.6 V, TA = –40C to +85C, unless otherwise noted, C1, C5, C6, C7 = 2.2 F, C2, C3, C4, C8, C9 = 1 F, CLKIN = 1 kHz in blanking mode.) ±1 10 1 0.3 VCC ±1 10 V V µA pF SHDN Low = Shutdown Mode SHDN High = Normal Mode V V µA pF Low = BLANK Period High = SCAN Period V V µA pF Low = External LDO High = Internal LDO kHz Duty Cycle = 50%, Rise/Fall Times = 20 ns V V µA pF *Guaranteed by design. Not 100% production tested. Specifications are subject to change without notice. –2– REV. B ADM8830 (VCC = 2.6 V to 3.6 V, TA = –40C to +85C, unless otherwise noted, C1, C5, C6, C7 = 2.2 F, C2, C3, C4, C8, C9 = 1 F, CLKIN = 1 kHz in blanking mode.) TIMING SPECIFICATIONS Parameter Min POWER-UP SEQUENCE +5 V Rise Time, tR5V +15 V Rise Time, tR15V –10 V Fall Time, tF10V Delay between –10 V Fall and +15 V, tDELAY POWER-DOWN SEQUENCE +5 V Fall Time, tF5V +15 V Fall Time, tF15V –10 V Rise Time, tR10V Typ Max Unit Test Conditions 300 8 12 µs ms ms 10% to 90%, Figure 2 10% to 90%, Figure 2 90% to 10%, Figure 2 3 ms Figure 2 75 40 40 ms ms ms 90% to 10%, Figure 2 90% to 10%, Figure 2 10% to 90%, Figure 2 TE Specifications are subject to change without notice. ABSOLUTE MAXIMUM RATINGS* THERMAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.) 20-Lead TSSOP Package: JA = 72°C/W 20-Lead LFCSP Package: JA = 31°C/W B SO LE Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.0 V Input Voltage to Digital Inputs . . . . . . . . . . . . . –0.3 V to +4.0 V Output Short Circuit Duration to GND . . . . . . . . . . . . . 10 sec Output Voltage +5.1 V Output . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V –10.2 V Output . . . . . . . . . . . . . . . . . . . . . . . .–12 V to +0.3 V +15.3 V Output . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.55 W (Derate 33 mW/°C above 25°C) Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class I *This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ORDERING GUIDE Temperature Range Package Description Package Option ADM8830ACP ADM8830ACP-REEL7 ADM8830ARU ADM8830ARU-REEL ADM8830ARU-REEL7 EVAL-ADM8830EB –40ºC to +85ºC –40ºC to +85ºC –40ºC to +85ºC –40ºC to +85ºC –40ºC to +85ºC Lead Frame Chip Scale Package Lead Frame Chip Scale Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Thin Shrink Small Outline Package Evaluation Board CP-20-1 CP-20-1 RU-20 RU-20 RU-20 O Model CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM8830 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– ADM8830 PIN CONFIGURATIONS TSSOP C1– 1 20 GND C1+ 2 19 –10VOUT VCC 3 18 C4+ VOUT 4 17 C4– 16 C2+ VCC 1 VOUT 2 LDO_IN 3 +5VOUT 4 +5VIN 5 TOP VIEW 15 C2– (Not to Scale) +5VIN 7 14 C3+ LDO_ON/OFF 8 13 C3– SHDN 9 12 +15VOUT SCAN/BLANK 10 11 CLKIN PIN 1 INDICATOR ADM8830 TOP VIEW 15 C4– 14 C2+ 13 C2– 12 C3+ 11 C3– LDO_ON/OFF 6 SHDN 7 SCAN/BLANK 8 CLKIN 9 +15VOUT 10 +5VOUT 6 ADM8830 TE LDO_IN 5 20 C1+ 19 C1– 18 GND 17 –10VOUT 16 C4+ LFCSP PIN FUNCTION DESCRIPTIONS Pin Number LFCSP Mnemonic Function 1, 2 3 4 19, 20 1 2 C1–, C1+ VCC VOUT 5 3 LDO_IN 6 4 7 5 8 6 9 7 External capacitor C1 is connected between these pins. A 2.2 µF capacitor is recommended. Positive Supply Voltage Input. Connect this pin to 3 V supply with a 2.2 µF decoupling capacitor. Voltage Doubler Output. This is derived by doubling the 3 V supply. A 2.2 µF capacitor to ground is required on this pin. Voltage Regulator Input. The user has the option to bypass this circuit using the LDO_ON/OFF pin. +5.1 V Output Pin. This is derived by doubling and regulating the 3 V supply. A 2.2 µF capacitor to ground is required on this pin to stabilize the regulator. +5.1 V Input Pin. This is the input to the voltage tripler and doubler inverter charge pump circuits. Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for regulation of the 5 V voltage doubler output. A logic low isolates the internal LDO from the rest of the charge pump circuits. This allows the use of an external LDO to regulate the 5 V voltage doubler output. The output of this LDO is then fed back into the voltage tripler and doubler/inverter circuits of the ADM8830. Digital Input. 3 V CMOS logic. Active low shutdown control. This shuts down the timing generator and enables the discharge circuit to dissipate the charge on the voltage outputs, thus driving them to 0 V. Drive Mode Input. 3 V CMOS logic. A logic high places the part in scan (high current) mode and the charge pump is driven by the internal oscillator. A logic low places the part in blanking (low current) mode and the charge pump is driven by the (slower) external oscillator. This is a power saving feature on the ADM8830. External CLOCK Input. During a blanking period, the oscillator circuit selects this pin to drive the charge pump circuit. This is at a lower frequency than the internal oscillator, resulting in lower quiescent current consumption, thus saving power. +15.3 V Output Pin. This is derived by tripling the +5.1 V regulated output. A 1 µF capacitor is required on this pin. External capacitor C3 is connected between these pins. A 1 µF capacitor is recommended. External capacitor C2 is connected between these pins. A 1 µF capacitor is recommended. External capacitor C4 is connected between these pins. A 1 µF capacitor is recommended. –10.2 V Output Pin. This is derived by doubling and inverting the +5.1 V regulated output. A 1 µF capacitor is required on this pin. Device Ground Pin. B SO +5VOUT +5VIN LDO_ON/OFF SHDN O 10 LE TSSOP 8 SCAN/BLANK 11 9 CLKIN 12 10 +15VOUT 13, 14 15, 16 17, 18 19 11, 12 13, 14 15, 16 17 C3–, C3+ C2–, C2+ C4–, C4+ –10VOUT 20 18 GND –4– REV. B 80 5.0752 5.104 70 5.0750 5.102 50 40 30 20 5.0744 5.0742 5.0740 30 50 70 90 110 130 150 170 190 OUTPUT CURRENT – A TPC 1. LDO Efficiency in Blanking Mode with VCC = 3 V 5.090 1000 BLANKING FREQUENCY – Hz 100 81 80 79 1 0 2 4 6 3 5 OUTPUT CURRENT – mA 7 TPC 4. LDO Efficiency in Scanning Mode with VCC = 3 V 1 2 4 3 5 ILOAD – mA 6 5.25 70 2 4 6 8 OUTPUT CURRENT – A 10 TPC 5. +15 V/–10 V Efficiency vs. Output Current in Blanking Mode, VCC = 3 V 250 5.20 DEVICE 1 @ +85C DEVICE 1 @ +25C O 5.10 5.05 DEVICE 1 @ –40C 5.00 4.95 4.90 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC – V TPC 7. LDO Variation over Supply and Temperature REV. B 8 90 80 70 60 50 40 0 20 60 80 40 OUTPUT CURRENT – A ICC (SCAN) 150 VOUT 5V OUTPUT RIPPLE VCC RIPPLE ICC (BLANK) 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC – V TPC 8. Supply Current vs. Voltage –5– 100 TPC 6. +15 V/–10 V Efficiency vs. Output Current in Scanning Mode, VCC = 3 V 200 100 7 TPC 3. LDO O/P Voltage vs. Load Current in Scanning Mode, VCC = 3.3 V 300 5.30 5.15 80 60 8 SUPPLY CURRENT – A 78 90 LE +15V/–10V EFFICIENCY – % 84 82 0 10000 100 B SO LDO POWER EFFICIENCY – % 5.092 5.0734 100 85 5.0V O/P – V 5.094 TPC 2. LDO Output Voltage (Unloaded) vs. Blanking Mode Frequency 83 5.096 5.0738 5.0736 10 5.098 TE 10 5.100 5.0746 LDO O/P – V 60 5.0748 +15V/–10V EFFICIENCY – % LDO OUTPUT VOLTAGE – V LDO POWER EFFICIENCY – % Typical Performance Characteristics–ADM8830 TPC 9. Output Ripple on LDO (5 V Output) ADM8830 +15V OUTPUT LOAD DISABLE LOAD ENABLE 5V OUTPUT 5V OUTPUT –10V OUTPUT 5VOUT TPC 11. 5 V Output Transient Response, Load Disconnected 20.1 20.0 –10V OUTPUT 19.9 19.8 19.7 19.6 19.5 5VOUT LE DISSIPATED POWER – mW +15V OUTPUT TPC 12. +15 V and –10 V Outputs at Power-Up TE TPC 10. 5 V Output Transient Response for Maximum Load Current –20 60 40 0 20 TEMPERATURE – C 80 B SO 19.4 –40 TPC 14. Power Dissipation over Temperature, VCC = 3.6 V, Scanning Mode with All O/Ps at Maximum Load O TPC 13. +15 V and –10 V Outputs at Power-Down (Unloaded) –6– REV. B ADM8830 SCANNING AND BLANKING A TFT LCD panel is essentially made up of a bank of capacitors, each representing a pixel in the display. These capacitors store different levels of charge, depending on the amount of luminescence required for a given pixel. When a picture is being displayed on the panel, a scan of all the pixel capacitors is performed, placing different levels of charge on each in order to create the image. The process of updating the display like this is called “scanning.” Once scanned, an image will be held by pixel capacitance and the controller and source line drivers can be put into a low power mode. This low power mode is referred to as the blanking mode on the ADM8830. Over a finite period of time, this pixel charge will leak and the capacitors will have to be refreshed in order to maintain the image. VCC SHDN t R5V 90% 10% +5V t F5V t R15V t F15V +15V t DELAY –10V –3V 90% 10% t F10V LOAD The ADM8830 caters to the two modes of operation described above as follows. When the TFT LCD panel is in scanning mode, a logic high on the SCAN/BLANK input places the device in high current power mode, providing extra power (extra current) to the LCD controller and the source line drivers. If the panel continues to be updated (as when a moving picture is being displayed), then the ADM8830 can be continually operated in scanning mode. If the same image is kept on the panel, a logic low is applied to the SCAN/BLANK input and the ADM8830 enters blanking (low current) mode. Depending on how often the image is being updated, the ADM8830 can be operated with a variable SCAN/BLANK duty cycle. This helps to maximize power efficiency and therefore extends the battery life. t R10V TE SCAN/BLANK EXTERNAL CLOCK Figure 2. Power Sequence TRANSIENT RESPONSE LE The ADM8830 features extremely fast transient response, making it very suitable for fast image updates on TFT LCD panels. This means that even under changing load conditions there is still very effective regulation of the 5 V output. TPCs 10 and 11 show how the 5.1 V output responds when a maximum load is dynamically connected and disconnected. Note that the output settles within 5 µs to less than 1% of the output level. 90% B SO EXTERNAL CLOCK The ADM8830 has an internal 100 kHz oscillator, but an external clock source can also be used to clock the part. This clock source must be applied to the CLKIN pin. Power is saved during blanking periods by disabling the internal oscillator and switching to the lower frequency external clock source. To achieve optimum performance of the charge pump circuitry, it is important that the duty cycle of the external clock source be 50% and that the rise and fall times be less than 20 ns. 10% tR tF tH tT tR: RISE TIME tF: FALL TIME tH @ 100% = DUTY CYCLE tT Figure 1. Duty Cycle of External Clock 0.28 0.4 3.10 POWER SEQUENCING O The gate drive supplies must be sequenced such that the –10 V supply is up before the +15 V supply for the TFT panel to power up correctly. The ADM8830 controls this sequence. When the device is turned on (a logic high on SHDN), the ADM8830 allows the –10 V output to ramp immediately but holds off the +15 V output. It continues to do this until the negative output has reached –3 V. At this point, the positive output is enabled and allowed to ramp up to +15 V. This sequence is highlighted in Figure 2. 0.9 0.75 0.25 0.5 SOLDER MASK BOARD METALLIZATION 1.95 0.2 0.25 DIMENSIONS IN MILLIMETERS Figure 3. Suggested LFCSP 4 mm  4 mm 20-Lead Land Pattern REV. B –7– 2.10 ADM8830 OUTLINE DIMENSIONS 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 20 C02565–0–10/03(B) 6.60 6.50 6.40 11 4.50 4.40 4.30 1 6.40 BSC 10 0.65 BSC 0.15 0.05 0.30 COPLANARITY 0.19 0.10 1.20 MAX TE PIN 1 0.20 0.09 0.75 0.60 0.45 8 0 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153AC LE 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm  4 mm Body (CP-20-1) Dimensions shown in millimeters 4.0 BSC SQ 0.60 MAX 0.60 MAX B SO PIN 1 INDICATOR 1.00 0.85 0.80 0.50 BSC 0.20 REF 0.75 0.55 0.35 20 1 BOTTOM VIEW 11 10 0.05 MAX 0.02 NOM 6 2.25 2.10 SQ 1.95 5 0.25 MIN 0.30 0.23 0.18 COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 O Location 3.75 BSC SQ 0.80 MAX 0.65 TYP 12 MAX SEATING PLANE Revision History TOP VIEW 16 15 Page 10/03—Data Sheet changed from REV. A to REV. B. Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3/03—Data Sheet changed from REV. SpA to REV. A. Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to TPC 12 and TPC 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 11/02—Data Sheet changed from REV. 0 to REV. SpA. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to captions of TPCs 2, 3, and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to caption of TPC 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Added TPC 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 –8– REV. B