ADM8832ACPZ-REEL7

Charge Pump Regulator for Color TFT Panel ADM8832 Data Sheet FUNCTIONAL BLOCK DIAGRAM APPLICATIONS ADM8832 CLKIN SCAN/ BLANK LDO_ON/ OFF LDO VOLTAGE REGULATOR CONTROL LOGIC DOUBLE TRIPLE C1 2.2µF C1– VOUT C6 2.2µF +5VOUT +5VIN C2+ C2– C3+ C3– C2 1µF VOLTAGE SHUTDOWN DISCHARGE INVERTER CONTROL GND C4+ C4– +5.1V C7 2.2µF C3 1µF +15VOUT VOLTAGE TRIPLER B SO C1+ LDO IN TIMING GENERATOR SHDN GENERAL DESCRIPTION VOLTAGE DOUBLER OSCILLATOR LE Handheld instruments TFT LCD panels Cellular phones C5 2.2µF VCC C4 1µF –10VOUT +15.3V C8 1µF –10.2V C9 1µF 03759-A-001 3 output voltages (+5.1 V, +15.3 V, −10.2 V) from one 3 V input supply Power efficiency optimized for use with TFT in mobile phones Low quiescent current Low shutdown current ( 2.7 V Blanking Period VCC = 3 V, IL = 5 mA (Scanning) VCC = 3 V, IL = 200 µA (Blanking) 8 mA Load IL Stepped from 10 µA to 8 mA 14.4 15.3 50 1 50 15.6 100 10 V µA µA mV p-p IL = 1 µA to 100 µA Scanning Period Blanking Period IL = 100 µA −10.4 −100 −10 −10.2 −50 −1 50 90 80 100 −9.6 V µA µA mV p-p % % kHz IL = –1 µA to −100 µA Scanning Period Blanking Period IL = –100 µA Relative to 5.1 V Output, IL = 100 µA (Scanning) Relative to 5.1 V Output, IL = 10 µA (Blanking) Scanning Period V V µA pF SHDN Low = Shutdown Mode SHDN High = Normal Mode V V µA pF Low = BLANK Period High = SCAN Period V V µA pF Low = External LDO High = Internal LDO 60 140 0.3 VCC 0.7 VCC O Digital Input Current Digital Input Capacitance 1 SCAN/BLANK Input Voltage ±1 10 0.3 VCC 0.7 VCC Digital Input Current Digital Input Capacitance1 LDO_ON/OFF Input Voltage ±1 10 0.3 VCC 0.7 VCC Digital Input Current Digital Input Capacitance1 Test Conditions 5.1 4 5 50 80 70 10 5 B SO Output Ripple −10.2 V OUTPUT Output Voltage Output Current Max 3.6 400 140 1 5.0 Power Efficiency Output Ripple Transient Response +15.3 V OUTPUT Output Voltage Output Current Typ TE +5.1 V OUTPUT Output Voltage Output Current Min 2.6 LE Parameter INPUT VOLTAGE, VCC SUPPLY CURRENT, ICC ±1 10 Rev. B | Page 3 of 12 ADM8832 Data Sheet Parameter CLKIN Minimum Frequency Input Voltage VIL VIH Digital Input Current Digital Input Capacitance1 1 Min Typ 0.9 1 Max 0.3 VCC 0.7 VCC ±1 10 Unit Test Conditions kHz Duty Cycle = 50%, Rise/Fall Times = 20 ns V V µA pF Guaranteed by design. Not 100% production tested. TIMING SPECIFICATIONS Table 2. Typ Max 300 8 12 3 Unit Test Conditions/Comments µs ms ms ms 10% to 90%, Figure 17 10% to 90%, Figure 17 90% to 10%, Figure 17 Figure 17 ms ms ms 90% to 10%, Figure 17 90% to 10%, Figure 17 10% to 90%, Figure 17 LE Min 75 40 40 O B SO Parameter POWER-UP SEQUENCE +5 V Rise Time, tR5V +15 V Rise Time, tR15V −10 V Fall Time, tF10V Delay between −10 V Fall and +15 V, tDELAY POWER-DOWN SEQUENCE +5 V Fall Time, tF5V +15 V Fall Time, tF15V −10 V Rise Time, tR10V TE VCC = 2.6 V to 3.6 V, TA = –40°C to +85°C, unless otherwise noted; C1, C5, C6, C7 = 2.2 µF, C2, C3, C4, C8, C9 = 1 µF, CLKIN = 1 kHz in blanking mode. Rev. B | Page 4 of 12 Data Sheet ADM8832 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL CHARACTERISTICS Table 3. 20-Lead LFCSP: θJA = 31°C/W Ratings −0.3 V to +4.0 V −0.3 V to +4.0 V 10 sec ESD CAUTION −0.3 V to +6 V −12 V to +0.3 V −0.3 V to +17 V −40°C to +85°C 3.55 W −65°C to +150°C Class I O B SO LE Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. TE Parameter Supply Voltage Input Voltage to Digital Inputs Output Short Circuit Duration to GND Output Voltage +5.1 V Output −10.2 V Output +15.3 V Output Operating Temperature Range Power Dissipation (Derate 33 mW/°C above 25°C) Storage Temperature Range ESD Rev. B | Page 5 of 12 ADM8832 Data Sheet 20 19 18 17 16 C1+ C1– GND –10VOUT C4+ PIN CONFIGURATION AND FUNCTION DESCRIPTIONS LDO_ON/OFF 6 SHDN 7 SCAN/BLANK 8 CLKIN 9 +15VOUT 10 C4– C2+ C2– C3+ C3– TE ADM8832 TOP VIEW (Not to Scale) 15 14 13 12 11 03759-A-002 VCC 1 2 3 4 5 VOUT LDO_IN +5VOUT +5VIN Figure 2. Pin Configuration Table 4. Pin Function Descriptions 3 4 LDO_IN +5VOUT 5 6 +5VIN LDO_ON/OFF 7 SHDN 8 SCAN/BLANK 9 CLKIN 10 +15VOUT Function Positive Supply Voltage Input. Connect this pin to 3 V supply with a 2.2 µF decoupling capacitor. Voltage Doubler Output. This is derived by doubling the 3 V supply. A 2.2 µF capacitor to ground is required on this pin. Voltage Regulator Input. The user has the option to bypass this circuit using the LDO_ON/OFF pin. +5.1 V Output Pin. This is derived by doubling and regulating the +3 V supply. A 2.2 µF capacitor to ground is required on this pin to stabilize the regulator. +5.1 V Input Pin. This is the input to the voltage tripler and doubler inverter charge pump circuits. Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for regulation of the 5 V voltage doubler output. A logic low isolates the internal LDO from the rest of the charge pump circuits. This allows the use of an external LDO to regulate the 5 V voltage doubler output. The output of this LDO is then fed back into the voltage tripler and doubler/inverter circuits of the ADM8832. Digital Input. 3 V CMOS logic. Active low shutdown control. This pin shuts down the timing generator and enables the discharge circuit to dissipate the charge on the voltage outputs, thus driving them to 0 V. Drive Mode Input. 3 V CMOS logic. A logic high places the part in scan (high current) mode, and the charge pump is driven by the internal oscillator. A logic low places the part in blanking (low current) mode, and the charge pump is driven by the (slower) external oscillator. This is a power saving feature on the ADM8832. External CLOCK Input. During a blanking period, the oscillator circuit selects this pin to drive the charge pump circuit. This is at a lower frequency than the internal oscillator, resulting in lower quiescent current consumption, thus saving power. +15.3 V Output Pin. This is derived by tripling the +5.1 V regulated output. A 1 µF capacitor is required on this pin. External capacitor C3 is connected between these pins. A 1 µF capacitor is recommended. External capacitor C2 is connected between these pins. A 1 µF capacitor is recommended. External capacitor C4 is connected between these pins. A 1 µF capacitor is recommended. −10.2 V Output Pin. This is derived by doubling and inverting the +5.1 V regulated output. A 1 µF capacitor is required on this pin. Device Ground Pin. External capacitor C1 is connected between these pins. A 2.2 µF capacitor is recommended. LE Mnemonic VCC VOUT O B SO Pin No. 1 2 11, 12 13, 14 15, 16 17 C3−, C3+ C2−, C2+ C4−, C4+ −10VOUT 18 19, 20 GND C1−, C1+ Rev. B | Page 6 of 12 Data Sheet ADM8832 90 85 70 84 LDO POWER EFFICIENCY (%) 60 50 40 30 20 81 80 70 90 110 130 150 OUTPUT CURRENT (µA) 170 190 78 0 3 4 5 OUTPUT CURRENT (mA) 6 7 8 100 5.0750 90 5.0746 5.0744 5.0742 5.0740 5.0734 100 1000 BLANKING FREQUENCY (Hz) 10000 03759-A-004 5.0736 B SO 5.0738 80 70 60 2 Figure 4. LDO Output Voltage (Unloaded) vs. Blanking Mode Frequency 5.102 O 5.100 5.098 5.096 5.094 6 OUTPUT CURRENT (µA) 8 10 100 Figure 7. +15 V/−10 V Efficiency vs. Output Current in Blanking Mode, VCC = 3 V 100 90 +15/–10V EFFICIENCY (%) 5.104 4 03759-A-007 +15V/–10V EFFICIENCY (%) LE 5.0748 80 70 60 50 5.092 0 1 2 3 4 5 6 ILOAD (mA) 7 8 03759-A-005 LDO O/P (V) 2 Figure 6. LDO Efficiency in Scanning Mode with VCC = 3 V 5.0752 5.090 1 03759-A-006 50 TE 30 Figure 3. LDO Efficiency in Blanking Mode with VCC = 3 V LDO OUTPUT VOLTAGE (V) 82 79 03759-A-003 10 10 83 03759-A-008 LDO POWER EFFICIENCY (%) TYPICAL PERFORMANCE CHARACTERISTICS 40 0 20 40 60 OUTPUT CURRENT (µA) 80 Figure 8. +15 V/−10 V Efficiency vs. Output Current in Scanning Mode, VCC = 3 V Figure 5. LDO O/P Voltage vs. Load Current in Scanning Mode, VCC = 3.3 V Rev. B | Page 7 of 12 ADM8832 Data Sheet 5.30 TEK STOP: SINGLE SEQ 10.0MS/s [ T ] 5.25 5.20 DEVICE 1 @ +85°C 5.0V O/P (V) 5.15 LOAD ENABLE 2 T DEVICE 1 @ +25°C 5.10 T 5.05 DEVICE 1 @ –40°C 5V OUTPUT 1 5.00 2.8 2.9 3.0 3.1 3.2 VCC (V) 3.3 3.4 3.5 3.6 CH2 2.00V M5.00µs CH2 1.20V Figure 12. 5 V Output Transient Response for Max load Current Figure 9. LDO Variation over Supply and Temperature TEK STOP: SINGLE SEQ 10.0MS/s [ T 300 250 ] T LE LOAD DISABLE 2 200 ICC (SCAN) 150 5V OUTPUT 0 2.6 2.7 B SO ICC (BLANK) 50 2.8 2.9 3.0 3.1 3.2 VCC (V) 3.3 3.4 3.5 3.6 CH1 20.0mV Figure 10. Supply Current vs. Voltage TEK STOP: 2.50MS/s [ VOUT 23 ACQS T T 1 ] CH2 2.00V M5.00µs CH2 1.20V 03759-A-013 100 03759-A-010 Figure 13. 5 V Output Transient Response, Load Disconnected TEK STOP: SINGLE SEQ 5.00KS/s [ T ] +15V OUTPUT T O 2 5V OUTPUT RIPPLE 1 VCC RIPPLE T 2 T T T 3 –10V OUTPUT T CH2 100mV M20.0µs CH1 –2.8mV 1 03759-A-011 CH1 20.0mV CH3 50.0mV 5VOUT CH1 CH3 5.00V 5.00V CH2 5.00V M10.0ms CH2 1.3V Figure 14. +15 V and −10 V Outputs at Power-Up Figure 11. Output Ripple on LDO (5 V Output) Rev. B | Page 8 of 12 03759-A-014 SUPPLY CURRENT (µA) CH1 20.0mV 03759-A-012 2.7 TE 4.90 2.6 03759-A-009 4.95 Data Sheet 5 ACQS T +15V OUTPUT 20.1 ] 20.0 T 1 –10V OUTPUT T CH2 5.00V 19.6 M10.0ms CH1 0V –20 0 20 40 TEMPERATURE (°C) TE 5.00V 5.00V 19.7 19.4 –40 03759-A-015 5VOUT CH1 CH3 19.8 19.5 T 2 19.9 Figure 15. +15 V and −10 V Outputs at Power-Down (Unloaded) 60 90 03759-A-016 [ DISSIPATED POWER (mW) TEK STOP: 500S/s ADM8832 O B SO LE Figure 16. Power Dissipation over Temperature, VCC = 3.6 V, Scanning Mode with All O/Ps at Maximum Load Rev. B | Page 9 of 12 ADM8832 Data Sheet THEORY OF OPERATION SCANNING AND BLANKING TRANSIENT RESPONSE A TFT LCD panel is made up of a bank of capacitors, each representing a pixel in the display. These capacitors store different levels of charge, depending on the amount of luminescence required for a given pixel. When a picture is displayed on the panel, a scan of all the pixel capacitors is performed, placing different levels of charge on each in order to create the image. The process of updating the display like this is called scanning. Once scanned, an image is held by pixel capacitance, and the controller and source line drivers can be put into a low power mode. This low power mode is referred to as the blanking mode on the ADM8832. Over a finite period of time, this pixel charge will leak and the capacitors will need to be refreshed in order to maintain the image. The ADM8832 uses scanning and blanking modes, as follows. When the TFT LCD panel is in scanning mode, a logic high on the SCAN/BLANK input places the device in high current power mode, providing extra power (extra current) to the LCD controller and the source line drivers. If the panel continues to be updated (as when a moving picture is being displayed), the ADM8832 can be continually operated in scanning mode. If the same image is kept on the panel, a logic low is applied to the SCAN/BLANK input, and the ADM8832 enters blanking (low current) mode. Depending on how often the image is updated, the ADM8832 can be operated with a variable SCAN/ BLANK duty cycle. This helps to maximize power efficiency and, therefore, extends the battery life. The ADM8832 features extremely fast transient response, making it very suitable for fast image updates on TFT LCD panels. This means that even under changing load conditions there is still very effective regulation of the 5 V output. Figure 12 and Figure 13 show how the 5.1 V output responds when a maximum load is dynamically connected and disconnected. Note that the output settles within 5 μs to less than 1% of the output level. EXTERNAL CLOCK 10% tF tR: RISE TIME tF: FALL TIME tH @ 100% = DUTY CYCLE tT tH tT POWER SEQUENCING 0.400 0.050 1.950 VCC 2.100 0.280 0.750 0.100 Figure 18. Duty Cycle of External Clock 0.500 O The gate drive supplies must be sequenced such that the −10 V supply is up before the +15 V supply for the TFT panel to power on correctly. The ADM8832 controls this sequence. When the device is turned on (a logic high on SHDN), the ADM8832 allows the −10 V output to ramp immediately, but holds off the +15 V output. It continues to do this until the negative output reaches −3 V. At this point, the positive output is enabled and allowed to ramp up to +15 V. This sequence is shown in Figure 17. 03759-A-017 tR 90% 0.900 B SO LE TE The ADM8832 has an internal 100 kHz oscillator, but an external clock source can also be used to clock the part. This clock source must be applied to the CLKIN pin. Power is saved during blanking periods by disabling the internal oscillator and by switching to the lower frequency external clock source. To achieve optimum performance of the charge pump circuitry, it is important that the duty cycle of the external clock source is 50% and that the rise and fall times are less than 20 ns. SHDN tR5V 90% 10% +5V tF5V tR15V 0.875 tR15V 90% 10% –3V 0.200 0.250 SOLDER MASK BOARD METALLIZATION –10V tR10V tF10V Figure 19. Suggested LFCSP 4 mm × 4mm 20 Lead Land Pattern LOAD 03759-A-018 SCAN/BLANK EXTERNAL CLOCK Figure 17. Power Sequence Rev. B | Page 10 of 12 03759-A-019 tF15V +15V Data Sheet ADM8832 OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 DETAIL A (JEDEC 95) 0.30 0.25 0.18 0.50 BSC PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 20 16 15 1 EXPOSED PAD 5 2.30 2.10 SQ 2.00 11 TOP VIEW 6 BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 0.203 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1 02-13-2017-B TE 0.80 0.75 0.70 PKG-003763 0.65 0.60 0.55 10 ORDERING GUIDE Package Description 20-Lead Frame Chip Scale Package [LFCSP] 20-Lead Frame Chip Scale Package [LFCSP] 20-Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. O 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C B SO Model 1 ADM8832ACPZ ADM8832ACPZ-REEL ADM8832ACPZ-REEL7 ADM8832-EVALZ LE Figure 20. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-20-6) Dimensions shown in millimeters Rev. B | Page 11 of 12 Package Option CP-20-6 CP-20-6 CP-20-6 ADM8832 Data Sheet O B SO LE TE NOTES ©2003–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03759-0-8/17(B) Rev. B | Page 12 of 12