ADMC200AP

a FEATURES Analog Input Block 11-Bit Resolution Analog-to-Digital (A/D) Converter 4 Single-Ended Simultaneously Sampled Analog Inputs 3.2 s Conversion Time/Channel 0 V–5 V Analog Input Range Internal 2.5 V Reference PWM Synchronized Sampling Capability 12-Bit PWM Timer Block Three-Phase Center-Based PWM 1.5 kHz–25 kHz PWM Switching Frequency Range Programmable Deadtime Programmable Pulse Deletion PWM Synchronized Output External PWM Shutdown Vector Transformation Block 12-Bit Vector Transformations Forward and Reverse Clarke Transformations Forward and Reverse Park Rotations 2.9 s Transformation Time DSP & Microcontroller Interface 12-Bit Memory Mapped Registers Twos Complement Data Format 6.25 MHz to 25 MHz Operating Clock Range 68-Lead PLCC Package Single 5 V DC Power Supply Industrial Temperature Range GENERAL DESCRIPTION RESET WR A0–3 RD CS IRQ CLK REFOUT REFIN CONVST U V W AUX PWMSYNC A AP B BP C CP STOP Motion Coprocessor ADMC200 FUNCTIONAL BLOCK DIAGRAM DATABUS CONTROL BUS EMBEDDED CONTROL SEQUENCER CONTROL REGISTERS INTERNAL REFERENCE 11-BIT A/D CONVERTER VECTOR TRANSFORMATION BLOCK 12-BIT PWM TIMER BLOCK D0 – D11 Flexible Analog Channel Sequencing The ADMC200 is a motion coprocessor that can be used with either microcontrollers or digital signal processors (DSP). It provides the functionality that is required to implement a digital control system. In a typical application, the DSP or microcontroller performs the control algorithms (position, speed, torque and flux loops) and the ADMC200 provides the necessary motor control functions: analog current data acquisition, vector transformation, and PWM drive signals. PRODUCT HIGHLIGHTS Simultaneous Sampling of Four Inputs The ADMC200 support acquisition of 2, 3, or 4 channels per group. Converted channel results are stored in registers and the data can be read in any order. The sampling and conversion time for two channels is 8 µs, three channels is 11.2 µs, and four channels is 14.4 µs (using a 12.5 MHz system clock). Embedded Control Sequencer The embedded control sequencer off-loads the DSP or microprocessor, reducing the instructions required to read analog input channels, control PWM timers and perform vector transformations. This frees the host processor for performing control algorithms. Fast DSP/Microprocessor Interface A four channel sample and hold amplifier allows three-phase motor currents to be sampled simultaneously, reducing errors from phase coherency. Sample and hold acquisition time is 1.6 µs and conversion time per channel is 3.2 µs (using a 12.5 MHz system clock). The high speed digital interface allows direct connection to 16-bit digital signal processors and microprocessors. The ADMC200 has 12 bit memory mapped registers with twos complement data format and can be mapped directly into the data memory map of a DSP. This allows for a single instruction read and write interface. Integration The ADMC200 integrates a four channel simultaneous sampling analog-to-digital converter, analog reference, vector transformation, and three-phase PWM timers into a 68-lead PLCC. Integration reduces cost, board space, power consumption, and design and test time. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 + = = 0 REFIN = 2.5 V; ADMC200–SPECIFICATIONS (V =MHz;5 VT = 5–%; AGND+85DGNDnlessV;otherwise noted) External Clock = 12.5 40 C to Cu DD A Parameter ANALOG-TO-DIGITAL CONVERTER Resolution Relative Accuracy Differential Nonlinearity Bias Offset Error Bias Offset Match Full-Scale Error Full-Scale Error Match Conversion Time/Channel Signal-to-Noise Ratio (SNR)2 Channel-to-Channel Isolation Two-/Three-Phase Mode Three-/Three-Phase Mode ANALOG INPUTS Input Voltage Level Analog Input Current Input Capacitance TRACK AND HOLD Aperture Delay Aperture Time Delay Match SHA Acquisition Time Droop Rate REFERENCE INPUT Voltage Level Reference Input Current REFERENCE OUTPUT Voltage Level Voltage Level Tolerance Drive Capability LOGIC VIL VIH VOL VOH Input Leakage Current Three-State Leakage Current Input Capacitance PWM TIMERS Resolution Programmable Deadtime Range Programmable Deadtime Increments Programmable Pulse Deletion Range Programmable Deletion Increments Minimum PWM Frequency 1 ADMC200AP Units 11 ±2 ±2 ±5 4 ±6 4 40 60 –58 –55 0–5 100 10 200 20 20 5 2.5 50 2.5 ±5 ± 200 0.8 2.0 0.4 4.5 1 1 20 12 0–10.08 2 0–10.16 1 1.5 Bits LSB max LSB max LSB max LSB max LSB max LSB max System CLK Cycles dB min dB max dB max Volts µA max pF typ ns max ns max System CLK Cycles mV/ms max V dc µA max Volts % max µA max V max V min V max V min µA max µA max pF typ Bits µs System CLK Cycles µs System CLK Cycle kHz Conditions/Comments Twos Complement Data Format Integral Nonlinearity Any Channel Between Channels Any Channel Between Channels fIN = 600 Hz Sine Wave, fSAMPLE = 55 kHz, 600 Hz Sine Wave Applied to Unselected Channels Any Channel Between Channels Full Load ISINK = 400 µA, VDD = 5 V ISOURCE = 20 µA, VDD = 5 V 160 ns 80 ns Resolution Varies with PWM Switching Frequency (10 MHz Clock: 20 kHz = 9 Bits, 10 kHz = 10 Bits, 5 kHz = 11 Bits, 2.5 kHz = 12 Bits). Higher Frequencies are Available with Lower Resolution Park & Clarke Transformation VECTOR TRANSFORMATION Radius Error Angular Error Reverse Transformation Time Forward Transformation Time EXTERNAL CLOCK INPUT Range INTERNAL SYSTEM CLOCK Range POWER SUPPLY CURRENT IDD NOTES 1 Measurements made with external reference. 2 Tested with PWM Switching Frequency of 25 kHz. Specifications subject to change without notice. 0.7 30 37 40 6.25–25 % max arc min max System CLK Cycles System CLK Cycles MHz If > 12.5 MHz, Then It Is Necessary to Divide Down via SYSCTRL Register 6.25–12.5 20 MHz mA max –2– REV. B ADMC200 Table I. Timing Specifications (VDD = 5 V Number Symbol Timing Requirements 5%; TA = – 40 C to +85 C) Min Max Units 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 9 tperclk tpwhclk tpwlclk tsucsb_wrb tsuaddr_wrb tsudata_wrb thdwrb_data thdwrb_addr thdwrb_csb tpwlwrb1 tpwhwrb1 thdwrb_clk_h1 tsuwrb_clk_h1 tsuwrb_clk_l1 thdclk_wrb_l1 tsucsb_rdb tsuaddr_rdb thdrdb_addr thdrdb_csb tpwlrdb tpwhrdb tsurdb_clk_h thdrdb_clk_h tpwlresetb CLK Period CLK Pulsewidth, High CLK Pulsewidth, Low CS Low before Falling Edge of WR ADDR Valid before Falling Edge of WR DATA Valid before Rising Edge of WR DATA Hold after Rising Edge of WR ADDR Hold after Rising Edge of WR CS Hold after Rising Edge of WR WR Pulsewidth, Low WR Pulsewidth, High WR Low after Rising Edge of CLK WR High before Rising Edge of CLK WR High before Falling Edge of CLK WR High after Falling Edge of CLK CS Low before Falling Edge of RD ADDR Valid before Falling Edge of RD ADDR Hold after Rising Edge of RD CS Hold after Rising Edge of RD RD Pulsewidth, Low RD Pulsewidth, High RD Low before Rising Edge of CLK RD Low after Rising Edge of CLK RESET Pulsewidth, Low 40 20 20 0 0 13 4.5 4.5 4.5 20 20 7 7 10 10 0 0 0 0 20 20 7.5 7.5 2 × tperclk 160 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTE 1 All WRITES to the ADMC200 must occur within 1 system clock cycle (0 wait states). Number Symbol Switching Characteristics Min Max Units 25 26 tdlyrdb_data thdrdb_data DATA Valid after Falling Edge of RD DATA Hold after Rising Edge of RD 23 0 ns ns 1 2 CLK 3 CLK 12 CS 8 15 13 9 Figure 1. Clock Input Timing A0–A3 11 WR 10 14 CLK 24 RESET DATA 4 6 7 NOTE: ALL WRITES TO THE ADMC200 MUST OCCUR WITHIN ONE SYSTEM CLOCK CYCLE (i.e. 0 WAIT STATES) 5 Figure 2. Reset Input Timing Figure 3. Write Cycle Timing Diagram REV. B –3– ADMC200 CLK 23 CS 22 A0–A3 20 RD 26 DATA 25 16 17 18 19 21 Figure 4. Read Cycle Timing Diagram ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE Part Number Temperature Range Package Description Package Option Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD Analog Reference Input Voltage . . . . . . . . . . . . –0.3 V to VDD Digital Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD Analog Reference Output Swing . . . . . . . . . . . . –0.3 V to VDD Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +280°C *Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ADMC200AP –40°C to +85°C 68-Lead PLCC P-68A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMC200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –4– REV. B ADMC200 PIN DESIGNATIONS Pin 1 2 3 4–9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34–36 37 38 39 40 Mnemonic D9 D10 D11 NC VDD A3 A2 A1 A0 NC RESET CONVST IRQ VDD DGND CLK WR RD CS NC VDD AGND AGND U V W SGND REFIN NC AUX REFOUT VDD DGND Type BIDIR BIDIR BIDIR SUP I/P I/P I/P I/P I/P I/P O/P SUP GND I/P I/P I/P I/P SUP GND GND I/P I/P I/P GND I/P I/P O/P SUP GND Description Data Bit 9 Data Bit 10 Data Bit 11, MSB No Connect +5 V Digital Power Supply Address Bit 3, MSB Address Bit 2 Address Bit 1 Address Bit 0, LSB No Connect Chip Reset A/D Conversion Start Interrupt Request (Pull-Up Required) +5 V Digital Power Supply Digital Ground External Clock Input Write Select Output Enable/Read Chip Select No Connect +5 V Analog Power Supply Analog Ground Analog Ground Analog Input U Analog Input V Analog Input W Analog Signal Ground Analog Reference Input No Connect Auxiliary Analog Input Internal 2.5 V Analog Reference +5 V Digital Power Supply Digital Ground Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Mnemonic DGND DGND DGND VDD NC DGND STOP PWMSYNC CP C BP NC B AP A DGND DGND DGND VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 Type GND GND GND SUP GND I/P O/P O/P O/P O/P Description Digital Ground Digital Ground Digital Ground +5 V Digital Power Supply No Connect Digital Ground PWM Timer Output Disable PWM Synchronization Output PWM Timer Output C Prime PWM Timer Output C PWM Timer Output B Prime No Connect PWM Timer Output B PWM Timer Output A Prime PWM Timer Output A Digital Ground Digital Ground Digital Ground +5 V Digital Power Supply Data Bit 0, LSB Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 8 O/P O/P O/P GND GND GND SUP BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR Pin Types Pin Types PIN CONFIGURATION NC D11 NC NC NC NC NC D10 D5 D9 D7 D6 D4 D2 D8 D3 D1 I/P = Input Pin O/P = Output Pin GND = Ground Pin BIDIR = Bidirectional Pin SUP = Supply Pin 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 PIN 1 IDENTIFIER 60 D0 59 V DD 58 DGND 57 DGND 56 DGND 55 A 54 AP VDD 10 A3 11 A2 12 A1 13 A0 14 NC 15 RESET 16 CONVST 17 IRQ 18 VDD 19 DGND 20 CLK 21 WR 22 RD 23 CS 24 NC 25 VDD 26 ADMC200 TOP VIEW (Not to Scale) 53 B 52 NC 51 BP 50 C 49 CP 48 PWMSYNC 47 STOP 46 DGND 45 NC 44 VDD 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 REFIN U NC AGND AGND DGND DGND SGND AUX DGND NC NC = NO CONNECT REV. B REFOUT VDD DGND NC V W –5– ADMC200 ANALOG INPUT BLOCK The ADMC200 contains an 11-bit resolution, successive approximation analog-to-digital (A/D) converter with twos complement output data format. The analog input range is ± 2.5 V (0 V–5 V) with a 2.5 V offset as defined by REFIN. The on-chip 2.5 V ± 5% reference is utilized by connecting the REFOUT pin to the REFIN pin. The A/D conversion time is determined by the system clock frequency, which can range from 6.25 MHz to 12.5 MHz. The Sample and Hold (SHA) acquisition time is 20 system clock cycles and is independent of the number of channels sampled and/or digitized. The input stage to the A/D converter is a four channel SHA which allows the four channels to be held simultaneously and then sequentially digitized. Forty system clock cycles are required to complete each A/D conversion. The analog channel sampling is flexible and is programmable through the SYSCTRL register. The minimum number of channels per conversion is two. The throughput time of the analog acquisition block can be calculated as follows: t AA = t SHA + ( n × tCONV ) registers respectively. The twos complement data is left justified and the LSB is set to zero. The relationship between input voltage and output coding is shown in Figure 5. OUTPUT CODE FULL-SCALE TRANSITION 01 1 1 1 1 1 1 1 1 1 0 FS = 5V 000000000000 LSB = 5V 2048 100000000000 0V 5V–1LSB 2.5 INPUT VOLTAGE Figure 5. Transfer Function Sample and Hold where tAA = analog acquisition time, n = # channels, tSHA = SHA acquisition time (20 × system clock period), tCONV = conversion time (40 × system clock period) per channel. A/D Conversions are initiated via the CONVST pin. A synchronizing pulse (PWMSYNC) is provided at the beginning of each PWM cycle. This pulse can be used to synchronize the A/D conversion process to the PWM switching frequency. Operating the A/D Converter After powering up the ADMC200, bring the RESET pin low for a minimum of two clock cycles in order to enable A/D conversions. Before initiating the first conversion (CONVST) after a reset, the SHA time of 20 system clock cycles must occur. A conversion is initiated by bringing CONVST high for a minimum of one system clock cycle. The SHA goes into hold mode at the falling edge of clock. Following completion of the A/D conversion process, a minimum of 20 system clock cycles are required before initiating another conversion in order to allow the sample and hold circuitry to reacquire the input signals. If a CONVST is initiated before the 20 clock cycles have elapsed, the embedded control sequencer will delay conversion until this requirement is met. PWM TIMER BLOCK OVERVIEW The A/D converter can be set up to convert a sequence of channels as defined in the SYSCTRL register (see Table V). Always write 0 to both Bits 0 and 1 of the SYSCTRL register. The default channel select mode after RESET is to convert channels V and W only. This is two-/three-phase mode. Three-/three-phase mode converts channels U, V, W and/or AUX. Three-/threephase mode is achieved by writing a 1 to Bit 3 of the SYSCTRL register. After the conversion process is complete, the channels can be read in any order. There are two methods that can be used to indicate when the A/D conversions are completed and the data is ready: interrupt driven and software timing. Interrupt Driven Method The PWM timers have 12-bit resolution and support programmable pulse deletion and deadtime. The ADMC200 generates three center-based signals A, B, and C based upon user-supplied duty cycles values. The three signals are then complemented and adjusted for programmable deadtime to produce the six outputs. The ADMC200 PWM master switching frequency can range from 2.5 kHz to 20 kHz, when using a 10 MHz system clock. The master frequency selection is set as a fraction of the PWMTM register. If the system clock is 10 MHz, then the minimum edge resolution available is 100 ns. The output format of the PWM block is active LO. There is an external input to the PWM timers (STOP) that will disable all six outputs within one system clock when the input is HIGH. The ADMC200 has a PWM Synchronization output (PWMSYNC) which brings out the master switching frequency from the PWM timers. The width of the PWMSYNC pulse is equal to one system clock cycle. For example, if the system clock is 10 MHz, the PWMSYNC width would be equal to 100 ns. PWM Master Switching Period Selection Interrupts can be used to indicate the end of conversion for a group of channels. Before beginning any A/D conversions, Bit 7 of the SYSCTRL register must be set to 1 to enable A/D conversion interrupts. Then, when an A/D conversion is complete, an interrupt will be generated. After an interrupt is detected Bit 0 of the SYSSTAT register must be checked to determine if the A/D converter was the source. Reading the SYSSTAT register automatically clears the interrupt flag bits. Software Timing Method An alternative method is to use the DSP or microcontroller to keep track of the amount of time elapsed between CONVST and the expected completion time (n × tCONV). Reading Results The 11-bit A/D conversion results for channels U, V, W and AUX are stored in the ADCU, ADCV, ADCW and ADCAUX The switching time is set by the PWMTM register which should be loaded with a value equal to the system clock frequency divided by the desired master switching frequency. For example, if the desired switching frequency is 8 kHz and the system clock frequency is 10 MHz, then the PWMTM register should be loaded with 1250 (10 MHz/8 kHz). The PWMCHA, PWMCHB, and PWMCHC registers are loaded with the –6– REV. B ADMC200 desired on-time and their values would be calculated as a ratio of the PWMTM register value. Note: Desired Pulse Density = (PWMCHx register)/( PWMTM register). The beginning of each PWM cycle is marked by the PWMSYNC signal. New values of PWMCHA, PWMCHB and PWMCHC must all be loaded into their respective registers at least four system clock cycles before the beginning of a new PWM cycle. All three registers must be updated for any of them to take effect. New PWM on/off times are calculated during these four clock cycles and therefore the PWMCHA, PWMCHB and PWMCHC registers must be loaded before this time. If this timing requirement is not met, then the PWM outputs may be invalid during the next PWM cycle. PWM Example full off (0%) and its prime to full on (100%). This is valid for A, AP, B, BP, C and CP. This feature would be used in an environment where the inverter’s power transistors have a minimum switching time. If the user-specified duty cycle would result in a pulse duration shorter than the minimum switching time of the transistors, then pulse deletion should be used to prevent this occurrence. With a 10 MHz system clock, the 0– 127 range of values in PWMPD yield a range of deadtime values from 0 µs to 12.7 µs in 100 ns steps. External PWM Shutdown The following example uses a system clock speed of 10 MHz. The desired PWM master switching frequency is 8 kHz and the desired on-time for the timers A, B and C are 25%, 50% and 10% respectively. The values for the PWMCHA, PWMCHB, and PWMCHC registers must be calculated as ratios of the PWMTM register (1250 in this example). To achieve these duty cycles, load the PWMCHA register with 313 (1250 × 0.25), PWMCHB with 625 (1250 × 0.5) and PWMCHC with 125 (1250 × 0.1). Programmable Deadtime There is an external input pin (STOP) to the PWM timers that will disable all six outputs when it goes HIGH. When the STOP pin goes HIGH, the PWM timer outputs will all go HIGH within one system clock cycle. When the STOP pin goes LOW, the PWM timer outputs are re-enabled within one system clock cycle. If external PWM shutdown isn’t required, tie the STOP pin LOW. VECTOR TRANSFORMATION BLOCK OVERVIEW With perfectly complemented PWM drive signals and nonideal switching characteristics of the power devices, both transistors in a particular leg might be switched on at the same time, resulting in either a power supply trip, inverter trip or device destruction. In order to prevent this, a delay must be introduced between the complemented signal edges. For example, the rising edge of AP occurs before the falling edge of A, and the falling edge of the complemented A occurs after the rising edge of A. This capability is known as programmable deadtime. The ADMC200 programmable deadtime value is loaded into the 7-bit PWMDT register, in which the LSB is set to zero internally, which means the deadtime value is always divisible by two. With a 10 MHz system clock, the 0–126 range of values in PWMDT yield a range of deadtime values from 0 µs to 12.6 µs in 200 ns steps. Figure 6 shows PWM timer A with a programmable deadtime of PWMDT. PWMTM The Vector Transformation Block performs both Park and Clarke coordinate transformations to control a three-phase motor (Permanent Magnet Synchronous Motor or Induction Motor) via independent control of the decoupled rotor torque and flux currents. The Park and Clarke transformations combine to convert three-phase stator current signals into two orthogonal rotor referenced current signals Id and Iq. Id represents the flux or magnetic field current and Iq represents the torque generating current. The Id and Iq current signals are used by the processor’s motor torque control algorithm to calculate the required direct Vd and quadrature Vq voltage components for the motor. The forward Park and Clarke transformations are used to convert the Vd and Vq voltage signals in the rotor reference frame to three phase voltage signals (U, V, W) in the stator reference frame. These are then scaled by the processor and written to the ADMC200’s PWM registers in order to drive the inverter. The figures below illustrate the Clarke and Park Transformations respectively. Iw 120° 120° 120° Iy Iu Iv Ix PWMCHA - PWMDT A Three-Phase Stator Currents Equivalent Two-Phase Currents Figure 7. Reverse Clarke Transformation AP PWMCHA + PWMDT Iy ρ Iq Figure 6. Programmable Deadtime Example Pulse Deletion 90° The pulse deletion feature prevents a pulse from being generated when the user-specified duty cycle results in a pulse duration shorter than the user-specified deletion value. The pulse deletion value is loaded into the 7-bit register PWMPD. When the user-specified on-time for a channel would result in a calculated pulsewidth less than the value specified in the PWMPD register, then the PWM outputs for that channel would be set to REV. B –7– ROTOR REFERENCE FRAME AXIS Ix Id Rotating Reference Frame Stationary Reference Frame Figure 8. Reverse Park Transformation ADMC200 Vq ρ Vy In order to perform a reverse transformation, first write to the PHIP2 and PHIP3 registers, and to the PHIP1 register if not in 2/3 mode. Then initiate the transformation by writing the reverse rotation angle to the RHO register. The reverse rotation will be completed in 37 system clock cycles after the rotation is initiated. If Bit 6 of the system control register is set, then an interrupt will be generated on completion. When an interrupt occurs, the user must check Bit 1 of the SYSSTAT register to determine if the vector transformation block was the source of the interrupt. During the vector transformation, the vector transformation registers must not be written to or the vector rotation results will be invalid. Reverse Clarke Transformation U 90° Vd Vx Stationary Reference Frame Rotating Reference Frame Figure 9. Forward Park Transformation Vy W 120° 120° 120° V Vx The first operation is the Clarke transformation in which the three phase motor current signals (Iu, Iv, Iw) are converted to sine and cosine orthogonal signals (Ix and Iy). These signals represent the equivalent currents in a two-phase ac machine and is the signal format required for the Park rotation. The threephase input signals are of the form: PHIP1 Iu = Is cosθ PHIP2 Iv = Is cos (θ + 120) PHIP3 Iw = Is cos (θ + 240) and the Park rotation requires inputs in the form Is cos θ and Is sin θ, therefore we need to generate Is sin θ. This is calculated from: IY Is sin θ = 1 (Is cos (θ + 240) – Is cos (θ +120)) 3 Equivalent Two-Phase Voltage Three-Phase Stator Voltage Figure 10. Forward Clarke Transformation Operating/Using the Vector Transformation Block After powering up the ADMC200, RESET must be driven low for a minimum of two clock cycles to enable vector transformations. The vector transformation block can perform either a forward or reverse transformation. Reverse Transformation is defined by the following operations: (a) Clarke: 3-phase current signals to 2-phase current signals followed by (b) Park: 2-phase current signals cross multiplied by sin ρ, cos ρ which effectively measures the current components with respect to the rotor (stationary) where ρ is the electrical angle of the rotor field with respect to the stator windings. Forward transformation is defined by the following operations: (a) Park: 2-phase voltage signals cross multiplied by sin ρ, cos ρ followed by (b) Clarke: 2-phase to 3-phase voltage signal conversion. In order to provide maximum flexibility in the target system, the ADMC200 operates in an asynchronous manner. This means that the functional blocks (analog input, reverse transformation, forward transformation and PWM timers) operate independently of each other. The reverse and forward vector transformation operations cannot occur simultaneously. All vector transformation registers, except for RHO/RHOP, are twos complement. RHO/RHOP are unsigned ratios of 360°. For example, 45° would be 45/360 × 212. Performing a Reverse Transformation After the reverse transform, registers Ix and Iy contain the 2phase input current information. In the case where 2 of 3-phase information (PHIP2/3 only) is provided, then PHIP1 will be derived from the simple fact that all sum to zero. This value is then placed in the IX register. IX = Ix = Is cos θ = – Is cos (θ + 120) – Is cos (θ + 240) Reverse Park Rotation IX/IY are then processed together with the digital angle ρ (RHO) by a Park rotation. If the input signals are Ix and Iy, then the rotation can be described by: ID IQ Id = Ix × cos ρ + Iy × sin ρ Iq = –Iy × sin ρ + Iy × cos ρ where ID and IQ are the outputs of the Park rotation. Cos ρ and sin ρ are required for the Park rotation, and are calculated internally. Substituting for Ix and Iy in the above yields: ID IQ Id = Is cos θ × cos ρ + Is sin θ × sin ρ = Is cos (θ – ρ) Iq = Is sin θ × cos ρ – Is cos θ × sin ρ = Is sin (θ – ρ) Performing a Forward Transformation A reverse transformation is initiated by writing to the reverse rotation angle register RHO and operates on the values in the PHIP1, PHIP2 and PHIP3 registers. When the reverse transformation is in 2/3 mode, PHIP1 is calculated from PHIP2 and PHIP3. This is used in systems where only two phase currents are measured. The reverse transformation 2/3 mode is set by clearing Bit 10 in the SYSCTRL register and is the default mode after RESET. –8– In order to perform a forward rotation, write values to the VD and VQ registers and then initiate the transformation by writing the rotation angle to the register RHOP. The forward transformation will only operate correctly when Bit 10 in the SYSCTRL register is set (i.e., in 3/3 mode). The forward rotation will be completed in 40 system clock cycles after the rotation is initiated. If Bit 6 of the system control register is set, then an interrupt will be generated on REV. B ADMC200 completion. When an interrupt occurs, the user must check Bit 1 of the system status register, SYSSTAT, to determine if the vector transformation block was the source of the interrupt. During the vector transformation, the transformation registers must not be written to or the vector rotation results will be invalid. Forward Park Rotation If the input signals are represented by Vd and Vq, then the transformation can be described by: VX Vx = Vd × cos ρ – Vq × sin ρ VY Vy = Vd × sin ρ + Vq × cos ρ where Vx and Vy are the outputs of the Park Rotation, and are the inputs to the reverse Clarke transformation. Forward Clarke Transformation (2 to 3 Phase) mode, when an enable interrupt occurs, the IRQ pin will be driven low, and will remain low until the SYSSTAT register is read. The combination of level mode and the open-drain driver allows multiple interrupt sources in an application to drive a single interrupt input line on the host DSP or microprocessor. Edge mode or level mode is determined with Bit 8 of the SYSCTRL register. Edge mode (0) is the default; a 1 in this bit will put the IRQ pin into level mode. The recommended method of using the interrupt generation capability is to set edge or level mode, enable the appropriate interrupts, and then monitor the IRQ line. After the IRQ pin goes low, the SYSSTAT register of the ADMC200 should be read, (1) to determine if it was this chip that caused the interrupt, if other lines are wired together with this IRQ pin, and (2) if it was this chip, to determine if it was generated by the Analog Input Block or the Vector Transformation Block. Once this is done, the appropriate interrupt handling routine may be executed. APPLICATION NOTE LIST The second operation to be applied to the above results, is the Forward Clarke Transformation where 2 phase (stator) voltage signals are converted to 3 phase (stator) voltage signals. For the inverse Clarke transform we require three phase outputs of the form below: PHV1 PHV2 PHV3 V cos α V cos (α + 120) V cos (α + 240) We have two quadrature voltages (V cosα and V sinα) available. PHV2 PHV3 V cos (α + 120) = – V cos (α + 240) = – 1 × V cos α – 3 × V sin α 2 2 1 × V cos α + 3 × V sin α 2 2 1. AN-407 AC Motor Control Experiments Using the ADMC200 Evaluation Board 2. AN-408 AC Motor Control Using the ADMC200 Motion Coprocessor 3. AN-409 Advanced Motor Control Techniques Using the ADMC200 Motion Coprocessor POWER SUPPLY CONNECTIONS AND SETUP INTERRUPT GENERATION There are two interrupt sources on the ADMC200 that may be independently enabled to generate interrupts. The first interrupt source is the Analog Input Block, which, if enabled, generates an interrupt at the end of conversion. The second interrupt source is the Vector Transformation Block, which, if enabled, generates an interrupt at the end of a Vector Transformation. When a 1 is stored in Bit 7 of the SYSCTRL register, ADC interrupts are enabled. When a 1 is stored in Bit 6 of the SYSCTRL register, Vector Transformation interrupts are enabled. Upon a reset of the chip, both bits are set to the default condition, 0, thus disabling all interrupts. When an enabled interrupt occurs, Bit 11 of the SYSSTAT register becomes a 1. If that interrupt had been an ADC interrupt, Bit 0 of SYSSTAT register would also be set to 1. If that interrupt had been a Vector Transformation interrupt, Bit 1 of SYSSTAT would be set to 1. Whenever the SYSSTAT register is read, these three bits go back to their default state, 0, immediately after their values are loaded onto the data bus. Upon a reset, these three bits also go to their default state, 0. The IRQ pin has an open-drain driver, which will drive it low at the appropriate times, but the user must supply an external pull-up resistor to bring the node back high when it is not being pulled low. The IRQ pin operates in one of two modes, edge mode or level mode. In edge mode, when an enabled interrupt occurs, the IRQ pin will be driven low for one system clock period. In level REV. B –9– The nominal positive power supply level (VDD) is +5 V ± 5%. The positive power supply VDD should be connected to all ADMC200 VDD pins (10, 19, 26, 39, 44, 59). The SGND pin (32) and both AGND pins (27, 28) should be star point connected at a point close to the AGND pins of the ADMC200. The DGND pins (20, 40, 41, 42, 43, 46, 56, 57, 58) should also be connected to AGND pins close to the ADMC200. Power supplies should be decoupled at the power pins using a 0.1 µF capacitor. A 220 nF capacitor must also be connected as close as possible between REFIN (Pin 33) and SGND (Pin 32). In addition, the IRQ requires a 15 K pull-up to the VDD supply. DSP/CONTROLLER INTERFACE The ADMC200 has a 12 bit bidirectional parallel port for interfacing with Analog Devices’ ADSP-2100 DSP family or microcontrollers/microprocessors. The ADMC200 coprocessor is designed to be conveniently interfaced to ADI’s family of fixed-point DSPs. Figures 11 and 12 show the interfacing between the ADMC200 and the ADSP2101/2105/2115, ADSP-2171, ADSP-2181, TMS320C2x DSPs. In the case of the TMS320C2x, some glue logic is required to decode the RD/WR lines and invert the CLKOUT1 signal. The ADSP-2101/2105/2115 CLKOUT frequency equals the crystal/clock frequency of its CLKIN. This signal (CLKOUT) can be used to directly drive the CLK line (Pin 21) on the ADMC200. The ADMC200 coprocessor can be operated with a clock frequency between the range of 6.25 MHz and 25 MHz. If the clock frequencies are greater than 12.5 MHz, then it is necessary to internally divide down the external clock to derive the ADMC200’s system clock (via SYSCTRL register). ADMC200 ADDRESS BUS VDD A0–A13 ADDRESS DECODE EN CS IRQ RD WR CLK D0–D11* A0–A3 ADSP-2101/ DMS ADSP-2105/ ADSP-2115–20MHz IRQ2 ADSP-2171–10MHz RD ADSP-2181–10MHz D0–D23 WR In the case of the ADSP-2171/2181, the system clock is internally scaled; a 10 MHz system clock will derive a 20 MHz CLKOUT. In the case of the TMS320C2x, the CLKOUT1 signal is derived from the system clock divided by a factor of 4; consequently a 50 MHz TMS320C25-50 will derive a 12.5 MHz CLKOUT1 for use by the ADMC200. Note: A pull-up resistor is required on the IRQ (Pin 18) output from the ADMC200. The STOP (Pin 47) must be tied low if not in use. SYSTEM CLOCK FREQUENCY ADMC200 CLKOUT DATA BUS *NOTE: BY MAPPING THE ADMC200 DATA BUS TO THE TWELVE HIGHEST BITS OF THE ADSP DATA BUS, FULL-SCALE OUTPUTS FROM THE ADC CAN BE REPRESENTED BY ± 1.0 IN FIXED POINT ARITHMETIC. Figure 11. ADI Digital Signal Processor/Microcomputer ADDRESS BUS VDD A0–A15 IS ADDRESS DECODE EN CS IRQ RD WR CLK D0–D11 DATA BUS A0–A3 The nominal range of the input clock for the ADMC200 is 6.25 MHz to 25 MHz. The external CLK frequency can be internally divided down by 2 by writing to Bit 5 of the SYSCTRL register. If the external CLK is faster than 12.5 MHz then it is necessary to internally divide it down. REGISTER ADDRESSING Four address lines (A0 through A3) are used in conjunction with the control lines (CS, WR, RD,) to select registers 0 through 15. The CS and RD control lines are active low. The registers are given symbolic names. Table II. Pin Function TMS320C20 INTn TMS320C25 STRB TMS320C25-50 R/W CLKOUT1 D0–D15 ADMC200 CS RD WR Figure 12. TI Second-Generation Devices TMS320C20/ C25/C25–50 Table III. Write Registers Name A3 A2 A1 A0 Enables the ADMC200 register interface (connect via chip select logic-active low) Places data from the internal register onto the data bus Loads the internal register with data on the data bus on its positive edge Register Function RHO PHIP1/VD PHIP2/VQ PHIP3 RHOP PWMTM PWMCHA PWMCHB PWMCHC PWMDT PWMPD SYSCTRL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Load RHO (ρ) and Start Reverse Transform Reverse Rotation Direct Input/Forward Direct Input Reverse Rotation Direct Input/Forward Direct Input Reverse Rotation Direct Input Load RHOP(ρ) and Start Forward Transform PWM Master Switching Period PWM Channel A On-Time PWM Channel B On-Time PWM Channel C On-Time PWM Programmable Deadtime (7-Bit Register) PWM Pulse Deletion Value (7-Bit Register) Reserved Reserved System Control Reserved Reserved –10– REV. B ADMC200 Table IV. Read Registers Name A3 A2 A1 A0 Register Function ID/PHV1/VX IQ/PHV2 IX/PHV3 IY/VY ADCV ADCW ADCAUX ADCU SYSCTRL SYSSTAT 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reverse Rotation Result (IDS)/Forward Result Cos +0° Reverse Rotation Result (IQS)/Forward Cos +120° Reverse Clarke Cos + 0°/Forward Result Cos +240° Reverse Clarke Cos +90°/Forward Cos +90° Reserved A/D Conversion Result Channel V A/D Conversion Result Channel W A/D Conversion Result Auxiliary Channel A/D Conversion Result Channel U Reserved Reserved Reserved Reserved System Control System Status Reserved Table V. System Control (SYSCTRL) Registers Bit Function RESET Default DESCRIPTION OF THE REGISTERS All unspecified register locations are reserved. SYSCTRL System Control Register (See Table V and VI) SYSSTAT System Status Register (See Table VII) ADCU These registers contain the results from the first ADCV three analog input channels U, V, and W. The ADCW output data format is twos complement and therefore Bit 0 is always zero as the A/D converter has 11-bit resolution. ADCAUX This register contains the conversion result of the auxiliary channel. PWMTM PWM Master Switching Period PWMCHA PWM Channel A on-time PWMCHB PWM Channel B on-time PWMCHC PWM Channel C on-time PWMDT PWM Programmable Deadtime Value PWMPD PWM Programmable Pulse Deletion Value ID/IQ These are the results of the reverse rotation (torque and flux components). PHV1/2/3 These are the results from the forward Clarke Transformation. PHIP1/2/3 The inputs for reverse vector transformation (Clarke and Park). IX/IY These registers contain the results of the Clarke transformation that are the inputs to the reverse Park rotation. VX, VY VX , VY contain the results of the forward Park rotation. RHOP RHOP is the angle used during the forward vector transformation. Writing to the RHOP register causes the forward rotation to start based on values in RHOP, VD and VQ registers. RHO RHO is the angle used during the reverse vector transformation. Writing to this register starts the reverse rotation using the values in the RHO, PHIP1/2/3 registers. RHO and RHOP are unsigned ratios of 360°. For example, 45 degrees would be 45/360 × 212. REV. B 0 1 3 4 5 6 7 8 10 Reserved, Must Be 0 Reserved, Must Be 0 Enables U Channel Conversion (1 = Enable) Three/Three-Phase Mode Enables AUX Channel Conversion (0 = Disable, 1 = Enable) Divide External Clock by 2 (0 = No, 1 = Yes) Park Interrupt Enable ADC Interrupt Enable (0 = Disable, 1 = Enable) IRQ Pin Format (Edge or Level Based Interrupt Requests) (0 = Edge) Reverse Rotation (0 = 2/3, 1 = 3/3) Forward Rotation (1 = Enable) 0 0 0 0 0 0 0 0 0 Bit 0, 1 Reserved for future use. Always write 0 to these bits. Bit 3 Channel U Conversion Enable. If Bit 3 is set to 1, then Channel U will be converted along with V, W and/or AUX. This bit selects three-/three-phase mode. Aux Channel Conversion Enable. If Bit 4 is set to 1, then the AUX input will be converted along with the channels V, W and/or U. If Bit 5 = 1, then the external clock will be divided by two to derive the system clock. If the external clock frequency is greater than 12.5 MHz, then this bit must be set. Park Interrupt Enable. This bit allows interrupts to be generated when the Park rotation is completed. ADC Interrupt Enable. This bit allows interrupts to be generated via the IRQ pin when the analog-todigital conversion process is complete. Bit 4 Bit 5 Bit 6 Bit 7 –11– ADMC200 Bit 8 IRQ Pin Format—Edge or Level Interrupt Selection. If Bit 8 is set to 0, then an interrupt will cause a pulse of one system clock to be generated on the IRQ pin. If Bit 8 is set to 1, then an interrupt causes the IRQ output to go LOW (logic 0). The IRQ output pin will remain LOW until the SYSSTAT register is read. If Bit 10 is set to 1, then the reverse Park transformation will be formed in 3/3 mode. For Forward transformations, this bit must be set to 1. Table VII. System Status Register (SYSSTAT) 1 RESET Default Bit Function 0 1 Table VI. SYSCTRL Analog Input Channel Selection 0 X2 0 4 Bit 3 Bit 4 Channels Converted Mode 0 0 1 1 0 1 0 1 V, W (Default) V, W, AUX U, V, W U, V, W, AUX Two/Three Phase Two/Three Phase Three/Three Phase Three/Three Phase 11 NOTES 1 Reading this register clears the interrupt status flags Bits 0, 1 and 11. 2 Undefined until the first Vector Transformation has started Bit 0 Bit 1 Bit 4 Bit 11 A/D Conversion Completion Interrupt. This register is set to 1 when the A/D conversion process has completed and ADC interrupts have been enabled in the SYSCTRL register. Interrupt Status. This register is set to 1 when the Vector Transformation is completed and the Vector Transformation completion interrupts have been enabled. This bit is set to 1 when the rotation results are valid. If any interrupt source on the ADMC200 occurs, then this bit is set to 1. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Plastic Leaded Chip Carrier (PLCC) (P-68A) 0.995 (25.27) SQ 0.985 (25.02) 9 10 PIN 1 IDENTIFIER 61 60 0.175 (4.45) 0.169 (4.29) 0.050 (1.27) TYP 0.925 (23.50) 0.895 (22.73) PIN 1 IDENTIFIER TOP VIEW (PINS DOWN) BOTTOM VIEW (PINS UP) 0.019 (0.48) 0.017 (0.43) 0.029 (0.74) 0.027 (0.69) 26 27 44 43 0.954 (24.23) SQ 0.950 (24.13) 0.104 (2.64) TYP –12– REV. B PRINTED IN U.S.A. C2071a–1.5–4/00 (rev. B) Bit 10 A/D Conversion Completion Interrupt (1 = True) Vector Transformation Completion Interrupt (1 = True) Rotation Results are Valid (1 = Valid) IRQ Generated from This Device (1 = True) 0