ADN2530YCPZ-REEL7

11.3 Gbps, Active Back-Termination, Differential VCSEL Driver ADN2530 FEATURES Up to 11.3 Gbps operation −40°C to +100°C operation Very low power: ISUPPLY = 65 mA Typical 26 ps rise/fall times Full back-termination of output transmission lines Crosspoint adjust function PECL-/CML-compatible data inputs Bias current range: 2 mA to 25 mA Differential modulation current range: 2.2 mA to 23 mA Automatic laser shutdown (ALS) 3.3 V operation Compact 3 mm × 3 mm LFCSP Voltage-input control for bias and modulation currents XFP-compliant bias current monitor GENERAL DESCRIPTION The ADN2530 laser diode driver is designed for direct modulation of packaged VCSELs with a differential resistance ranging from 35 Ω to 140 Ω. The active back-termination technique provides excellent matching with the output transmission lines while reducing the power dissipation in the output stage. The back-termination in the ADN2530 absorbs signal reflections from the TOSA end of the output transmission lines, enabling excellent optical eye quality to be achieved even when the TOSA end of the output transmission lines is significantly misterminated. The small package provides the optimum solution for compact modules where laser diodes are packaged in low pin count optical subassemblies. The modulation and bias currents are programmable via the MSET and BSET control pins. By driving these pins with control voltages, the user has the flexibility to implement various average power and extinction ratio control schemes, including closed-loop control and look-up tables. The eye crosspoint in the output eye diagram is adjustable via the crosspoint adjust (CPA) control voltage input. The automatic laser shutdown (ALS) feature allows the user to turn on/off the bias and modulation currents by driving the ALS pin with the proper logic levels. The product is available in a space-saving 3 mm × 3 mm LFCSP specified from −40°C to +100°C. APPLICATIONS 10 Gb Ethernet optical transceivers 10G-BASE-LRM optical transceivers 8× and 10× Fibre Channel optical transceivers XFP/X2/XENPAK/MSA 300 optical modules SONET OC-192/SDH STM-64 optical transceivers FUNCTIONAL BLOCK DIAGRAM VCC VCC VCC CPA ALS ADN2530 IMODP 100Ω IMOD IMODN VCC 50Ω 50Ω GND DATAP DATAN CROSS POINT ADJUST IBMON IBIAS 800Ω 800Ω 200Ω 200Ω 200Ω 10Ω 05457-001 MSET GND BSET Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADN2530 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Package Thermal Specifications ................................................. 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 Input Stage................................................................................... 10 Bias Current ................................................................................ 10 Automatic Laser Shutdown (ALS) ........................................... 11 Modulation Current................................................................... 11 Load Mistermination ................................................................. 13 Crosspoint Adjust....................................................................... 13 Power Consumption .................................................................. 13 Applications Information .............................................................. 15 Typical Application Circuit....................................................... 15 Layout Guidelines....................................................................... 15 Design Example.......................................................................... 16 Headroom Calculations ........................................................ 16 BSET and MSET Pin Voltage Calculation .......................... 16 IBIAS Monitor Accuracy Calculations................................ 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18 REVISION HISTORY 8/06—Rev. 0 to Rev. A Changes to Figure 1.......................................................................... 1 Changes to Table 3............................................................................ 5 Changes to Figure 24...................................................................... 10 Changes to Figure 30...................................................................... 11 Changes to Modulation Current Section .................................... 12 Changes to Typical Application Circuit Section......................... 15 10/05—Revision 0: Initial Version Rev. A | Page 2 of 20 ADN2530 SPECIFICATIONS VCC = VCCMIN to VCCMAX, TA = −40°C to +100°C, 100 Ω differential load impedance, crosspoint adjust disabled, unless otherwise noted. Typical values are specified at 25°C and IMOD = 10 mA with crosspoint adjust disabled, unless otherwise noted. Table 1. Parameter BIAS CURRENT (IBIAS) Bias Current Range Bias Current While ALS Asserted Compliance Voltage 1 MODULATION CURRENT (IMODP, IMODN) Modulation Current Range Modulation Current While ALS Asserted Crosspoint Adjust (CPA) Range 2 Rise Time (20% to 80%)2, 3 , 4 Fall Time (20% to 80%)2, 3, 4 Random Jitter2, 3, 4 Deterministic Jitter2, 4, 5 Deterministic Jitter 2, 4, 6 Differential |S22| Compliance Voltage1 DATA INPUTS (DATAP, DATAN) Input Data Rate Differential Input Swing Differential |S11| Input Termination Resistance BIAS CONTROL INPUT (BSET) BSET Voltage to IBIAS Gain BSET Input Resistance MODULATION CONTROL INPUT (MSET) MSET Voltage to IMOD Gain MSET Input Resistance BIAS MONITOR (IBMON) IBMON to IBIAS Ratio Accuracy of IBIAS to IBMON Ratio VCC − 0.7 Min 2 0.55 0.55 2.2 2.2 35 26 26.4 26 26.5 0.55 V, which satisfies the requirement The maximum voltage at the IBIAS pin must be less than the maximum IBIAS compliance specification as described by where K is the MSET voltage to IMOD ratio. The value of K depends on the actual resistance of the TOSA and can be obtained from Figure 34. For a TOSA resistance of 60 Ω, the typical value of K = 24 mA/V. Assuming that IMOD = 10 mA and using the preceding equation, the MSET voltage is given by VCOMPLIANCE_MAX = VCC − 0.75 − 22 × IBIAS (A) For this example, VMSET = IMOD (mA) 24 mA/V = VCOMPLIANCE_MAX = VCC – 0.75 − 22 × 0.01 = 2.33 V VIBIAS = 1.5 V < 2.33 V, which satisfies the requirement To calculate the headroom at the modulation current pins (IMODP and IMODN), the voltage has a dc component equal to VCC due to the ac-coupled configuration and a swing equal to IMOD × 50 Ω, as RTOSA < 100 Ω. For proper operation of the ADN2530, the voltage at each modulation output pin should be within the normal operation region shown in Figure 35. 10 = 0.42 V 24 The MSET voltage range can be calculated using the required IMOD range and the minimum and maximum K values. These can be obtained from the minimum and maximum curves in Figure 34. Rev. A | Page 16 of 20 ADN2530 IBIAS Monitor Accuracy Calculations 6 ACCURACY OF IBIAS TO IBMON RATIO (%) Referring to Figure 40, the IBMON output current accuracy is ±4.3% for the minimum IBIAS of 4 mA and ±3.0% for the maximum IBIAS value of 14 mA. The accuracy of the IBMON output current as a percentage of the nominal IBIAS is given by IBMON _ Accuracy MIN = 4 mA 4.3 100 × = ± 2.15% 100 8 mA 5 4 3 2 for the minimum IBIAS value, and by 05457-041 1 IBMON _ Accuracy MAX = 14 mA 3.0 100 × = ± 5.25% 100 8 mA 0 0 5 10 15 20 25 IBIAS (mA) Figure 40. Accuracy of IBIAS to IBMON Ratio This example assumes that the nominal value of IBIAS is 8 mA and that the IBIAS range for all operating conditions is 4 mA to 14 mA. The accuracy of the IBIAS to IBMON ratio is given in the Table 1 and is plotted in Figure 40. for the maximum IBIAS value. This gives a worse-case accuracy for the IBMON output current of ±5.25% of the nominal IBIAS value over all operating conditions. The IBMON output current accuracy numbers can be combined with the accuracy numbers for the 750 Ω IBMON resistor (RIBMON) and any other error sources to calculate an overall accuracy for the IBMON voltage. Rev. A | Page 17 of 20 ADN2530 OUTLINE DIMENSIONS 3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12° MAX 0.90 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 1.50 REF 0.60 MAX 0.50 0.40 0.30 PIN 1 INDICATOR *1.65 1.50 SQ 1.35 13 12 16 EXPOSED PAD 1 9 (BOTTOM VIEW) 4 8 5 0.25 MIN *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model ADN2530YCPZ-WP 1 ADN2530YCPZ-R21 ADN2530YCPZ-REEL71 1 Temperature Range −40°C to +100°C −40°C to +100°C −40°C to +100°C Package Description 16-Lead LFCSP_VQ, 50-Piece Waffle Pack 16-Lead LFCSP_VQ, 250-Piece Reel 16-Lead LFCSP_VQ, 1500-Piece Reel Package Option CP-16-3 CP-16-3 CP-16-3 Branding F08 F08 F08 Z = Pb-free part. Rev. A | Page 18 of 20 ADN2530 NOTES Rev. A | Page 19 of 20 ADN2530 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05457–0–8/06(A) Rev. A | Page 20 of 20