ADN2531ACPZ-R2

11.3 Gbps, Active Back-Termination, Differential Laser Diode Driver ADN2531 FEATURES 3.3 V operation Up to 11.3 Gbps operation Typical 26 ps rise/fall times Bias current range: 10 mA to 100 mA Differential modulation current range: 10 mA to 80 mA Voltage input control for bias and modulation currents Data inputs sensitivity: 150 mV p-p differential Automatic laser shutdown (ALS) Crosspoint adjustment (CPA) VCSEL, FP, DFB laser support SFF/SFP/XFP/SFP+ MSA compliant Optical evaluation board available Compact, 3 mm × 3 mm LFCSP GENERAL DESCRIPTION The ADN2531 laser diode driver can work with directly modulated laser diodes, including vertical-cavity surface-emitting laser (VCSEL), Fabry-Perot (FP) lasers, and distributed feedback (DFB) lasers, with a differential loading resistance ranging from 5 Ω to 140 Ω. The active back-termination in the ADN2531 absorbs signal reflections from the laser diode side of the output transmission lines, enabling excellent optical eye quality even when the TOSA end of the output transmission lines is significantly mismatched. The ADN2531 is a SFP+ MSA-compliant device, and its small package and enhanced ESD protection provides the optimum solution for compact modules in which laser diodes are packaged in low pin-count optical subassemblies. The modulation and bias currents are programmable via the MSET and BSET control pins. By driving these pins with control voltages, the user has the flexibility to implement various average optical power and extinction ratio control schemes, including a closed-loop or a look-up table control. The automatic laser shutdown (ALS) feature allows turning the bias on and off while simultaneously modulating currents by driving the ALS pin with a low voltage transistor-to-transistor logic (LVTTL) source. The product is available in a space-saving, 3 mm × 3 mm LFCSP package and operates from −40°C to +100°C. APPLICATIONS Optical transmitters, up to 11.3 Gbps, for SONET/SDH, Ethernet, and Fibre Channel applications SFF/SFP/SFP+/XFP/X2/XENPAK/XPAK MSA compliant 300-pin optical modules, up to 11.3 Gbps FUNCTIONAL BLOCK DIAGRAM VCC VCC VCC CPA ALS ADN2531 IMODP 100Ω IMOD IMODN VCC 50Ω 50Ω GND DATAP DATAN CROSSPOINT ADJUST IBMON IBIAS 400Ω 800Ω 200Ω 200Ω 200Ω 10Ω 07881-001 MSET GND BSET Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADN2531 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Package Thermal Specifications ................................................. 4  Absolute Maximum Ratings............................................................ 5  ESD Caution .................................................................................. 5  Pin Configuration and Function Descriptions ............................. 6  Typical Performance Characteristics ............................................. 7  Test Circuit ...................................................................................... 10  Theory of Operation ...................................................................... 11  Input Stage ................................................................................... 11  Bias Current ................................................................................ 11  Automatic Laser Shutdown (ALS) ........................................... 12  Modulation Current ................................................................... 12  Load Mistermination ................................................................. 14  Crosspoint Adjust ....................................................................... 14  Power Consumption .................................................................. 14  Applications Information .............................................................. 15  Typical Application Circuit ....................................................... 15  Layout Guidelines....................................................................... 16  Design Example .......................................................................... 16  Outline Dimensions ....................................................................... 18  Ordering Guide .......................................................................... 18  REVISION HISTORY 9/09—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADN2531 SPECIFICATIONS VCC = VCCMIN to VCCMAX, TA = −40°C to +100°C, 12 Ω differential load impedance, crosspoint adjust disabled, unless otherwise noted. Typical values are specified at 25°C and IBIAS = IMOD = 40 mA with crosspoint adjust disabled, unless otherwise noted. Table 1. Parameter BIAS CURRENT (IBIAS) Bias Current Range Bias Current While ALS Asserted Compliance Voltage 1 MODULATION CURRENT (IMODP, IMODN) Modulation Current IMOD Range IMOD While ALS Asserted Crosspoint Adjust (CPA) Range 2 Rise Time (20% to 80%)2, 3, 4 Fall Time (20% to 80%)2, 3, 4 Random Jitter2, 3, 4 Deterministic Jitter2, 4, 5 Deterministic Jitter 2, 4, 6 Differential |S22| Compliance Voltage1 DATA INPUTS (DATAP, DATAN) Input Data Rate Differential Input Swing Differential |S11| Input Termination Resistance BIAS CONTROL INPUT (BSET) BSET Voltage to IBIAS Gain BSET Input Resistance MODULATION CONTROL INPUT (MSET) MSET Voltage to IMOD Gain MSET Input Resistance BIAS MONITOR (IBMON) IBMON to IBIAS Ratio Accuracy of IBIAS to IBMON Ratio VCC − 1.1 Min 10 0.6 0.55 10 70 35 26 26 0.6 V, which satisfies the requirement The maximum voltage at the IBIAS pin must be less than the maximum IBIAS compliance specification as described by VCOMPLIANCE_MAX = VCC − 0.75 − 4.4 × IBIAS (A) For this example, VCOMPLIANCE_MAX = VCC − 0.75 − 4.4 × 0.04 = 2.374 V Therefore, VIBIAS = 1.32 V < 2.374 V, which satisfies the requirement. To calculate the headroom at the modulation current pins (IMODP and IMODN), the voltage has a dc component equal to VCC due to the ac-coupled configuration and a swing equal to IMOD × 50 Ω because RTOSA is less than 100 Ω. For proper operation of the ADN2531, the voltage at each modulation output pin should be within the normal operation region shown in Figure 36. Assuming the dc voltage drop across L1, L2, L3, and L4 is 0 V and IMOD is 40 mA, the minimum voltage at the modulation output pins is equal to VCC − (IMOD × 12)/2 = VCC − 0.24 V Therefore, VCC − 0.24 > VCC − 1.1 V, which satisfies the requirement. The maximum voltage at the modulation output pins is equal to VCC + (IMOD × 12)/2 = VCC + 0.24 V DESIGN EXAMPLE Assuming that the impedance of the TOSA is 12 Ω, the forward voltage of the laser at low current is VF = 1.5 V, IBIAS = 40 mA, IMOD = 40 mA, and VCC = 3.3 V, this design example calculates • • • Therefore, VCC + 0.24 < VCC + 1.1 V, which satisfies the requirement. Headroom calculations must be repeated for the minimum and maximum values of the required IBIAS and IMOD ranges to ensure proper device operation over all operating conditions. The headroom for the IBIAS, IMODP, and IMODN pins. The typical voltage required at the BSET and MSET pins to produce the desired bias and modulation currents. The IBIAS monitor accuracy over the IBIAS current range. BSET and MSET Pin Voltage Calculations To set the desired bias and modulation currents, the BSET and MSET pins of the ADN2531 must be driven with the appropriate dc voltage. The voltage range required at the BSET pin to generate the required IBIAS range can be calculated using the BSET voltage to IBIAS gain specified in Table 1. Assuming that IBIAS = 40 mA and that IBIAS/VBSET = 100 mA/V (which is the typical IBIAS/VBSET ratio), the BSET voltage is given by VBSET = I BIAS (mA) 100 mA/V = 40 = 0.4 V 100 Headroom Calculations To ensure proper device operation, the voltages on the IBIAS, IMODP, and IMODN pins must meet the compliance voltage specifications in Table 1. Considering the typical application circuit shown in Figure 40, the voltage at the IBIAS pin can be written as VIBIAS = VCC − VF − (IBIAS × RTOSA) − VLA where: VCC is the supply voltage. VF is the forward voltage across the laser at low current. RTOSA is the resistance of the TOSA. VLA is the dc voltage drop across L5, L6, L7, and L8. For proper operation, the minimum voltage at the IBIAS pin should be greater than 0.6 V, as specified by the minimum IBIAS compliance specification in Table 1. Assuming that the voltage drop across the 50 Ω transmission lines is negligible and that VLA = 0 V, VF = 1.5 V, and IBIAS = 40 mA, VIBIAS = 3.3 − 1.5 − (0.04 × 12) = 1.32 V The BSET voltage range can be calculated using the required IBIAS range and the minimum and maximum BSET voltage to IBIAS gain values specified in Table 1. The voltage required at the MSET pin to produce the desired modulation current can be calculated using V MSET = I MOD K where K is the MSET voltage to IMOD ratio. Rev. 0 | Page 16 of 20 ADN2531 The value of K depends on the actual resistance of the TOSA and can be obtained from Figure 35. For a TOSA resistance of 12 Ω, the typical value of K is 110 mA/V. Assuming that IMOD = 40 mA and using the preceding equation, the MSET voltage is given by V MSET 40 = = = 0.36 V 110 mA/V 110 I MOD (mA) This example assumes that the nominal value of IBIAS is 40 mA and that the IBIAS range for all operating conditions is 10 mA to 80 mA. The accuracy of the IBIAS to IBMON ratio is given in Table 1 and is plotted in Figure 41. Referring to Figure 41, the IBMON output current accuracy is ±4.3% for the minimum IBIAS of 10 mA and ±3.0% for the maximum IBIAS value of 80 mA. The accuracy of the IBMON output current as a percentage of the nominal IBIAS is given by The MSET voltage range can be calculated using the required IMOD range and the minimum and maximum K values. These values can be obtained from the minimum and maximum curves in Figure 35. IBMON _ Accuracy MIN = 10 mA for the minimum IBIAS value, and by 4.3 100 × = ± 1.075% 100 40 mA IBIAS Monitor Accuracy Calculations 6 ACCURACY OF IBIAS TO IBMON RATIO (%) IBMON _ Accuracy MAX = 80 mA 5 3.0 100 × = ± 6.0% 100 40 mA 4 3 2 for the maximum IBIAS value. This gives a worse-case accuracy for the IBMON output current of ±6.0% of the nominal IBIAS value over all operating conditions. The IBMON output current accuracy numbers can be combined with the accuracy numbers for the 750 Ω IBMON resistor (RIBMON) and any other error sources to calculate an overall accuracy for the IBMON voltage. 1 0 20 40 IBIAS (mA) 60 80 100 Figure 41. Accuracy of IBIAS to IBMON Ratio 07881-040 0 Rev. 0 | Page 17 of 20 ADN2531 OUTLINE DIMENSIONS 3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12° MAX 0.90 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 071708-A 0.60 MAX BOTTOM VIEW 0.50 0.40 0.30 PIN 1 INDICATOR *1.65 1.50 SQ 1.35 13 12 16 1 EXPOSED PAD 9 8 4 5 0.25 MIN 1.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 42. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model ADN2531ACPZ-WP 1 ADN2531ACPZ-R21 ADN2531ACPZ-R71 EVAL-ADN2531-NTZ1 EVAL-ADN2531-NPZ1 1 Temperature Range −40°C to +100°C −40°C to +100°C −40°C to +100°C Package Description 16-Lead LFCSP_VQ, 50-Piece Waffle Pack 16-Lead LFCSP_VQ, 250-Piece Reel 16-Lead LFCSP_VQ, 1,500-Piece Reel Optical Evaluation Board Without Laser Populated Optical Evaluation Board with Laser Populated Package Option CP-16-3 CP-16-3 CP-16-3 Branding F0K F0K F0K Z = RoHS Compliant Part. Rev. 0 | Page 18 of 20 ADN2531 NOTES Rev. 0 | Page 19 of 20 ADN2531 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07881-0-9/09(0) Rev. 0 | Page 20 of 20