ADN2805ACPZ

1.25 Gbps Clock and Data Recovery IC ADN2805 Data Sheet FEATURES GENERAL DESCRIPTION Locks to 1.25 Gbps NRZ serial data input Patented clock recovery architecture No reference clock required Loss-of-lock indicator I2C interface to access optional features Single-supply operation: 3.3 V Low power: 390 mW typical 5 mm × 5 mm 32-lead LFCSP, Pb free The ADN2805 provides the receiver functions of quantization and clock and data recovery for 1.25 Gbps. The ADN2805 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are specified for −40°C to +85°C ambient temperature, unless otherwise noted. The ADN2805 is available in a compact 5 mm × 5 mm 32-lead LFCSP. APPLICATIONS GbE line card FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN (OPTIONAL) LOL CF1 CF2 FREQUENCY DETECT LOOP FILTER PHASE DETECT LOOP FILTER VCC VEE PIN NIN BUFFER PHASE SHIFTER VCO VREF DATA RE-TIMING DATAOUTP/ DATAOUTN CLKOUTP/ CLKOUTN ADN2805 07121-001 2 2 Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved. ADN2805 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Theory of Operation ...................................................................... 10  Applications....................................................................................... 1  Functional Description.................................................................. 12  General Description ......................................................................... 1  Frequency Acquisition............................................................... 12  Functional Block Diagram .............................................................. 1  Input Buffer................................................................................. 12  Revision History ............................................................................... 2  Lock Detector Operation .......................................................... 12  Specifications..................................................................................... 3  SQUELCH Mode........................................................................ 13  Jitter Specifications....................................................................... 3  System Reset................................................................................ 13  Output and Timing Specifications ............................................. 4  I2C Interface ................................................................................ 13  Absolute Maximum Ratings............................................................ 6  Applications Information .............................................................. 14  Thermal Characteristics .............................................................. 6  PCB Design Guidelines ............................................................. 14  ESD Caution.................................................................................. 6  Outline Dimensions ....................................................................... 16  Pin Configuration and Function Descriptions............................. 7  Ordering Guide .......................................................................... 16  I C Interface Timing and Internal Register Description............. 8  2 REVISION HISTORY 3/12—Rev. A to Rev. B Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 5/10—Rev. 0 to Rev. A Changes to Figure 5 and Table 6..................................................... 7 Changes to Figure 14...................................................................... 14 Added Exposed Pad Notation to Outline Dimensions ............. 16 1/08—Revision 0: Initial Version Rev. B | Page 2 of 16 Data Sheet ADN2805 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 1. Parameter QUANTIZER—DC CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Input Common-Mode Level QUANTIZER—AC CHARACTERISTICS Data Rate S11 Input Resistance Input Capacitance LOSS-OF-LOCK (LOL) DETECT VCO Frequency Error for LOL Assert VCO Frequency Error for LOL Deassert LOL Response Time ACQUISITION TIME Lock-to-Data Mode Optional Lock to REFCLK Mode DATA RATE READBACK ACCURACY Fine Readback POWER SUPPLY Power Supply Voltage Power Supply Current OPERATING TEMPERATURE RANGE Conditions Min @ PIN or NIN, dc-coupled PIN − NIN DC-coupled 1.8 0.2 2.3 Typ Max Unit 2.5 2.8 2.0 2.8 V V V 1250 @ 2.5 GHz Differential −15 100 0.65 Mbps dB Ω pF With respect to nominal With respect to nominal 1000 250 200 ppm ppm μs GbE 1.5 20.0 ms ms In addition to REFCLK accuracy 3.0 3.3 118 Locked to 1.25 Gbps −40 100 ppm 3.6 131 +85 V mA °C JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 2. Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Peaking Jitter Generation Jitter Tolerance Conditions GbE, IEEE 802.3, 637 kHz Rev. B | Page 3 of 16 Min 0.749 Typ Max Unit 0 0.001 0.02 0.03 0.003 0.04 dB UI rms UI p-p UI p-p ADN2805 Data Sheet OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter LVDS OUTPUT CHARACTERISTICS CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN Differential Output Swing Output Offset Voltage Output Impedance LVDS Outputs Timing Rise Time Fall Time Setup Time Hold Time 2 I C® INTERFACE DC CHARACTERISTICS Input High Voltage Input Low Voltage Input Current Output Low Voltage I2C INTERFACE TIMING SCK Clock Frequency SCK Pulse Width High SCK Pulse Width Low Start Condition Hold Time Start Condition Setup Time Data Setup Time Data Hold Time SCK/SDA Rise/Fall Time Stop Condition Setup Time Bus Free Time Between a Stop and a Start REFCLK CHARACTERISTICS Input Voltage Range Input Low Voltage Input High Voltage Minimum Differential Input Drive Reference Frequency Required Accuracy LVTTL DC INPUT CHARACTERISTICS Input High Voltage Input Low Voltage Input High Current Input Low Current LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage Output Low Voltage 1 Conditions Min Typ Max Unit VOD (see Figure 3) VOS (see Figure 3) Differential 240 1125 300 1200 100 400 1275 mV mV Ω 115 115 400 400 220 220 440 440 ps ps ps ps 0.3 VCC +10.0 0.4 V V μA V 20% to 80% 80% to 20% TS (see Figure 2), GbE TH (see Figure 2), GbE LVCMOS VIH VIL VIN = 0.1 VCC or VIN = 0.9 VCC VOL, IOL = 3.0 mA See Figure 10 360 360 0.7 VCC −10.0 400 tHIGH tLOW tHD;STA tSU;STA tSU;DAT tHD;DAT tR/tF tSU;STO tBUF Optional lock-to-REFCLK mode @ REFCLKP or REFCLKN VIL VIH 600 1300 600 600 100 300 20 + 0.1 Cb 1 600 1300 300 0 VCC 100 10 160 100 VIH VIL IIH, VIN = 2.4 V IIL, VIN = 0.4 V 2.0 VOH, IOH = −2.0 mA VOL, IOL = 2.0 mA 2.4 0.8 5 −5 Cb = total capacitance of one bus line in pF. If mixed with high speed mode devices, faster fall times are allowed. Rev. B | Page 4 of 16 0.4 kHz ns ns ns ns ns ns ns ns ns V V mV p-p MHz ppm V V μA μA V V Data Sheet ADN2805 Timing Characteristics CLKOUTP TH 07121-002 TS DATAOUTP/ DATAOUTN Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP/N VOH VOS 07121-003 |VOD| VOL Figure 3. Differential Output Specifications 5mA RLOAD 100Ω 100Ω VDIFF SIMPLIFIED LVDS OUTPUT STAGE Figure 4. Differential Output Stage Rev. B | Page 5 of 16 07121-004 5mA ADN2805 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted. Thermal Resistance 4-layer board with exposed paddle soldered to VEE. Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Range Rating 4.2 V VEE − 0.4 V VCC + 0.4 V 125°C −65°C to +150°C Table 5. Thermal Resistance Package Type 32-Lead LFCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 6 of 16 θJA 28 Unit °C/W Data Sheet ADN2805 32 VCC 31 VCC 30 VEE 29 DATAOUTP 28 DATAOUTN 27 SQUELCH 26 CLKOUTP 25 CLKOUTN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDIC ATOR ADN2805* TOP VIEW (Not to Scale) 24 VCC 23 VEE 22 NC 21 SDA 20 SCK 19 SADDR5 18 VCC 17 VEE * THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND. 07121-005 NC 9 REFCLKP 10 REFCLKN 11 VCC 12 VEE 13 CF2 14 CF1 15 LOL 16 VCC 1 VCC 2 VREF 3 NIN 4 PIN 5 NC 6 NC 7 VEE 8 Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6, 7, 9, 22 8 10 11 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 32 Exposed Pad 1 Mnemonic VCC VCC VREF NIN PIN NC VEE REFCLKP REFCLKN VCC VEE CF2 CF1 LOL VEE VCC SADDR5 SCK SDA VEE VCC CLKOUTN CLKOUTP SQUELCH DATAOUTN DATAOUTP VEE VCC VCC Pad Type 1 AI P AO AI AI P DI DI P P AO AO DO P P DI DI DI P P DO DO DI DO DO P P AI P Description Connect to VCC. Power for Limiting Amplifier, LOS. Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor. Differential Data Input. CML. Differential Data Input. CML. No Connect. GND for Limiting Amplifier, LOS. Differential REFCLK Input. 10 MHz to 160 MHz. Differential REFCLK Input. 10 MHz to 160 MHz. VCO Power. VCO GND. Frequency Loop Capacitor. Frequency Loop Capacitor. Loss-of-Lock Indicator. LVTTL active high. FLL Detector GND. FLL Detector Power. Slave Address Bit 5. I2C Clock Input. I2C Data Input. Output Buffer, I2C GND. Output Buffer, I2C Power. Differential Recovered Clock Output. LVDS. Differential Recovered Clock Output. LVDS. Disable Clock and Data Outputs. Active high. LVTTL. Differential Recovered Data Output. LVDS. Differential Recovered Data Output. LVDS. Phase Detector, Phase Shifter GND. Phase Detector, Phase Shifter Power. Connect to VCC. Connect to GND. Works as a heat sink. Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output. Rev. B | Page 7 of 16 ADN2805 Data Sheet I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION R/W CTRL. SLAVE ADDRESS [6...0] A5 SET BY PIN 19 0 0 0 0 0 X 07121-006 1 MSB = 1 0 = WR 1 = RD S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P 07121-007 Figure 6. Slave Address Configuration Figure 7. I2C Write Data Transfer SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) S SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M) DATA A(M) P P = STOP BIT A(M) = LACK OF ACKNOWLEDGE BY MASTER A(M) = ACKNOWLEDGE BY MASTER 07121-008 S Figure 8. I2C Read Data Transfer SDA SLAVE ADDRESS A6 SUB ADDRESS A5 A7 STOP BIT DATA A0 D7 D0 SCK S WR ACK ACK SLADDR[4...0] ACK SUB ADDR[6...1] DATA[6...1] Figure 9. I2C Data Transfer Timing tF tSU;DAT tHD;STA tBUF SDA tR tR tSU;STO tF tLOW tHIGH tHD;STA S tSU;STA tHD;DAT S Figure 10. I2C Port Timing Diagram Rev. B | Page 8 of 16 P S 07121-010 SCK P 07121-009 START BIT Data Sheet ADN2805 Table 7. Internal Register Map 1, 2 Reg. Name FREQ0 FREQ1 FREQ2 RATE MISC R/W R R R R R Address 0x0 0x1 0x2 0x3 0x4 D7 D6 D5 MSB MSB 0 MSB COARSE_RD[8] MSB X X X CTRLA CTRLB W W 0x8 0x9 CTRLC W 0x11 fREF Range Config Reset LOL MISC[4] 0 0 1 2 D4 D3 D2 D1 Coarse Data Rate Readback Static LOL Data Rate LOL Status Measure Complete Data Rate/DIV_fREF Ratio 0 System 0 Reset Reset MISC[2] 0 0 0 0 D0 LSB LSB LSB COARSE_RD[1] COARSE_RD[0] (LSB) X Measure Data Rate 0 Lock to Reference 0 Squelch Mode Output Boost All writeable registers default to 0x00. X = don’t care. Table 8. Miscellaneous Register, MISC1 D7 X 1 D6 X D5 X Static LOL D4 0 = waiting for next LOL 1 = static LOL until reset LOL Status D3 0 = locked 1 = acquiring Data Rate Measurement Complete D2 0 = measuring data rate 1 = measurement complete D1 X Coarse Rate Readback LSB D0 COARSE_RD[0] X = don’t care. Table 9. Control Register, CTRLA 1 fREF Range D7 0 0 1 1 1 D6 0 1 0 1 Data Rate/DIV_fREF Ratio D5 D4 D3 D2 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 n 2n 1 0 0 0 256 10 MHz to 20 MHz 20 MHz to 40 MHz 40 MHz to 80 MHz 80 MHz to 160 MHz Measure Data Rate D1 Set to 1 to measure data rate Lock to Reference D0 0 = lock to input data 1 = lock to reference clock Where DIV_fREF is the divided down reference referred to the 10 MHz to 20 MHz band. Table 10. Control Register, CTRLB Configure LOL D7 0 = LOL pin normal operation 1 = LOL pin is static LOL Reset MISC[4] D6 Write a 1 followed by 0 to reset MISC[4] System Reset D5 Write a 1 followed by 0 to reset ADN2805 D4 Set to 0 Reset MISC[2] D3 Write a 1 followed by 0 to reset MISC[2] D2 Set to 0 D1 Set to 0 D0 Set to 0 Table 11. Control Register, CTRLC D7 Set to 0 D6 Set to 0 D5 Set to 0 D4 Set to 0 D3 Set to 0 D2 Set to 0 Squelch Mode D1 0 = SQUELCH DATAOUT and CLKOUT 1 = SQUELCH DATAOUT or CLKOUT Rev. B | Page 9 of 16 Output Boost D0 0 = default output swing 1 = boost output swing ADN2805 Data Sheet THEORY OF OPERATION Another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second-order phase-locked loop, and this zero is placed in the feedback path and, thus, does not appear in the closed-loop transfer function. Jitter peaking in a conventional second-order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function. Because this circuit has no zero in the closed-loop transfer, jitter peaking is minimized. The delay and phase loops together simultaneously provide wideband jitter accommodation and narrow-band jitter filtering. The linearized block diagram in Figure 11 shows that the jitter transfer function, Z(s)/X(s), is second-order low-pass, providing excellent filtering. Note that the jitter transfer has no zero, unlike an ordinary second-order phase-locked loop. This means that the main PLL has virtually zero jitter peaking (see Figure 12). This makes this circuit ideal for signal regenerator applications where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation. The error transfer, e(s)/X(s), has the same high-pass form as an ordinary phase-locked loop. This transfer function is free to be optimized to give excellent wideband jitter accommodation because the jitter transfer function, Z(s)/X(s), provides the narrow-band jitter filtering. INPUT DATA e(s) X(s) d/sc o/s 1/n Z(s) RECOVERED CLOCK d = PHASE DETECTOR GAIN o = VCO GAIN c = LOOP INTEGRATOR psh = PHASE SHIFTER GAIN n = DIVIDE RATIO JITTER TRANSFER FUNCTION Z(s) 1 = cn n psh X(s) s2 +s +1 do o TRACKING ERROR TRANSFER FUNCTION 07121-011 e(s) s2 = d psh do X(s) s2 + s + c cn Figure 11. ADN2805 PLL/DLL Architecture JITTER PEAKING IN ORDINARY PLL ADN2805 Z(s) X(s) o n psh d psh c FREQUENCY (kHz) 07121-012 The delay and phase loops together track the phase of the input data signal. For example, when the clock lags input data, the phase detector drives the VCO to a higher frequency and increases the delay through the phase shifter; both of these actions serve to reduce the phase error between the clock and data. The faster clock picks up phase, while simultaneously, the delayed data loses phase. Because the loop filter is an integrator, the static phase error is driven to zero. psh JITTER GAIN (dB) The ADN2805 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter. A separate phase control loop, comprised of the VCO, tracks the low frequency components of input jitter. The initial frequency of the VCO is set by yet a third loop, which compares the VCO frequency with the input data frequency and sets the coarse tuning voltage. The jitter tracking phase-locked loop (PLL) controls the VCO by the fine-tuning control. Figure 12. ADN2805 Jitter Response vs. Conventional PLL The delay and phase loops contribute to overall jitter accommodation. At low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. In this case, the VCO is frequency modulated and jitter is tracked as in an ordinary phase-locked loop. The amount of low frequency jitter that can be tracked is a function of the VCO tuning range. A wider tuning range gives larger accommodation of low frequency jitter. The internal loop control voltage remains small for small phase errors; therefore, the phase shifter remains close to the center of its range and thus contributes little to the low frequency jitter accommodation. At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at either one extreme of its tuning range or at the other. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation. As such, the delaylocked loop control voltage is larger, and, consequently, the phase shifter takes on the burden of tracking the input jitter. The phase shifter range, in UI, can be seen as a broad plateau on the jitter tolerance curve. The phase shifter has a minimum range of 2 UI at all data rates. Rev. B | Page 10 of 16 Data Sheet ADN2805 The gain of the loop integrator is small for high jitter frequencies; therefore, larger phase differences are needed to make the loop control voltage large enough to tune the range of the phase shifter. Large phase errors at high jitter frequencies cannot be tolerated. In this region, the gain of the integrator determines the jitter accommodation. Because the gain of the loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. At the highest frequencies, the loop gain is very small, and little tuning of the phase shifter can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. The jitter accommodation is roughly 0.5 UI in this region. The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 1.5 MHz at 1.25 Gbps. Rev. B | Page 11 of 16 ADN2805 Data Sheet FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION When LOL deasserts, the FLL turns off. The PLL/DLL pulls in the VCO frequency until the VCO frequency equals the data frequency. The frequency loop requires a single external capacitor between CF1 and CF2, Pin 15 and Pin 14. A 0.47 μF ± 20%, X7R ceramic chip capacitor with 300MΩ INSULATION RESISTANCE Figure 14. Typical Applications Circuit Rev. B | Page 14 of 16 07121-014 1nF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0.1µF VCC VCC VREF NIN PIN NC NC VEE VCC Data Sheet ADN2805 VCC Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also REFCLKP and REFCLKN, if a high frequency reference clock is used, such as 155 MHz). It is also necessary for the PIN/NIN input traces to be matched in length, and the CLKOUTP/ CLKOUTN and DATAOUTP/DATAOUTN output traces to be matched in length to avoid skew between the differential traces. ADN2805 50Ω CIN PIN 50Ω CIN NIN TIA 50Ω 0.1µF VREF 50Ω 3kΩ 2.5V 07121-015 Transmission Lines Figure 15. AC-Coupled Input Configuration The high speed inputs, PIN and NIN, are internally terminated with 50 Ω to an internal reference voltage (see Figure 15). A 0.1 μF is recommended between VREF, Pin 3, and GND to provide an ac ground for the inputs. Soldering Guidelines for Lead Frame Chip Scale Package The lands on the 32-lead LFCSP are rectangular. The printed circuit board (PCB) pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central exposed pad. The pad on the PCB should be at least as large as this exposed pad. The user must connect the exposed pad to VEE using plugged vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE. As with any high speed mixed-signal design, take care to keep all high speed digital traces away from sensitive analog nodes. VCC V1 CIN V2 ADN2805 PIN TIA V1b CIN V2b 50Ω NIN V1 1 2 COUT + 50Ω VREF DATAOUTP CDR BUFFER DATAOUTN COUT – 3 4 V1b V2 VREF V2b VTH VDIFF NOTES: 1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO. 2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS. 3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER DOES NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2805. THE QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT. Figure 16. Example of Baseline Wander Rev. B | Page 15 of 16 07121-016 VDIFF = V2 – V2b VTH = ADN2805 QUANTIZER THRESHOLD ADN2805 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 17. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADN2805ACPZ ADN2805ACPZ-500RL7 ADN2805ACPZ-RL7 EVAL-ADN2805EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 32-Lead LFCSP_WQ 32-Lead LFCSP_WQ, Tape-Reel, 500 pieces 32-Lead LFCSP_WQ, Tape-Reel, 1,500 pieces Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07121-0-3/12(B) Rev. B | Page 16 of 16 Package Option CP-32-7 CP-32-7 CP-32-7