OC-48/OC-48 FEC Clock and Data Recovery
IC with Integrated Limiting Amp
ADN2811
FEATURES
PRODUCT DESCRIPTION
Meets SONET requirements for jitter transfer/generation/
tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: ±100 mV
1.9 GHz minimum bandwidth
Patented clock recovery architecture
Loss of signal detect range: 3 mV to 15 mV
Single reference clock frequency for both native SONET and
15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz
REFCLK
LVPECL/LVDS/LVCMOS/LVTTL compatible inputs
(LVPECL/LVDS only at 155.52 MHz)
19.44 MHz on-chip oscillator to be used with external crystal
Loss of lock indicator
Loopback mode for high speed test data
Output squelch and bypass features
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm × 7 mm, 48-lead LFCSP
The ADN2811 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at OC-48 and
OC-48 FEC rates. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance. All
specifications are quoted for −40°C to +85°C ambient
temperature, unless otherwise noted.
The device is intended for WDM system applications and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both the 2.48 Gb/s and
2.66 Gb/s digital wrapper rates are supported by the ADN2811,
without any change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at the
output.
APPLICATIONS
The ADN2811 is available in a compact, 7 mm × 7 mm, 48-lead
chip scale package.
SONET OC-48, SDH STM-16, and 15/14 FEC
WDM transponders
Regenerators/repeaters
Test equipment
Backplane applications
FUNCTIONAL BLOCK DIAGRAM
SLICEP/N
2
VCC
VEE
CF1
ADN2811
CF2
LOL
LOOP
FILTER
2
PIN
2
QUANTIZER
NIN
PHASE
SHIFTER
PHASE
DET.
LOOP
FILTER
VCO
FREQUENCY
LOCK
DETECTOR
/n
REFSEL[0..1]
REFCLKP/N
XO1
XTAL
OSC
XO2
LEVEL
DETECT
DATA
RETIMING
2
THRADJ
SDOUT
FRACTIONAL
DIVIDER
DATAOUTP/N
REFSEL
03019-B-001
VREF
2
CLKOUTP/N
RATE
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADN2811
TABLE OF CONTENTS
Specifications..................................................................................... 3
Limiting Amplifier ..................................................................... 12
Absolute Maximum Ratings............................................................ 5
Slice Adjust .................................................................................. 12
Thermal Characteristics .............................................................. 5
Loss of Signal (LOS) Detector .................................................. 12
ESD Caution.................................................................................. 5
Reference Clock.......................................................................... 12
Pin Configuration and Functional Descriptions.......................... 6
Lock Detector Operation .......................................................... 13
Definition of Terms .......................................................................... 8
Squelch Mode ............................................................................. 14
Maximum, Minimum, and Typical Specifications ................... 8
Test Modes: Bypass and Loopback........................................... 14
Input Sensitivity and Input Overdrive....................................... 8
Applications Information .............................................................. 15
Single-Ended vs. Differential ...................................................... 8
PCB Design Guidelines ............................................................. 15
LOS Response Time ..................................................................... 9
Choosing AC-Coupling Capacitors ......................................... 17
Jitter Specifications....................................................................... 9
DC-Coupled Application .......................................................... 18
Theory of Operation ...................................................................... 10
LOL Toggling during Loss of Input Data................................ 18
Functional Description .................................................................. 12
Outline Dimensions ....................................................................... 19
Clock and Data Recovery .......................................................... 12
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/04—Data Sheet Changed from Rev. A to Rev. B
Updated Format.................................................................. Universal
Changes to Table 6 and Table 7......................................................13
Updated Outline Dimensions ........................................................19
Changes to Ordering Guide ...........................................................19
12/02—Data Sheet Changed from Rev. 0 to Rev. A.
Change to FUNCTIONAL DESCRIPTION Reference Clock ..10
Updated OUTLINE DIMENSIONS .............................................16
Rev. B | Page 2 of 20
ADN2811
SPECIFICATIONS
Table 1. TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 4.7 µF, SLICEP = SLICEN = VCC, unless otherwise noted
Parameter
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common-Mode Level
Differential Input Sensitivity
Input Overdrive
Input Offset
Input rms Noise
QUANTIZER—AC CHARACTERISTICS
Upper –3 dB Bandwidth
Small Signal Gain
S11
Input Resistance
Input Capacitance
Pulse Width Distortion2
QUANTIZER SLICE ADJUSTMENT
Gain
Control Voltage Range
Slice Threshold Offset
LEVEL SIGNAL DETECT (SDOUT)
Level Detect Range (See Figure 4)
Response Time, DC-Coupled
Hysteresis (Electrical), PRBS 223
LOSS OF LOCK DETECT (LOL)
LOL Response Time
POWER SUPPLY VOLTAGE
POWER SUPPLY CURRENT
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer BW
Jitter Peaking
Jitter Generation
Conditions
Min
@ PIN or NIN, DC-Coupled
0
DC-Coupled. (See Figure 24)
PIN–NIN, AC-Coupled1, BER = 1 × 10−10
Figure 6
0.4
4
2
500
244
BER = 1 × 10−10
0.115
−0.8
1.3
0.200
CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
Rise Time
Fall time
Unit
1.2
2.4
V
V
V
mV p-p
mV p-p
µV
µV rms
10
5
GHz
dB
dB
Ω
pF
ps
0.300
+0.8
VCC
V/V
V
V
mV
±1.0
RTHRESH = 2 kΩ
RTHRESH = 20 kΩ
RTHRESH = 90 kΩ
RTHRESH = 2 kΩ
RTHRESH = 20 kΩ
RTHRESH = 90 kΩ
9.4
2.5
0.7
0.1
5.6
3.9
3.2
13.3
5.3
3.0
0.3
6.6
6.1
6.7
18.0
7.6
5.2
5
7.8
8.5
9.9
mV
mV
mV
µs
dB
dB
dB
3.0
150
60
3.3
164
3.6
215
µs
V
mA
From fVCO error > 1000 ppm
PIN–NIN = 10 mV p-p
OC-48
OC-48
OC-48, 12 kHz–20 MHz
590
0.025
0.05
Jitter Tolerance
Max
1.9
54
−15
100
0.65
10
Differential
@ 2.5 GHz
Differential
SliceP–SliceN = ±0.5 V
SliceP–SliceN
@ SliceP or SliceN
Typ
OC-48 (See Figure 11)
600 Hz
6 kHz
100 kHz
1 MHz
VSE (See Figure 5)
VDIFF (See Figure 5)
VOH
VOL
20% to 80%
80% to 20%
Rev. B | Page 3 of 20
880
0.0033
0.09
923
203
5.5
1.03
300
600
kHz
dB
UI rms
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
455
910
VCC
VCC − 0.6
84
84
600
1200
VCC − 0.3
150
150
mV
mV
V
V
ps
ps
ADN2811
Parameter
Setup Time
Hold Time
REFCLK DC INPUT CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Common-Mode Level
TEST DATA DC INPUT CHARACTERISTICS4 (TDINP/N)
Peak-to-Peak Differential Input Voltage
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
Conditions
TS (See Figure 3) OC-48
TH (See Figure 3) OC-48
Min
140
150
@ REFCLKP or REFCLKN
0
100
DC-Coupled, Single-Ended
CML Inputs
VIH
VIL
VIN = 0.4 V or VIN = 2.4 V
VOH, IOH = −2.0 mA
VOL, IOL = +2.0 mA
1
3
Rev. B | Page 4 of 20
Max
Unit
ps
ps
VCC
VCC/2
V
mV
V
0.8
V
2.0
−5
0.8
+5
V
V
µA
0.4
V
V
2.4
PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.
PWD measurement made on quantizer outputs in Bypass mode.
Measurement is equipment limited.
4
TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.
2
Typ
ADN2811
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage (VCC)
Minimum Input Voltage (All Inputs)
Maximum Input Voltage (All Inputs)
Maximum Junction Temperature
Storage Temperature
Lead Temperature (Soldering 10 Sec)
THERMAL CHARACTERISTICS
Ratings
5.5 V
VEE − 0.4 V
VCC + 0.4 V
165°C
−65°C to +150°C
300°C
Thermal Resistance
48-lead LFCSP, 4-layer board with exposed paddle soldered
to VCC
θJA = 25°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 5 of 20
ADN2811
48 LOOPEN
47 VCC
46 VEE
45 SDOUT
44 BYPASS
43 VEE
42 VEE
41 CLKOUTP
40 CLKOUTN
39 SQUELCH
38 DATAOUTP
37 DATAOUTN
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
ADN2811
TOPVIEW
36 VCC
35 VCC
34 VEE
33 VEE
32 NC
31 NC
30 RATE
29 VEE
28 VCC
27 VEE
26 VCC
25 CF2
03019-B-002
PIN 1
INDICATOR
REFCLKN 13
REFCLKP 14
REFSEL 15
VEE 16
TDINP 17
TDINN 18
VEE 19
VCC 20
CF1 21
VEE 22
REFSEL1 23
REFSEL0 24
THRADJ 1
VCC 2
VEE 3
VREF 4
PIN 5
NIN 6
SLICEP 7
SLICEN 8
VEE 9
LOL 10
XO1 11
XO2 12
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2, 26, 28, Pad
3, 9, 16, 19, 22, 27,
29, 33, 34, 42, 43, 46
4
5
6
7
8
10
11
12
13
14
15
17
18
20, 47
21
23
24
25
30
31, 32
35, 36
37
38
39
40
41
44
45
48
1
Mnemonic
THRADJ
VCC
VEE
Type1
AI
P
P
Description
LOS Threshold Setting Resistor.
Analog Supply.
Ground.
VREF
PIN
NIN
SLICEP
SLICEN
LOL
XO1
XO2
REFCLKN
REFCLKP
REFSEL
TDINP
TDINN
VCC
CF1
REFSEL1
REFSEL0
CF2
RATE
NC
VCC
DATAOUTN
DATAOUTP
SQUELCH
CLKOUTN
CLKOUTP
BYPASS
SDOUT
LOOPEN
AO
AI
AI
AI
AI
DO
AO
AO
DI
DI
DI
AI
AI
P
AO
DI
DI
AO
DI
DI
P
DO
DO
DI
DO
DO
DI
DO
DI
Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
Loss of Lock Indicator. LVTTL active high.
Crystal Oscillator.
Crystal Oscillator.
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
Reference Source Select. 0 = on-chip oscillator with external crystal; 1 = external clock source, LVTTL.
Differential Test Data Input.
Differential Test Data Input.
Digital Supply.
Frequency Loop Capacitor.
Reference Frequency Select (See Table 5) LVTTL.
Reference Frequency Select (See Table 5) LVTTL.
Frequency Loop Capacitor.
Data Rate Select (See Table 4) LVTTL.
No Connect.
Output Driver Supply.
Differential Retimed Data Output. CML.
Differential Retimed Data Output. CML.
Disable Clock and Data Outputs. Active high. LVTTL.
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Bypass CDR Mode. Active high. LVTTL.
Loss of Signal Detect Output. Active high. LVTTL.
Enable Test Data Inputs. Active high. LVTTL.
Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output
Rev. B | Page 6 of 20
ADN2811
CLKOUTP
TH
03019-B-003
TS
DATAOUTP/N
Figure 3. Output Timing
18
THRADJ RESISTOR VS. LOS TRIP POINT
16
14
12
mV
10
8
6
03019-B-004
4
2
0
0
10
20
30
40
50
60
RESISTANCE (kΩ)
70
80
90
100
Figure 4. LOS Comparator Trip Point Programming
OUTP
VCML
VSE
OUTN
OUTP–OUTN
VDIFF
03019-B-005
VSE
0V
Figure 5. Single-Ended vs. Differential Output Specs
Rev. B | Page 7 of 20
ADN2811
DEFINITION OF TERMS
MAXIMUM, MINIMUM, AND TYPICAL
SPECIFICATIONS
SINGLE-ENDED VS. DIFFERENTIAL
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the
distribution. This procedure is intended to tolerate production
variations. If the mean shifts by 1.5 standard deviations, the
remaining 4.5 standard deviations still provide a failure rate of
only 3.4 parts per million. For all tested parameters, the test
limits are guardbanded to account for tester variation and
therefore guarantee that no device is shipped outside of data
sheet specifications.
AC-coupling is typically used to drive the inputs to the
quantizer. The inputs are internally dc biased to a commonmode potential of ~0.6 V. Driving the ADN2811 single-ended
and observing the quantizer input with an oscilloscope probe at
the point indicated in Figure 7 shows a binary signal with an
average value equal to the common-mode potential and
instantaneous values both above and below the average value. It
is convenient to measure the peak-to-peak amplitude of this
signal and call the minimum required value the quantizer
sensitivity. Referring to Figure 6, since both positive and
negative offsets need to be accommodated, the sensitivity is
twice the overdrive.
10mV p-p
VREF
INPUT SENSITIVITY AND INPUT OVERDRIVE
SCOPE
PROBE
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the
logic output of the quantizer and the analog voltage input is
shown in Figure 6. For a sufficiently large positive input voltage,
the output is always Logic 1; similarly for negative inputs, the
output is always Logic 0. However, the transitions between
output Logic Levels 1 and 0 are not at precisely defined input
voltage levels but occur over a range of input voltages. Within
this zone of confusion, the output may be either 1 or 0, or it may
even fail to attain a valid logic state. The width of this zone is
determined by the input voltage noise of the quantizer. The
center of the zone of confusion is the quantizer input offset
voltage. Input overdrive is the magnitude of signal required to
guarantee the correct logic level with 1 × 10−10 confidence level.
PIN
+
QUANTIZER
50Ω
50Ω
03019-B-007
VREF
Figure 7. Single-Ended Sensitivity Measurement
5mV p-p
VREF
SCOPE
PROBE
OUTPUT
ADN2811
PIN
NOISE
1
ADN2811
+
QUANTIZER
NIN
50Ω
0
50Ω
INPUT (V p-p)
OVERDRIVE
SENSITIVITY
(2× OVERDRIVE)
Figure 6. Input Sensitivity and Input Overdrive
03019-B-006
OFFSET
03019-B-008
VREF
Figure 8. Differential Sensitivity Measurement
Driving the ADN2811 differentially (see Figure 8), sensitivity
seems to improve by observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a
single-ended probe. A 5 mV p-p signal appears to drive the
ADN2811 quantizer. However, the single-ended probe measures
only half the signal. The true quantizer input signal is twice this
value since the other quantizer input is complementary to the
signal being observed.
Rev. B | Page 8 of 20
ADN2811
LOS RESPONSE TIME
Jitter Tolerance
The LOS response time is the delay between the removal of the
input signal and the indication of loss of signal (LOS) at
SDOUT. The LOS response time of the ADN2811 is 300 ns typ
when the inputs are dc-coupled. In practice, the time constant
of the ac-coupling at the quantizer input determines the LOS
response time.
Jitter tolerance is defined as the peak-to-peak amplitude of the
sinusoidal jitter applied on the input signal that causes a 1 dB
power penalty. This is a stress test that is intended to ensure no
additional penalty is incurred under the operating conditions
(see Figure 10). Figure 11 shows the typical OC-48 jitter
tolerance performance of the ADN2811.
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
ADN2811 performance with respect to those specifications.
Jitter Generation
Jitter generation specification limits the amount of jitter that
can be generated by the device with no jitter and wander
applied at the input. For OC-48 devices, the band-pass filter has
a 12 kHz high-pass cutoff frequency with a roll-off of
20 dB/decade and a low-pass cutoff frequency of at least
20 MHz. The jitter generated should be less than 0.01 UI rms
and 0.1 UI p-p.
Jitter Transfer
1.5
f0
f1
f2
f3
0.1
SLOPE = –20dB/DECADE
fC
JITTER FREQUENCY (kHz)
03019-B-009
ACCEPTABLE
RANGE
Figure 9. Jitter Transfer Curve
Rev. B | Page 9 of 20
03019-B-010
0.15
f4
JITTER FREQUENCY (Hz)
Figure 10. SONET Jitter Tolerance Mask
100
ADN2811
10
1
OC-48 SONET MASK
ٛ0.1
1
10
100
1k
10k
100k
MODULATION FREQUENCY (Hz)
Jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal versus the
frequency. This parameter measures the limited amount of jitter
on an input signal that can be transferred to the output signal
(see Figure 9).
JITTER GAIN (dB)
SLOPE = –20dB/DECADE
Figure 11. OC-48 Jitter Tolerance Curve
1M
10M
03019-B-011
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions measured in UI (unit
intervals), where 1 UI = 1 bit period. Jitter on the input data
can cause dynamic phase errors on the recovered clock
sampling edge. Jitter on the recovered clock causes jitter on the
retimed data.
15
AMPLITUDE (UI p- p)
The ADN2811 CDR is designed to achieve the best bit-errorrate (BER) performance, and has exceeded the jitter generation,
transfer, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia Technologies specification.
INPUT JITTER AMPLITUDE (UI)
JITTER SPECIFICATIONS
ADN2811
THEORY OF OPERATION
The delay-locked and phase-locked loops together track the
phase of the input data signal. For example, when the clock lags
input data, the phase detector drives the VCO to a higher
frequency and also increases the delay through the phase shifter.
Both of these actions serve to reduce the phase error between
the clock and data. The faster clock picks up phase while the
delayed data loses phase. Since the loop filter is an integrator,
the static phase error is driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for the frequency compensation of a secondorder phase-locked loop, and this zero is placed in the feedback
path and therefore does not appear in the closed-loop transfer
function. Jitter peaking in a conventional second-order phaselocked loop is caused by the presence of this zero in the closedloop transfer function. Since this circuit has no zero in the
closed-loop transfer, jitter peaking is minimized.
The delay- and phase-locked loops together simultaneously
provide wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 12 shows that
the jitter transfer function, Z(s)/X(s), is a second-order low-pass
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means the main PLL loop has low jitter peaking (see Figure 13),
which makes this circuit ideal for signal regenerator
applications where jitter peaking in a cascade of regenerators
can contribute to hazardous jitter accumulation.
psh
INPUT
DATA
X(s)
e(s)
d/sc
o/s
Z(s)
RECOVERED
CLOCK
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
JITTER TRANSFER FUNCTION
Z(s)
1
=
cn
n psh
X(s)
s2
+s
+1
do
o
TRACKING ERROR TRANSFER FUNCTION
e(s)
=
X(s)
s2 + s
s2
do
d psh
+
cn
c
03019-B-012
The ADN2811 is a delay-locked and phase-locked loop circuit
for clock recovery and data retiming from an NRZ encoded
data stream. The phase of the input data signal is tracked by two
separate feedback loops that share a common control voltage. A
high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of the
input jitter. A separate phase control loop, comprised of the
VCO, tracks the low frequency components of the input jitter.
The initial frequency of the VCO is set by yet a third loop,
which compares the VCO frequency with the reference
frequency and sets the coarse tuning voltage. The jitter tracking
phase-locked loop controls the VCO by the fine tuning control.
Figure 12. PLL/DLL Architecture
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation
since the jitter transfer function, Z(s)/X(s), provides the narrowband jitter filtering.
The delay- and phase-locked loops contribute to overall jitter
accommodation. At low frequencies of input jitter on the data
signal, the integrator in the loop filter provides high gain to
track large jitter amplitudes with small phase error. In this case,
the VCO is frequency modulated and jitter is tracked as in an
ordinary phase-locked loop. The amount of low frequency jitter
that can be tracked is a function of the VCO tuning range. A
wider tuning range gives larger accommodation of low
frequency jitter. The internal loop control voltage remains small
for small phase errors, so the phase shifter remains close to the
center of its range, and therefore contributes little to the low
frequency jitter accommodation.
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track the input jitter. In this case,
the VCO control voltage becomes large and saturates, and the
VCO frequency dwells at one or the other extreme of its tuning
range. The size of the VCO tuning range therefore has only a
small effect on the jitter accommodation. The delay-locked loop
control voltage is now larger; thus the phase shifter takes on the
burden of tracking input jitter. The phase shifter range, in UI,
can be seen as a broad plateau on the jitter tolerance curve. The
phase shifter has a minimum range of 2 UI at all data rates.
Rev. B | Page 10 of 20
ADN2811
Rev. B | Page 11 of 20
JITTER PEAKING
IN ORDINARY PLL
JITTER
GAIN
(dB)
ADN2811
Z(s)
X(s)
o
n psh
d psh
c
f (kHz)
Figure 13. Jitter Response vs. Conventional PLL
03019-B-013
The gain of the loop integrator is small for high jitter
frequencies, so larger phase differences are needed to make the
loop control voltage big enough to tune the range of the phase
shifter. Large phase errors at high jitter frequencies cannot be
tolerated. In this region, the gain of the integrator determines
the jitter accommodation. Since the gain of the loop integrator
declines linearly with frequency, jitter accommodation is lower
with higher jitter frequency. At the highest frequencies, the loop
gain is very small and little tuning of the phase shifter can be
expected. In this case, jitter accommodation is determined by
the eye opening of the input data, the static phase error, and the
residual loop jitter generation. Jitter accommodation is roughly
0.5 UI in this region. The corner frequency between the
declining slope and the flat region is the closed-loop bandwidth
of the delay-locked loop, which is roughly 5 MHz.
ADN2811
FUNCTIONAL DESCRIPTION
CLOCK AND DATA RECOVERY
REFERENCE CLOCK
The ADN2811 recovers clock and data from serial bit streams at
OC-48 as well as the 15/14 FEC rates. The data rate is selected
by the RATE input (see Table 4).
There are three options for providing the reference frequency to
the ADN2811: differential clock, single-ended clock, or crystal
oscillator. See Figure 14, Figure 15, and Figure 16 for example
configurations.
Table 4. Data Rate Selection
Data Rate
OC-48
OC-48 FEC
Frequency (MHz)
2488.32
2666.06
ADN2811
REFCLKP
LIMITING AMPLIFIER
BUFFER
The limiting amplifier has differential inputs (PIN/NIN) that
are internally terminated with 50 Ω to an on-chip voltage reference (VREF = 0.6 V typically). These inputs are normally
ac-coupled, although dc coupling is possible as long as the input
common-mode voltage remains above 0.4 V (see Figure 22,
Figure 23, and Figure 24). Input offset is factory trimmed to
achieve better than 4 mV typical sensitivity with minimal drift.
The limiting amplifier can be driven differentially or singleended.
REFCLKN
100kΩ
100kΩ
VCC/2
XO1
XO2
VCC
VCC
CRYSTAL
OSCILLATOR
03019-B-014
VCC
REFSEL
Figure 14. Differential REFCLK Configuration
SLICE ADJUST
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise by
applying a differential voltage input of ±0.8 V to SLICEP/N
inputs. If no adjustment of the slice level is needed, SLICEP/N
should be tied to VCC.
ADN2811
VCC
REFCLKP
CLK
OSC
OUT
BUFFER
REFCLKN
NC
100kΩ
LOSS OF SIGNAL (LOS) DETECTOR
VCC/2
XO1
VCC
XO2
VCC
VCC
CRYSTAL
OSCILLATOR
REFSEL
Figure 15. Single-Ended REFCLK Configuration
ADN2811
VCC
REFCLKP
If the LOS detector is used, the quantizer slice adjust pins must
both be tied to VCC. This is to avoid interaction with the LOS
threshold level.
BUFFER
NC
REFCLKN
100kΩ
Note that it is not expected to use both LOS and slice adjust at
the same time; systems with optical amplifiers need the slice
adjust to evade ASE. However, a loss of signal in an optical link
that uses optical amplifiers causes the optical amplifier output
to be full-scale noise. Under this condition, the LOS would not
detect the failure. In this case, the loss of lock signal indicates
the failure because the CDR circuitry is unable to lock onto a
signal that is full-scale noise.
Rev. B | Page 12 of 20
03019-B-015
The receiver front end level signal detect circuit indicates when
the input signal level has fallen below a user adjustable
threshold. The threshold is set with a single external resistor
from Pin 1, THRADJ, to GND. The LOS comparator trip point
versus the resistor value is illustrated in Figure 4 (this is only
valid for SLICEP = SLICEN = VCC). If the input level to the
ADN2811 drops below the programmed LOS threshold,
SDOUT (Pin 45) indicates the loss of signal condition with a
Logic 1. The LOS response time is ~300 ns by design, but is
dominated by the RC time constant in ac-coupled applications.
100kΩ
100kΩ
VCC/2
XO1
19.44MHz
XO2
CRYSTAL
OSCILLATOR
REFSEL
Figure 16. Crystal Oscillator Configuration
003019-B-016
RATE
0
1
ADN2811
The ADN2811 can accept any of the following reference clock
frequencies: 19.44 MHz, 38.88 MHz, 77.76 MHz at LVTTL/
LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/
LVDS levels via the REFCLKN/P inputs, independent of data
rate. The input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV
(e.g., LVPECL or LVDS) or a standard single-ended low voltage
TTL input, providing maximum system flexibility. The
appropriate division ratio can be selected using the REFSEL0/1
pins, according to Table 5. Phase noise and duty cycle of the
reference clock are not critical, and 100 ppm accuracy is
sufficient.
REFSEL must be tied to VCC when the REFCLKN/P inputs are
active, or tied to VEE when the oscillator is used. No connection
between the XO pin and REFCLK input is necessary (see
Figure 14, Figure 15, and Figure 16). Note that the crystal should
operate in series resonant mode, which renders it insensitive to
external parasitics. No trimming capacitors are required.
LOCK DETECTOR OPERATION
The lock detector monitors the frequency difference between
the VCO and the reference clock and deasserts the loss of lock
signal when the VCO is within 500 ppm of center frequency
(see Figure 17). This enables the phase loop, which pulls the
VCO frequency in the remaining amount and also acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss of lock signal is reasserted and
control returns to the frequency loop, which reacquires and
maintains a stable clock signal at the output.
Table 5. Reference Frequency Selection
REFSEL[1..0]
00
01
10
11
XX
Applied Reference
Frequency (MHz)
19.44
38.88
77.76
155.52
REFCLKP/N Inactive. Use 19.44 MHz
XTAL oscillator on Pins XO1, XO2 (Pull
REFCLKP to VCC).
The frequency loop requires a single external capacitor between
CF1 and CF2. The capacitor specification is given in Table 7.
Table 7. Recommended CF Capacitor Specification
Parameter
Temperature Range
Capacitance
Leakage
Rating
An on-chip oscillator to be used with an external crystal is also
provided as an alternative to using the REFCLKN/P inputs.
Details of the recommended crystal are given in Table 6.
Table 6. Required Crystal Specifications
Parameter
Mode
Frequency/Overall Stability
Frequency Accuracy
Temperature Stability
Aging
ESR
Value
−40°C to +85°C
>3.0 µF
6.3 V
Value
Series Resonant
19.44 MHz ±100 ppm
±100 ppm
±100 ppm
±100 ppm
50 Ω max
LOL
1
1000
500
0
500
Figure 17. Transfer Function of LOL
Rev. B | Page 13 of 20
1000
fVCO ERROR
(ppm)
03019-B-017
REFSEL
1
1
1
1
0
ADN2811
ADN2811
PIN
+
0
QUANTIZER
NIN
CDR
50Ω
50Ω
VREF
1
FROM
QUANTIZER
OUTPUT
1
50Ω
RETIMED
DATA
CLK
0
50Ω
LOOPEN BYPASS DATAOUTP/N
TDINP/N
CLKOUTP/N SQUELCH
03019-B-018
VCC
Figure 18. Test Modes
SQUELCH MODE
When the squelch input is driven to a TTL high state, both the
clock and data outputs are set to the zero state to suppress
downstream processing. If desired, this pin can be directly
driven by the LOS detector output, SDOUT. If the squelch
function is not required, the pin should be tied to VEE.
TEST MODES: BYPASS AND LOOPBACK
When the bypass input is driven to a TTL high state, the
quantizer output is connected directly to the buffers driving the
data out pins, thus bypassing the clock recovery circuit (see
Figure 18). This feature can help the system deal with
nonstandard bit rates.
The loopback mode can be invoked by driving the LOOPEN
pin to a TTL high state, which facilitates system diagnostic
testing. This connects the test inputs (TDINP/N) to the clock
and data recovery circuit (per Figure 18). The test inputs have
internal 50 Ω terminations and can be left floating when not in
use. TDINP/N are CML inputs and can only be dc-coupled
when being driven by CML outputs. The TDINP/N inputs must
be ac-coupled if being driven by anything other than CML
outputs. Bypass and loopback modes are mutually exclusive.
Only one of these modes can be used at any given time. The
ADN2811 is put into an indeterminate state if the BYPASS and
LOOPEN pins are set to Logic 1 at the same time.
Rev. B | Page 14 of 20
ADN2811
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane to both analog and
digital grounds is recommended. The VEE pins should be
soldered directly to the ground plane to reduce series
inductance. If the ground plane is an internal plane and
connections to the ground plane are made through vias,
multiple vias may be used in parallel to reduce the series
inductance, especially on Pins 33 and 34, which are the ground
returns for the output buffers.
Use of a 10 µF electrolytic capacitor between VCC and GND is
recommended at the location where the 3.3 V supply enters the
PCB. 0.1 µF and 1 nF ceramic chip capacitors should be placed
between IC power supply VCC and GND as close as possible to
the ADN2811’s VCC pins. Again, if connections to the supply
and ground are made through vias, the use of multiple vias in
parallel helps to reduce series inductance, especially on Pins 35
and 36, which supply power to the high speed CLKOUTP/N
and DATAOUTP/N output buffers. Refer to the schematic in
Figure 19 for recommended connections.
Transmission Lines
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections, including PIN,
NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN
(also REFCLKP, REFCLKN for a 155.2 MHz REFCLK). It is also
recommended that the PIN/NIN input traces are matched in
length and that the CLKOUTP/N and DATAOUTP/N output
traces are matched in length. All high speed CML outputs,
CLKOUTP/N and DATAOUTP/N, also require 100 Ω back
termination chip resistors connected between the output pin
and VCC. These resistors should be placed as close as possible
to the output pins. These 100 Ω resistors are in parallel with
on-chip 100 Ω termination resistors to create a 50 Ω back
termination (see Figure 20).
The high speed inputs, PIN and NIN, are internally terminated
with 50 Ω to an internal reference voltage (see Figure 21). A
0.1 µF capacitor is recommended between VREF, Pin 4, and
GND to provide an ac ground for the inputs.
As with any high speed mixed-signal design, care should be
taken to keep all high speed digital traces away from sensitive
analog nodes.
Soldering Guidelines for Chip-Scale Package
The lands on the 48-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package land length and 0.05 mm wider than the package land
width. The land should be centered on the pad. This ensures
that the solder joint size is maximized. The bottom of the chip
scale package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to analog VCC.
If vias are used, they should be incorporated into the pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz.
copper to plug the via.
Rev. B | Page 15 of 20
ADN2811
VCC
50Ω
TRANSMISSION
LINES
4 × 100Ω
CLKOUTP
VCC
CLKOUTN
µC
DATAOUTP
10µF
1nF
DATAOUTN
DATAOUTP
SQUELCH
CLKOUTN
CLKOUTP
VEE
VEE
BYPASS
SDOUT
VCC
VEE
DATAOUTN
LOOPEN
0.1µF
48 47 46 45 44 43 42 41 40 39 38 37
RTH THRADJ
VCC
VCC
1nF
0.1µF
0.1µF
VEE
VREF
50Ω
PIN
TIA
NIN
50Ω
SLICEP
CIN
VCC
SLICEN
VEE
LOL
µC
XO1
19.44MHz
XO2
1
36
2
35
3
34
4
33
EXPOSED PAD
TIED OFF TO
VCC PLANE
WITH VIAS
5
6
32
31
7
30
8
29
28
9
0.1µF
1nF
10
11
27
26
ADN2811
25
12
VCC
VCC
VCC
0.1µF
1nF
VEE
VEE
NC
NC
RATE
µC
VEE
VCC
0.1µF
1nF
VEE
VCC
VCC
CF2
4.7µF
(SEE TABLE 7 FOR SPECS)
µC
REFSEL0
µC
REFSEL1
VEE
CF1
VCC
VEE
NC
TDINN
TDINP
NC
VEE
REFSEL
REFCLKP
VCC
NC
REFCLKN
13 14 15 16 17 18 19 20 21 22 23 24
03019-B-019
VCC
0.1µF
1nF
Figure 19. Typical Application Circuit
VCC
VCC
VCC
ADN2811
VTERM
100Ω
100Ω
100Ω
100Ω
0.1µ F
0.1µ F
50Ω
CIN
50Ω
CIN
PIN
50Ω
50Ω
TIA
NIN
50Ω
50Ω
50Ω
VTERM
0.1µ F
VREF
03019-B-021
ADN2811
03019-B-020
50Ω
Figure 20. AC-Coupled Output Configuration
Figure 21. AC-Coupled Input Configuration
Rev. B | Page 16 of 20
ADN2811
CHOOSING AC-COUPLING CAPACITORS
The choice of ac-coupling capacitors at the input (PIN, NIN)
and output (DATAOUTP, DATAOUTN) of the ADN2811 must
be chosen carefully. When choosing the capacitors, the time
constant formed with the two 50 Ω resistors in the signal path
must be considered. When a large number of consecutive
identical digits (CIDs) are applied, the capacitor voltage can
drop due to baseline wander (see Figure 22), causing pattern
dependent jitter (PDJ).
V1
ADN2811
CIN
V2
PIN
TIA
CIN
V2b
COUT
+
50Ω
VREF
V1b
For the ADN2811 to work robustly at OC-48, a minimum
capacitor of 0.1 µF to PIN/NIN and 0.1 µF on DATAOUTP/
DATAOUTN should be used. This is based on the assumption
that 1000 CIDs must be tolerated and that the PDJ should be
limited to 0.01 UI p-p.
DATAOUTP
LIMAMP
CDR
COUT
50Ω
DATAOUTN
NIN
1
2
3
4
V1
V1b
V2
VREF
V2b
VTH
VDIFF
NOTES
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS 0.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE VREF LEVEL,
WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN,THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS,
CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER HIGH OR LOW DEPENDING ON
THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2811. THE QUANTIZER WILL BE
ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
Figure 22. Example of Baseline Wander
Rev. B | Page 17 of 20
03019-B-022
VDIFF = V2–V2b
VTH = ADN2811 QUANTIZER THRESHOLD
ADN2811
DC-COUPLED APPLICATION
VCC
The inputs to the ADN2811 can also be dc-coupled. This may
be necessary in burst mode applications where there are long
periods of CIDs and baseline wander cannot be tolerated. If the
inputs to the ADN2811 are dc-coupled, care must be taken not
to violate the input range and common-mode level
requirements of the ADN2811 (see Figure 23, Figure 24, and
Figure 25). If dc-coupling is required and the output levels of
the TIA do not adhere to the levels shown in Figure 24 and
Figure 25, there needs to be level shifting and/or an attenuator
between the TIA outputs and the ADN2811 inputs.
ADN2811
50Ω
TIA
50Ω
PIN
NIN
50Ω
VREF
03019-B-023
0.1µ F
50Ω
Figure 23. ADN2811 with DC-Coupled Inputs
LOL TOGGLING DURING LOSS OF INPUT DATA
INPUT (V)
If the input data stream is lost due to a break in the optical link
(or for any reason), the clock output from the ADN2811 stays
within 1000 ppm of the VCO center frequency as long as there
is a valid reference clock. The LOL pin toggles at a rate of
several kHz because the LOL pin toggles between a Logic 1 and
a Logic 0 while the frequency loop and phase loop swap control
of the VCO. The chain of events is as follows:
The ADN2811 is locked to the input data stream; LOL = 0.
•
The input data stream is lost due to a break in the link. The
VCO frequency drifts until the frequency error is greater
than 1000 ppm. LOL is asserted to a Logic 1 as control of
the VCO is passed back to the frequency loop.
VSE = 5mV MIN
VCM = 0.4V MIN
(DC-COUPLED)
NIN
03019-B-024
•
V p-p = PIN – NIN = 2 × VSE = 10mV AT SENSITIVITY
PIN
Figure 24. Minimum Allowed DC-Coupled Input Levels
V p-p = PIN – NIN = 2 × VSE = 2.4V MAX
PIN
The frequency loop pulls the VCO to within 500 ppm of its
center frequency. Control of the VCO is passed back to the
phase loop and LOL is deasserted to a Logic 0.
•
The phase loop tries to acquire, but there is no input data
present so the VCO frequency drifts.
•
The VCO frequency drifts until the frequency error is
greater than 1000 ppm. LOL is asserted to a Logic 1 as
control of the VCO is passed back to the frequency loop.
This process is repeated until a valid input data stream is
re-established.
Rev. B | Page 18 of 20
VSE = 1.2V MAX
VCM = 0.6V
(DC-COUPLED)
NIN
Figure 25. Maximum Allowed DC-Coupled Input Levels
03019-B-025
•
INPUT (V)
ADN2811
OUTLINE DIMENSIONS
7.00
BSC SQ
0.60 MAX
0.60 MAX
37
36
PIN 1
INDICATOR
TOP
VIEW
12° MAX
PIN 1
INDICATOR
48
1
EXPOSED
PAD
6.75
BSC SQ
5.25
5.10 SQ
4.95
(BOTTOM VIEW)
0.50
0.40
0.30
1.00
0.85
0.80
0.30
0.23
0.18
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.50 BSC
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 26. 48-Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body
(CP-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADN2811ACP-CML
ADN2811ACP-CML-RL
EVAL-ADN2811-CML
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead LFCSP
48-Lead LFCSP, Tape-Reel, 2500 pcs
Evaluation Board
Rev. B | Page 19 of 20
Package Option
CP-48
CP-48
ADN2811
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03019–0–5/04(B)
Rev. B | Page 20 of 20
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