Dual-Loop, 50 Mbps to 2.7 Gbps
Laser Diode Driver
ADN2841
Data Sheet
FEATURES
APPLICATIONS
50 Mbps to 2.7 Gbps operation
Typical rise/fall time: 80 ps
Bias current range: 2 mA to 100 mA
Modulation current range: 5 mA to 80 mA
Monitor photodiode current: 50 µA to 1200 µA
Closed-loop control of power and extinction ratio
Laser fail and laser degrade alarms
Automatic laser shutdown (ALS)
Dual MPD functionality for DWDM
Optional clocked data
Full current parameter monitoring
5 V operation
48-lead LFCSP
32-lead LFCSP (reduced functionality)
DWDM dual MPD wavelength fixing
SONET OC-1/3/12/48
SDH STM-1/4/16
Fibre Channel
Gigabit Ethernet
GENERAL DESCRIPTION
The ADN2841 uses a unique control algorithm to control both
the average power and extinction ratio of the laser diode (LD)
after initial factory setup. Because power and extinction ratio
control are fully integrated, external component count is low
and PCB area is small. Programmable alarms are provided for
laser fail (end of life) and laser degrade (impending fail).
The ADN2841 has circuitry for a second monitor photodiode,
which enables DWDM wavelength control.
GND
IMODN
CLKSEL
VCC
VCCx
DEGRADE
FAIL
ALS
IMPDMON2
IBMON
IMMON
IMPDMON
FUNCTIONAL BLOCK DIAGRAM
VCC
LD
VCC
IMODP
MPD
IMPD
DATAP
DATAN
IMOD
CLKP
IMPD2
CLKN
CONTROL
GND
PSET
IBIAS
IBIAS
ASET
GND ERSET
ADN2841
GND
ERCAP
GND
PAVCAP
IDTONE
LBWSET
02659-001
GND
GND
Figure 1.
Rev. C
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ADN2841
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Alarms .............................................................................................9
Applications ....................................................................................... 1
Monitor Currents ....................................................................... 10
General Description ......................................................................... 1
Dual MPD DWDM Function (48-Lead LFCSP Only) ......... 10
Functional Block Diagram .............................................................. 1
IDTONE (48-Lead LFCSP Only) ............................................. 10
Revision History ............................................................................... 2
Data and Clock Inputs ............................................................... 11
Specifications..................................................................................... 3
CCBIAS........................................................................................ 11
Absolute Maximum Ratings ............................................................ 5
Automatic Laser Shutdown ....................................................... 11
Thermal Resistance ...................................................................... 5
Alarm Interfaces ......................................................................... 11
ESD Caution .................................................................................. 5
Power Consumption .................................................................. 11
Pin Configurations and Function Descriptions ........................... 6
Application Circuits ....................................................................... 12
Typical Performance Characteristics ............................................. 8
Outline Dimensions ....................................................................... 15
Theory of Operation ........................................................................ 9
Ordering Guide .......................................................................... 16
Control ........................................................................................... 9
Loop Bandwidth Selection .......................................................... 9
REVISION HISTORY
2/2017—Rev. B to Rev. C
Changed CP-48-1 to CP-48-4 ...................................... Throughout
Changes to Figure 3 and Figure 4 ................................................... 6
Changes to Figure 11 ...................................................................... 12
Changes to Figure 12 ...................................................................... 13
Changes to Figure 13 ...................................................................... 14
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
9/2013—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Table 2 ............................................................................ 5
Added Thermal Resistance Section and Table 3 .......................... 5
Changes to Figure 3, Figure 4, and Table 4 ....................................6
Added Typical Performance Characteristics Section;
moved Figure 5 and Figure 6 ...........................................................8
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
8/2002—Rev. 0 to Rev. A
Replaced Figure 8 ........................................................................... 10
Updated Outline Dimensions ....................................................... 11
10/2001—Revision 0: Initial Version
Rev. C | Page 2 of 16
Data Sheet
ADN2841
SPECIFICATIONS
VCC = 5 V ± 10%. All specifications TMIN to TMAX, unless otherwise noted. Typical values are specified at 25°C.
Table 1.
Parameter 1
LASER BIAS (BIAS)
Current, IBIAS
Compliance Voltage
IBIAS During ALS
ALS Response Time
CCBIAS Compliance Voltage
MODULATION CURRENT (IMODP, IMODN)
Output Current, IMOD
Compliance Voltage
IMOD During ALS
Rise Time
Fall Time
Jitter
Pulse Width Distortion
MONITOR PD (MPD, MPD2)
Input Current
Voltage
POWER SET INPUT (PSET PIN)
Capacitance
Input Current
Voltage
EXTINCTION RATIO SET INPUT (ERSET PIN)
Allowable Resistance Range
Voltage
ALARM SET (ASET PIN)
Allowable Resistance Range
Voltage
Hysteresis
CONTROL LOOP
Time Constant
DATA INPUTS (DATAP, DATAN, CLKP, CLKN PINS)
AC-Coupled 2
V p-p (Single-Ended Peak-to-Peak)
Input Impedance
tSETUP 3
tHOLD3
LOGIC INPUTS (ALS, LBWSET, CLKSEL PINS)
VIH
VIL
ALARM OUTPUTS
VOH
VOL
IDTONE PIN
Compliance Voltage
IOUT/IIN Ratio
fIN 4
Min
Typ
2
1.2
Max
Unit
100
VCC
0.1
mA
V
mA
μs
V
80
VCC
0.1
120
120
20
mA
V
mA
ps
ps
ps p-p
ps
1200
1.6
μA
V
pF
μA
V
10
1.2
5
1.8
80
80
18
50
50
1.15
1.23
80
1200
1.35
1.2
1.15
1.23
25
1.35
kΩ
V
25
1.35
kΩ
V
%
1.2
1.15
1.23
5
0.22
2.25
100
150
0
sec
sec
500
50
95
–70
2.4
Test Conditions/Comments
Average current
Average current
LBWSET = GND
LBWSET = VCC
mV
Ω
ps
ps
0.8
V
V
0.8
V
V
Internal 30 kΩ pull-up
2.4
User to supply current sink in the
range of 50 μA to 4 mA
VCC − 1.5
V
1
MHz
2
0.01
Rev. C | Page 3 of 16
ADN2841
Data Sheet
Parameter1
IBMON, IMMON, IMPDMON, IMPDMON2 PINS
IBMON, IMMON Division Ratio
IMPDMON, IMPDMON2 Division Ratio
IMPDMON to IMPDMON2 Matching
Compliance Voltage
SUPPLY
ICC5
VCC6
Min
Typ
Max
Unit
Test Conditions/Comments
1
VCC − 1.2
A/A
A/A
%
V
IBIAS current/IMOD current
IMPD current/IMPD2 current
IMPD = 1200 μA
A
V
IBIAS = IMOD = 0 A
5.5
100
1
0
4.5
0.05
5.0
1
Temperature range: −40°C to +85°C.
When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin.
3
Guaranteed by design and characterization. Not production tested.
4
IDTONE may cause eye distortion.
5
ICC for power calculation is the typical ICC given.
6
All VCCx pins should be shorted together.
2
SETUP
tS
HOLD
tH
02659-002
DATAP/DATAN
CLKP
Figure 2. Setup and Hold Time
Rev. C | Page 4 of 16
Data Sheet
ADN2841
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 2.
θJA is specified for the worst-case conditions, that is, a device
soldered onto a 4-layer circuit board for surface-mount packages.
Parameter
VCC to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ MAX)
Power Dissipation
1
1
Rating
7V
Table 3. Thermal Resistance
Package Type
48-Lead LFCSP
32-Lead LFCSP
−40°C to +85°C
−65°C to +150°C
150°C
(TJ MAX − TA)/θJA mW
ESD CAUTION
Transient currents of up to 100 mA will not cause SCR latch-up.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 5 of 16
θJA
25
32
Unit
°C/W
°C/W
ADN2841
Data Sheet
GND 1
LBWSET 2
ASET 3
ERSET 4
PSET 5
GND 6
IMPD 7
IMPDMON 8
IMPDMON2 9
IMPD2 10
GND4 11
VCC4 12
ADN2841
36
35
34
33
32
31
30
29
28
27
26
25
GND2
IDTONE
GND2
IBMON
IMMON
GND3
VCC3
ALS
FAIL
DEGRADE
CLKSEL
GND
LBWSET
ASET
ERSET
PSET
IMPD
IMPDMON
GND4
VCC4
1
2
3
4
5
6
7
8
CCBIAS
IBIAS
GND2
GND2
IMODP
GND2
IMODN
VCC2
ADN2841
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
IBMON
IMMON
GND3
VCC3
ALS
FAIL
DEGRADE
CLKSEL
Figure 3. Pin Configuration, 48-Lead LFCSP
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE
MUST BE CONNECTED TO VCC OR THE GND PLANE.
Figure 4. Pin Configuration, 32-Lead LFCSP
Table 4. Pin Function Descriptions
48-Lead
LFCSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Pin No.
32-Lead
LFCSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Mnemonic
GND
LBWSET
ASET
ERSET
PSET
GND
IMPD
IMPDMON
IMPDMON2
IMPD2
GND4
VCC4
ERCAP
PAVCAP
GND
VCC1
GND1
DATAN
DATAP
GND1
CLKP
CLKN
GND
GND
GND
CLKSEL
DEGRADE
Description
Supply Ground.
Select Low Loop Bandwidth (Active = VCC).
Alarm Current Threshold Set Pin.
Extinction Ratio Set Pin.
Average Optical Power Set Pin.
Ground.
Monitor Photodiode Input.
Mirrored Current from Monitor Photodiode.
Mirrored Current from Monitor Photodiode 2. For use with two MPDs.
Monitor Photodiode Input 2. For use with two MPDs.
Supply Ground.
Supply Voltage.
Extinction Ratio Loop Capacitor.
Average Power Loop Capacitor.
Ground.
Supply Voltage.
Supply Ground.
Data, Negative Differential Terminal.
Data, Positive Differential Terminal.
Supply Ground.
Data Clock, Positive Differential Terminal. Used if CLKSEL = VCC.
Data Clock, Negative Differential Terminal. Used if CLKSEL = VCC.
Ground.
Ground.
Ground.
Clock Select (Active = VCC). Used if data is clocked into the chip.
Degrade Alarm Output.
Rev. C | Page 6 of 16
02659-004
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE
MUST BE CONNECTED TO VCC OR THE GND PLANE.
02659-003
ERCAP
PAVCAP
GND
VCC1
GND1
DATAN
DATAP
GND1
CLKP
CLKN
GND
GND
13
14
15
16
17
18
19
20
21
22
23
24
ERCAP
PAVCAP
VCC1
DATAN
DATAP
GND1
CLKP
CLKN
9
10
11
12
13
14
15
16
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
PIN 1
INDICATOR
CCBIAS
IBIAS
IBIAS
GND2
GND2
IMODP
IMODP
GND2
IMODN
IMODN
VCC2
GND2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
48-Lead
LFCSP
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
EP
Pin No.
32-Lead
LFCSP
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EP
ADN2841
Mnemonic
FAIL
ALS
VCC3
GND3
IMMON
IBMON
GND2
IDTONE
GND2
GND2
VCC2
IMODN
IMODN
GND2
IMODP
IMODP
GND2
GND2
IBIAS
IBIAS
CCBIAS
Exposed Pad
Description
Fail Alarm Output.
Automatic Laser Shutdown.
Supply Voltage.
Supply Ground.
Modulation Current Mirror Output.
Bias Current Mirror Output.
Supply Ground.
IDTONE. Requires external current sink to ground.
Supply Ground.
Supply Ground.
Supply Voltage.
Modulation Current Negative Output. Connect to 25 Ω.
Modulation Current Negative Output. Connect to 25 Ω.
Supply Ground.
Modulation Current Positive Output. Connect to laser diode.
Modulation Current Positive Output. Connect to laser diode.
Supply Ground.
Supply Ground.
Laser Diode Bias Current.
Laser Diode Bias Current.
Extra Laser Diode Bias When AC-Coupled.
The exposed pad on the bottom of the package must be connected to VCC or the GND plane.
Rev. C | Page 7 of 16
ADN2841
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
02659-012
02659-013
Average power = −3 dBm, extinction ratio = 9.5 dB; eye diagrams obtained using a Mitsubishi FU-445SDF.
Figure 5. Unfiltered 2.5 Gbps Optical Eye
Figure 6. Filtered 2.5 Gbps Optical Eye
Rev. C | Page 8 of 16
Data Sheet
ADN2841
THEORY OF OPERATION
Laser diodes have current-in to light-out transfer functions as
shown in Figure 7. Two key characteristics of this transfer function
are the threshold current, ITH, and the slope in the linear region
beyond the threshold current, referred to as slope efficiency, LI.
OPTICAL POWER
ER =
P1
P0
PAV =
P1
ΔP
ΔI
LI =
ΔP
ΔI
CURRENT
02659-005
P0
ITH
LOOP BANDWIDTH SELECTION
For anyrate operation, the user should hardwire the LBWSET
pin high and use 1 μF capacitors to set the actual loop bandwidth.
These capacitors are placed between the PAVCAP and ERCAP
pins and ground. It is important that these capacitors be low
leakage multilayer ceramics with an insulation resistance greater
than 100 GΩ or a time constant of 1000 sec, whichever is less.
The ADN2841 can be optimized for 2.7 Gbps operation by
keeping the LBWSET pin low. This results in a much shorter
loop time constant (a 10× reduction). The value of the PAVCAP
and ERCAP capacitors required for 2.7 Gbps operation is 22 nF.
P1 + P0
2
PAV
Note that IERSET and IPSET change from device to device. However,
the control loops determine the actual values. It is not required
to know the exact values for LI or MPD optical coupling.
Figure 7. Laser Transfer Function
CONTROL
ALARMS
A monitor photodiode (MPD) is required to control the LD.
The MPD current is fed into the ADN2841 to control the
optical power and extinction ratio, continuously adjusting the
bias current and modulation current in response to the laser’s
changing threshold current and light-to-current (LI) slope
(slope efficiency).
The ADN2841 alarms are designed to allow interface compliance
to ITU-T G.958 (11/94), Section 10.3.1.1.2 (transmit fail) and
Section 10.3.1.1.3 (transmit degrade). The ADN2841 has two
active high alarms, DEGRADE and FAIL. A resistor between
ground and the ASET pin is used to set the current at which
these alarms are raised. The current through the ASET resistor
is a ratio of 100:1 to the FAIL alarm threshold. The DEGRADE
alarm will be raised at 90% of this level.
The ADN2841 uses automatic power control (APC) to maintain
a constant power over time and temperature.
The ADN2841 uses closed-loop extinction ratio control to
allow optimum setting of extinction ratio for every device.
Therefore, SONET/SDH interface standards can be met over
device variation, temperature, and time. Closed-loop modulation control eliminates the need to overmodulate the LD or
to include external components for temperature compensation.
This reduces research and development time and secondsourcing issues caused by characterizing LDs.
Average power and extinction ratio are set using the PSET and
ERSET pins, respectively. Potentiometers are connected between
these pins and ground. The potentiometer RPSET is used to change
the average power. The potentiometer RERSET is used to adjust
the extinction ratio. Both PSET and ERSET are kept 1.23 V
above GND.
RPSET and RERSET can be calculated using the following formulas:
R PSET =
1.23 V
I AV
where IAV is the average MPD current.
R ERSET =
I MPD _ CW
PCW
×
1.23 V
ER − 1
ER + 1
Example:
I FAIL = 50 mA ∴ I DEGRADE = 45 mA
I ASET =
R ASET =
1.23 V
I ASET
=
1.23 V
500 μA
= 2.46 kΩ
Note that the smallest value for RASET is 1.2 kΩ, because this
value corresponds to the IBIAS maximum of 100 mA.
The laser degrade alarm, DEGRADE, gives a warning of
imminent laser failure if the laser diode degrades further
or if environmental conditions—for example, increasing
temperature—continue to stress the LD.
The laser fail alarm, FAIL, is activated when the transmitter can
no longer be guaranteed to be SONET/SDH compliant. This
occurs when one of the following conditions arises:
•
•
× 0.2 × PAV
where
IMPD_CW is the MPD current at the specified PCW.
PCW is the dc optical power specified on the laser data sheet.
PAV is the required average power.
I BIASTRIP 50 mA
=
= 500 μA
100
100
The ASET threshold is reached.
The ALS pin is set high. This shuts off the modulation
and bias currents to the LD, resulting in the MPD current
dropping to 0. This gives closed-loop feedback to the
system in which ALS has been enabled.
The DEGRADE pin goes high only when the bias current
exceeds 90% of the ASET current.
Rev. C | Page 9 of 16
ADN2841
Data Sheet
If the monitor current functions IMPDMON and IMPDMON2
are not required, the IMPD and IMPD2 pins can be grounded,
and the monitor photodiode output can be connected directly
to PSET.
MONITOR CURRENTS
IBMON, IMMON, IMPDMON, and IMPDMON2 are current
controlled current sources from VCC. They mirror the bias, modulation, and MPD current for increased monitoring functionality.
An external resistor to GND gives a voltage proportional to the
current monitored.
IDTONE (48-LEAD LFCSP ONLY)
The IDTONE pin is supplied for fiber identification/supervisory
channels or control purposes in WDM. This pin modulates the
Optical 1 level over a possible range of 2% of minimum IMOD to
10% of maximum IMOD. The level of modulation is set by connecting an external current sink between the IDTONE pin and ground.
There is a gain of 2 from this pin to the IMOD current.
DUAL MPD DWDM FUNCTION (48-LEAD LFCSP
ONLY)
The ADN2841 has circuitry for an optional second monitor
photodiode, MPD2. The second photodiode current is mirrored
to IMPDMON2 for wavelength control purposes and is summed
internally for the power control loop. For single MPD circuits,
the IMPD2 pin is tied to GND.
Figure 8 shows how an AD9850/AD9851 DDS can be used with
the ADN2841 to allow fiber identification.
Note that using IDTONE during transmission may cause
optical eye degradation.
The second monitor photodiode enables the system designer to
use the two currents to control the wavelength of the laser diode
using various optical filtering techniques inside the laser module.
REF CLOCK
20MHz TO 180MHz
10kHz TO 1MHz
9
1.25mA TO 20mA
AD9850/AD9851
21
IOUT
DDS
20
RSET
12
IOUTB
AD8602
LP FILTER
(DC-COUPLED)
50Ω
1/2
35
IDTONE
0.125mA TO 2mA
BC550
ADN2841
50Ω
500Ω
37.5µA TO 600µA
AD8602
CONTROLLER
50µA TO 800µA
32
1/2
BC550
1.3kΩ
Figure 8. Circuitry to Allow Fiber Identification
Rev. C | Page 10 of 16
1kΩ
IMMON
02659-006
CLKIN
Data Sheet
ADN2841
DATA AND CLOCK INPUTS
ALARM INTERFACES
Data and clock inputs are ac-coupled (10 nF recommended)
and terminated via a 100 Ω internal resistor between the DATAP
and DATAN pins and also between the CLKP and CLKN pins.
A high impedance circuit sets the common-mode voltage that
is designed to change over temperature. It is recommended that
ac coupling be used to eliminate the need for matching between
common-mode voltages.
A 30 kΩ internal pull-up resistor is used to pull the digital high
value of the alarm outputs to VCC. However, the ADN2841 has a
feature that allows the user to externally wire resistors in parallel
with the 30 kΩ pull-up resistors, thus enabling the user to interface to non-VCC levels. Non-VCC alarm output levels must be
below the VCC used for the ADN2841.
The ADN2841 die temperature must be kept below 125°C. The
θJA is 25°C/W for the 48-lead LFCSP and 32°C/W for the 32-lead
LFCSP when soldered on a 4-layer board. Both LFCSP packages
have an exposed pad and, therefore, must be soldered to the PCB
to achieve this thermal performance.
ADN2841
DATAP
TO FLIP-FLOPS
DATAN
50Ω
VREG
TDIE = TAMBIENT + (θJA × P)
R
R = 2.5kΩ, DATA
R = 3kΩ, CLK
ICC = ICCMIN + (0.3 × IMOD)
P = VCC × ICC + (IBIAS × VIBIAS) + (IMOD × VIMODx)
400µA TYP
02659-007
Thus, the maximum combination of IBIAS + IMOD must be
calculated.
VCC
Figure 9. AC Coupling of Data Inputs
CCBIAS
VCC
CCBIAS should be connected to the IBIAS pin if the laser diode
is connected to the ADN2841 using a capacitor. CCBIAS is a
current sink to GND.
ADN2841
ADN2850
Rx
SDO
CLK
CLK
CS
IMODP
IBIAS
DAC1
PSET
DAC2
ERSET
IDTONE
SDI
DATAN
The ADN2841 ALS pin allows compliance with ITU-T G.958
(11/94), Section 9.7. When ALS is logic high, both bias and
modulation currents are turned off.
Tx
DATAP
AUTOMATIC LASER SHUTDOWN
Correct operation of ALS can be confirmed by the FAIL alarm
being raised when ALS is asserted. Note that this is the only
time that DEGRADE will be low while FAIL is high.
VCC
IMPD
CS
DATAP
DATAN
IDTONE
02659-008
50Ω
POWER CONSUMPTION
Figure 10. Application Using Optical Supervisor ADN2850 as a Dual, 10-Bit
Digital Potentiometer Using Thin Film Resistor Technology to Give Very Low
Temperature Coefficients
Rev. C | Page 11 of 16
ADN2841
Data Sheet
APPLICATION CIRCUITS
FAIL
DEGRADE
VCC
VCC
25
GND
CLKSEL
DEGRADE
ALS
FAIL
VCC3
GND3
IBMON
IMMON
GND2
GND2
GND2
37
IDTONE
36
GND
VCC2
25Ω
CLKN
CLKN
IMODN
CLKP
CLKP
GND2
GND1
IMODN
FU-445SDF-WM1
VCC
IMODP
ADN2841
IMODP
DATAN
DATAN
GND2
VCC1
1
ERCAP
GND4
IMPD2
IMPDMON2
IMPDMON
IMPD
CCBIAS
GND
PAVCAP
PSET
GND
IBIAS
ERSET
IBIAS
ASET
48
DATAP
GND1
LBWSET
VCC
DATAP
GND2
GND
VCC
GND
GND
VCC4
VCC
24
13
12
1.5kΩ
VCC
NOTES
1. PLACE DECOUPLING CAPACITORS AS CLOSE AS POSSIBLE TO THE
ACTUAL SUPPLY PINS OF THE ADN2841 AND THE LASER DIODE USED.
100nF
100nF
100nF
GND
Figure 11. 2.7 Gbps Test Circuit, DC-Coupled, Data Not Clocked, Fast Loop Time Constant Selected
Rev. C | Page 12 of 16
10µF
02659-009
100nF
Data Sheet
ADN2841
FAIL
DEGRADE
VCC
VCC
25
GND
CLKSEL
DEGRADE
ALS
FAIL
VCC3
GND3
IBMON
IMMON
GND2
GND2
GND2
37
IDTONE
36
GND
VCC2
CLKN
CLKN
IMODN
CLKP
CLKP
GND2
GND1
IMODN
VCC
IMODP
VCC
ADN2841
IMODP
DATAN
GND1
GND2
VCC1
IMPD2
1
ERCAP
GND4
IMPDMON2
IMPDMON
CCBIAS
IMPD
PAVCAP
ERSET
GND
IBIAS
ASET
IBIAS
GND
48
DATAP
GND2
LBWSET
VCC
DATAP
DATAN
VCC4
25Ω
GND
VCC
GND
GND
PSET
VCC
24
13
12
VCC
1.5kΩ
VCC
100nF
100nF
100nF
100nF
GND
Figure 12. Anyrate Test Circuit, Capacitively Coupled, Data Clocked, Slow Loop Time Constant Selected
Rev. C | Page 13 of 16
10µF
02659-010
NOTES
1. PLACE DECOUPLING CAPACITORS AS CLOSE AS POSSIBLE TO THE
ACTUAL SUPPLY PINS OF THE ADN2841 AND THE LASER DIODE USED.
ADN2841
Data Sheet
VCC
VCC
VCC
75Ω
32Ω
EA MODULATOR
10nF
100nH
VCC
VCC
GND2
VCC2
IMODN
IMODN
GND2
IMODP
GND2
IBIAS
GND2
IMODP
GND
IBIAS
1
37
CCBIAS
48
GND2
GND2
ASET
ERSET
IBMON
PSET
IMMON
GND
GND3
ADN2841
IMPD
ALS
FAIL
IMPDMON2
VCC
24
VCC
VCC
8
25
GND
GND
CLKP
13
CLKN
GND
GND1
DATAP
DATAN
GND1
VCC4
VCC1
CLKSEL
GND
GND4
PAVCAP
DEGRADE
ERCAP
IMPD2
12
VCC
VCC3
IMPDMON
VCC
VCC
IDTONE
LBWSET
VCC
36
VCC
2
1
1/2
OP293
1/2
OP293
3
DAC
1kΩ
6
7
5
DAC
1kΩ
NOTES
1. PLACE DECOUPLING CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL
SUPPLY PINS OF THE ADN2841 AND THE LASER DIODE USED.
2. THE OP293 HAS BEEN SELECTED BECAUSE OF ITS GAIN BANDWIDTH PRODUCT
AND SHOULD BE USED IN THIS APPLICATION.
Figure 13. Applications Circuit
Rev. C | Page 14 of 16
02659-011
–V CC
Data Sheet
ADN2841
OUTLINE DIMENSIONS
7.10
7.00 SQ
6.90
DETAIL A
(JEDEC 95)
0.30
0.23
0.18
PIN 1
INDICATOR
37
36
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
48
1
0.50
BSC
5.20
5.10 SQ
5.00
EXPOSED
PAD
12
0.80
0.75
0.70
END VIEW
PKG-004509
SEATING
PLANE
24
13
0.25 MIN
BOTTOM VIEW
5.50 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-22-2017-B
TOP VIEW
0.45
0.40
0.35
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4
Figure 14. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
25
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
32
24
1
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
PKG-003898
SEATING
PLANE
SIDE VIEW
0.50
0.40
0.30
8
9
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD
Figure 15. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
Rev. B | Page 15 of 16
0.25 MIN
02-22-2017-A
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
ADN2841
Data Sheet
ORDERING GUIDE
Model 1
ADN2841ACPZ-32
ADN2841ACPZ-32-RL7
ADN2841ACPZ-48
ADN2841ACPZ-48-RL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead LFCSP
32-Lead LFCSP
48-Lead LFCSP
48-Lead LFCSP
Z = RoHS Compliant Part.
©2001–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02659–0–2/17(C)
Rev. C | Page 16 of 16
Package Option
CP-32-7
CP-32-7
CP-48-4
CP-48-4
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