3.3 V, 4.25 Gbps,
Limiting Amplifier
ADN2892
Data Sheet
FEATURES
GENERAL DESCRIPTION
Input sensitivity: 3.5 mV p-p
70 ps rise/fall times
CML outputs: 750 mV p-p differential
Bandwidth selectable for multirate 1×/2×/4× FC modules
Optional LOS output inversion
Programmable LOS detector: 3.5 mV to 35 mV
Rx signal strength indicator (RSSI)
SFF-8472-compliant average power measurement
Single-supply operation: 3.3 V
Low power dissipation: 160 mW
Available in space-saving, 3 mm × 3 mm, 16-lead LFCSP
Extended temperature range: −40°C to +95°C
SFP reference design available
The ADN2892 is a 4.25 Gbps limiting amplifier with integrated
loss of signal (LOS) detection circuitry and a received signal
strength indicator (RSSI). This part is optimized for Fibre
Channel (FC) and Gigabit Ethernet (GbE) optoelectronic
conversion applications. The ADN2892 has a differential input
sensitivity of 3.5 mV p-p and accepts up to a 2.0 V p-p
differential input overload voltage. The ADN2892 has current
mode logic (CML) outputs with controlled rise and fall times.
The ADN2892 has a selectable low-pass filter with a −3 dB
cutoff frequency of 1.5 GHz. By setting BW_SEL to Logic 0, the
filter can limit the relaxation oscillation of a low cost CD laser
used in a legacy 1 Gbps FC transmitter. The limited BW also
reduces the rms noise and in turn improves the receiver optical
sensitivity for a lower data rate application, such as 1× FC and
GbE.
APPLICATIONS
1×, 2×, and 4× FC transceivers
SFP/SFF/GBIC optical transceivers
GbE transceivers
Backplane receivers
By monitoring the bias current through a photodiode, the onchip RSSI detector measures the average power received with
2% typical linearity over the entire valid input range of the
photodiode. The on-chip RSSI detector facilitates SFF-8472compliant optical transceivers by eliminating the need for
external RSSI detector circuitry.
Additional features include a programmable loss-of-signal
(LOS) detector and output squelch. The ADN2892 is available
in a 3 mm × 3 mm, 16-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
AVCC
AVEE
BW_SEL
SQUELCH
DRVCC
DRVEE
ADN2892
50Ω
50Ω
OUTP
PIN
NIN
OUTN
LPF
50Ω
50Ω
V+
3.5kΩ
PD_VCC
PD_CATHODE
VREF
LOS
RSSI/LOS
DETECTOR
THRADJ
RSSI_OUT
LOS_INV
10kΩ
ADuC7020
04986-001
ADN2882
Figure 1. RSSI Function Capable—Applications Setup Block Diagram
Rev. C
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Tel: 781.329.4700 ©2005–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADN2892
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Limiting Amplifier ..................................................................... 10
Applications ....................................................................................... 1
Loss-of-Signal (LOS) Detector ................................................. 10
General Description ......................................................................... 1
Received Signal Strength Indicator (RSSI) ............................. 10
Functional Block Diagram .............................................................. 1
Squelch Mode ............................................................................. 10
Revision History ............................................................................... 2
BW_SEL (Bandwidth Selection) Mode ................................... 10
Specifications..................................................................................... 3
LOS_INV (Lose of Signal_Invert) Mode ................................ 10
Absolute Maximum Ratings ............................................................ 5
Applications Information .............................................................. 11
Thermal Resistance ...................................................................... 5
PCB Design Guidelines ............................................................. 11
ESD Caution .................................................................................. 5
Pad Coating and Pb-Free Soldering ........................................ 12
Pin Configuration and Function Descriptions ............................. 6
Outline Dimensions ....................................................................... 13
Typical Performance Characteristics ............................................. 7
Ordering Guide .......................................................................... 13
Theory of Operation ...................................................................... 10
REVISION HISTORY
3/2017—Rev. B to Rev. C
Changes to Figure 2 .......................................................................... 6
Changes to Figure 18 ...................................................................... 11
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 13
7/2013—Rev. 0 to Rev. A
Change to Output Voltage Swing Parameter, Table 1 ...................3
Changes to Figure 2 ...........................................................................6
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 13
2/2014—Rev. A to Rev. B
Changes to Figure 2 .......................................................................... 6
4/2005—Revision 0: Initial Version
Rev. C | Page 2 of 16
Data Sheet
ADN2892
SPECIFICATIONS
Test Conditions: VCC = 2.9 V to 3.6 V, VEE = 0 V, TA = −40°C to +95°C, unless otherwise noted.
Table 1.
Parameter
QUANTIZER DC CHARACTERISTICS
Input Voltage Range
Input Common Mode
Peak-to-Peak Differential Input Range
Input Sensitivity
Input Offset Voltage
Input RMS Noise
Input Resistance
Input Capacitance
QUANTIZER AC CHARACTERISTICS
Input Data Rate
Small Signal Gain
S11
S22
Random Jitter
Deterministic Jitter
Low Frequency Cutoff
Power Supply Rejection
LOSS OF SIGNAL DETECTOR (LOS)
LOS Assert Level
Electrical Hysteresis
LOS Assert Time
LOS Deassert Time
RSSI
Input Current Range
RSSI Output Linearity
Gain
Offset
Compliance Voltage (At PD_CATHODE)
Min
VCC − 1.2
2.1
6.6
Max
Unit
Test Conditions/Comments
VCC − 0.2
2.7
2.0
V
V
V p-p
mV p-p
µV
µV rms
Ω
pF
At PIN or NIN, dc-coupled
DC-coupled
PIN − NIN, ac-coupled
PIN − NIN, BER ≤ 1 × 10−10
3.5
100
235
50
0.65
1.0
4.25
51
−10
−10
3.0
10
30
45
2.9
22.4
2.5
2.8
3.5
35
5.0
5.0
950
62
5
3.9
21.0
mV p-p
mV p-p
dB
dB
ns
ns
1000
µA
%
mA/mA
nA
V
V
VCC − 0.4
VCC − 0.9
1.5
2.9
−40
600
Gbps
dB
dB
dB
ps rms
ps p-p
kHz
dB
4.8
55.0
2
1.0
145
BW_SEL (BANDWIDTH SELECTION)
Channel Bandwidth
POWER SUPPLIES
VCC
ICC
OPERATING TEMPERATURE RANGE
CML OUTPUT CHARACTERISTICS
Output Impedance
Output Voltage Swing
Output Rise and Fall Time
Typ
GHz
Single-ended
Differential
Differential, f < 4.25 GHz
Differential, f < 4.25 GHz
Input ≥ 10 mV p-p, 4× FC, K28.7 pattern
Input ≥ 10 mV p-p, 4× FC, K28.5 pattern
100 kHz < f < 10 MHz
RTHRADJ = 100 kΩ
RTHRADJ = 1 kΩ
1.0 Gbps, PRBS 223 − 1
4× FC, PRBS 223 − 1
DC-coupled
DC-coupled
5 µA ≤ IIN ≤ 1000 µA
IRSSI/IPD_CATHODE
IPD_CATHODE = 5 µA
IPD_CATHODE = 1000 µA
−3 dB cutoff frequency of the on-chip,
two-pole, low-pass filter, when BW_SEL = 0
3.3
48
+25
3.6
54
+95
V
mA
°C
TMIN to TMAX
50
750
70
940
103
Ω
mV p-p
ps
Single-ended
Differential
20% to 80%
Rev. C | Page 3 of 16
ADN2892
Parameter
LOGIC INPUTS (SQUELCH, LOS_INV, AND BW_SEL)
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current (SQUELCH, LOS_INV)
Data Sheet
Min
VOL, Output Low Voltage
Max
Unit
0.8
39
V
V
µA
−38
µA
2.0
Input Current (BW_SEL)
LOGIC OUTPUTS (LOS)
VOH, Output High Voltage
Typ
2.4
V
0.4
Rev. C | Page 4 of 16
V
Test Conditions/Comments
IINH, VIN = 2.4 V, 100 kΩ pull-down,
on-chip resistor
IINL, VIN = 0.0 V, 100 kΩ pull-up,
on-chip resistor
Open drain output, 4.7 kΩ − 10 kΩ
pull-up resistor to VCC
Open drain output, 4.7 kΩ − 10 kΩ
pull-up resistor to VCC
Data Sheet
ADN2892
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Power Supply Voltage
Minimum Voltage (All Inputs and Outputs)
Maximum Voltage (All Inputs and Outputs)
Storage Temperature
Operating Temperature Range
Production Soldering Temperature
Junction Temperature
Rating
4.2 V
VEE − 0.4 V
VCC + 0.4 V
−65°C to +150°C
−40°C to +95°C
J-STD-20
125°C
θJA is specified for 4-layer PCB with exposed paddle soldered
to GND.
Table 3.
Package Type
3 mm × 3 mm, 16-lead LFCSP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 5 of 16
θJA
28
Unit
°C/W
ADN2892
Data Sheet
13 SQUELCH
14 RSSI_OUT
16 PD_CATHODE
15 PD_VCC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12 DRVCC
AVCC 1
PIN 2
ADN2892
11 OUTP
NIN 3
TOP VIEW
(Not to Scale)
10 OUTN
9
DRVEE
NOTES
1. THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO
THE GND PLANE WITH FILLED VIAS.
04986-002
LOS 8
LOS_INV 7
THRADJ 5
BW_SEL 6
AVEE 4
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
AVCC
PIN
NIN
AVEE
THRADJ
BW_SEL
LOS_INV
I/O Type1
P
AI
AI
P
AO
DI
DI
8
9
10
11
12
13
14
15
16
Exposed Pad
LOS
DRVEE
OUTN
OUTP
DRVCC
SQUELCH
RSSI_OUT
PD_VCC
PD_CATHODE
Pad
DO
P
DO
DO
P
DI
AO
P
AO
P
1
Description
Analog Power Supply.
Differential Data Input, Positive Port, 50 Ω On-Chip Termination.
Differential Data Input, Negative Port, 50 Ω On-Chip Termination.
Analog Ground.
LOS Threshold Adjust Resistor.
With one 100 kΩ on-chip, pull-up resistor, BW_SEL = 0 for 1×/2× FC, BW_SEL = 1 for 4× FC.
With one 100 kΩ on-chip, pull-down resistor, LOS_INV = 1 inverts the LOS output
to be active low for SFF.
LOS Detector Output, Open Collector.
Output Buffer Ground.
Differential Data Output, CML, Negative Port, 50 Ω, On-Chip Termination.
Differential Data Output, CML, Positive Port, 50 Ω, On-Chip Termination.
Output Buffer Power Supply.
Disable Outputs, 100 kΩ On-Chip, Pull-Down Resistor.
Average Current Output.
Power Input for RSSI Measurement.
Photodiode Bias Voltage.
Connect to Ground.
P = power; DI = digital input; DO = digital output; AI = analog input; and AO = analog output.
Rev. C | Page 6 of 16
Data Sheet
ADN2892
TYPICAL PERFORMANCE CHARACTERISTICS
0.06
+95C
150mV/DIV
TRIP AND RELEASE (V)
0.05
+25C
0.04
0.03
–40C
0.02
DEASSERTION
–40C
+25C
+95C
0
1k
50ps/DIV
Figure 3. Eye of ADN2892 at 25°C, 4.25 Gbps, and 10 mV Input
04986-026
04986-012
0.01
ASSERTION
10k
RTH ()
100k
Figure 6. LOS Trip and Release vs. RTH at 4.25 Gbps
8
04986-023
150mV/DIV
ELECTRICAL HYSTERESIS (dB)
7
1GBPS
6
5
4.25GBPS
4
3
2
0
1k
50ps/DIV
Figure 4. Eye of ADN2892 at 95°C, 4.25 Gbps, and 10 mV Input
04986-027
1
10k
RTH ()
100k
Figure 7. LOS Electrical Hysteresis vs. RTH at 25°C
16
14
12
SAMPLES
150mV/DIV
10
8
6
200ps/DIV
2
04986-024
04986-010
4
0
5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6
ELECTRICAL HYSTERESIS (dB)
Figure 5. Eye of ADN2892 at 25°C, 1.063 Gbps, and 10 mV Input (BW_SEL = 0)
Rev. C | Page 7 of 16
Figure 8. Sample Lot Distribution—Worst-Case Condition:
Conditions = 4.25 Gbps, 100 kΩ at −40°C, 3.6 V
ADN2892
Data Sheet
1200
4.0
3.5
RSSI OUTPUT CURRENT (A)
1000
2.5
2.0
1.5
1.0
600
400
200
04986-028
0.5
0
1.0
800
1.5
2.0
2.5
3.0
RATE (Gbps)
3.5
4.0
04986-017
JITTER (ps)
3.0
0
4.5
0
Figure 9. Random Jitter vs. Data Rate
200
400
600
800
1000
PD_CATHODE CURRENT (PHOTODIODE CURRENT) (A)
Figure 12. RSSI Output vs. Average Photodiode Current
60
18
16
50
RSSI OUTPUT CURRENT (A)
14
JITTER (ps)
12
10
8
6
4
40
30
20
1.5
2.0
2.5
3.0
RATE (Gbps)
3.5
4.0
0
4.5
0
Figure 13. RSSI Output vs. Average Photodiode Current (Zoomed)
Figure 10. Deterministic Jitter vs. Data Rate
COMPLIANCE VOLTAGE REFERRED TO VCC (V)
60
50
40
30
20
0
100k
04986-016
POWER SUPPLY-NOISE REJECTION (dB)
70
10
1M
SUPPLY-NOISE FREQUENCY
10
20
30
40
50
PD_CATHODE CURRENT (PHOTODIODE CURRENT) (A)
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
–0.50
–0.55
–0.60
04986-018
0
1.0
04986-020
04986-029
10
2
–0.65
–0.70
0
10M
Figure 11. PSRR vs. Supply-Noise Frequency
100
200
300 400 500 600 700
INPUT CURRENT (A)
800
900
Figure 14. PD_CATHODE Compliance Voltage vs.
Input Current RSSI (Refer to VCC)
Rev. C | Page 8 of 16
1000
Data Sheet
ADN2892
900
49.0
800
600
48.0
ICC (mA)
5A REFERRED OFFSET (nA)
48.5
700
500
400
47.5
47.0
300
200
0
–40
–20
0
20
40
TEMPERATURE (C)
60
80
46.0
–40
100
Figure 15. RSSI Offset—Difference Between Measured RSSI Output and
PD_CATHODE (Input) Current of 5 μA
5.0
4.5
3.5
3.0
2.5
+100C
2.0
+30C
1.5
1.0
0.5
–40C
0
0
200
400
600
PD_CATHODE CURRENT (A)
800
04986-021
RSSI LINEARITY (%)
4.0
1000
Figure 16. RSSI Linearity % vs. PD_CATHODE Current
Rev. C | Page 9 of 16
04986-025
04986-019
46.5
100
–20
0
20
40
TEMPERATURE (C)
60
80
Figure 17. ADN2892 ICC Current vs. Temperature
100
ADN2892
Data Sheet
THEORY OF OPERATION
LIMITING AMPLIFIER
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)
Input Buffer
The ADN2892 has an on-chip, RSSI circuit. By monitoring the
current supplied to the photodiode, the RSSI circuit provides an
accurate, average power measurement. The output of the RSSI is a
current that is directly proportional to the average amount of PIN
photodiode current. Placing a resistor between the RSSI_OUT pin
and GND converts the current to a GND referenced voltage. This
function eliminates the need for external RSSI circuitry for SFF8472-compliant optical receivers. For more information, see
Figure 12 to Figure 16.
The ADN2892 limiting amplifier provides differential inputs
(PIN/NIN), each with a single-ended, on-chip 50 Ω termination.
The amplifier can accept either dc-coupled or ac-coupled signals;
however, an ac-coupled signal is recommended. Using a dccoupled signal, the amplifier needs a nominal VCC − 0.7 V
common-mode voltage and ±0.5 V headroom. If the input
common-mode voltage is 2.4 V, the available headroom is reduced
down to ±0.3 V.
The ADN2892 limiting amplifier is a high gain device. It is
susceptible to dc offsets in the signal path. The pulse width
distortion presented in the NRZ data or a distortion generated by
the TIA may appear as dc offset or a corrupted signal to the
ADN2892 inputs. An internal offset correction loop can
compensate for certain levels of offset.
CML Output Buffer
The ADN2892 provides differential CML outputs, OUTP and
OUTN. Each output has an internal 50 Ω termination to VCC.
Connect the PD_VCC, PD_CATHODE, and RSSI_OUT pins to
AVCC to disable the RSSI feature.
SQUELCH MODE
Driving the SQUELCH input to logic high disables the limiting
amplifier outputs. Using LOS output to drive the SQUELCH
input, the limiting amplifier outputs stop toggling anytime a
signal input level to the limiting amplifier drops below the
programmed LOS threshold.
The SQUELCH pin has a 100 kΩ, internal pull-down resistor.
LOSS-OF-SIGNAL (LOS) DETECTOR
BW_SEL (BANDWIDTH SELECTION) MODE
The on-chip LOS circuit drives LOS to logic high when the
input signal level falls below a user-programmable threshold.
The threshold level can be set anywhere from 3.5 mV p-p to
35 mV p-p typical by a resistor connected between the
THRADJ pin and VEE. See Figure 6 and Figure 7 for the LOS
threshold vs. THRADJ. The ADN2892 LOS circuit has an
electrical hysteresis greater than 2.5 dB to prevent chatter at the
LOS signal. The LOS output is an open-collector output that
must be pulled up externally with a 4.7 kΩ to 10 kΩ resistor.
Driving the BW_SEL input signal to logic high, the amplifier
provides a 3.8 GHz bandwidth. Driving the BW_SEL input
signal to logic low, the amplifier accepts input signals through a
1.5 GHz, 2-pole, low-pass filter that improves receiving
sensitivity.
The low-pass filter reduces the possible relaxation oscillation of
low speed, low cost laser source by limiting the input signal
bandwidth.
The BW_SEL pin has a 100 kΩ, on-chip pull-up resistor. Setting
the BW_SEL pin open disables the low-pass filter.
LOS_INV (LOSE OF SIGNAL_INVERT) MODE
Some applications, such as SFF, need the LOS assertion and
deassertion voltage reversed. When the LOS_INV pin is pulled
to logic high, the LOS output assertion is pulled down to
electrical low.
The LOS_INV pin has a 100 kΩ on-chip, pull-down resistor.
Rev. C | Page 10 of 16
Data Sheet
ADN2892
APPLICATIONS INFORMATION
The exposed pad should connect to the GND plane using filled
vias so that solder does not leak through the vias during reflow.
Using filled vias in parallel under the package greatly reduces
the thermal resistance and enhances the reliability of the
connectivity of the exposed pad to the GND plane during
reflow.
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used to ensure
optimal performance.
Output Buffer Power Supply and Ground Planes
Pin 9 (DRVEE) and Pin 12 (DRVCC) are the power supply and
ground pins that provide current to the differential output buffer.
To reduce possible series inductance, Pin 9, which is the ground
return of the output buffer, should connect to ground directly. If the
ground plane is an internal plane and connections to the ground
plane are vias, multiple vias in parallel to ground can reduce series
inductance.
To reduce power supply noise, a 10 μF electrolytic decoupling
capacitor between power and ground should be close to where the
3.3 V supply enters the PCB. The other 0.1 μF and 1 nF ceramic
chip decoupling capacitors should be close to the VCC and VEE
pins to provide optimal supply decoupling and a shorter current
return loop.
Similarly, to reduce the possible series inductance, Pin 12, which
supplies power to the high speed differential OUTP/OUTN output
buffer, should connect to the power plane directly. If the power
plane is an internal plane and connections to the power plane are
vias, multiple vias in parallel can reduce the series inductance,
especially on Pin 12. See Figure 18 for the recommended
connections.
VCC
16
C2
NIN
AVEE
12
2
CONNECT
EXPOSED
PAD TO
GND
11
10
4
9
5
C12
VCC
ADN2892
3
6
R2
RSSI MEASUREMENT
TO ADC
C7
7
C8
DRVCC
OUTP
C3
TO HOST
BOARD
OUTN C4
DRVEE
8
LOS
PIN
C10
13
1
THRADJ
ADN2882
C1
14
LOS_INV
AVCC
15
R1
C1 TO C4, C11: 0.01µF, X5R/X7R DIELECTRIC, 0201 CASE
C5, C7, C9, C10, C12: 0.1µF, X5R/X7R DIELECTRIC, 0402 CASE
C6, C8: 1nF, X5R/X7R DIELECTRIC, 0201 CASE
R3
4.7kΩ TO 10kΩ
ON HOST BOARD
VCC
TO ADuC7020
Figure 18. Typical ADN2892 Applications Circuit
Rev. C | Page 11 of 16
04986-008
C6
BW_SEL
C5
SQUELCH
VCC
PD_VCC
PD_CATHODE
0.1µF
RSSI_OUT
C9
VCC
ADN2892
Data Sheet
PCB Layout
Soldering Guidelines for the LFCSP
Figure 19 shows the recommended PCB layout. The 50 Ω
transmission lines are the traces that bring the high frequency
input and output signals (PIN, NIN, OUTP, and OUTN) from a
terminated source to a terminated load with minimum reflection.
To avoid a signal skew between the differential traces, each
differential PIN/NIN and OUTP/OUTN pair should have
matched trace lengths from a differential source to a differential
load. C1, C2, C3, and C4 are ac coupling capacitors in series
with the high speed, signal input/output paths. To minimize the
possible mismatch, the ac coupling capacitor pads should be the
same width as the 50 Ω transmission line trace width. To reduce
supply noise, a 1 nF decoupling capacitor should be placed as
close as possible to the VCC pins on the same layer and not
through vias. A 0.1 µF decoupling capacitor can be placed on
the bottom of the PCB directly underneath the 1 nF capacitor.
All high speed, CML outputs have internal 50 Ω resistor
termination between the output pin and VCC. The high speed
inputs, PIN and NIN, also have the internal 50 Ω termination to
an internal reference voltage.
The lands on the 16-lead LFCSP are rectangular. The PCB pad
for these should be 0.1 mm longer than the package land length
and 0.05 mm wider than the package land width. The land should
be centered on the pad. This ensures that the solder joint size is
maximized. The bottom of the LFCSP has a central exposed pad.
The pad on the printed circuit board should be at least as large
as the exposed pad. Users must connect the exposed pad to VEE
using filled vias so that solder does not leak through the vias
during reflow. This ensures a solid connection from the exposed
pad to VEE.
PAD COATING AND PB-FREE SOLDERING
Table 5.
Pad Coating
Pb-Free Reflow Portfolio
Matt-Tin
J-STD-20B
As with any high speed, mixed-signal design, keep all high
speed digital traces away from sensitive analog nodes.
R1, C9, C10 ON BOTTOM
DVCC GND DOUBLE-VIAS TO REDUCE
INDUCTANCE TO SUPPLY
AND GND
TO ROSA
GND
AVCC
PLACE C5 ON
BOTTOM OF BOARD
UNDERNEATH C6
C1
1
PLACE C7 ON
BOTTOM OF BOARD
UNDERNEATH C8
EXPOSED PAD
C8
C6
C3
PIN
NIN
OUTN
C4
C2
TRANSMISSION LINES SAME
WIDTH AS AC COUPLING
CAPS TO REDUCE REFLECTIONS
DOUBLE-VIA TO GND
TO REDUCE INDUCTANCE
VIA TO C12, R2
ON BOTTOM
VIAS TO BOTTOM
Figure 19. Recommended ADN2892 PCB Layout (Top View)
Rev. C | Page 12 of 16
04986-009
∼4mm
OUTP
FILLED VIAS TO
GND
Data Sheet
ADN2892
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.20
0.50
BSC
13
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
16
12
1
1.65
1.50 SQ
1.45
EXPOSED
PAD
9
TOP VIEW
0.80
0.75
0.70
TOP VIEW
4
8
5
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-004395
0.50
0.40
0.30
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
02-06-2017-A
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
Figure 20. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-27)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADN2892ACPZ-500RL7
ADN2892ACPZ-RL7
EVAL-ADN2892EBZ
1
Temperature Range
–40°C to +95°C
–40°C to +95°C
Package Description
16-Lead LFCSP, 500 pieces
16-Lead LFCSP, 1,500 pieces
Evaluation Board
Z = RoHS-Compliant Part.
Rev. C | Page 13 of 16
Package Option
CP-16-27
CP-16-27
Branding
F05
F05
ADN2892
Data Sheet
NOTES
Rev. C | Page 14 of 16
Data Sheet
ADN2892
NOTES
Rev. C | Page 15 of 16
ADN2892
Data Sheet
NOTES
©2005–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04986-0-3/17(C)
Rev. C | Page 16 of 16
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