Continuous Rate 6.5 Mbps to 8.5 Gbps Clock and
Data Recovery IC with Integrated Limiting Amp/EQ
ADN2913
Data Sheet
FEATURES
GENERAL DESCRIPTION
Serial data input: 6.5 Mbps to 8.5 Gbps
No reference clock required
Exceeds SONET/SDH requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 6.3 mV typical (limiting amplifier mode)
Optional limiting amplifier, equalizer (EQ), and 0 dB EQ inputs
Programmable jitter transfer bandwidth to support G.8251 OTN
Programmable slice level
Sample phase adjust (5.65 Gbps or greater)
Output polarity invert
Programmable LOS threshold via I2C
I2C interface to access optional features
Loss of signal (LOS) alarm (limiting amplifier mode only)
Loss of lock (LOL) indicator
PRBS generator/detector
Application aware power
352 mW at 8.5 Gbps, equalizer mode, no clock output
380 mW at 6.144 Gbps, limiting amplifier mode,
no clock output
340 mW at 622 Mbps, 0 dB EQ mode, no clock output
Power supplies: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V
4 mm × 4 mm, 24-lead LFCSP
The ADN2913 provides the receiver functions of quantization,
signal level detection, and clock and data recovery for continuous
data rates from 6.5 Mbps to 8.5 Gbps. The ADN2913 automatically
locks to all data rates without the need for an external reference
clock or programming. ADN2913 jitter performance exceeds all
jitter specifications required by SONET/SDH, including jitter
transfer, jitter generation, and jitter tolerance.
The ADN2913 provides manual or automatic slice adjust and
manual sample phase adjusts. Additionally, the user can select a
limiting amplifier, equalizer, or 0 dB EQ at the input. The equalizer
is adaptive or it can be manually set.
The receiver front-end loss of signal (LOS) detector
circuit indicates when the input signal level falls below a userprogrammable threshold. The LOS detection circuit has hysteresis
to prevent chatter at the LOS output. In addition, the input signal
strength can be read through the I2C registers.
The ADN2913 also supports pseudorandom binary sequence
(PRBS) generation, bit error detection, and input data rate
readback features.
The ADN2913 is available in a compact 4 mm × 4 mm, 24-lead
lead frame chip scale package (LFCSP). All ADN2913 specifications are defined over the ambient temperature range of −40°C
to +85°C, unless otherwise noted.
APPLICATIONS
SONET/SDH OC-1/OC-3/OC-12/OC-48 and all associated
FEC rates
1GE, 1GFC, 2GFC, 4GFC, 8GFC, CPRI OS/L.6 up to OS/L.60
Any rate regenerators/repeaters
FUNCTIONAL BLOCK DIAGRAM
SCK
SDA
LOL
I2C REGISTERS
FREQUENCY
ACQUISITION
AND LOCK
DETECTOR
LOS
THRESH
SLICE
ADJUST
I2C_ADDR
REFCLKP/
REFCLKN
(OPTIONAL)
TXD
FIFO
SAMPLE
PHASE
ADJUST
DATA
INPUT
SAMPLER
2
0dB EQ
50Ω
50Ω
I2C
VCM
CML
DDR
÷N
DOWNSAMPLER
AND LOOP
FILTER
LA
NIN
CML
CLK
LOS
DETECT
PIN
CLKOUTP/
CLKOUTN
DATA RATE
ADN2913
LOS
DATOUTP/
DATOUTN
÷2
DCO
RXD
RXCK
EQ
CLOCK
I2C
PHASE
SHIFTER
11777-001
VCC
FLOAT
Figure 1.
Rev. B
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Technical Support
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ADN2913
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Limiting Amplifier ..................................................................... 22
Applications ....................................................................................... 1
Slice Adjust .................................................................................. 22
General Description ......................................................................... 1
Edge Select................................................................................... 22
Functional Block Diagram .............................................................. 1
Loss of Signal (LOS) Detector .................................................. 23
Revision History ............................................................................... 2
Passive Equalizer ........................................................................ 24
Specifications..................................................................................... 3
0 dB EQ ........................................................................................ 24
Jitter Specifications ....................................................................... 5
Lock Detector Operation .......................................................... 26
Output and Timing Specifications ............................................. 6
Harmonic Detector .................................................................... 26
Timing Diagrams.......................................................................... 8
Output Disable and Squelch ..................................................... 27
Absolute Maximum Ratings ............................................................ 9
I2C Interface ................................................................................ 27
Thermal Characteristics .............................................................. 9
Reference Clock (Optional) ...................................................... 27
ESD Caution .................................................................................. 9
Additional Features Available via the I2C Interface ............... 29
Pin Configuration and Function Descriptions ........................... 10
Input Configurations ................................................................. 31
Typical Performance Characteristics ........................................... 11
Applications Information .............................................................. 34
I C Interface Timing and Internal Register Descriptions ......... 13
Transmission Lines..................................................................... 34
Register Map ............................................................................... 14
Soldering Guidelines for Lead Frame Chip Scale Package ... 34
Theory of Operation ...................................................................... 20
Outline Dimensions ....................................................................... 35
Functional Description .................................................................. 22
Ordering Guide .......................................................................... 35
2
Frequency Acquisition ............................................................... 22
REVISION HISTORY
8/2017—Rev. A to Rev. B
Changed CP-24-14 to CP-24-7 .................................... Throughout
Updated Outline Dimensions ....................................................... 34
Changes to Ordering Guide .......................................................... 34
2/2016—Rev. 0 to Rev. A
Changes to Figure 5 ........................................................................ 10
Changes to Table 7 .......................................................................... 15
Updated Outline Dimensions ....................................................... 33
Changes to Ordering Guide .......................................................... 33
12/2013—Revision 0: Initial Version
Rev. B | Page 2 of 35
Data Sheet
ADN2913
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data
pattern: PRBS 223 − 1, ac-coupled, I2C register default settings, unless otherwise noted.
Table 1.
Parameter
DATA RATE SUPPORT RANGE
INPUT—DC CHARACTERISTICS
Peak-to-Peak Differential Input1
Input Resistance
0 dB EQ PATH—CML INPUT
Input Voltage Range
Input Common-Mode Level
Differential Input Sensitivity
OC-48
8GFC2
LIMITING AMPLIFIER INPUT PATH
Differential Input Sensitivity
OC-48
8GFC2
EQUALIZER INPUT PATH
Differential Input Sensitivity
8GFC2
INPUT—AC CHARACTERISTICS
S11
LOSS OF SIGNAL (LOS) DETECT
Loss of Signal Detect
Test Conditions/Comments
PIN − NIN
Differential
At PIN or NIN, dc-coupled, RX_TERM_FLOAT = 1
(float)
DC-coupled (see Figure 33), 600 mV p-p differential,
RX_TERM_FLOAT = 1 (float)
DCO Frequency Error for LOL Deassert
LOL Assert Response Time
ACQUISITION TIME
Lock to Data (LTD) Mode
Optional LTR Mode4
DATA RATE READBACK ACCURACY
Coarse Readback
Fine Readback
Typ
Max
8.5
Unit
Gbps
95
100
1.0
105
V
Ω
0.5
VCC
V
0.65
VCC − 0.15
V
22
200
mV p-p
mV p-p
BER = 1 × 10−10
6.3
mV p-p
JTSPAT, BER = 1 × 10−12
8.3
mV p-p
15 inch FR-4, 100 Ω differential transmission line,
adaptive equalizer (EQ) on
JTSPAT, BER = 1 × 10−12
115
mV p-p
At 7.5 GHz, differential return loss, see Figure 14
−12
dB
10
5
128
5.7
135
110
mV p-p
mV p-p
mV p-p
dB
μs
μs
1000
ppm
250
10
51
25
ppm
ms
μs
μs
24
0.5
0.5
6.0
ms
ms
ms
ms
±5
%
ppm
Jitter tolerance scrambled pattern (JTSPAT),
ac-coupled, RX_TERM_FLOAT = 0 (VCM = 1.2 V),
BER = 1 × 10−12
Loss of signal minimum program value
Loss of signal maximum program value
Hysteresis (Electrical)
LOS Assert Time
LOS Deassert Time
LOSS OF LOCK (LOL) DETECT
DCO Frequency Error for LOL Assert
Min
0.0065
AC-coupled3
AC-coupled3
With respect to nominal, data collected in lock to
reference (LTR) mode
With respect to nominal, data collected in LTR mode
10.0 Mbps
2.5 Gbps
8.5 Gbps, JTSPAT
10.0 Mbps
2.5 Gbps
8.5 Gbps, JTSPAT
In addition to reference clock accuracy
Rev. B | Page 3 of 35
±100
ADN2913
Parameter
POWER SUPPLY VOLTAGE
VCC
VDD
VCC1
POWER SUPPLY CURRENT
VCC
VDD
VCC1
TOTAL POWER DISSIPATION
Clock Output Enabled
Clock Output Disabled
Data Sheet
Test Conditions/Comments
Min
Typ
Max
Unit
1.14
2.97
1.62
1.2
3.3
1.8
1.26
3.63
3.63
V
V
V
Limiting amplifier mode, clock output enabled
1.25 Gbps
3.125 Gbps
4.25 Gbps
6.144 Gbps
8GFC,2 JTSPAT
1.25 Gbps
3.125 Gbps
4.25 Gbps
6.144 Gbps
8GFC,2 JTSPAT
1.25 Gbps
3.125 Gbps
4.25 Gbps
6.144 Gbps
8GFC,2 JTSPAT
277.1
256.2
270.1
303.1
319.1
7.24
7.21
7.23
7.26
7.20
35.6
19.0
22.2
19.4
22.2
311.0
288.3
304.0
340.4
359.5
8.28
8.21
8.33
8.17
8.1
46.8
24.1
28.2
24.6
28.4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Limiting amplifier mode, 1.25 Gbps
Limiting amplifier mode, 3.125 Gbps
Limiting amplifier mode, 4.25 Gbps
Limiting amplifier mode, 6.144 Gbps
Limiting amplifier mode, 8GFC,2 JTSPAT
Equalizer mode, 8.5 Gbps
Limiting amplifier mode, 6.144 Gbps
0 dB EQ mode, 622 Mbps
420.4
365.5
388
422.5
446.6
352
380
340
+85
mW
mW
mW
mW
mW
mW
mW
mW
°C
OPERATING TEMPERATURE RANGE
−40
See Figure 34.
Fibre Channel Physical Interface-4 standard, FC-PI-4, Rev 8.00, May 21, 2008.
3
When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 100 Ω differential input termination
of the ADN2913 input stage.
4
This typical acquisition specification applies to all selectable reference clock frequencies in the range of 11.05 MHz to 176.8 MHz.
1
2
Rev. B | Page 4 of 35
Data Sheet
ADN2913
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data
pattern: PRBS 223 − 1, ac-coupled to 100 Ω differential termination load, I2C register default settings, unless otherwise noted.
Table 2.
Parameter
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer Bandwidth (BW) 1
8GFC 2
OC-48
OC-12
OC-3
Jitter Peaking
8GFC2
OC-48
OC-12
OC-3
Jitter Generation
8GFC2
OC-48
OC-12
OC-3
Jitter Tolerance
8GFC,2 JTSPAT
Sinusoidal Jitter at 340 kHz
Sinusoidal Jitter at 5.098 MHz
Sinusoidal Jitter at 80 MHz
Rx Jitter Tracking Test 3
510 kHz, 1 UI
100 kHz, 5 UI
OC-48
OC-12
Test Conditions/Comments
Min
Typ
Max
Unit
1242
663
157
175
44
1676
896
181
kHz
kHz
kHz
kHz
kHz
20 kHz to 80 MHz
20 kHz to 10 MHz
0.004
0.004
0.01
0.01
0.021
0.023
dB
dB
dB
dB
Unfiltered
Unfiltered
12 kHz to 20 MHz
Unfiltered
12 kHz to 20 MHz
Unfiltered
12 kHz to 5 MHz
Unfiltered
12 kHz to 5 MHz
Unfiltered
12 kHz to 1.3 MHz
Unfiltered
12 kHz to 1.3 MHz
Unfiltered
TRANBW[2:0] = 4 (default)
0.005
0.044
0.0025
TRANBW[2:0] = 4 (default)
OTN mode, TRANBW[2:0] = 1
0.0046
0.0156
0.0276
0.0007
0.0011
0.0038
0.0076
0.0002
0.0003
0.0008
0.0018
UI rms
UI p-p
UI rms
UI rms
UI p-p
UI p-p
UI rms
UI rms
UI p-p
UI p-p
UI rms
UI rms
UI p-p
UI p-p
6.7
0.53
0.59
UI p-p
UI p-p
UI p-p