ADN4612ACPZ

11.3 Gbps, 12 × 12 Digital Crosspoint Switch ADN4612 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VCC DVCC IP11 TO IP0 Rx VTTIE, VTTIW IN11 TO IN0 EQ Rx CONTROL EQUALIZATION SIGNAL DETECT 12 × 12 SWITCH MATRIX Tx OP11 TO OP0 PREEMPHASIS VTTON, VTTOS ON11 TO ON0 XPT CONTROL CONNECTIVITY MAP (A/B/C/D) SELECT Tx CONTROL 6-TAP FFE OUTPUT LEVEL EEPROM MAP1, MAP0 RESET UPDATE SPI/I2C SCK/SCL SERIAL INTERFACE CONTROL LOGIC SDO/SDA ADN4612 SDI/I2C_A1 CS/I2C_A0 LOS_IRQ VEE Figure 1. APPLICATIONS Fiber optic network switching 10 Gigabit Ethernet over backplane 10GBASE-KR 802.3ap XLAUI/CAUI (802.3ba) SONET OC-192/STM-64x 1×, 2×, 4×, 8×, and 10× Fibre Channel GENERAL DESCRIPTION The ADN4612 is a 12 × 12 asynchronous, protocol agnostic, digital crosspoint switch with 12 differential PECL-/CML-compatible inputs and 12 differential CML outputs. The ADN4612 is optimized for nonreturn-to-zero (NRZ) signaling with data rates of up to 11.3 Gbps per port. Each port provides programmable input equalization, loss of signal (LOS) detection, programmable output swing, and output preemphasis/deemphasis. Rev. C The ADN4612 nonblocking switch core implements a 12 × 12 crossbar and supports independent channel switching through the serial control interface. The ADN4612 has low latency and very low channel-to-channel skew. The ADN4612 is packaged in an 88-lead LFCSP package and operates from −40°C to +85°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 11020-001 DC to 11.3 Gbps per port, NRZ data rate Multitime constant, programmable receive equalization Compensates 25 inches of FR408 at 10.3125 Gbps Compensates 15 inches of FR408 at 11.3 Gbps 6-tap programmable transmit feedforward equalization (FFE) Compensates 15 inches of FR408 at 10.3125 Gbps Compensates 10 inches of FR408 at 11.3 Gbps Low power 150 mW per channel at 2.5 V (outputs enabled) 12 × 12, fully differential, nonblocking array Double rank connection programming 2-pin selectable connection maps Per lane lost of signal (LOS) detection Flexible output termination supply range (1.8 V to 3.3 V) DC- or ac-coupled differential CML inputs and outputs Programmable CML output levels Load from EEPROM for automatic power-on ready operation Per lane input and output P/N pair inversion for routing ease 50 Ω on-chip input/output termination Supports 64-bit/66-bit, scrambled or not coded NRZ data up to 11.3 Gbps Serial (I2C or SPI slave) control interface 88-lead LFCSP, 12 mm × 12 mm, Pb-free package −40°C to +85°C operating temperature range ADN4612 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Descriptions ..................................................................... 47 Applications ....................................................................................... 1 Software Reset Register ............................................................. 47 Functional Block Diagram .............................................................. 1 Tx Enable Control Registers ..................................................... 47 General Description ......................................................................... 1 Tx Reference Enable Register ................................................... 48 Revision History ............................................................................... 3 Squelch Control Register ........................................................... 48 Specifications..................................................................................... 4 Rx and Tx Swap Sign Registers................................................. 48 Input/Output Specifications........................................................ 4 XPT Broadcast Lane Number Register ................................... 50 Power Supply and Thermal Specifications ................................ 5 Tx 0 Driver Control Registers .................................................. 50 Electrical Specifications—Control Logic Pins .......................... 6 Tx 0 Driver Enable Registers .................................................... 52 I C Master and Slave Timing Specifications ............................. 6 Tx 0 Driver Resolution Registers ............................................. 53 SPI Timing Specifications ........................................................... 7 Tx 1 Driver Control Registers .................................................. 53 EEPROM Master I C Timing Specifications ............................ 8 Tx 1 Driver Enable Registers .................................................... 53 RESET Timing Specifications ..................................................... 9 Tx 1 Driver Resolution Registers ............................................. 53 Absolute Maximum Ratings.......................................................... 10 Tx 2 Driver Control Registers .................................................. 54 Thermal Resistance .................................................................... 10 Tx 2 Driver Enable Registers .................................................... 54 ESD Caution ................................................................................ 10 Tx 2 Driver Resolution Registers ............................................. 54 Pin Configuration and Function Descriptions ........................... 11 Tx 3 Driver Control Registers .................................................. 54 Typical Performance Characteristics ........................................... 13 Tx 3 Driver Enable Registers .................................................... 54 Standard Test ............................................................................... 17 Tx 3 Driver Resolution Registers ............................................. 54 Equalization Test ........................................................................ 18 Tx 4 Driver Control Registers .................................................. 54 Preemphasis Test ........................................................................ 20 Tx 4 Driver Enable Registers .................................................... 54 Test Circuits ..................................................................................... 22 Tx 4 Driver Resolution Registers ............................................. 55 Theory of Operation ...................................................................... 23 Tx 5 Driver Control Registers .................................................. 55 Introduction ................................................................................ 23 Tx 5 Driver Enable Registers .................................................... 55 Receivers ...................................................................................... 24 Tx 5 Driver Resolution Registers ............................................. 55 Switch Core ................................................................................. 26 Tx 6 Driver Control Registers .................................................. 55 Transmitters ................................................................................ 27 Tx 6 Driver Enable Registers .................................................... 55 Preemphasis/Deemphasis Support for Legacy Rates ............. 33 Tx 6 Driver Resolution Registers ............................................. 55 Load from Memory .................................................................... 34 Tx 7 Driver Control Registers .................................................. 55 I2C Serial Control Interface ........................................................... 37 Tx 7 Driver Enable Registers .................................................... 55 I2C Data Write ............................................................................. 37 Tx 7 Driver Resolution Registers ............................................. 56 I2C Data Read .............................................................................. 38 Tx 8 Driver Control Registers .................................................. 56 SPI Serial Control Interface........................................................... 39 Tx 8 Driver Enable Registers .................................................... 56 Write Operation .......................................................................... 39 Tx 8 Driver Resolution Registers ............................................. 56 Read Operation ........................................................................... 39 Tx 9 Driver Control Registers .................................................. 56 Applications Information .............................................................. 40 Tx 9 Driver Enable Registers .................................................... 56 Applications Circuit ................................................................... 41 Tx 9 Driver Resolution Registers ............................................. 56 Power Consumption .................................................................. 41 Tx 10 Driver Control Registers ................................................ 56 Printed Circuit Board (PCB) Layout Guidelines ................... 42 Tx 10 Driver Enable Registers .................................................. 56 Register Map.................................................................................... 44 Tx 10 Driver Resolution Registers ........................................... 57 2 2 Rev. C | Page 2 of 76 Data Sheet ADN4612 Tx 11 Driver Control Registers .................................................57  Tx 11 Driver Enable Registers ...................................................57  Rx 11 to Rx 6 LOS Assert and Deassert Level Control Register ......................................................................................... 66  Tx 11 Driver Resolution Registers ............................................57  Rx 11 to Rx 6 LOS IRQ Enable Register .................................. 67  Rx 0 to Rx 5 Active and Passive Equalization Control Registers .......................................................................................57  Rx Offset Calibration Control Registers .................................. 67  XPT Map A Tx Lane Select Registers ....................................... 68  Rx 5 to Rx 0 Enable Control Register .......................................59  XPT Map B Tx Lane Select Registers ....................................... 69  Rx 5 to Rx 0 Equalizer Enable Control Register .....................59  XPT Map C Tx Lane Select Registers ....................................... 70  Rx 5 to Rx 0 LOS Enable Control Register ..............................59  XPT Map D Tx Lane Select Registers ...................................... 71  Rx 5 to Rx 0 LOS Time Control Registers ...............................60  XPT Map Tx Lane Status Registers .......................................... 73  Rx 5 to Rx 0 LOS Status Register...............................................61  Boot from EEPROM Control Register ..................................... 74  Rx 5 to Rx 0 LOS Sticky Status Register ...................................61  XPT Table Selection Control Register ...................................... 74  Rx 5 to Rx 0 LOS IRQ Enable Register.....................................62  Update XPT Table Register ........................................................ 74  Rx 6 to Rx 11 Active and Passive Equalization Control Registers .......................................................................................62  EEPROM Checksum Register ................................................... 75  Rx 11 to Rx 6 Enable Control Register .....................................63  Revision ID Register ................................................................... 75  Rx 11 to Rx 6 Equalizer Enable Control Register ...................64  Chip ID Register ......................................................................... 75  Rx 11 to Rx 6 LOS Enable Control Register ............................64  Outline Dimensions ........................................................................ 76  Rx 11 to Rx 6 LOS Time Control Registers .............................65  Ordering Guide ........................................................................... 76  EEPROM Status Register ........................................................... 75  Rx 11 to Rx 6 LOS Status Register ............................................66  Rx 11 to Rx 6 LOS Sticky Status Register .................................66  REVISION HISTORY 5/2016—Rev. B. to Rev. C Changes to Figure 73 ......................................................................41 1/2016—Rev. A to Rev. B Change to Output Voltage Swing Parameter, Table 1 ................... 4 Updated Outline Dimensions ........................................................76 10/2013—Revision A: Initial Version Rev. C | Page 3 of 76 ADN4612 Data Sheet SPECIFICATIONS VCC = VTTO 1 = 2.5 V, VTTI 2 = V1P8 = DVCC = 1.8 V, VEE = 0 V, RL = 50 Ω, data rate = 11.3 Gbps, data pattern = PRBS 15, ac-coupled inputs and outputs, differential input swing = 800 mV p-p, EQ setting = 0x12, 3 PE boost = 1.94 dB, 4 unless otherwise noted. INPUT/OUTPUT SPECIFICATIONS Table 1. Parameter DYNAMIC PERFORMANCE Data Rate (NRZ) Deterministic Jitter (No Channel) Random Jitter (No Channel) Residual Deterministic Jitter with Receive Equalization Residual Deterministic Jitter with Transmit Preemphasis Propagation Delay Lane-to-Lane Skew Switching Time Output Rise/Fall Time INPUT CHARACTERISTICS Differential Input Voltage Swing Input Voltage Range Differential Input Return Loss (SDD11) OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Range Output Voltage Setting Resolution Per Port Output Current Differential Output Return Loss (SDD22) TERMINATION CHARACTERISTICS Resistance LOS CHARACTERISTICS Assert Level Deassert Level LOS-to-Output Squelch LOS-to-Output Enable Test Conditions/Comments Min Typ Max Unit 11.3 11 14 0.5 0.25 Gbps ps p-p ps p-p ps rms UI 0.25 UI 0.24 UI 0.31 UI 520 ±40 ps ps 10 44 ns ps DC Data rate = 10.3125 Gbps Data rate = 11.3 Gbps Input trace = 25-inch FR408, data rate = 10.3125 Gbps, EQ setting = 0x94 Input trace = 15-inch FR408, data rate = 11.3 Gbps, EQ setting = 0x72 Output trace = 15-inch FR408, data rate = 10.3125 Gbps, PE boost = 5.46 dB Output trace = 10-inch FR408, data rate = 11.3 Gbps, PE boost = 6.02 dB 50% input to 50% output (maximum EQ) Signal path and switch architecture is balanced and symmetric (maximum EQ) 50% logic switching to 50% output data 5 20% to 80%, test pattern = 0000000011111111 VICM 6 = 1.8 V, VCC = VMIN to VMAX, TA = TMIN to TMAX Single-ended absolute voltage level, VIL minimum Single-ended absolute voltage level, VIH maximum At 2.125 GHz At 5.5 GHz