FEATURES
FUNCTIONAL BLOCK DIAGRAMS
APPLICATIONS
VIN1
ADN4654
ISOLATION
BARRIER
LDO
VDD1
LDO
VDD2
DIN1+
DOUT1+
DIN1–
DOUT1–
LVDS
DIGITAL ISOLATOR
LVDS
DOUT2+
DIN2–
DOUT2–
GND1
17011-001
DIN2+
GND2
Figure 1.
VIN1
ADN4655
LDO
VDD1
VIN2
ISOLATION
BARRIER
LDO
VDD2
DIN1+
DOUT1+
DIN1–
DOUT1–
LVDS
DIGITAL ISOLATOR
LVDS
DOUT2+
DIN2+
DOUT2–
DIN2–
GND1
GND2
Figure 2.
VIN1
ADN4656
VDD1
Isolated video and imaging data
Analog front-end isolation
Data plane isolation
Isolated high speed clock and data links
VIN2
17011-102
5 kV rms and 3.75 kV rms LVDS isolators
Complies with TIA/EIA-644-A LVDS standard
Multiple dual-channel configurations
Any data rate up to 1.1 Gbps switching with low jitter
4 ns typical propagation delay
2.6 ps rms typical random jitter, rms
90 ps typical peak-to-peak total jitter at 1.1 Gbps
2.5 V or 3.3 V supplies
−75 dBc power supply ripple rejection, phase spur level
Glitch immunity
±8 kV IEC 61000-4-2 ESD protection across isolation barrier
High common-mode transient immunity: >25 kV/μs
Passes EN 55022 Class B radiated emissions limits with
1.1 Gbps PRBS
Safety and regulatory approvals (20-lead SOIC_W package)
UL (pending): 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 424 VPEAK
Fail-safe output high for open, short, and terminated input
conditions (ADN4655/ADN4656)
Operating temperature range: −40°C to +125°C
7.8 mm minimum creepage and clearance
LDO
VIN2
ISOLATION
BARRIER
LDO
VDD2
DIN1+
DOUT1+
DIN1–
DOUT1–
LVDS
DIGITAL ISOLATOR
LVDS
DIN2+
DOUT2+
DIN2–
DOUT2–
GND2
GND1
17011-050
Data Sheet
5 kV RMS and 3.75 kV RMS,
Dual-Channel LVDS Gigabit Isolators
ADN4654/ADN4655/ADN4656
Figure 3.
GENERAL DESCRIPTION
The ADN4654/ADN4655/ADN46561 are signal isolated, low
voltage differential signaling (LVDS) buffers that operate at up
to 1.1 Gbps with low jitter. The devices integrate Analog
Devices, Inc., iCoupler® technology, enhanced for high speed
operation to provide galvanic isolation of the TIA/EIA-644-A
compliant LVDS drivers and receivers. This integration allows
drop-in isolation of an LVDS signal chain.
The ADN4654/ADN4655/ADN4656 comprise multiple
channel configurations, and the LVDS receivers on the ADN4655
and ADN4656 include a fail-safe mechanism to ensure a Logic
1
1 on the corresponding LVDS driver output when the inputs are
floating, shorted, or terminated but not driven.
For high speed operation with low jitter, the LVDS and isolator
circuits rely on a 2.5 V supply. An integrated on-chip low dropout
(LDO) regulator can provide the required 2.5 V from an external
3.3 V power supply. The devices are fully specified over a wide
industrial temperature range and come in a 20-lead, wide body
SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP
package with 3.75 kV rms isolation.
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. D
Document Feedback
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ADN4654/ADN4655/ADN4656
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................8
Applications ....................................................................................... 1
Pin Configurations and Function Descriptions ............................9
Functional Block Diagrams ............................................................. 1
Typical Performance Characteristics ........................................... 12
General Description ......................................................................... 1
Test Circuits and Switching Characteristics................................ 17
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 18
Specifications..................................................................................... 3
Truth Table and Fail-Safe Receiver .......................................... 18
Receiver Input Threshold Test Voltages .................................... 4
Isolation ....................................................................................... 19
Timing Specifications .................................................................. 4
Applications Information .............................................................. 20
Insulation and Safety Related Specifications ............................ 5
PCB Layout ................................................................................. 20
Package Characteristics ............................................................... 6
Application Examples ................................................................ 20
Regulatory Information ............................................................... 6
Magnetic Field Immunity.......................................................... 22
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics (Pending) ............................................................ 7
Insulation Lifetime ..................................................................... 22
Outline Dimensions ....................................................................... 24
Recommended Operating Conditions ...................................... 7
Ordering Guide .......................................................................... 25
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
REVISION HISTORY
9/2019—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 25
6/2019—Rev. B to Rev. C
Added ADN4656 ................................................................ Universal
Changes to Features Section............................................................ 1
Added Figure 3; Renumbered Sequentially .................................. 1
Added Note 1, Table 8 ...................................................................... 7
Added Figure 8 and Table 15; Renumbered Sequentially ......... 11
Changes to Magnetic Field Immunity Section ........................... 22
Changes to Ordering Guide .......................................................... 25
3/2019—Rev. A to Rev. B
Changes to Title, Features Section, General Description
Section, and Figure 2 ........................................................................ 1
Changes to Table 4 ............................................................................ 5
Added Table 5.................................................................................... 5
Changes to Table 7 ............................................................................ 6
Changes to Table 8 and Figure 4 ..................................................... 7
Changes to Table 10, Table 11, and Table 12 ................................. 8
Added Figure 44.............................................................................. 23
Changes to Ordering Guide .......................................................... 23
1/2019—Rev. 0 to Rev. A
Added ADN4655 ................................................................ Universal
Added Figure 2; Renumbered Sequentially ...................................1
Changes to General Description Section .......................................1
Changes to Table 1.............................................................................3
Changes to Table 3.............................................................................4
Added Timing Diagram Section and Figure 3 ..............................5
Changes to Figure 5 Caption and Table 12 Title ...........................9
Added Figure 6 and Table 13; Renumbered Sequentially ......... 10
Changes to Theory of Operation Section and Truth Table and
Fail Safe Receiver Section .............................................................. 17
Added Table 15 ............................................................................... 17
Moved Isolation Section ................................................................ 18
Moved PCB Layout Section .......................................................... 19
Changes to PCB Layout Section ................................................... 19
Changes to Ordering Guide .......................................................... 23
11/2018—Revision 0: Initial Version
Rev. D | Page 2 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
SPECIFICATIONS
For all minimum and maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = −40°C to +125°C, unless otherwise noted. For all
typical specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUTS (RECEIVERS)
Input Threshold
High
Low
Symbol
Min
−100
Differential Input Voltage
Input Common-Mode Voltage
Input Current, High and Low
|VID|
VIC
IIH, IIL
100
0.5|VID|
−5
Differential Input Capacitance1
CINx±
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
VOS, Peak to Peak1
Output Short-Circuit Current
Differential Output
Capacitance1
POWER SUPPLY
Supply Current
Power Supply Ripple Rejection,
Phase Spur Level
COMMON-MODE TRANSIENT
IMMUNITY3
100
mV
mV
|VOD|
|ΔVOD|
VOS
ΔVOS
VOS(PP)
IOS
2
250
310
1.125
1.17
mV
V
μA
pF
450
mV
50
1.375
50
150
−20
12
mV
V
mV
mV
mA
mA
pF
55
82
65
80
3.6
mA
mA
mA
mA
V
2.625
V
5
COUTx±
Test Conditions/Comments
See Figure 38 and Table 2
See Figure 38 and Table 2
DINx± = VDDx or 0 V, other input = 1.2 V, VDDx =
2.5 V or 0 V
DINx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V2
See Figure 36 and Figure 37, load resistance (RL) =
100 Ω
See Figure 36 and Figure 37, RL = 100 Ω
See Figure 36, RL = 100 Ω
See Figure 36, RL = 100 Ω
See Figure 36, RL = 100 Ω
DOUTx± = 0 V
|VOD| = 0 V
DOUTx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V, VDD1 or VDD2 = 0 V
IDD1, IIN1,
IDD2, or IIN2
VIN1 or
VIN2
VDD1 or
VDD2
PSRR
3.0
58
50
60
3.3
2.375
2.5
|CM|
25
ADN4654 only
LDO Output Range
Unit
2.4 − 0.5|VID|
+5
ADN4655/ADN4656 only
LDO Input Range
Max
See Figure 38 and Table 2
VTH
VTL
OUTPUTS (DRIVERS)
Differential Output Voltage
Typ
−75
dBc
50
kV/μs
1
No output load, inputs with 100 Ω, no applied |VID|
All outputs loaded, RL = 100 Ω, frequency = 0.55 GHz
No output load, inputs with 100 Ω, |VID| = 200 mV
All outputs loaded, RL = 100 Ω, frequency = 0.55 GHz
No external supply on VDD1 or VDD2
Phase spur level on DOUTx± with 0.55 GHz clock on
DINx± and applied ripple of 100 kHz, 100 mV p-p on
a 2.5 V supply to VDD1 or VDD2
Common-mode voltage (VCM) = 1000 V, transient
magnitude = 800 V
These specifications are guaranteed by design and characterization.
t denotes time.
3
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining any DOUTx+/DOUTx− pin in the same state as the corresponding DINx+/DINx−
pin (no change in output), or producing the expected transition on any DOUTx+/DOUTx− pin if the applied common-mode transient edge is coincident with a data
transition on the corresponding DINx+/DINx− pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
2
Rev. D | Page 3 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
RECEIVER INPUT THRESHOLD TEST VOLTAGES
Table 2. Test Voltages for Receiver Operation
Applied Voltages
DINx+ (V)
DINx− (V)
1.25
1.15
1.15
1.25
2.4
2.3
2.3
2.4
0.1
0
0
0.1
1.5
0.9
0.9
1.5
2.4
1.8
1.8
2.4
0.6
0
0
0.6
Input Voltage, Differential, VID (V)
0.1
−0.1
0.1
−0.1
0.1
−0.1
0.6
−0.6
0.6
−0.6
0.6
−0.6
Input Voltage, Common-Mode, VIC (V)
1.2
+1.2
2.35
+2.35
0.05
+0.05
1.2
+1.2
2.1
+2.1
0.3
+0.3
Driver Output, Differential VOD (mV)
>250
250
250
250
250
250
1.3V
DINx+
(DINx– = 1.2V)
1.2V
400
II
μm min
V
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
Test Conditions/Comments
1 minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 5. 20-Lead SSOP Package
Parameter
Rated Dielectric Insulation
Voltage
Minimum Clearance
Symbol
Value
3.75
Unit
kV rms
Test Conditions/Comments
1 minute duration
L (I01)
5.3
mm min
Minimum Creepage
L (I02)
5.3
mm min
Minimum PCB Clearance
L (PCB)
5.6
mm min
Minimum Internal Clearance
Comparative Tracking Index
Material Group
CTI
22
>400
II
μm min
V
Measured from input terminals to output terminals, shortest distance
through air
Measured from input terminals to output terminals, shortest distance path
along body
Measured from input terminals to output terminals, shortest distance
through air, line of sight, in the PCB mounting plane
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. D | Page 5 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
PACKAGE CHARACTERISTICS
Table 6.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
1
2
Symbol
RI-O
CI-O
CI
Min
Typ
1013
2.2
3.7
Max
Unit
Ω
pF
pF
Test Conditions/Comments
Frequency = 1 MHz
The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
See Table 12 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation
waveforms and insulation levels.
Table 7.
UL (Pending)
To Be Recognized Under UL 1577
Component Recognition Program1
Single Protection, Isolation Voltage
20-Lead SOIC, 5000 V rms
20-Lead SSOP, 3750 V rms
File E214100
1
2
CSA (Pending)
To be approved under CSA
Component Acceptance Notice 5A
VDE (Pending)
To be certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Reinforced insulation, VIORM = 424 VPEAK, VIOSM = 8000 VPEAK
File 205078
File 2471900-4880-0001
In accordance with UL 1577, each ADN4654/ADN4655/ADN4656 is proof tested by applying an insulation test voltage ≥ 6000 V rms (20-lead SOIC_W) or ≥ 4500 V rms (20-lead
SSOP) for 1 sec.
In accordance with DIN V VDE V 0884-10, each ADN4654/ADN4655/ADN4656 is proof tested by applying an insulation test voltage ≥ 795 VPEAK for 1 sec (partial discharge
detection limit = 5 pC).
Rev. D | Page 6 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS (PENDING)
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of
the safety data.
Table 8.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input or Safety Test Subgroup 2 and
Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Basic
Reinforced
Safety Limiting Values
Maximum Junction Temperature
Total Power Dissipation at 25°C
20-Lead SOIC
20-Lead SSOP
Insulation Resistance at TS
VIORM × 1.875 = VPD (M), 100% production test,
tINI = tM = 1 sec, partial discharge < 5 pC
Symbol
Characteristic
Unit
VIORM
VPD (M)
I to IV
I to IV
I to III
40/125/21
2
424
795
VPEAK
VPEAK
636
VPEAK
509
VPEAK
VIOTM
7000
VPEAK
VIOSM
VIOSM
10,000
8000
VPEAK
VPEAK
TS
PS
150
°C
2.78
1.8
>109
W
W
Ω
VPD (M)
VIORM × 1.5 = VPD (M), tINI = 60 sec, tM = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = VPD (M), tINI = 60 sec, tM = 10 sec,
partial discharge < 5 pC
VPEAK = 12.8 kV, 1.2 μs rise time, 50 μs, 50% fall time
VPEAK = 12.8 kV, 1.2 μs rise time, 50 μs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 5)
VIO = 500 V
RS
For information about tM, tINI, and VIO, see DIN V VDE V 0884-10.
3.0
RECOMMENDED OPERATING CONDITIONS
20-LEAD SOIC
Table 9.
2.5
SAFE LIMITING POWER (W)
2.0
Parameter
Operating Temperature
Supply Voltages
Supply to LDO Regulator
LDO Bypass, VINx Shorted to VDDx
20-LEAD SSOP
1.5
1.0
0.5
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
17011-002
1
Test Conditions/Comments1
Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
Rev. D | Page 7 of 25
Symbol
TA
Rating
−40°C to +125°C
VIN1, VIN2
VDD1, VDD2
3.0 V to 3.6 V
2.375 V to 2.625 V
ADN4654/ADN4655/ADN4656
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 10.
Parameter
VIN1 to GND1/VIN2 to GND2
VDD1 to GND1/VDD2 to GND2
Input Voltage (DINx+, DINx−) to GNDx on
the Same Side
Output Voltage (DOUTx+, DOUTx−) to
GNDx on the Same Side
Short-Circuit Duration (DOUTx+, DOUTx−)
to GNDx on the Same Side
Operating Temperature Range
Storage Temperature Range
Junction Temperature (TJ Maximum)
Power Dissipation
Electrostatic Discharge (ESD)
Human Body Model (All Pins to
Respective GNDx, 1.5 kΩ, 100 pF)
IEC 61000-4-2 (LVDS Pins to Isolated
GNDx Across Isolation Barrier)
20-Lead SOIC
20-Lead SSOP
Thermal performance is directly linked to PCB design and
operation environment. Close attention to PCB thermal design
is required.
Rating
−0.3 V to +6.5 V
−0.3 V to +2.8 V
−0.3 V to VDD + 0.3 V
θJA is the natural convection junction to ambient thermal
resistance measured in a one-cubic foot sealed enclosure.
−0.3 V to VDD + 0.3 V
Table 11. Thermal Resistance
Continuous
−40°C to +125°C
−65°C to +150°C
150°C
(TJ maximum − TA)/θJA
Package Type1
RW-20
RS-20
1
θJA
45.7
69.6
Unit
°C/W
°C/W
Test Condition 1: thermal impedance simulated with 4-layer standard JEDEC PCB.
ESD CAUTION
±4 kV
±8 kV
±7 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 12. Maximum Continuous Working Voltage1
Parameter
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
RW-20
Rating
RS-20
Constraint
424 VPEAK
424 VPEAK
424 V PEAK
424 V PEAK
50-year minimum insulation lifetime for 1% failure
50-year minimum insulation lifetime for 1% failure
848 VPEAK
875 VPEAK
848 V PEAK
620 V PEAK
50-year minimum insulation lifetime for 1% failure
Lifetime limited by package creepage, maximum approved working voltage
1079 VPEAK
536 VPEAK
754 V PEAK
380 V PEAK
Lifetime limited by package creepage, maximum approved working voltage
Lifetime limited by package creepage, maximum approved working voltage
The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for
more details.
Rev. D | Page 8 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VIN1 1
20
VIN2
GND1 2
19
GND2
VDD1 3
18
VDD2
GND1 4
17
GND2
DIN1– 6
DIN2+ 7
ADN4654
DOUT1+
TOP VIEW
(Not to Scale) 15 DOUT1–
14 DOUT2+
16
DIN2– 8
13
DOUT2–
VDD1 9
12
VDD2
GND1 10
11
GND2
17011-003
DIN1+ 5
Figure 6. ADN4654 Pin Configuration
Table 13. ADN4654 Pin Function Descriptions
Pin No.
1
Mnemonic
VIN1
2, 4, 10
3, 9
GND1
VDD1
5
6
7
8
11, 17, 19
12, 18
DIN1+
DIN1−
DIN2+
DIN2−
GND2
VDD2
13
14
15
16
20
DOUT2−
DOUT2+
DOUT1−
DOUT1+
VIN2
Description
Optional 3.3 V Power Supply and LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN1 directly to VDD1.
Ground, Side 1.
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If supplying
3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO regulator.
Noninverted Differential Input 1.
Inverted Differential Input 1.
Noninverted Differential Input 2.
Inverted Differential Input 2.
Ground, Side 2.
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If supplying
3.3 V to VIN2, connect a 1 μF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO regulator.
Inverted Differential Output 2.
Noninverted Differential Output 2.
Inverted Differential Output 1.
Noninverted Differential Output 1.
Optional 3.3 V Power Supply and LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN2 directly to VDD2.
Rev. D | Page 9 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
VIN1 1
20
VIN2
GND1 2
19
GND2
VDD1 3
18
VDD2
GND1 4
17
GND2
DIN1– 6
DOUT2+ 7
ADN4655
DOUT1+
TOP VIEW
(Not to Scale) 15 DOUT1–
14 DIN2+
16
DOUT2– 8
13
DIN2–
VDD1 9
12
VDD2
GND1 10
11
GND2
17011-106
DIN1+ 5
Figure 7. ADN4655 Pin Configuration
Table 14. ADN4655 Pin Function Descriptions
Pin No.
1
Mnemonic
VIN1
2, 4, 10
3, 9
GND1
VDD1
5
6
7
8
11, 17, 19
12, 18
DIN1+
DIN1−
DOUT2+
DOUT2−
GND2
VDD2
13
14
15
16
20
DIN2−
DIN2+
DOUT1−
DOUT1+
VIN2
Description
Optional 3.3 V Power Supply and LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN1 directly to VDD1.
Ground, Side 1.
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If supplying
3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO regulator.
Noninverted Differential Input 1.
Inverted Differential Input 1.
Noninverted Differential Output 2.
Inverted Differential Output 2.
Ground, Side 2.
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If supplying
3.3 V to VIN2, connect a 1 μF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO regulator.
Inverted Differential Input 2.
Noninverted Differential Input 2.
Inverted Differential Output 1.
Noninverted Differential Output 1.
Optional 3.3 V Power Supply and LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN2 directly to VDD2.
Rev. D | Page 10 of 25
ADN4654/ADN4655/ADN4656
VIN1 1
20
VIN2
GND1 2
19
GND2
VDD1 3
18
VDD2
GND1 4
17
GND2
16
DIN1+
15
DIN1–
DIN2+ 7
14
DOUT2+
DIN2– 8
13
DOUT2–
VDD1 9
12
VDD2
GND1 10
11
GND2
DOUT1+ 5
DOUT1– 6
ADN4656
TOP VIEW
(Not to Scale)
17011-051
Data Sheet
Figure 8. ADN4656 Pin Configuration
Table 15. ADN4656 Pin Function Descriptions
Pin No.
1
Mnemonic
VIN1
2, 4, 10
3, 9
GND1
VDD1
5
6
7
8
11, 17, 19
12, 18
DOUT1+
DOUT1−
DIN2+
DIN2−
GND2
VDD2
13
14
15
16
20
DOUT2−
DOUT2+
DIN1−
DIN1+
VIN2
Description
Optional 3.3 V Power Supply and LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN1 directly to VDD1.
Ground, Side 1.
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If supplying
3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO regulator.
Noninverted Differential Output 1.
Inverted Differential Output 1.
Noninverted Differential Input 2.
Inverted Differential Input 2.
Ground, Side 2.
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If supplying
3.3 V to VIN2, connect a 1 μF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO regulator.
Inverted Differential Output 2.
Noninverted Differential Output 2.
Inverted Differential Input 1.
Noninverted Differential Input 1.
Optional 3.3 V Power Supply and LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN2 directly to VDD2.
Rev. D | Page 11 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD1 = VDD2 = 2.5 V, TA = 25°C, RL = 100 Ω, 0.55 GHz input with |VID| = 200 mV, and VIC = 1.1 V for ADN4654, unless otherwise noted.
90
70
80
60
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
70
50
40
30
20
60
50
40
30
20
100
150
200
250
300
350
400
450
500
550
INPUT CLOCK FREQUENCY (MHz)
0
–50
70
60
SUPPLY CURRENT (mA)
60
50
40
30
20
IDD1
IDD2
IIN1
IIN2
50
100
150
200
250
300
350
400
450
500
550
INPUT CLOCK FREQUENCY (MHz)
0
3.00
SUPPLY CURRENT (mA)
40
30
20
IDD1
IDD2
IIN1
IIN2
50
75
100
3.30
3.45
3.60
2.65
50
40
30
20
10
125
17011-006
SUPPLY CURRENT (mA)
50
25
3.15
Figure 13. Supply Current vs. Supply Voltage, VIN1/VIN2
60
0
IIN1 (DIN1± ACTIVE)
IIN2 (DIN1± ACTIVE)
IIN1 (DIN2± ACTIVE)
IIN2 (DIN2± ACTIVE)
SUPPLY VOLTAGE, VIN1/VIN2 (V)
60
AMBIENT TEMPERATURE (°C)
125
20
70
–25
100
30
70
0
–50
75
40
Figure 10. Supply Current vs. Input Clock Frequency
(DIN1± and DIN2± Switching)
10
50
50
10
17011-005
SUPPLY CURRENT (mA)
70
0
25
Figure 12. Supply Current vs. Ambient Temperature
(DIN1± and DIN2± with 550 MHz Clock Inputs)
80
0
0
AMBIENT TEMPERATURE (°C)
Figure 9. Supply Current vs. Input Clock Frequency
(DIN1± Switching, DIN2± Not Switching)
10
–25
17011-008
50
IDD1
IDD2
IIN1
IIN2
17011-009
0
17011-004
0
10
17011-007
IDD1
IDD2
IIN1
IIN2
10
Figure 11. Supply Current vs. Ambient Temperature
(DIN1± with 550 MHz Clock Input, DIN2± Not Switching)
0
2.35
IDD1
IDD2
IDD1
IDD2
(DIN1±
(DIN1±
(DIN2±
(DIN2±
ACTIVE)
ACTIVE)
ACTIVE)
ACTIVE)
2.50
SUPPLY VOLTAGE, VDD1 /VDD2 (V)
Figure 14. Supply Current vs. Supply Voltage, VDD1/VDD2
Rev. D | Page 12 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
2.60
2.55
2.50
2.45
2.40
VDD1
VDD2
2.35
3.0
3.1
3.2
3.3
3.4
3.5
3.6
LDO INPUT VOLTAGE, VIN1/VIN2 (V)
1.40
1.35
1.30
VOH CHANNEL 1
VOH CHANNEL 2
2.40
2.45
2.50
2.55
2.60
2.65
Figure 18. Driver Output High Voltage, VOH vs. Supply Voltage, VDD1/VDD2
1.25
330
320
310
300
290
280
270
VOD CHANNEL 1
VOD CHANNEL 2
0
50
100
150
200
250
300
350
400
450
500
550
Figure 16. Driver Differential Output Voltage vs. Input Clock Frequency
1.10
1.05
1.00
0.95
0.90
2.35
VOL CHANNEL 1
VOL CHANNEL 2
2.40
2.45
2.50
2.55
2.60
2.65
SUPPLY VOLTAGE, VDD1 /VDD2 (V)
Figure 19. Driver Output Low Voltage, VOL vs. Supply Voltage, VDD1/VDD2
1.375
DRIVER OUTPUT OFFSET VOLTAGE, VOS (V)
450
400
350
300
250
200
150
100
50
VOD CHANNEL 1
VOD CHANNEL 2
75
100
125
150
OUTPUT LOAD, RL (Ω)
Figure 17. Driver Differential Output Voltage, VOD vs. Output Load, RL
1.325
1.275
1.225
1.175
1.125
2.35
17011-012
0
50
1.15
VOS CHANNEL 1
VOS CHANNEL 2
2.40
2.45
2.50
2.55
SUPPLY VOLTAGE, VDD1 /VDD2 (V)
2.60
2.65
17011-015
260
1.20
17011-014
DRIVER OUTPUT LOW VOLTAGE, VOL (V)
340
INPUT CLOCK FREQUENCY (MHz)
DRIVER DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV)
1.45
SUPPLY VOLTAGE, VDD1 /VDD2 (V)
350
250
1.50
1.25
2.35
17011-011
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (mV)
Figure 15. LDO Output Voltage, VDD1/VDD2 vs. LDO Input Voltage, VIN1/VIN2
1.55
17011-013
DRIVER OUTPUT HIGH VOLTAGE, VOH (V)
1.60
17011-010
LDO OUTPUT VOLTAGE, VDD1 /VDD2 (V)
2.65
Figure 20. Driver Output Offset Voltage, VOS vs. Supply Voltage, VDD1/VDD2
Rev. D | Page 13 of 25
ADN4654/ADN4655/ADN4656
3.60
3.45
3.40
3.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
SUPPLY VOLTAGE, VDD1 AND VDD2 (V)
Figure 21. Differential Propagation Delay vs. Supply Voltage, VDD1 and VDD2
3.8
3.7
3.6
3.5
3.4
3.3
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
3.2
3.1
3.0
–50
–25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
DIFFERENTIAL OUTPUT TRANSITION TIME (ps)
3.55
3.50
3.45
3.40
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
0
0.2
0.4
0.6
0.8
1.0
DIFFERENTIAL INPUT VOLTAGE, VID (V)
1.2
1.4
0.5
1.0
1.5
2.0
2.5
240
tF CHANNEL 2
tR CHANNEL 2
tF CHANNEL 1
tR CHANNEL 1
220
200
180
160
140
120
2.35
2.40
2.45
2.50
2.55
2.60
2.65
SUPPLY VOLTAGE, VDD1 /VDD2 (V)
17011-018
DIFFERENTIAL PROPAGATION DELAY (ns)
3.60
3.30
0
Figure 25. Differential Output Transition Time vs. Supply Voltage, VDD1/VDD2
Figure 22. Differential Propagation Delay vs. Ambient Temperature
3.35
3.35
Figure 24. Differential Propagation Delay vs. Receiver Input Offset Voltage, VIC
DIFFERENTIAL OUTPUT TRANSITION TIME (ps)
3.9
3.40
RECEIVER INPUT OFFSET VOLTAGE, VIC (V)
17011-017
DIFFERENTIAL PROPAGATION DELAY (ns)
4.0
3.45
3.30
17011-016
3.35
3.50
17011-019
3.50
3.55
Figure 23. Differential Propagation Delay vs. Differential Input Voltage, VID
240
220
200
180
160
tF CHANNEL 2
tR CHANNEL 2
tF CHANNEL 1
tR CHANNEL 1
140
120
–50
–25
0
25
50
75
AMBIENT TEMPERATURE (°C)
100
125
17011-021
3.55
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
17011-020
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
DIFFERENTIAL PROPAGATION DELAY (ns)
DIFFERENTIAL PROPAGATION DELAY (ns)
3.60
Data Sheet
Figure 26. Differential Output Transition Time vs. Ambient Temperature
Rev. D | Page 14 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
30
90
DETERMINISTIC JITTER (ps)
20
15
10
70
60
50
40
30
20
5
2.40
2.45
2.50
2.55
2.60
2.65
SUPPLY VOLTAGE, VDD1 AND VDD2 (V)
10
CHANNEL 1
CHANNEL 2
0
2.35
2.40
2.50
2.55
2.60
2.65
Figure 30. Deterministic Jitter vs. Supply Voltage, VDD1/VDD2
Figure 27. Duty Cycle Skew, tSK(D) vs. Supply Voltage, VDD1 and VDD2
90
30
CHANNEL 1
CHANNEL 2
80
DETERMINISTIC JITTER (ps)
25
20
15
10
70
60
50
40
30
20
5
–25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
10
0
-40
80
-10
5
20
35
50
65
80
95
110
AMBIENT TEMPERATURE (°C)
125
Figure 31. Deterministic Jitter vs. Ambient Temperature
Figure 28. Duty Cycle Skew, tSK(D) vs. Ambient Temperature
90
-25
17011-026
0
–50
tSK(D) CHANNEL 2
tSK(D) CHANNEL 1
17011-123
DUTY CYCLE SKEW, tSK(D) (ps)
2.45
SUPPLY VOLTAGE, VDD1 /VDD2 (V)
17011-025
0
2.35
tSK(D) CHANNEL 2
tSK(D) CHANNEL 1
17011-122
DUTY CYCLE SKEW, tSK(D) (ps)
80
25
CHANNEL 1
CHANNEL 2
200k
160k
140k
50
120k
HITS
60
40
100k
80k
30
60k
20
40k
10
20k
200
400
600
800
1000
DATA RATE (Mbps)
1200
0
–80
–60
–40
–20
0
TIME (ps)
20
40
60
17011-128
0
0
17011-024
DETERMINISTIC JITTER (ps)
180k
70
Figure 32. Time Interval Error (TIE) Histogram for DOUT1± at 550 MHz
Figure 29. Deterministic Jitter vs. Data Rate
Rev. D | Page 15 of 25
CH2 50mV
300ps/DIV
DELAY 61.0828ns
CH1 50mV
Figure 33. Eye Diagram for DOUT1± at 300 MHz
300
100
0
–100
–200
–300
–400
–200
0
TIME (ps)
200
400
600
17011-130
VOLTAGE (mV)
200
–600
300ps/DIV
DELAY 61.0828ns
Figure 35. Eye Diagram for DOUT2± at 300 MHz
400
–400
CH2 50mV
Figure 34. Eye Diagram for DOUT1± at 550 MHz
Rev. D | Page 16 of 25
17011-129
CH1 50mV
Data Sheet
17011-127
ADN4654/ADN4655/ADN4656
Data Sheet
ADN4654/ADN4655/ADN4656
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
DOUTx+
DINx+
DINx–
VIN–
D
V
RL/2
DOUTx–
VOS
V
VOD
R
DINx–
D
DOUTx–
NOTES
1. VTEST = 0V TO 2.4V
3.75kΩ
DINx+
VTEST
SIGNAL
GENERATOR
V
RL
3.75kΩ
VOUT+
VOUT–
Figure 38. Voltage Definitions
V VOD
50Ω
17011-030
DOUTx+
VOD
DOUTx–
NOTES
1. VID = VIN+ – VIN–
2. VIC = (VIN+ + VIN–)/2
3. VOD = VOUT+ – VOUT–
4. VOS = (VOUT+ + VOUT–)/2
Figure 36. Driver Test Circuit
DINx+
DINx–
17011-031
R
VID
VIN+
RL/2
D
DOUTx+
R
50Ω DINx–
Rev. D | Page 17 of 25
RL
D
DOUTx–
NOTES
1. CL INCLUDES PROBE AND JIG CAPACITANCE.
Figure 37. Driver Test Circuit (Full Load Across Common-Mode Range)
CL
Figure 39. Timing Test Circuit
CL
17011-032
DOUTx+
17011-029
DINx+
R
ADN4654/ADN4655/ADN4656
Data Sheet
THEORY OF OPERATION
The ADN4654/ADN4655/ADN4656 are TIA/EIA-644-A LVDS
compliant isolated buffers. LVDS signals applied to the inputs are
transmitted on the outputs of the buffer, and galvanic isolation
is integrated between the two sides of the device. This integration
allows drop-in isolation of the LVDS signal chains.
can detect either state), as shown in Table 16 for the ADN4654. The
ADN4655/ADN4656 incorporates a fail-safe circuit to ensure
that the LVDS outputs are in a known state (logic high) when
the input state is undefined (−100 mV < VID < +100 mV), as
shown in Table 17.
The LVDS receiver detects the differential voltage present across
a termination resistor on an LVDS input. An integrated digital
isolator transmits the input state across the isolation barrier,
and an LVDS driver outputs the same state as the input.
This input state occurs when the inputs are floating (unconnected
with no termination resistor), shorted, or when there is no
active driver connected to the inputs with a termination resistor
present. Open-circuit, short-circuit, and terminated or idle bus
fail-safes, respectively, ensure a known output state for these
conditions, as implemented by the ADN4655/ADN4656.
When there is a positive differential voltage of ≥100 mV across
any DINx± pin, the corresponding DOUTx+ pin sources current.
This current flows across the connected transmission line and
termination at the receiver at the far end of the bus, while
DOUTx− sinks the return current. When there is a negative
differential voltage of ≤−100 mV across any DINx± pin, the
corresponding DOUTx+ pin sinks current and the DOUTx− pin
sources current. Table 16 and Table 17 show these input and
output combinations.
The output drive current is between ±2.5 mA and ±4.5 mA
(typically ±3.1 mA), developing between ±250 mV and ±450 mV
across a 100 Ω termination resistor (RT). The received voltage is
centered around 1.2 V. Because the differential voltage (VID)
reverses polarity, the peak-to-peak voltage swing across RT is
twice the differential voltage magnitude (|VID|).
TRUTH TABLE AND FAIL-SAFE RECEIVER
The LVDS standard, TIA/EIA-644-A, defines normal receiver
operation under two conditions: an input differential voltage
of ≥+100 mV corresponding to one logic state, and a voltage of
≤−100 mV for the other logic state. Between these thresholds,
standard LVDS receiver operation is undefined (the LVDS receiver
After these input states (−100 mV < VID < +100 mV) trigger
the fail-safe circuit, there is a delay of up to 1.2 μs before the
output is guaranteed to be high (VOD ≥ 250 mV). During this
time, the output may transition to, or stay in, a logic low state
(VOD ≤ −250 mV).
The fail-safe circuit triggers as soon as the input differential voltage
remains between +100 mV and −100 mV for some nanoseconds.
Therefore, very slow rise and fall times on the input signal,
outside typical LVDS operation (350 ps maximum tR/tF), can
potentially trigger the fail-safe circuit on a high to low crossover.
At the minimum |VID| of 100 mV for normal operation, the rise
and fall time must be ≤5 ns to avoid triggering a fail-safe state.
Increasing |VID| to 200 mV allows an input rise and fall time of
up to 10 ns without triggering a fail-safe state. For speed applications with restricting data rates less than 30 Mbps, where slow
high to low transitions in excess of this limit are expected, use
external biasing resistors to introduce a minimum |VID| of
100 mV if the fail-safe cannot trigger.
Table 16. ADN4654 Input and Output Operation
Powered On
Yes
Yes
Yes
No
Input (DINx±)
VID (mV)
≥100
≤−100
−100 < VID < +100
Don’t care
Logic
High
Low
Indeterminate
Don’t care
Powered On
Yes
Yes
Yes
Yes
Output (DOUTx±)
VOD (mV)
≥250
≤−250
Indeterminate
≥250
Logic
High
Low
Indeterminate
High
Table 17. ADN4655/ADN4656 Input and Output Operation
Powered On
Yes
Yes
Yes
No
Input (DINx±)
VID (mV)
≥100
≤−100
−100 < VID < +100
Don’t care
Logic
High
Low
Indeterminate
Don’t care
Rev. D | Page 18 of 25
Powered On
Yes
Yes
Yes
Yes
Output (DOUTx±)
VOD (mV)
≥250
≤−250
≥250
≥250
Logic
High
Low
High
High
Data Sheet
ADN4654/ADN4655/ADN4656
ISOLATION
In response to any change in the input state detected by the
integrated LVDS receiver, an encoder circuit sends narrow (~1 ns)
pulses to a decoder circuit using integrated transformer coils.
The decoder is bistable and is, therefore, either set or reset by
the pulses that indicate input transitions. The decoder state
determines the LVDS driver output state in normal operation,
which reflects the isolated LVDS buffer input state.
On power-up, the output state may initially be in the incorrect
dc state if there are no input transitions. The output state is
corrected within 1 μs by the refresh pulses.
If the decoder receives no internal pulses for more than
approximately 1 μs, the device assumes that the input side is
unpowered or nonfunctional, in which case, the output is set to
a positive differential voltage (logic high).
In the absence of input transitions for more than approximately
1 μs, a periodic set of refresh pulses, indicative of the correct input
state, ensures dc correctness at the output (including the fail-safe
output state, if applicable).
Rev. D | Page 19 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
APPLICATIONS INFORMATION
The ADN4654/ADN4655/ADN4656 can operate with high
speed LVDS signals up to 0.55 GHz clock, or 1.1 Gbps nonreturn to
zero (NRZ) data. When operating with such high frequencies,
apply best practices for the LVDS trace layout and termination.
Place a 100 Ω termination resistor as close as possible to the
receiver, across the DINx+ and DINx− pins.
Controlled 50 Ω impedance traces are needed on LVDS signal
lines for full signal integrity, reduced system jitter, and minimizing
electromagnetic interference (EMI) from the PCB. Trace widths,
lateral distance within each pair, and distance to the ground plane
underneath all must be chosen appropriately. Via fencing to the
PCB ground between pairs is also a best practice to minimize
crosstalk between adjacent pairs.
The ADN4654/ADN4655/ADN4656 pass EN 55022 Class B
emissions limits without extra considerations required for the
isolator when operating with up to 1.1 Gbps PRBS data. When
isolating high speed clocks (for example, 0.55 GHz), a reduced
PCB clearance (isolation gap) may be required with the 20-lead
SOIC_W model to reduce dipole antenna effects and provide
sufficient margin below Class B emissions limits.
The best practice for high speed PCB design avoids any other
emissions from PCBs in applications that use the ADN4654/
ADN4655/ADN4656. Take care when configuring off-board
connections, where switching transients from high speed LVDS
signals (clocks in particular) can conduct onto cabling, resulting
in radiated emissions. Use common-mode chokes, ferrites, or
other filters as appropriate at the LVDS connectors, as well as
cable shield or PCB ground connections to earth or chassis.
The ADN4654/ADN4655/ADN4656 require appropriate
decoupling of the VDDx pins with 100 nF capacitors. If the
integrated LDO regulator is not used, and a 2.5 V supply is
connected directly, connect the appropriate VINx pin to the supply
as well, as shown in Figure 40, using the ADN4654 as an
example.
100nF
GND1
VDD1
100Ω
100Ω
20
2
19
VIN2
GND2
VDD2
3
18
GND1
4
17
GND2
DIN1+
5
16
DOUT1+
ADN4654
DIN1–
TOP VIEW
6 (Not to Scale) 15
DIN2+
7
14
DOUT2+
DIN2–
8
13
DOUT2–
9
12
10
11
VDD1
GND1
100nF
DOUT1–
VDD2
GND2
100nF
17011-033
VIN1
100nF
1
Figure 40. Required PCB Layout When Not Using LDO Regulator (2.5 V Supply)
When the integrated LDO regulator is used, bypass capacitors
of 1 μF are required on the VINx pins and on the nearest VDDx
pins (LDO output), as shown in Figure 41.
100nF
1µF
1µF
VIN1
20
GND1
2
19
3
18
GND1
4
17
GND2
DIN1+
5
16
6
TOP VIEW
(Not to Scale) 15
DOUT1+
DIN1–
DIN2+
7
14
DOUT2+
DIN2–
8
13
DOUT2–
9
12
10
11
VDD1
100Ω
100Ω
100nF
1µF
1µF
VIN2
1
VDD1
GND1
ADN4654
100nF
GND2
VDD2
DOUT1–
VDD2
GND2
100nF
17011-034
PCB LAYOUT
Figure 41. Required PCB Layout When Using LDO Regulator (3.3 V Supply)
APPLICATION EXAMPLES
High speed LVDS interfaces for the analog front-end (AFE),
processor to processor communication, or video and imaging data
can be isolated using the ADN4654, as an example, between
components, between boards, or at a cable interface. The ADN4654
provides the galvanic isolation required for robust external ports,
and the low jitter and high drive strength of the device allow
communication along short cable runs of a few meters. High
common-mode immunity ensures communication integrity
even in harsh, noisy environments, and isolation can protect
against electromagnetic compatibility (EMC) transients up to
±8 kV peak, such as ESD, electrical fast transient (EFT), and
surge. The ADN4654 can isolate a range of video and imaging
protocols, including protocols that use current mode logic
(CML) rather than LVDS for the physical layer. One example is
High-Definition Multimedia Interface (HDMI), where
ac coupling and biasing and termination resistor networks are
used as shown in Figure 42 to convert between CML (used by
the transition minimized differential signaling (TMDS) data
and clock lanes) and the LVDS levels required by the ADN4654.
Additional Analog Devices isolator components, such as the
ADuM1250/ADuM1251 I2C isolators, can be used to isolate
control signals and power (ADuM5020 isoPower integrated,
isolated dc-to-dc converter). This circuit supports resolutions
up to 720p.
Other circuits can use the ADN4654 for isolating MIPI CSI-2,
DisplayPort, and LVDS-based protocols such as FPD-Link. Use
of a field-programmable gate array (FPGA) or an applicationspecific integrated circuit (ASIC) serializer/deserializer (SERDES)
expands bandwidth through multiple ADN4654 devices to
support 1080p or 4K video resolutions, providing an alternative
to short reach fiber links.
Rev. D | Page 20 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
3
4
TMDS D0+
TMDS D0–
TMDS CLK+
TMDS CLK–
ISOLATION
2
ISOLATION
TMDS D2+
TMDS D2–
ADN4654 (×2)
TERMINATION, AC COUPLING,
AND BIASING NETWORKS
TMDS D1+
TMDS D1–
1
HDMI SOURCE
ADuM1250
TVS NETWORK,
CONNECTORS,
AND CABLE
TVS NETWORK, CONNECTORS,
CABLE, AND BIASING NETWORKS
2
TMDS D0+
TMDS D0–
TMDS D1+
TMDS D1–
TMDS D2+
TMDS D2–
TMDS CLK+
TMDS CLK–
SDA
SDA
SCK
SCK
HDMI SINK
1
ADuM1251
CEC
CEC
HPD
HPD
ADuM5020 (×2)
VDDP
OSC
REC
REG
VDDP
OSC
VISO (3.3V)
SUPPLY FOR ISOLATORS
REC
REG
VISO (5V, 100mA)
17011-038
NOTES
1. SUPPLY BIASED TERMINATION
2. AC COUPLING
3. COMMON-MODE BIASING
4. DIFFERENTIAL TERMINATION
+5V
Figure 42. Example Isolated Video Interface (HDMI) Using the ADN4654
Rev. D | Page 21 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
The pulses at the transformer output have an amplitude greater
than 0.5 V. The decoder has a sensing threshold of about 0.25 V,
therefore establishing a 0.25 V margin in which induced voltages
are tolerated. The voltage (V) induced across the receiving coil
is given by
2
V = (−dβ/dt)∑πrn ; n = 1, 2, …, N
where:
dβ is the change in magnetic flux density.
dt is the change in time.
rn is the radius of the nth turn in the receiving coil.
N is the number of turns in the receiving coil.
100
10
1
DISTANCE = 100mm
DISTANCE = 5mm
0.1
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 44. Maximum Allowable Current for Various Current to ADN4654
Spacings
In combinations of strong magnetic field and high frequency,
any loops formed by PCB traces can induce sufficiently large
error voltages to trigger the thresholds of succeeding circuitry.
Avoid PCB structures that form loops.
INSULATION LIFETIME
1k
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
DISTANCE = 1m
1k
0.01
1k
Given the geometry of the receiving coil in the ADN4654/
ADN4655/ADN4656 and an imposed requirement that the
induced voltage be, at most, 50% of the 0.25 V margin at the
decoder, a maximum allowable external magnetic flux density is
calculated as shown in Figure 43.
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation as well as on
the materials and material interfaces.
100
10
1
0.1
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
17011-035
0.01
0.001
1k
10k
17011-036
The limitation on the magnetic field immunity of the device is
set by the condition in which the induced voltage in the transformer receiving coil is sufficiently large, either to falsely set or
reset the decoder. The following analysis defines such conditions.
The ADN4654/ADN4655/ADN4656 are examined in a 2.375 V
operating condition because this operating condition represents
the most susceptible mode of operation for these products.
insensitive to external fields. Only extremely large, high frequency
currents that are close to the component can potentially be a
concern. For the 1 MHz example noted, a 2.29 kA current must be
placed 5 mm from the ADN4654/ADN4655/ADN4656 to affect
component operation.
MAXIMUM ALLOWABLE CURRENT (kA)
MAGNETIC FIELD IMMUNITY
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Figure 43. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.92 kgauss induces a
voltage of 0.125 V at the receiving coil. This voltage is about
50% of the sensing threshold and does not cause a faulty output
transition. If such an event occurs with the worst case polarity
during a transmitted pulse, the applied magnetic field reduces
the received pulse from >0.5 V to 0.375 V. This voltage is still
higher than the 0.25 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADN4654/
ADN4655/ADN4656 transformers. Figure 44 expresses these
allowable current magnitudes as a function of frequency for
selected distances. The ADN4654/ADN4655/ADN4656 are
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components, which allows the components to
be categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation barrier, pollution degree, and material group. The
material group and creepage for ADN4654/ADN4655/ADN4656
are detailed in Table 4 and Table 5.
Rev. D | Page 22 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
Testing and modeling show that the primary driver of long-term
degradation is displacement current in the polyimide insulation
causing incremental damage. The stress on the insulation can be
broken down into broad categories, such as dc stress, which causes
little wear out because there is no displacement current, and an
ac component time varying voltage stress, which causes wear out.
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this type of waveform reflects
isolation from line voltage. However, many practical applications
have combinations of 60 Hz ac and dc across the isolation barrier,
as shown in Equation 1. Because only the ac portion of the
stress causes wear out, the equation can be rearranged to solve
for the ac rms voltage, as shown in Equation 2. For insulation
wear out with the polyimide materials used in this product, the
ac rms voltage determines the product lifetime.
VRMS VAC RMS2 VDC 2
(1)
VAC RMS VRMS 2 VDC 2
(2)
or
where:
VRMS is the total rms working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
The working voltage across the barrier from Equation 1 is
VRMS VAC RMS2 VDC 2
VRMS 2402 4002
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the creepage
required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
VAC RMS VRMS 2 VDC 2
VAC RMS 4662 4002
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. Table 12 compares the value to the limits for the
working voltage for the expected lifetime. Note that the dc
working voltage limit in Table 12 is set by the creepage of the
package as specified in IEC 60664-1. This value can differ for
specific system level standards.
Rev. D | Page 23 of 25
VAC RMS
VPEAK
VRMS
VDC
TIME
Figure 45. Critical Voltage Example
17011-037
The lifetime of insulation caused by wear out is determined by
the thickness of the insulation, material properties, and the voltage
stress applied. It is important to verify that the product lifetime
is adequate at the application working voltage. The working
voltage supported by an isolator for wear out may not be the
same as the working voltage supported for tracking. The working
voltage applicable to tracking is specified in most standards.
creepage, clearance, and lifetime of a device, see Figure 45 and
the following equations.
ISOLATION VOLTAGE
Insulation Wear Out
ADN4654/ADN4655/ADN4656
Data Sheet
OUTLINE DIMENSIONS
7.50
7.20
6.90
11
20
5.60
5.30
5.00
1
8.20
7.80
7.40
10
PIN 1
INDICATOR
TOP VIEW
0.05 MIN
COPLANARITY
0.10
0.38
0.22
PKG-004600
0.65 BSC
0.25
0.09
1.85
1.75
1.65
SIDE VIEW
END VIEW
8°
4°
0°
SEATING
PLANE
0.95
0.75
0.55
COMPLIANT TO JEDEC STANDARDS MO-150-AE
06-01-2006-A
2.00 MAX
Figure 46. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
13.00 (0.5118)
12.60 (0.4961)
20
11
7.60 (0.2992)
7.40 (0.2913)
10
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
1.27
(0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
45°
0.25 (0.0098)
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 47. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
Rev. D | Page 24 of 25
1.27 (0.0500)
0.40 (0.0157)
06-07-2006-A
1
Data Sheet
ADN4654/ADN4655/ADN4656
ORDERING GUIDE
Model1
ADN4654BRSZ
ADN4654BRSZ-RL7
ADN4654BRWZ
ADN4654BRWZ-RL7
ADN4655BRSZ
ADN4655BRSZ-RL7
ADN4655BRWZ
ADN4655BRWZ-RL7
ADN4656BRSZ
ADN4656BRSZ-RL7
ADN4656BRWZ
ADN4656BRWZ-RL7
EVAL-ADN4654EBZ
EVAL-ADN4654EB1Z
EVAL-ADN4655EBZ
EVAL-ADN4655EB1Z
EVAL-ADN4656EBZ
EVAL-ADN4656EB1Z
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
ADN4654 SSOP Evaluation Board
ADN4654 SOIC_W Evaluation Board
ADN4655 SSOP Evaluation Board
ADN4655 SOIC_W Evaluation Board
ADN4656 SSOP Evaluation Board
ADN4656 SOIC_W Evaluation Board
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17011-0-9/19(D)
Rev. D | Page 25 of 25
Package Option
RS-20
RS-20
RW-20
RW-20
RS-20
RS-20
RW-20
RW-20
RS-20
RS-20
RW-20
RW-20
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