12-Bit High Output Current Source
ADN8810
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High precision 12-bit current source
Low noise
Long term stability
Current output from 0 mA to 300 mA
Output fault indication
Low drift
Programmable maximum current
24-lead, 4 mm × 4 mm LFCSP
3-wire serial interface
ENCOMP
RESET
RESET
4.096V
VREF
CS
SERIAL
INTERFACE
5V
5V
3.3V
DVDD
AVDD
PVDD
FB
ADN8810
IOUT
SCLK
RSN
1.6
SDI
APPLICATIONS
Tunable laser current source
Programmable high output current source
Automatic test equipment
FAULT
SB
AVSS DVSS DGND
03195-0-001
3
D1
RSN
ADDR0-2
ADDRESS
RSN
1.6
SB
FAULT
INDICATION
Figure 1.
GENERAL DESCRIPTION
The ADN8810 is a 12-bit current source with an adjustable fullscale output current of up to 300 mA. The full-scale output current
is set with two external sense resistors. The output compliance
voltage is 2.5 V, even at output currents up to 300 mA.
The device is particularly suited for tunable laser control and
can drive tunable laser front mirror, back mirror, phase, gain,
and amplification sections. A host CPU or microcontroller
controls the operation of the ADN8810 over a 3-wire serial
peripheral interface (SPI). The 3-bit address allows up to eight
devices to be independently controlled while attached to the
same SPI bus.
Noise and digital feedthrough are kept low to ensure low jitter
operation for laser diode applications. Full-scale and scaled
output currents are given in Equation 1 and Equation 2,
respectively.
I FS
VREF
10 RSN
(1)
I OUT Code
VREF
1 RSN
0.1
4096 RSN 15 k
(2)
The ADN8810 is guaranteed with ±4 LSB integral nonlinearity
(INL) and ±0.75 LSB differential nonlinearity (DNL).
Rev. C
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ADN8810
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Setting Full-Scale Output Current ........................................... 10
Applications ....................................................................................... 1
Power Supplies ............................................................................ 10
Functional Block Diagram .............................................................. 1
Serial Data Interface ................................................................... 10
General Description ......................................................................... 1
Standby and Reset Modes ......................................................... 11
Revision History ............................................................................... 2
Power Dissipation....................................................................... 11
Specifications..................................................................................... 3
Using Multiple ADN8810 Devices for Additional Output
Current......................................................................................... 11
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Terminology ...................................................................................... 9
Functional Description .................................................................. 10
Adding Dither to the Output Current ..................................... 12
Driving Common-Anode Laser Diodes ................................. 12
PCB Layout Recommendations ............................................... 13
Suggested Pad Layout for CP-24 Package ............................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
11/2017—Rev. B. to Rev. C
Changed RS to RSN .......................................................... Throughout
Change to Figure 1 ........................................................................... 1
Changes to Maximum Full-Scale Output Current Parameter
and Power Supply Rejection Ratio Parameter, Table 1 ................ 3
Moved Timing Characteristics Section, Table 2, and Figure 2 ..... 4
Added Lead Temperature Range (Soldering 10 sec) Parameter,
Table 3 ................................................................................................ 5
Changes to Figure 3 and Table 4 ..................................................... 6
Changes to Setting Full-Scale Output Current Section ............. 10
Changes to Adding Dither to the Output Current Section,
Figure 20, and Figure 21 ................................................................ 12
Changes to PCB Layout Recommendations Section and
Figure 25 .......................................................................................... 13
Updated to Outline Dimensions .................................................. 14
3/2016—Rev. A to Rev. B
Changes to Figure 3 and Table 4......................................................7
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
4/2009—Rev. 0 to Rev. A
Changes to Table 3.............................................................................6
Changes to Figure 25...................................................................... 14
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
1/2004—Revision 0: Initial Version
Rev. C | Page 2 of 14
Data Sheet
ADN8810
SPECIFICATIONS
AVDD = DVDD = 5 V, PVDD = 3.3 V, AVSS = DVSS = DGND = 0 V, TA = 25°C, covering output current (IOUT) from 2% full-scale
current (IFS) to 100% IFS, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter
DC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Offset
Offset Drift
Gain Error
REFERENCE INPUT
Reference Input Voltage
Input Current
Bandwidth
ANALOG OUTPUT
Output Current Change vs. Output
Voltage Change
Maximum Full-Scale Output Current
Output Compliance Voltage
AC PERFORMANCE
Settling Time
Bandwidth
Current Noise Density at 10 kHz
Standby Recovery
POWER SUPPLY 1
Power Supply Voltage
Power Supply Rejection Ratio
Supply Current
FAULT DETECTION
Load Open Threshold
Load Short Threshold
FAULT Logic Output
Symbol
Test Conditions/Comments
Min
N
INL
DNL
Typ
4
VREF
3.9
BWREF
VOUT = 0.7 V to 2.0 V
IFS, MAX
VCOMP
RSN = 1.37 Ω
−40°C to +85°C; IFS = 300 mA
IDVDD
IAVDD
IPVDD
IAVDD
IPVDD
±4
±0.75
8
15
Bits
LSB
LSB
LSB
ppm/°C
1
%FS
4.096
4.3
1
V
µA
MHz
400
ppm/V
2
ΔIOUT/ΔVOUT
DVDD
AVDD
PVDD
PSRR
Unit
12
RSN resistance (RSN) = 1.6 Ω;
IOUT = 127 mA
τS
BW
iN
Max
100
300
2.0
IFS = 250 mA
IFS = 100 mA
IFS = 50 mA
3.0
4.5
3.0
AVDD = 4.5 V to 5.5 V 2
PVDD = 3.0 V to 3.6 V2
IOUT = 0 mA, SB = DVDD
IOUT = 0 mA, SB = DVDD
IOUT = 0 mA, SB = DVDD
SB = 0 V
SB = 0 V
2.5
mA
V
3
5
7.5
3
1.5
6
µs
MHz
nA/√Hz
nA/√Hz
nA/√Hz
µs
5
5
3.3
0.4
0.4
11
1
3
1
0.33
5.5
5.5
5.5
5
5
50
2
PVDD − 0.6
AVSS + 0.2
VOH
VOL
DVDD = 5.0 V
DVDD = 5.0 V
Rev. C | Page 3 of 14
4.5
0.5
V
V
V
µA/V
µA/V
µA
mA
mA
mA
mA
V
V
V
V
ADN8810
Data Sheet
Parameter
LOGIC INPUTS
Input Leakage Current
Input Low Voltage
Symbol
IIL
VIL
Input High Voltage
VIH
INTERFACE TIMING 3
Clock Frequency
RESET Pulse Width
fCLK
t11
Test Conditions/Comments
DVDD = 3.0 V
DVDD = 5 V
DVDD = 3.0 V
DVDD = 5 V
Min
Typ
Max
Unit
1
0.5
0.8
µA
V
V
V
V
12.5
MHz
ns
2.4
4
40
With respect to AVSS.
RSN = 20 Ω.
3
See Table 2 for timing specifications.
1
2
TIMING CHARACTERISTICS
Table 2. Timing Characteristics 1, 2
Parameter
fCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
2
Min
Typ
Max
12.5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
80
40
40
15
15
35
20
15
2
30
40
30
Guaranteed by design. Not production tested.
Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10%
to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2.
t1
SCLK
t6
CS
t3
t4
t7
t5
t10
t8
SDI
t2
t9
A3*
A2
A1
A0
D11
D10
D0
t12
RESET
* ADDRESS BIT A3 MUST BE LOGIC LOW
Figure 2. Timing Diagram
Rev. C | Page 4 of 14
t11
03195-0-002
1
Description
SCLK frequency
SCLK cycle time
SCLK width high
SCLK width low
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold
SCLK high to CS high hold
Data setup
Data hold
CS high pulse width
RESET pulse width
CS high to RESET low hold
Data Sheet
ADN8810
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range, CP Package
Lead Temperature Range (Soldering 10 sec)
Rating
6V
GND to VS+ 0.3 V
Indefinite
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. C | Page 5 of 14
ADN8810
Data Sheet
20 SCLK
19 SDI
21 CS
22 RESET
ADDR2 1
18 DVSS
RSN 2
ADDR1 4
ADDR0 5
17 NIC
16 AVSS
ADN8810
FB 3
TOP VIEW
(Not to Scale)
15 AVDD
14 VREF
FAULT 6
ENCOMP 12
PVDD 11
IOUT 10
IOUT 9
SB 7
PVDD 8
13 NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO DGND.
03195-0-003
PIN 1
INDICATOR
23 DVDD
24 DGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8, 11
9, 10
12
13, 17
14
15
16
18
19
20
21
22
23
24
Mnemonic
ADDR2
RSN
FB
ADDR1
ADDR0
FAULT
SB
PVDD
IOUT
ENCOMP
NIC
VREF
AVDD
AVSS
DVSS
SDI
SCLK
CS
RESET
DVDD
DGND
EPAD
Type
Digital Input
Analog Input
Analog Input
Digital Input
Digital Input
Digital Output
Digital Input
Analog Power
Analog Output
Digital Input
Not Applicable
Analog Input
Analog Power
Analog Ground
Digital Ground
Digital Input
Digital Input
Digital Input
Digital Input
Digital Power
Digital Ground
Heat Sink
Description
Chip Address, Bit 2.
Sense Resistor RS2 Feedback.
Sense Resistor RS1 Feedback.
Chip Address, Bit 1.
Chip Address, Bit 0.
Load Open/Short Indication.
Active Deactivates Output Stage (High Output Impedance State).
Power Supply for IOUT (3.3 V Recommended).
Current Output.
Connect to AVSS.
Not Internally Connected.
Input for High Accuracy External Reference Voltage (ADR292ER).
Power Supply for DAC.
Connect to Analog Ground or Most Negative Potential in Dual-Supply Applications.
Connect to Digital Ground or Most Negative Potential in Dual-Supply Applications.
Serial Data Input.
Serial Clock Input.
Chip Select; Active Low.
Asynchronous Reset to Return DAC Output to Code Zero; Active Low.
Power Supply for Digital Interface.
Digital.
Exposed Pad. Connect the exposed pad to DGND.
Rev. C | Page 6 of 14
Data Sheet
ADN8810
TYPICAL PERFORMANCE CHARACTERISTICS
1.2
0.20
1.0
0.15
0.10
0.6
∆DNL (LSB)
INL ERROR (LSB)
0.8
0.4
0.2
0
0.05
0
–0.05
–0.2
–0.10
–0.6
–0.8
0
500
03195-0-008
03195-0-005
–0.4
–0.15
–0.20
–40
1,000 1,500 2,000 2,500 3,000 3,500 4,000 4,500
CODE
–15
Figure 4. Typical INL Plot
10
35
TEMPERATURE (°C)
60
85
60
85
Figure 7. ∆DNL vs. Temperature
0.4
0.258
0.3
0.257
0.1
0
–0.1
–0.3
0
500
0.255
0.254
0.253
0.252
0.251
03195-0-006
–0.2
0.256
0.250
–40
1,000 1,500 2,000 2,500 3,000 3,500 4,000 4,500
CODE
–15
Figure 8. Full-Scale Output vs. Temperature
20.765
0.15
20.760
0.10
20.755
FULL-SCALE OUTPUT (mA)
0.20
0.05
0
–0.05
–0.10
03195-0-007
∆INL (LSB)
Figure 5. Typical DNL Plot
–0.15
–0.20
–40
–15
10
35
TEMPERATURE (°C)
10
35
TEMPERATURE (°C)
60
RSN = 20Ω
20.750
20.745
20.740
20.735
20.730
03195-0-010
DNL ERROR (LSB)
0.2
03195-0-009
FULL-SCALE OUTPUT (A)
RSN = 1.6Ω
20.725
20.720
–40
85
Figure 6. ∆INL vs. Temperature
–15
10
35
TEMPERATURE (°C)
60
Figure 9. Full-Scale Output vs. Temperature
Rev. C | Page 7 of 14
85
ADN8810
Data Sheet
100k
0.50
CODE = x000
RSN = 1.6Ω
0.45
10k
OUTPUT IMPEDANCE (Ω)
0.40
0.30
0.25
0.20
0.15
1k
100
03195-0-011
0.05
0
–40
–15
10
35
TEMPERATURE (°C)
60
1
85
10
100
1k
10k
FREQUENCY (Hz)
100k
CODE = x000
CODE: x700 TO xFFF
10
5V/DIV
VOLTAGE (2.7V/DIV)
CS
8
IDVDD (µA )
1M
Figure 13. Output Impedance vs. Frequency
Figure 10. PVDD Supply Current (IPVDD) vs. Temperature
12
03195-0-014
10
0.10
6
4
0
–40
–15
10
35
60
300mA/DIV
IOUT
03195-0-012
2
85
03195-0-015
IPVDD (mA)
0.35
TIME (1µs/DIV)
TEMPERATURE (°C)
Figure 11. DVDD Supply Current (IDVDD) vs. Temperature
Figure 14. Full-Scale Settling Time
1.5
CODE: x7FF TO x800
RSN = 1.6Ω
CODE = x000
5V/DIV
CS
1.3
1.2
IOUT
10mA/DIV
1.0
–40
03195-0-016
1.1
03195-0-013
IAVDD (mA)
1.4
–15
10
35
TEMPERATURE (°C)
60
85
TIME (200ns/DIV)
Figure 15. 1 LSB Settling Time
Figure 12. AVDD Supply Current (IAVDD) vs. Temperature
Rev. C | Page 8 of 14
Data Sheet
ADN8810
TERMINOLOGY
Offset Error
Offset error, or zero-code error, is an interpolation of the output
voltage at code 0x000 as predicted by the line formed from the
output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS).
Ideally, the offset error is 0 V. Offset error occurs from a
combination of the offset voltage of the amplifier and offset
errors in the DAC. It is expressed in LSBs.
Offset Drift
This is a measure of the change in offset error with a change in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the output transfer characteristic from
ideal. The transfer characteristic is the line formed from the
output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS).
It is expressed as a percent of the full-scale range.
Output Current Change vs. Output Voltage Change
This is a measure of the ADN8810 output impedance and is
similar to a load regulation spec in voltage references. For a
given code, the output current changes slightly as output voltage
increases. It is measured as an absolute value in (ppm of fullscale range)/V.
GAIN ERROR
PLUS
OFFSET ERROR
INTERPOLATED
IDEAL
ACTUAL
(EXAGGERATED)
OFFSET
ERROR
Rev. C | Page 9 of 14
0x040
DAC CODE
0xFFF
Figure 16. Output Transfer Function
03195-0-004
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity. The ADN8810 is guaranteed
monotonic by design. Figure 5 shows a typical DNL vs. code plot.
Compliance Voltage
The maximum output voltage from the ADN8810 is a function
of output current and supply voltage. Compliance voltage
defines the maximum output voltage at a given current and
supply voltage to guarantee the device operates within its INL,
DNL, and gain error specifications.
OUTPUT VOLTAGE
Relative Accuracy
Relative accuracy or integral nonlinearity (INL) is a measure of
the maximum deviation, in least significant bits (LSBs), from an
ideal line passing through the endpoints of the DAC transfer
function. Figure 4 shows a typical INL vs. code plot. The
ADN8810 INL is measured from 2% to 100% of the full-scale
(FS) output.
ADN8810
Data Sheet
FUNCTIONAL DESCRIPTION
The ADN8810 is a single 12-bit current output digital-to-analog
converter (DAC) with a 3-wire SPI interface. Up to eight devices
can be independently programmed from the same SPI bus.
The full-scale output current is set with two external resistors.
The maximum output current can reach 300 mA. Figure 17
shows the functional block diagram of the ADN8810.
DVDD AVDD FAULT
BIAS
GEN
SB
FB
DVDD provides power for the digital circuitry. This
includes the serial interface logic, the SB and RESET logic
inputs, and the FAULT output. Tie DVDD to the same
supply line used for other digital circuitry. It is not
necessary for DVDD to be low noise.
•
PVDD is the power pin for the output amplifier. It can
operate from as low as 3.0 V to minimize power dissipation
in the ADN8810. For best performance, PVDD must be
low noise.
ENCOMP
FAULT
DETECTION
PVDD
1.5kΩ
VREF
•
PVDD
12-BIT
DAC
Current is returned through the following three pins:
•
AVSS is the return path for both AVDD and PVDD. This
pin is connected to the substrate of the die as well as the
slug on the bottom of the lead frame chip scale package
(LFCSP). For single-supply operation, connect this pin to a
low noise ground plane.
•
DVSS returns current from the digital circuitry powered by
DVDD. Connect DVSS to the same ground line or plane
used for other digital devices in the application.
•
DGND is the ground reference for the digital circuitry. In a
single-supply application, connect DGND to DVSS.
IOUT
IOUT
12-BIT
DATA LATCH
CONTROL
LOGIC
SCLK
SDI
DGND
ADDRESS
DECODER
ADDR2 ADDR1 ADDR0 RESET
AVSS
1.5kΩ
RSN
15kΩ
DVSS
03195-0-017
CS
Figure 17. Functional Blocks, Pins, and Internal Connections
SETTING FULL-SCALE OUTPUT CURRENT
Two external resistors set the full-scale output current from the
ADN8810. These resistors are equal in value and are labeled RSN
in Figure 1. Use 1% or better tolerance resistors to achieve the
most accurate output current and the highest output
impedance.
Equation 3 shows the approximate full-scale output current.
The exact output current is determined by the data register code
as shown in Equation 4. The variable code is an integer from 0
to 4095, representing the full 12-bit range of the ADN8810.
I FS ≈
4.096
10 × RSN
IOUT =
Code
1 RSN
×
×
+ 0. 1
1,000 RSN 15 kΩ
(3)
(4)
The ADN8810 is designed to operate with a 4.096 V reference
voltage connected to VREF. The output current is directly
proportional to this reference voltage. To achieve the best
performance, use a low noise precision (the ADR292, ADR392,
or REF198 is recommended).
POWER SUPPLIES
There are three principal supply current paths through the
ADN8810:
•
AVDD provides power to the analog front end of the
ADN8810 including the DAC. Use this supply line to
power the external voltage reference. For best performance,
AVDD must be low noise.
For single-supply operation, set AVDD to 5 V, set PVDD from
3.0 V to 5 V, and connect AVSS, AGND, and DGND to ground.
SERIAL DATA INTERFACE
The ADN8810 uses a serial peripheral interface (SPI) with three
input signals: SDI, CLK, and CS. Figure 2 shows the timing
diagram for these signals.
Data applied to the SDI pin is clocked into the input shift
register on the rising edge of CLK. After all 16 bits of the dataword have been clocked into the input shift register, a logic high
on CS loads the shift register byte into the ADN8810. If more
than 16 bits of data are clocked into the shift register before CS
goes high, bits are pushed out of the register in first-in first-out
(FIFO) fashion.
The four MSB of the data byte are checked against the address
of the device. If they match, the next 12 bits of the data byte are
loaded into the DAC to set the output current. The first bit
(MSB) of the data byte must be a logic zero, and the following
three bits must correspond to the logic levels on pins ADDR2,
ADDR1, and ADDR0, respectively, for the DAC to be updated.
Up to eight ADN8810 devices with unique addresses can be
driven from the same serial data bus.
Table 5 shows how the 16-bit DATA input word is divided into
an address byte and a data byte. The first four bits in the input
word correspond to the address. Note that the first bit loaded
(A3) must always be zero. The remaining bits set the 12-bit data
byte for the DAC output. Three example inputs are demonstrated.
Rev. C | Page 10 of 14
Data Sheet
•
•
•
Example 1: This SDI input sets the device with an address
of 111 to its minimum output current, 0 A. Connecting the
ADN8810 pins ADDR2, ADDR1, and ADDR0 to VDD
sets this address.
Example 2: This input sets the device with an address of
000 to a current equal to half of the full-scale output.
Example 3: The ADN8810 with an address of 100 is set to
full-scale output.
Using Equation 5, the power dissipation in the ADN8810 is
found to be 267 mW. At TA = 85°C, this makes the junction
temperature 93.5°C, which is well below the 150°C limit. Note
that even with PVDD set to 5 V, the junction temperature
increases to only 110°C.
STANDBY AND RESET MODES
USING MULTIPLE ADN8810 DEVICES FOR
ADDITIONAL OUTPUT CURRENT
Applying a logic low to the SB pin deactivates the ADN8810
and puts the output into a high impedance state. The device
continues to draw 1.3 mA of typical supply current in standby.
When logic high is reasserted on the SB pin, the output current
returns to its previous value within 6 µs.
Connect multiple ADN8810 devices in parallel to increase the
available output current. Each device can deliver up to 300 mA
of current. To program all parallel devices simultaneously, set all
device addresses to the same address byte and drive all CS, SDI,
and CLK from the same serial data interface bus. The circuit in
Figure 18 uses two ADN8810 devices and delivers 600 mA to
the pump laser.
Applying logic low to RESET sets the ADN8810 data register to
all zeros, bringing the output current to 0 A. When RESET is
deasserted, the data register can be reloaded. Data cannot be
loaded into the device while it is in standby or reset mode.
CS
POWER DISSIPATION
SERIAL
INTERFACE
(FROM µC
OR DSP)
The power dissipation of the ADN8810 is equal to the output
current multiplied by the voltage drop from PVDD to the
output.
PDISS = IOUT × (PVDD − VOUT ) − IOUT ² × RSN
Example 4: A 300 mA full-scale output current is required
to drive a laser diode within an 85°C environment. The
laser diode has a 2 V drop and PVDD is 3.3 V.
FB
SCLK
IOUT
ADN8810
RSN
SDI
RSN
1.37Ω
RSN
1.37Ω
ADDR2 ADDR1 ADDR0
(5)
The power dissipated by the ADN8810 causes a temperature
increase in the device. For this reason, PVDD must be as low as
possible to minimize power dissipation.
IOUT
SCLK
ADN8810
While in operation, the ADN8810 die temperature, also known
as junction temperature, must remain below 150°C to prevent
damage. The junction temperature is approximately
TJ = TA + θ JA × PDISS
FB
CS
RSN
SDI
RSN
1.37Ω
RSN
1.37Ω
D1
ADDR2 ADDR1 ADDR0
ILD
600mA
Figure 18. Using Multiple Devices for Additional Output Current
(6)
where:
TA is the ambient temperature in °C,
θJA is the thermal resistance of the package (32°C/W).
Table 5. Serial Data Input Examples
SDI Input
Example 1
Example 2
Example 3
A3
0
0
0
Address Byte
A2
A1
1
1
0
0
1
0
A0
1
0
0
D11
0
1
1
D10
0
0
1
D9
0
0
1
D8
0
0
1
Rev. C | Page 11 of 14
D7
0
0
1
Data Byte
D6
D5
0
0
0
0
1
1
D4
0
0
1
D3
0
0
1
D2
0
0
1
D1
0
0
1
D0
0
0
1
03195-0-018
•
ADN8810
ADN8810
Data Sheet
ADDING DITHER TO THE OUTPUT CURRENT
The 4.096 V reference must also be referred to the −5 V supply
voltage. The diode current is still determined by Equation 7.
Some tunable laser applications require the laser diode bias
current to be modulated or dithered. This is accomplished by
dithering the VREF voltage input to the ADN8810. Figure 19
demonstrates one method.
All logic levels must be shifted down to 0 V and −5 V levels as
well. This includes RESET, CS, SCLK, SDI, SB, and all ADDR pins.
Figure 22 shows a simple method to level shift a standard TTL
or CMOS (0 V to 5 V) signal down using external FETs.
R2
1.62kΩ
ADR292
AD8605
5V
VREF
VOUT
VIN
GND
CS
SCLK
Figure 19. Adding Dither to the Reference Voltage
Set the gain of the dither by adjusting the ratio of R2 to R1.
Increase C to lower the cutoff frequency of the high-pass filter
created by C and R1. The cutoff frequency of Figure 19 is
approximately 98 Hz.
The AD8605 is recommended as a low offset, rail-to-rail input
amplifier for this circuit.
FB
I = 300mA
@ CODE 0x7FF
NC
RESET
TTL/CMOS
LOGIC LEVELS
ADN8810
SDI
3
IOUT
FDC633N
OR EQUIV
RSN
ADDR0-2
SB
RSN
6.81Ω
AVSS DVSS DGND
03195-0-020
TO VREF
D1
ENCOMP DVDD AVDD PVDD
NOTE: LEAVE FB WITH NO CONNECTION
Figure 20. Driving Common-Anode-to-VDD Laser Diodes
–5V
DRIVING COMMON-ANODE LASER DIODES
The ADN8810 can power common-anode laser diodes. These
are laser diodes whose anodes are fixed to the laser module case.
The module case is typically tied to either VDD or ground. For
common anode to ground applications, a −5 V supply must be
provided.
ADR292
VIN
VREF
VOUT
GND
CS
–5V
SCLK
ADN8810
SDI
3
I = 300mA
@ CODE 0x7FF
NC
IOUT
FDC633N
OR EQUIV
RSN
ADDR0-2
SB
1
Code
1
×
+
I = 4.096 × 1.1
R
SN 16.5 kΩ 4096
FB
RESET
–5V TO 0V
LOGIC LEVELS
In Figure 20, RSN sets up the diode current by the following
equation:
D1
ENCOMP DVDD AVDD PVDD
RSN
6.81Ω
AVSS DVSS DGND
(7)
–5V
–5V
NOTE: LEAVE FB WITH NO CONNECTION
where Code is an integer value from 0 to 4095.
Using the values in Figure 20, the diode current is 300.7 mA at a
code value of 2045 (0x7FF), or half full-scale. This effectively
provides 11-bit current control from 0 mA to 300 mA of diode
current.
Figure 21. Driving Common-Anode-to-Ground Laser Diodes with a Negative
Supply
The maximum output current of this configuration is limited by
the compliance voltage at the IOUT pin of the ADN8810. The
voltage at IOUT cannot exceed 1 V below PVDD, in this case,
4 V. The IOUT voltage is equal to the voltage drop across RSN
plus the gate-to-source voltage of the external FET. For this
reason, select a FET with a low threshold voltage.
In addition, the voltage across the RSN resistor cannot exceed the
voltage at the cathode of the laser diode. Given a forward laser
diode voltage drop of 2 V in Figure 20, the voltage at the RSN pin
(I × RSN) cannot exceed 3 V. This sets an upper limit to the value
of code in Equation 5.
Although the configuration for anode-to-ground diodes is
similar, the supply voltages must be shifted down to 0 V and
−5 V, as shown in Figure 21. The AVDD, DVDD, and PVDD
pins are connected to ground with AVSS connected to −5 V.
Rev. C | Page 12 of 14
+3V
NDC7003P
OR EQUIV
TTL/CMOS
LEVEL
100kΩ
NDC7002N
OR EQUIV
TO: RESET
CS
SCLK
SDI
10kΩ
–5V
–5V
Figure 22. Level Shifting TTL/CMOS Logic
03195-0-021
4.096V
5V
5V
03195-0-022
DITHER
R1
1.62kΩ
03195-0-019
C
1µF
5V
Data Sheet
ADN8810
PCB LAYOUT RECOMMENDATIONS
ADN8810
POWER SUPPLY
3V
DVSS AVSS
DGND
ADN8810
LOAD
IOUT
03195-0-023
LOAD
GND
LOGIC GROUND
RETURN
PVDD
IOUT
TO LOAD
RSN
RSN
Y
Figure 24. Use Identical Trace Lengths for Sense Resistors
SUGGESTED PAD LAYOUT FOR CP-24 PACKAGE
GND
TO OTHER 5V
DIGITAL LOGIC
DVDD AVDD
X
RSN
Figure 25 shows the dimensions for the PCB pad layout for the
ADN8810. The package is a 4 mm × 4 mm, 24-lead LFCSP. The
metallic slug underneath the package must be soldered to a
copper pad connected to AVSS, the lowest supply voltage to the
ADN8810. For single-supply applications, this is ground. Use
multiple vias to this pad to improve the thermal dissipation of
the package.
0.027
(0.69)
Figure 23. Star Supply and Ground Technique
To improve thermal dissipation, solder the slug on the bottom
of the LFCSP package be soldered to the PCB with multiple
vias into a low noise ground plane. Connecting these vias to a
copper area on the bottom side of the board further improves
thermal dissipation.
Use identical trace width and lengths for the two output sense
resistors. These lengths are shown as X and Y in Figure 24.
Differences in trace lengths cause differences in parasitic series
resistance. Because the sense resistors can be as low as 1.37 Ω,
small parasitic differences can lower both the output current
accuracy and the output impedance. See the AN-619
Application Note for a sample layout for these traces.
0.004
(0.10)
0.172
(4.36)
0.011
(0.28)
0.109
(2.78)
0.020
(0.50)
PACKAGE
OUTLINE
DIMENSIONS ARE SHOWN
IN INCHES AND (MM).
0.106
(2.68)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
Figure 25. Suggested PCB Layout for the CP-24-10 Pad Landing
Rev. C | Page 13 of 14
03195-0-025
5V
FB
03195-0-024
Although they can be driven from the same power supply voltage,
keep DVDD and AVDD current paths separate on the printed
circuit board (PCB) to maintain the highest accuracy; likewise
for AVSS and DGND. Tie common potentials together at a
single point located near the power regulator. This technique
is known as star grounding and is shown in Figure 23. This
method reduces digital crosstalk into the laser diode or load.
ADN8810
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.20
1
0.50
BSC
2.20
2.10 SQ
2.00
EXPOSED
PAD
13
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
PKG-004714
SEATING
PLANE
0.50
0.40
0.30
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
6
12
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
7
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
02-21-2017-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 26. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADN8810ACPZ
ADN8810ACPZ-REEL7
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
©2004–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03195-0-11/17(C)
Rev. C | Page 14 of 14
Package Option
CP-24-10
CP-24-10
