Thermoelectric Cooler Controller
ADN8830
FEATURES
High Efficiency
Small Size: 5 mm ⴛ 5 mm LFCSP
Low Noise: 0.707
8
4
2
1.9
1.6
1.5
for ( fCLK > Z 1)
(30)
VDD R1
for ( fCLK > Z 1)
4 fCLK L1
(31)
Here it can be directly seen that increasing the inductor value or
clock frequency will reduce the ripple. Choosing a low ESR
capacitor will ensure R1 remains low. Operating from a lower
supply voltage will also help reduce the output ripple voltage
from the L-C filter. With a clock frequency equal to Z1 but
presumably greater than fC, the worst-case output voltage ripple is
(16R1 C1 f
2
ΔOUT AMAX = VDD
2
2
CLK
32L1C1 fCLK
) for ( f
+1
CLK
= Z 1) (32)
Which, if fCLK < Z1, can be further simplified to
Using the recommended values of L1 = 4.7 μH and C1 = 22 μF
results in a cutoff frequency of 15.7 kHz. With a TEC resistance
of 2 Ω, the damping factor is 0.12. The cutoff frequency can be
decreased to lower the output voltage ripple with slower clock
frequencies by increasing L1 or C1. Increasing C1 may appear
to be a simpler approach as it would not increase the physical
size of the inductor, but there is a potential stability danger in
lowering the damping factor too far. It is recommended that ζ
remain greater than 0.05 to provide a reasonable settling time
for the TEC. Increasing ζ also makes finding the proper PID
compensation easier as there is less ringing in the L-C output
filter. To allow adequate phase and gain margin for the PWM
amplifier, Table III should be used to find the lower limit of
cutoff frequency for a given damping factor.
L1 fCLK
The worst-case voltage ripple occurs when the duty cycle of the
PWM output is exactly 50%, or when OUT A = 0.5 VDD. As
shown in Equation 31
ΔOUT AMAX =
(27)
Table III. Minimum L-C Filter Cutoff
Frequency vs. Damping Factor
(29)
VDD D (1 – D) R1
OUT AMAX ≈
This cutoff frequency should be much lower than the clock
frequency to achieve adequate filtering of the switched output
waveform. Also of importance is the damping factor, , of the
L-C filter. Too low a damping factor will result in a longer
settling time and could potentially cause stability problems for
the temperature control loop. Neglecting R1 and R2 again, the
damping factor is simply
ζ=
(28)
With a clock frequency greater than Z1, and presumably greater
than fC, the output voltage ripple is
Practically speaking, R1 and R2 are several tens of milliohms and
are much smaller than the TEC resistance, which can be a few
ohms. The cutoff frequency can be roughly approximated as
1
fC =
2π
1
2πR1C1
VDD
32L1C1 fCLK
2
for ( fCLK < Z 1)
(33)
A typical 100 μF surface-mount electrolytic capacitor can have
an ESR of over 100 mΩ, pulling this zero to below 16 kHz, and
resulting in an excess of ripple voltage across the TEC. Low ESR
capacitors, such as ceramic or polymer aluminum capacitors,
are recommended instead. Polymer aluminum capacitors can
provide more bulk capacitance per unit area over ceramic ones,
saving board space. Table IV shows a limited list of capacitors
with their equivalent series resistances.
This is by no means a complete list of all capacitor manufacturers
or capacitor types that can be used in the application. The 22 μF
capacitor recommended has a maximum ESR of 35 mΩ, which
puts Z1 at 207 kHz. Using a 3.3 V supply with the recommended
inductor and capacitor listed with a 1 MHz clock frequency will
yield a worst-case ripple voltage at OUT A of about 6 mV.
External FET Requirements
External FETs are required for both the PWM and linear amplifiers
that drive OUT A and OUT B from the ADN8830. Although it
is important to select FETs that can supply the maximum current
required to the TEC, they should also have a low enough resistance (rDS, ON) to prevent excessive power dissipation and improve
efficiency. Other key requirements from these FET pairs are
slightly different for the PWM and linear outputs.
–15–
ADN8830
The gate drive outputs for the PWM amplifier at P1 (Pin 21)
and N1 (Pin 22) have a typical nonoverlap delay of 65 ns.
This is done to ensure that one FET is completely off before
the other FET is turned on, preventing current from shooting
through both simultaneously.
Bear in mind that the addition of these capacitors is only
for local stabilization. The stability of the entire TEC application may need adjustment, which should be done around the
compensation amplifier. This is covered in the Compensation
Loop section.
The input capacitance (CISS) of the FET should not exceed 5 nF.
The P1 and N1 outputs from the ADN8830 have a typical output
impedance of 6 Ω. This creates a time constant in combination
with CISS of the external FETs equal to 6 Ω CISS. To ensure
shoot-through does not occur through these FETs, this time
constant should remain less than 30 ns.
There is one additional consideration for selecting both the
linear output FETs; they must have a minimum threshold
voltage (VT) of 0.6 V. Lower threshold voltages could cause
shoot-through current in the linear output transistors.
Table V shows the recommended FETs that can be used for the
linear output in the ADN8830 application. Table V includes the
appropriate external gate-to-drain capacitance (external CGD)
and snubber capacitor value (CSNUB) connected from OUT B to
ground that should be added to ensure local stability. Table VI
shows the recommended PWM output FETs. Although other
transistors can be used, these combinations have been tested
and are proved stable and reliable for typical applications.
The linear output from the ADN8830 uses N2 (Pin 10) and
P2 (Pin 11) to drive the gates of the linear side FETs, shown as
Q3 and Q4 in Figure 1. Local compensation for the linear amplifier is achieved through the gate-to-drain capacitances (CGD) of
Q3 and Q4. The value of CGD, which can be determined from
the data sheet, is usually referred to as CRSS, the reverse transfer
capacitance. The exact CRSS value should be determined from a
graph that shows capacitance versus drain-to-source voltage,
using the power supply voltage as the appropriate VDS.
Data sheets for these devices can be found at their respective
websites:
To ensure stability of the linear amplifier, the total CGD of the
PMOS device, Q3, should be greater than 2.5 nF and the total
CGD of the NMOS should be greater than 150 pF. External
capacitance can be added around the FET to increase the effective
CGD of the transistor. This is the function of C6 in the typical
application schematic shown in Figure 1. If external capacitance
must be added, it will generally only be required around the
PMOS transistor.
In the event of zero output current through the TEC, there will
be no current flowing through Q3 and Q4. In this condition,
these FETs will not provide any small signal gain and thus no
negative feedback for the linear amplifier. This leaves only a
feedforward signal path through CGD, which could cause a
settling problem at OUT B. This is often seen as a small signal
oscillation at OUT B, but only when the TEC is at or very near
zero current.
The remedy for this potential minor instability is to add
capacitance from OUT B to ground. This may need to be determined empirically, but a good starting point is 1.5 times the
total CGD. This is the function of C12 in Figure 1. Note that
while adding more CGD around Q3 and Q4 will help to ensure
stability, it could potentially increase instability in the zero current
dead band region, requiring additional capacitance from
OUT B to ground.
Fairchild – www.fairchildsemi.com
Vishay Siliconix – www.vishay.com
International Rectifier – www.irf.com
Calculating Power Dissipation and Efficiency
The total efficiency of the ADN8830 application circuit is simply
the ratio of the output power to the TEC divided by the total
power delivered from the supply. The idea in minimizing power
dissipation is to avoid both drawing additional power and reducing heat generated from the circuit. The dominant sources
of power dissipation will include resistive losses, gate charge
loss, core loss from the inductor, and the current used by the
ADN8830 itself.
The on-channel resistance of both the linear and PWM output
FETs will affect efficiency primarily at high output currents.
Because the linear amplifier operates in a high gain configuration,
it will be at either ground or VDD when significant current is
flowing through the TEC. In this condition, the power dissipation
through the linear output FET will be
PFET , LIN = rDS , ON × ITEC
2
(34)
using either the rDS, ON for the NMOS or the PMOS depending
on the direction of the current flow. In the typical application
setup in Figure 2, if the TEC is cooling the target object, the
PMOS is sourcing the current. If the TEC is heating the
object, the NMOS will be sinking current.
Table IV. Partial List of Capacitors and Key Specifications
Value (F)
ESR (m⍀)
Voltage Rating (V)
Part Number
Manufacturer
Website
10
22*
22
22
47
68
100
60
35
35
35
25
18
95
6.3
8
8
8
6.3
8
10
NSP100M6.3D2TR
ESRD220M08B
NSP220M8D5TR
EEFFD0K220R
NSP470M6.3D2TR
ESRD680M08B
594D107X_010C2T
NIC Components
Cornell Dubilier
NIC Components
Panasonic
NIC Components
Cornell Dubilier
Vishay
www.niccomp.com
www.cornell-dubilier.com
www.niccomp.com
www.maco.panasonic.co.jp
www.niccomp.com
www.cornell-dubilier.com
www.vishay.com
*Recommend capacitor in typical application circuit Figure 1.
–16–
REV. D
ADN8830
Although the FETs that drive OUT A alternate between Q1 and
Q2 being on, they have an equivalent series resistance that is
equal to a weighted average of their rDS, ON values.
REQIV = D × rDS , P 1 + (1 – D ) × rDS , N 1
(35)
The resistive power loss from the PWM transistors is then
PFET , PWM = REQIV × ITEC
2
(36)
There is also a power loss from the continuing charging and
discharging of the gate capacitances on Q1 and Q2. The power
dissipated due to gate charge loss (PGCL) is
PGCL =
1
2
CISSVDD fCLK
2
PADN 8830 = VDD × 10 mA
(37)
(40)
There are certainly other minor mechanisms for power dissipation in the circuit. However, a rough estimate of the total power
dissipated can be found by summing the preceding power dissipation equations. Efficiency is then found by comparing the
power dissipated with the required output power to the load.
Efficiency =
PLOAD
PLOAD + PDISS , TOT
(41)
where
PLOAD = ILOAD ×VLOAD
using the appropriate input capacitance (CISS) for the NMOS
and PMOS. Both transistors are switching, so PGCL should be
calculated for each one and will be added to find the total power
dissipated from the circuit.
The series resistance of the inductor, R2 from Figure 14, will
also exhibit a power dissipation equal to
PR2 = R2 × ITEC
total current used by the ADN8830. The power dissipated from
the device itself is
2
The measured efficiency of the system will likely be less than the
calculated efficiency. Measuring the efficiency of the application
circuit is fairly simple but must be done in an exact manner to
ensure the correct numbers are being measured. Using two high
current, low impedance ammeters and two voltmeters, the circuit should be set up as shown in Figure 15.
(38)
POWER SUPPLY
Core loss from the inductor arises as a result of nonidealities of
the inductor. Although this is difficult to calculate explicitly, it
can be estimated as 80% of PRLS at 1 MHz switching frequencies and 50% of PRL at 100 kHz. Judging conservatively
PLOSS = 0.8 × PRL
VDD
GND
A
V
(39)
A
Finally, the power dissipated by the ADN8830 is equal to the
current used by the device multiplied by the supply voltage.
Again, this exact equation is difficult to determine as we have
already taken into account some of the current while finding the
gate charge loss. A reasonable estimate is to use 40 mA as the
ADN8830
V
TEC
LOAD
Figure 15. Measuring Efficiency of the ADN8830 Circuit
Table V. Recommended FETs for Linear Output Amplifier
Part Number
Type
CGD (nF)
FDW2520C*
NMOS
PMOS
NMOS
PMOS
NMOS
PMOS
0.17
0.15
0.5
2.2
0.23
0.6
IRF7401
IRF7233
FDR6674A
FDR840P
Ext. CGD (nF)
CSNUB (nF)
2.2
3.3
1.0
3.3
1.0
3.3
rDS, ON (m⍀)
IMAX (A)
Manufacturer
18
35
22
20
9.5
12
6.0
4.5
8.7
9.5
11.5
10
Fairchild
Fairchild
International Rectifier
International Rectifier
Fairchild
Fairchild
*Recommend transistors in typical application circuit Figure 1.
Table VI. Recommended FETs for PWM Output Amplifier
Part Number
Type
CISS (nF)
rDS,ON (m⍀)
Continuous IMAX (A)
Manufacturer
FDW2520C*
NMOS
PMOS
NMOS
PMOS
NMOS
PMOS
1.33
1.33
1.0
3.5
1.6
1.5
18
35
30
17
22
40
6.0
4.5
5.3
7.3
8.7
6.7
Fairchild
Fairchild
Vishay Siliconix
Vishay Siliconix
International Rectifier
International Rectifier
Si7904DN
Si7401DN
IRF7401
IRF7404
*Recommend transistors in typical application circuit Figure 1.
REV. D
–17–
ADN8830
The voltmeter to the TEC or output load should include the series
ammeter since the power delivered to the ammeter is considered part
of the total output power. However, the voltmeter measuring the
voltage delivered to the ADN8830 circuit should not include the
series ammeter from the power supply. This prevents a false supply
voltage power measurement since we are interested only in the
supply voltage power delivered to the ADN8830 circuit. Figures 16
and 17 show some efficiency measurements using the typical application circuit shown in Figure 1.
POWER SUPPLY
VDD
AVDD
NOISE
SENSITIVE
SECTION
VSY = 3V
EFFICIENCY (%)
OUTPUT
SECTION
PVDD
TEC
OR
LOAD
The low noise power and ground are referred to as AVDD and
AGND, with the output supply and ground paths labeled PVDD
and PGND. These pins are labeled on the ADN8830 and should
be connected appropriately. Both sets of external FETs should be
connected to PVDD and PGND. All output filtering and PVDD
supply bypass capacitors should be connected to PGND.
80
VSY = 5V
60
40
20
0
500
PGND
Figure 18. Using Star Connections to Minimize
Noise Pickup from Switched Output
100
0
AGND
GND
1,000
ITEC (mA)
1,500
2,000
Figure 16. Efficiency with fCLK = 1 MHz
All remaining connections to ground and power supply should be
done through AVDD and AGND. A 4-layer board layout is recommended for best performance with split power and ground
planes between the top and bottom layers. This provides the
lowest impedance for both supply and ground points. Setting the
ADN8830 above the AGND plane will reduce the potential noise
injection into the device. Figure 19 shows the top layer of the
layout used for the ADN8830 evaluation boards, highlighting the
power and ground split planes.
100
VSY = 3V
80
EFFICIENCY (%)
VSY = 5V
60
40
20
0
0
500
1,000
ITEC (mA)
1,500
2,000
Figure 17. Efficiency with fCLK = 200 kHz
Note that higher efficiency can be achieved using a lower supply
voltage or a slower clock frequency. This is due to the fact that the
dominant source of power dissipation at high clock frequencies is the
gate charge loss on the PWM transistors.
Layout Considerations
The two key considerations for laying out the board for the
ADN8830 are to minimize both the series resistance in the output
and the potential noise pickup in the precision input section. The
best way to accomplish both of these objectives is to divide the
layout into two sections, one for the output components and the
other for the remainder of the circuit. These sections should have
independent power supply and ground current paths that are each
connected together at a single point near the power supply. This is
used to minimize power supply and ground voltage bounce on the
more sensitive input stages to the ADN8830 caused by the switching of the PWM output. Such a layout technique is referred to as a
“star” ground and supply connection. Figure 18 shows a block diagram of the concept.
Figure 19. Top Layer Reference Layout for ADN8830
Proper supply voltage bypassing should also be taken into consideration to minimize the ripple voltage on the power supply. A
minimum bypass capacitance of 10 μF should be placed in close
proximity to each component connected to the power supply. This
includes Pins 8 and 20 on the ADN8830 and both external PMOS
transistors. An additional 0.1 μF capacitor should be placed in
parallel to each 10 μF capacitor to provide bypass for high frequency noise. Using a large bulk capacitor, 100 μF or greater, in
parallel with a low ESR capacitor where AVDD and PVDD connect will further improve voltage supply ripple. This is covered in
more detail in the Power Supply Ripple section.
–18–
REV. D
ADN8830
Power Supply Ripple
Minimizing ripple on the power supply voltage can be an important consideration, particularly in signal source laser applications.
If the laser diode is operated from the same supply rail as the TEC
controller, ripple on the supply voltage could cause inadvertent
modulation of the laser frequency. As most laser diodes are driven
from a 5 V supply, it is recommended the ADN8830 be operated
from a separate 3.3 V regulated supply unless higher TEC voltages
are required. Operation from 3.3 V also improves efficiency, thus
minimizing power dissipation.
The power supply ripple is primarily a function of the supply bypass capacitance, also called bulk capacitance, and the inductor
ripple current. Similar to the L-C filter at the PWM amplifier
output, using more capacitance with low equivalent series resistance (ESR) will lower the supply ripple. A larger inductor value
will reduce the inductor ripple current, but this may not be
practical in the application. A recommended approach is to use a
standard electrolytic capacitor in parallel with a low ESR capacitor.
A surface-mount 220 μF electrolytic in parallel with a 22 μF polymer aluminum low ESR capacitor can occupy an approximate total
board area of only 0.94 square inches or 61 square millimeters.
Using these capacitors along with a 4.7 μH inductor can yield a
supply ripple of less than 5 mV.
High frequency transient spikes may appear on the supply voltage
as well. This is due to the fast switching times on the PWM transistors and the sharp edges of their gate voltages. Although these
transient spikes can reach several tens of millivolts at their peak,
they typically last for less than 20 ns and have a resonance greater
than 100 MHz. Additional bulk capacitance will not appreciably
affect the level of these spikes as such capacitance is not reactive at
these frequencies. Adding 0.01 μF ceramic capacitors on the supply line near the PWM PMOS transistor can reduce this switching
noise. Inserting an RF inductor with a High-Q around 100 MHz in
series with PVDD will also block this noise from traveling back to
the power supply.
Setting Maximum Output Current and Short-Circuit
Protection
Although the maximum output voltage can be programmed
through VLIM to protect the TEC from overvoltage damage,
the user may wish to protect the ADN8830 circuit from a possible
short circuit at the output. Such a short could quickly damage the
external FETs or even the power supply since they would attempt
to drive excessive current. Figure 20 shows a simple modification
that will protect the system from an output short circuit.
VS
TO
FETS
AND
DECOUPLING
CAPS
RS
10m⍀
PVDD
AVDD
A 10 mΩ resistor placed in series with the PVDD supply line creates a
voltage drop proportional to the absolute value of the output current.
The AD8601 is a CMOS amplifier that is configured as a comparator. As long as the voltage at its inverting input (VS) exceeds
the voltage set by the resistor divider at the noninverting input (VX),
the gate of Q1 will remain at ground. This leaves Q1 on, effectively
connecting D1 to the positive rail and leaving the voltage on C1 at
VDD. Should enough current flow through RS to drop VS below VX,
Q1 will turn off and C1 will discharge through R2 down to a logic
low to activate the ADN8830 shutdown. Once VS returns to a
voltage greater than VX, Q1 will turn back on and C1 will charge
back to VDD through R1. The shutdown and reactivation time
constants are approximately
SD = C1 × R1
ON = C1 × R1
(42)
The shutdown time constant should be a minimum of 10 clock
cycles to ensure high current switching transients do not trigger a
false activation. If powered from 5 V, the circuit shown will shut
down the ADN8830 should PVDD deliver over 5 A for more than
1 ms. After shutdown, the circuit will reactivate the ADN8830 in
about 1 second.
The voltage drop across RS is found as
2
VRS =
IOUT RL RS
ηVDD
(43)
where RL is the load resistance or resistance of the TEC and is
the efficiency of the system. An estimate of efficiency can be calculated
either from the Calculating Power Dissipation and Efficiency section
or from Figures 16 and 17. A reasonable approximation is =
0.85. Although the exact resistance of a TEC varies with temperature, an estimation can be made by dividing the maximum voltage
rating of the TEC by its maximum current rating.
In addition to providing protection against a short at the output,
this circuit will also protect the FETs against shoot-through current.
Shoot-through will not occur when using the recommended
transistors and additional capacitance shown in Tables V and VI.
However, if different transistors are used where their shootthrough potential is unknown, implementing the short-circuit
protection circuit will unconditionally protect these transistors.
To set a maximum output current limit, use the circuit in Figure
21. This circuit can share the 10 mΩ power supply shunt resistor
as the short-circuit protection circuit to sense the output current.
In normal operation Q1 is on, pulling the ADN8830 VLIM pin
down to the voltage set by VLIMIT. This sets the maximum output voltage limit as described in the Setting the Maximum TEC
Voltage and Current section.
PVDD
R3
1k⍀
Q1
FDV304P
OR EQUIVALENT
AD8601
R4
100k⍀
VX
R1
1M⍀
SD
R2
1k⍀
D1
MA116CT-ND
OR
EQUIVALENT
C1
1F
VSY
TO
FETS
AND
DECOUPLING PVDD
CAPS
R3
178⍀
PVDD
AVDD
R1
3.48k⍀
AD8605
R4
100k⍀
DENOTES
AGND
RS
10m⍀
Q1
FDV301N
OR
EQUIVALENT
C1
1nF
TO
VLIM
R2
1.47k⍀
VX
DENOTES
PGND
VLIMIT
(0V TO 1.5V)
Figure 20. Implementing Output Short-Circuit Protection
DENOTES
AGND
DENOTES
PGND
Figure 21. Setting a Maximum Output Current Limit
REV. D
–19–
ADN8830
5V
IOUTA
ADT70
IOUTB
+INOA
TO THERM_IN
= 1V @ 25ⴗC
R3
82.5⍀
OUTOA
25mV/ⴗC
+INIA
RGA
INST
AMP
4.99k⍀
R3
82.5⍀
RGB
–INIA
RTD
1k⍀
R3
1k⍀
GND
SENSE
AGND
OUTIA
–INOA
1k⍀
5.11k⍀
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Using an RTD for Temperature Feedback to the ADN8830
If the voltage at VSY drops below VX, Q1 is turned off and the
VLIM pin will be set to 1.5 V, effectively setting the maximum
voltage across the outputs to 0 V. The voltage divider for VX is
calculated from Equation 43.
TO
TEC
AVDD
RS
10m⍀
TO
OUT B
IL
AVDD
AVDD
R1
3.48k⍀
200k⍀
VHI
TO
VLIM
R2
1.47k⍀
1nF 300k⍀
Design Example 5
A maximum output current limit needs to be set at 1.5 A for a
TEC with a maximum voltage rating of 2.5 V. The ADN8830 is
powered from 5 V. The TEC resistance is estimated at 1.67 Ω and
efficiency at 85%. Using Equation 43, the voltage drop across
RS will be 8.8 mV when 1.5 A is delivered to the TEC. The trip
voltage VX is set to 4.991 V with R3 = 178 Ω and R4 = 100 kΩ
as shown in Figure 21. To set the output voltage limit to 2.5 V,
the voltage at VLIMIT should be set to 0.875 V according to
Equation 17.
8
AD626
VX
AD8602
Q1,Q2
FDG6303N
OR
EQUIVALENT
300k⍀
TO
VREF
VLO 200k⍀
VLIMIT
(0V TO 1.5V)
Figure 23. High Accuracy Output Current Limit
The C1 capacitor is added to smooth the voltage transitions at
VLIM. Once an overcurrent condition is detected, the output
voltage will turn down to 0 V within 30 ms.
For a more exact measurement of the output current, place a
sense resistor in series with the output load, as shown in Figure 23.
The AD626 instrumentation amplifier is set for a gain of 100
with a reference voltage of 2.47 V from VREF. The output of
the AD626 is equal to 100 × RS × IL and is fed to the AD8602,
which is set up as a window comparator. With VX greater than
VLO but less than VHI, VLIM will be pulled down to the voltage at VLIMIT. Should VX fall outside the voltage window,
VLIM will be pulled to 1.5 V as in Figure 21. The trip points
should be set according to
VHI = VREF + 100 × RS I LIMIT +
VLO = VREF – 100 × RS I LIMIT –
AVDD
The upper and lower trip point voltages can be set independently,
allowing different maximum output current limits depending on
the direction of the current. The resistor divider for VHI and
VLO is tapped to VREF to maintain window accuracy with any
changes in VREF. Using the values from Figure 23 with a 5 V
supply, the output current will not exceed 1.5 A in either direction.
Adding the current sensing resistor will slightly reduce efficiency.
The power dissipated by this resistor is D × ITEC2 × RS if the
TEC is heating, or (1–D) × ITEC2 × RS if the TEC is cooling.
Include this when calculating efficiency as described in the
Calculating Power Dissipation and Efficiency section.
(44)
–20–
REV. D
ADN8830
PVDD
Using an RTD for Temperature Sensing
The ADN8830 can be used with a resistive temperature device
(RTD) as the temperature feedback sensor. The resistance of an
RTD is linear with respect to temperature, offering an advantage over thermistors that have an exponential relationship to
temperature. A constant current applied through an RTD will
yield a voltage proportional to temperature. However, this voltage could be on the order of only 0.5 mV/°C, thus requiring the
use of additional amplification to achieve a usable signal level.
The ADT70 from Analog Devices can be used to bias and amplify
the voltage across an RTD, which can then be fed directly to the
THERMIN pin on the ADN8830 to provide temperature
feedback for the TEC controller. The ADT70 uses a 0.9 mA
current source to drive the RTD and an instrumentation amplifier with adjustable gain to boost the RTD voltage. Application
notes and typical schematics for this device can be found in the
ADT70 Data Sheet.
Most RTDs have a positive temperature coefficient, also called
tempco, as opposed to thermistors, which have a negative tempco.
For the OUT A output to drive the TEC– input as shown in
Figure 1, the signal from an RTD must be conditioned to create
a negative tempco. This can be easily done using an inverting
amplifier. Alternately, OUT A can be connected to drive TEC+
with OUT B driving TEC– with a positive tempco at THERMIN.
This is highlighted in the Output Driver Amplifiers section.
For the ADN8830, proper operation care should be taken
to ensure the voltage at THERMIN remains within 0.4 V
and 2.0 V. Using a 1 kΩ RTD with the ADT70 will yield a
THERMIN voltage of 0.9 V at 25°C. Using the application
circuit shown in Figure 22 will provide a nominal output
voltage of 1.0 V at 25°C and a total gain of 66.7 mV/Ω.
Using an RTD with a temperature coefficient of 0.375 Ω/°C
will give a THERMIN voltage swing from 1.5 V at 5°C to
0.5 V at 45°C, well within the input range of the ADN8830.
OUT A
Q1
P1
L1
RL
OUT B
Q2
N1
C1
Q3
N2
NO CONNECTION TO P2 REQUIRED
Figure 24. Using the ADN8830 to Drive a Heating Element
Current is delivered from the PWM amplifier through Q3 when
the voltage at THERMIN is lower than TEMPSET. If the object
temperature is greater than the target temperature, Q3 will turn
off and the current through the load goes to zero, allowing the
object to cool back toward the ambient temperature. As the
target temperature is approached, a steady output current should
be reached. Naturally, a proper compensation network must be
found to ensure stability and adequate temperature settling time.
The P2 output from the ADN8830 should be left unconnected.
Suggested Pad Layout for CP-32 Package
Figure 25 shows the dimensions for the PC board pad layout for
the ADN8830, which is a 5 5, 32-lead lead frame chipscale
package. This package has a metallic heat slug that should be
soldered to a copper pad on the PC board. Although the package slug is electrically connected to the substrate of the IC, the
copper pad should be left electrically floating. This prevents
potential noise injection into the substrate while maintaining
good thermal conduction to the PC board.
0.69
(0.0272)
0.10
(0.0039)
Using a Resistive Load as a Heating Element
The ADN8830 can be used in applications that do not necessarily drive a TEC but require only a high current output into a
load resistance. Such applications generally only require heating
above ambient temperature and simply use the power dissipated
by the load element to accomplish this. Because the power
dissipated by such an element is proportional to the square of
the output voltage, the ADN8830 application circuit must be
modified. Figure 24 shows the preferred method for driving a
heating element load.
5.36
(0.2110)
0.28
(0.0110)
3.78
(0.1488)
0.50
(0.0197)
3.68
(0.1449)
PACKAGE
OUTLINE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
THERMAL PAD SHOULD BE SOLDERED TO AN ELECTRICALLY FLOATING
PAD ON THE PC BOARD
Figure 25. Suggested PC Board Layout for CP-32
Pad Landing
REV. D
–21–
ADN8830
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
0.50
BSC
1
24
TOP VIEW
0.80
0.75
0.70
8
16
9
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
0.50
0.40
0.30
PIN 1
INDICATOR
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
112408-A
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 26. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADN8830ACPZ
ADN8830ACPZ-REEL
ADN8830ACPZ-REEL7
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Package Option
CP-32-7
CP-32-7
CP-32-7
Z = RoHS Compliant Part.
REVISION HISTORY
3/12—Rev. C to Rev. D
8/03—Rev. A to Rev. B
Added EPAD Notation ..................................................................... 3
Updated Outline Dimensions ........................................................22
Changes to Ordering Guide ...........................................................22
Updated Ordering Guide ................................................................. 3
Updated Thermal Setup Section ..................................................... 8
Updated Outline Dimensions........................................................ 23
11/03—Rev. B to Rev. C
2/03—Rev. 0 to Rev. A
Changes to Ordering Guide ............................................................. 3
Deleted Figure 24 ............................................................................21
Deleted Boosting the Output Voltage section .............................22
Deleted Figure 26 ............................................................................22
Deleted Equations 45, 46 and 47 ...................................................22
Updated Outline Dimensions ........................................................23
Renumbered Figures .......................................................... Universal
Changes to Thermistor Setup Section ............................................ 8
Changes to Figure 14 ...................................................................... 15
Changes to Figure 23 ...................................................................... 20
Changes to Figure 25 ...................................................................... 21
Updated Outline Dimensions........................................................ 23
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02793-0-3/12(B)
–22–
REV. D