Thermoelectric Cooler (TEC) Controller
ADN8831
Data Sheet
FEATURES
GENERAL DESCRIPTION
Two integrated zero drift, rail-to-rail, chop amplifiers
TEC voltage and current operation monitoring
Programmable TEC maximum voltage and current
Programmable TEC current heating and cooling limits
Configurable PWM switching frequency up to 1 MHz
Power efficiency: > 90%
Temperature lock indication
Optional internal or external clock source
Clock phase adjustment for multiple drop operation
Supports negative temperature coefficient (NTC) thermistors
or positive temperature coefficient (PTC) resistance
thermal detectors (RTDs)
5 V typical and optional 3 V supplies
Standby and shutdown mode availability
Adjustable soft start feature
5 mm × 5 mm 32-lead LFCSP
The ADN88311 is a monolithic TEC controller. It has two integrated, zero drift, rail-to-rail comparators, and a PWM driver.
A unique PWM driver works with an analog driver to control
external selected MOSFETs in an H-bridge. By sensing the
thermal detector feedback from the TEC, the ADN8831 can
drive a TEC to settle the programmable temperature of a laser
diode or a passive component attached to the TEC module.
The ADN8831 supports NTC thermistors or positive temperature coefficient (PTC) RTDs. The target temperature is set as an
analog voltage input either from a DAC or from an external
resistor divider driven by a reference voltage source.
A proportional integral differential (PID) compensation
network helps to quickly and accurately stabilize the ADN8831
thermal control loop. An adjustable PID compensation network
example is described in the AN-695 Application Note, Using the
ADN8831 TEC Controller Evaluation Board. A typical reference
voltage of 2.5 V is available from the ADN8831 for thermistor
temperature sensing or for TEC voltage/current measuring and
limiting in both cooling and heating modes.
APPLICATIONS
Thermoelectric cooler (TEC) temperature control
DWDM optical transceiver modules
Optical fiber amplifiers
Optical networking systems
Instruments requiring TEC temperature control
FUNCTIONAL BLOCK DIAGRAM
ILIMC ILIMH
ITEC
VLIM
VTEC
CS
LFB
LIMITER/MONITOR
IN1P
LINEAR
MOSFET
DRIVER
AMPLIFIER
Chop1
IN1N
LPGATE
LNGATE
SFB
OUT1
CONTROL
IN2P
SPGATE
PWM
MOSFET
DRIVER
AMPLIFIER
Chop2
SNGATE
COMPSW
SW
IN2N
TMPGD VREF
SS/SB
COMPOSC
OSCILLATOR
SYNCO
SYNCI/SD PHASE FREQ
04663-001
SOFT START
SHUTDOWN
REF
OUT2
Figure 1.
1
Product is covered by U.S. Patent No. 6,486,643.
Rev. C
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ADN8831
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Temperature Lock Indicator ..................................................... 13
Applications ....................................................................................... 1
Soft Start on Power-Up .............................................................. 13
General Description ......................................................................... 1
Shutdown Mode ......................................................................... 13
Functional Block Diagram .............................................................. 1
Standby Mode ............................................................................. 13
Revision History ............................................................................... 2
TEC Voltage/Current Monitor ................................................. 13
Detailed Block Diagram .................................................................. 3
Maximum TEC Voltage Limit .................................................. 13
Specifications..................................................................................... 4
Maximum TEC Current Limit ................................................. 14
Electrical Characteristics ............................................................. 4
Applications Information .............................................................. 15
Absolute Maximum Ratings............................................................ 6
Signal Flow .................................................................................. 15
Thermal Characteristics .............................................................. 6
Thermistor Setup........................................................................ 15
ESD Caution .................................................................................. 6
Thermistor Amplifier (Chop1) ................................................ 15
Pin Configuration and Function Descriptions ............................. 7
PID Compensation Amplifier (Chop2) .................................. 16
Typical Performance Characteristics ............................................. 9
MOSFET Driver Amplifier ....................................................... 17
Theory of Operation ...................................................................... 11
Outline Dimensions ....................................................................... 18
Oscillator Clock Frequency ....................................................... 12
Ordering Guide .......................................................................... 18
Oscillator Clock Phase ............................................................... 12
REVISION HISTORY
9/2019—Rev. B to Rev. C
Changes to Figure 3 .......................................................................... 7
Changes to Table 4 ............................................................................ 8
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
9/2018—Rev. A to Rev. B
Added Patent Information .............................................................. 1
8/2012—Rev. 0 to Rev. A
Changes to Features and General Description Sections.............. 1
Moved Figure 2 ................................................................................. 3
Changes to Figure 2 .......................................................................... 3
Changes to Table 1 ............................................................................ 4
Changes to Table 2 and Table 3 ....................................................... 6
Changes to Figure 3 and Table 4 ......................................................7
Changes to Theory of Operation Section and Figure 12 .......... 11
Changes to Figure 14 and Figure 15............................................. 11
Changes to Oscillator Clock Frequency Section and Oscillator
Clock Phase Section ....................................................................... 12
Changes to Soft Start on Power-Up Section, Shutdown Mode
Section, Standby Mode Section, and TEC Voltage/Current
Monitor Section .............................................................................. 13
Changes to Figure 17...................................................................... 15
Changes to PID Compensation Amplifier (Chop2) Section .... 16
Changes to MOSFET Driver Amplifier Section and Figure 21... 17
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
9/2005—Revision 0: Initial Version
Rev. C | Page 2 of 18
Data Sheet
ADN8831
DETAILED BLOCK DIAGRAM
VTEC
ITEC
CS
30
29
28
31
32
ADN8831
ILIMC
VC
1.25V
5kΩ
1.25V
20kΩ
20kΩ
VOLTAGE
LIMIT
IN1P 2
Chop1
1.25V
20kΩ
OUT1 4
Chop2
10kΩ
25kΩ
VB
20kΩ
100kΩ
gm1
VC
20kΩ
100kΩ
ILIMH
20kΩ
OUT2 7
LINEAR AMPLIFIER
1kΩ
LFB
20kΩ
IN2N 6
LFB
gm2
VB
ILIMC
VB
= 2.5V, VDD > 4.0V
25
80kΩ
VB
1kΩ
SFB
20kΩ
IN1N 3
26
27
2kΩ
25kΩ
5kΩ
1
IN2P 5
LFB LNGATE LPGATE
DRIVER
ILIMH VLIM
24
COMPSW
23
SFB
22
PGND
21
SNGATE
20
SW
19
SPGATE
18
PVDD
17
COMPOSC
gm3
VB
ITEC
= 1.5V, VDD < 4.0V
SOFT START
2.5V
SD
REFERENCE
250mV
1.25V
OSCILLATOR
SB
TEMPERATURE
GOOD
9
10
11
12
13
AVDD
PHASE
TMPGD
AGND
FREQ
Figure 2. Detailed Block Diagram
Rev. C | Page 3 of 18
14
15
SS/SB SYNCO
SD
DETECT
16
SYNCI/SD
04663-003
VREF 8
ADN8831
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 3.0 V to 5.0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter1
PWM OUTPUT DRIVER
Output Transition Time
Nonoverlapping Clock Delay
Output Resistance
Output Voltage Swing2
LINEAR OUTPUT AMPLIFIER
Output Resistance
Output Voltage Swing2
POWER SUPPLY
Power Supply Voltage
Supply Current
Shutdown Current
Soft Start Charging Current
Undervoltage Lockout3
Standby Current
Standby Threshold
ERROR/COMPENSATION AMPLIFIERS
Input Offset Voltage
Input Voltage Range
Common-Mode Rejection Ratio
Output Voltage High
Output Voltage Low
Power Supply Rejection Ratio
Output Current
Gain Bandwidth Product
OSCILLATOR
Sync Range
Symbol
Test Conditions/Comments
tR, tF
CL = 3300 pF
RO (SNGATE, SPGATE)
SFB
IL = 10 mA, VDD = 3.0 V
VLIM = VREF
RO, LNGATE
RO, LPGATE
LFB
IOUT = 2 mA, VDD = 3.0 V
IOUT = 2 mA, VDD = 3.0 V
VDD
ISY
ISD
ISS
UVLO
ISB
VSB
VOS1
VOS2
VCM1, VCM2
CMRR1, CMRR2
VOH1, VOH2
VOL1, VOL2
PSRR1, PSRR2
IOUT1, IOUT2
GBW1, GBW2
fCLK
Typ
40
20
80
6
0
Max
Unit
VDD
ns
ns
Ω
V
VDD
Ω
Ω
V
200
100
0
PWM not switching
−40°C ≤ TA ≤ +85°C
SYNCI/SD = 0 V
VSS = 0 V
Low to high threshold
SYNCI/SD = VDD, SS/SB = 0 V
SYNCI/SD = VDD
3.0
8
5.5
12
15
8
8
2.2
2
150
2.6
VCM1 = 1.5 V, VIN1P − VIN1M
VCM2 = 1.5 V, VIN2P − VIN2M
10
10
0
VCM1, VCM2 = 0.2 V to VDD − 0.2 V
200
100
100
VDD
120
VDD − 0.03
25
3.0 V ≤ VDD ≤ 5.0 V
Sourcing and sinking
VOUT = 0.5 V to (VDD − 1 V)
Oscillator Frequency
fCLK
Nominal Free-Run Oscillation
Frequency
Phase Adjustment Range2
fCLK-NOMINAL
SYNCI/SD connected to external
clock
COMPOSC = VDD, RFREQ = 118 kΩ,
SYNCI/SD = VDD, VDD = 5.0 V
COMPOSC = VDD, SYNCI/SD = VDD
ΦCLK
VPHASE = 0.13 V, fSYNCI/SD = 1 MHz
VPHASE = 2.3 V, fSYNCI/SD = 1 MHz
Phase Adjustment Default
REFERENCE VOLTAGE
Reference Voltage
Min
ΦCLK
PHASE = open
VREF
IREF = 2 mA
IREF = 0 mA
Rev. C | Page 4 of 18
110
5
2
300
800
1000
200
μV
μV
V
dB
V
mV
dB
mA
MHz
1000
kHz
1250
kHz
1000
kHz
50
Degrees
330
Degrees
180
2.37
V
mA
mA
μA
μA
V
mA
mV
2.35
2.47
Degrees
2.57
V
V
Data Sheet
Parameter1
LOGIC Controls
Logic Low Output Voltage
Logic High Output Voltage
Logic Low Input Voltage
Logic High Input Voltage
Output High Impedance
Output Low Impedance
Output High Impedance
Output Low Impedance
TEC CURRENT MEASUREMENT
ITEC Gain
ITEC Output Range High
ITEC Output Range Low
ITEC Input Range2
ITEC Bias Voltage
Maximum ITEC Driving Current
TEC VOLTAGE MEASUREMENT
VTEC Gain
VTEC Output Range2
VTEC Bias Voltage2
VTEC Output Load Resistance
VOLTAGE LIMIT
VLIM Gain
VLIM Input Range2
VLIM Input Current, Cooling
VLIM Input Current, Heating
VLIM Input Current Accuracy, Heating
CURRENT LIMIT
ILIMC Input Voltage Range
ILIMH Input Voltage Range
ILIMC Limit Threshold
ILIMH Limit Threshold
TEMPERATURE GOOD
High Threshold
Low Threshold
1
2
3
ADN8831
Symbol
Test Conditions/Comments
Min
VOL
VOH
VIL
VIH
TMPGD, SYNCO, IOUT = 0 A
TMPGD, SYNCO, IOUT = 0 A
VDD − 0.2
Max
Unit
0.2
V
V
V
V
Ω
Ω
Ω
Ω
0.2
3
VDD = 5.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 3.0 V
AV, ITEC
VITEC, HIGH
VITEC, LOW
VCS, VLFB
VITEC, B
IOUT, TEC
Typ
(VITEC – VREF/2) / (VLFB − VCS)
No load
VLFB = VCS = 0
AV, VTEC
VVTEC
VVTEC, B
RVTEC
(VVTEC – VREF/2)/(VLFB − VSFB)
VDD = 5.0 V
VLFB = VSFB = 0 V
IVTEC = 300 μA
AV, LIM
VVLIM
IVLIM, COOL
IVLIM, HEAT
IVLIM, HEAT
(VLFB − VSFB)/VVLIM
35
20
50
25
25
VDD − 0.05
0
1.10
0.23
0.05
1.20
1.20
±1.5
0.25
1.25
35
0.05
VDD
1.30
0.28
2.5
1.35
5
V/V
V
V
V
V
mA
V/V
V
V
Ω
IFREQ
1.0
1.18
V/V
V
nA
mA
A/A
VITEC = 2.0 V, RS = 20 mΩ
VITEC = 0.5 V
VREF/2
0.1
1.98
0.48
2.0
0.5
VDD − 1
VREF/2
2.02
0.52
V
V
V
V
IN2M tied to OUT2, VIN2P = 1.5 V
IN2M tied to OUT2, VIN2P = 1.5 V
1.55
1.45
1.60
1.40
V
V
0
VOUT2 < VREF/2
VOUT2 > VREF/2
IVLIM/IFREQ
0.8
VILIMC
VILIMH
VTH, ILIMC
VTH, ILIMH
VOUT1, TH1
VOUT1, TH2
Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 μA).
Guaranteed by design or indirect test methods.
The ADN8831 does not work when the supply voltage is less than UVLO.
Rev. C | Page 5 of 18
VDD
100
ADN8831
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings at 25°C, unless otherwise noted.
Table 2.
Parameter
Supply Voltage
Input Voltage
Storage Temperature Range
Junction Temperature
Lead Temperature (Soldering, 60 sec)
Rating
6V
GND to VS + 0.3 V
−65°C to +150°C
125°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond the
maximum operating conditions for extended periods may affect
product reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
32-lead LFCSP (ACPZ)
ESD CAUTION
Rev. C | Page 6 of 18
θJA
33.4
θJC
1.02
Unit
°C/W
Data Sheet
ADN8831
32
31
30
29
28
27
26
25
ILIMH
VLIM
VTEC
ITEC
CS
LFB
LNGATE
LPGATE
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADN8831
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
COMPSW
SFB
PGND
SNGATE
SW
SPGATE
PVDD
COMPOSC
NOTES
1. EXPOSED PAD. THE LFCSP HAS AN EXPOSED PAD
THAT MUST BE CONNECTED TO AGND (PIN 12) AND
THE ASSOCIATED PRINTED CIRCUIT BOARD
(PCB) GROUND PLANE.
04663-002
AVDD
PHASE
TMPGD
AGND
FREQ
SS/SB
SYNCO
SYNCI/SD
9
10
11
12
13
14
15
16
ILIMC
IN1P
IN1N
OUT1
IN2P
IN2N
OUT2
VREF
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
ILIMC
IN1P
IN1N
OUT1
IN2P
IN2N
OUT2
VREF
AVDD
PHASE
TMPGD
AGND
FREQ
SS/SB
Type
Analog Input
Analog Input
Analog Input
Analog Output
Analog Input
Analog Input
Analog Output
Analog Output
Power
Analog Input
Digital Output
Ground
Analog Input
Analog Input
15
SYNCO
Digital Output
16
SYNCI/SD
Digital Input
17
COMPOSC
Analog Output
18
19
20
21
22
23
24
25
26
27
28
29
30
PVDD
SPGATE
SW
SNGATE
PGND
SFB
COMPSW
LPGATE
LNGATE
LFB
CS
ITEC
VTEC
Power
Analog Output
Analog Input
Analog Output
Ground
Analog Input
Analog Input
Analog Output
Analog Output
Analog Input
Analog Input
Analog Output
Analog Output
Description
Sets TEC Cooling Current Limit.
Noninverting Input to Error Amplifier.
Inverting Input to Error Amplifier.
Output of Error Amplifier.
Noninverting Input to Compensation Amplifier.
Inverting Input to Compensation Amplifier.
Output of Compensation Amplifier.
2.5 V Voltage Reference Output.
Power for Nondriver Sections. 3.0 V minimum; 5.5 V maximum.
Sets SYNCO Clock Phase Relative to SYNCI/SD Clock.
Logic Output. Active high. Indicates when the OUT1 voltage is within ±100 mV of IN2P voltage.
Analog Ground. Connect to low noise ground.
Sets Switching Frequency with an External Resistor.
Sets Soft Start Time for Output Voltage. Pull low (VTEC = 0 V) to put the ADN8831 into standby
mode.
Phase Adjustment Clock Output. Phase set from PHASE pin. Used to drive SYNCI/SD of other
ADN8831 devices.
Optional Clock Input. If not connected, clock frequency is set by FREQ pin. Pull low to put
the ADN8831 into shutdown mode. Pull high to negate shutdown mode.
Compensation for Oscillator. Connect to PVDD when in free-run mode, connect to R-C
network when in external clock mode.
Power for Output Driver Sections. 3.0 V minimum; 5.5 V maximum.
PWM Output Drives External PMOS Gate.
Connects to PWM FET Drains.
PWM Output Drives External NMOS Gate.
Power Ground. External NMOS devices connect to PGND. Connect to digital ground.
PWM Feedback. Connect to the TEC module negative (−) terminal.
Compensation Pin for Switching Amplifier.
Linear Output Drives External PMOS Gate.
Linear Output Drives External NMOS Gate.
Linear Feedback. Connect to H-Bridge transistor output and current sense resistor.
Linear Feedback. Connect to the TEC module positive (+) terminal.
Indicates TEC Current.
Indicates TEC Voltage.
Rev. C | Page 7 of 18
ADN8831
Pin No.
31
32
Mnemonic
VLIM
ILIMH
EP
Data Sheet
Type
Analog Input
Analog Input
Metal paddle at the
back of package
Description
Sets Maximum Voltage Across TEC Module.
Sets TEC Heating Current Limit.
Exposed Pad. The LFCSP has an exposed pad that must be connected to AGND (Pin 12) and
the associated PCB ground plane.
Rev. C | Page 8 of 18
Data Sheet
ADN8831
TYPICAL PERFORMANCE CHARACTERISTICS
360
SYNCI/SD = 1MHz
TA = 25°C
VDD = 3V
SPGATE
PHASE SHIFT (Degrees)
VOLTAGE (1V/DIV)
300
SNGATE
TA = 25°C
VDD = 5V
240
180
120
0
10ns/DIV
04663-007
04663-004
60
0
0.4
0.8
1.2
1.6
2.0
2.4
VPHASE (V)
Figure 4. SPGATE and SNGATE Rise Time Using Circuit Shown Figure 12
Figure 7. Clock Phase Shift vs. Phase Voltage
2.485
VDD = 5V
SNGATE
SPGATE
VREF (V)
TA = 25°C
VDD = 5V
2.475
04663-005
2.470
2.465
–40
10ns/DIV
04663-008
VOLTAGE (1V/DIV)
2.480
–15
10
35
60
85
TEMPERATURE (°C)
Figure 5. SNGATE and SPGATE Fall Time Using Circuit Shown in Figure 12
Figure 8. VREF vs. Temperature
360
1000
SYNCI/SD = 1MHz
TA = 25°C
VDD = 5V
240
180
120
60
0
0
0.4
0.8
1.2
1.6
2.0
800
600
400
200
0
2.4
VPHASE (V)
04663-009
SWITCHING FREQUENCY (kHz)
VDD = 5V
TA = 25°C
04663-006
PHASE SHIFT (Degrees)
300
0
250
500
750
RFREQ (kΩ)
Figure 9. Switching Frequency vs. RFREQ
Figure 6. Clock Phase Shift vs. Phase Voltage
Rev. C | Page 9 of 18
1000
ADN8831
Data Sheet
740
15
VDD = 5V
TA = 25°C
720
SUPPLY CURRENT (mA)
12
700
680
660
6
–15
10
35
60
85
0
200
04663-011
640
–40
9
3
04663-010
SWITCHING FREQUENCY (kHz)
VDD = 5V
400
600
800
SWITCHING FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 10. Switching Frequency vs. Temperature
Figure 11. Supply Current vs. Switching Frequency
Rev. C | Page 10 of 18
1000
Data Sheet
ADN8831
THEORY OF OPERATION
Adjusting the PID network optimizes the step response of
the TEC control loop. A compromised settling time and the
maximum current ringing become available when this is done.
Details of how to adjust the compensation network are in the
PID Compensation Amplifier (CHOP2) section. The TEC is
differentially driven in an H-bridge configuration. The ADN8831
drives external MOSFET transistors to provide the TEC current.
To further improve the power efficiency of the system, one side
of the H-bridge uses a PWM driver. Only one inductor and one
capacitor are required to filter out the switching frequency. The
other side of the H-bridge uses linear output without requiring
any additional circuitry. This proprietary configuration allows
the ADN8831 to provide efficiency of >90%. For most applications, a 4.7 μH inductor, a 22 μF capacitor, and a switching
frequency of 1 MHz, maintain less than 0.5% worst-case output
voltage ripple across a TEC.
The ADN8831 is a single chip TEC controller that sets and
stabilizes a TEC temperature. A voltage applied to the input
of the ADN8831 corresponds to a target TEC temperature
setpoint (TEMPSET). By controlling an external FET H-bridge,
the appropriate current is then applied to the TEC to pump
heat either to or away from an object attached to the TEC.
The objective temperature is measured with a thermal sensor
attached to the TEC and the sensed temperature (voltage) is
fed back to the ADN8831 to complete a closed thermal control
loop of the TEC. For best stability, the thermal sensor is to be
closed to the object. In most laser diode modules, a TEC and a
NTC thermistor are already mounted in the same package to
regulate the laser diode temperature.
The ADN8831 integrates two self-correcting, auto-zero amplifiers
(Chop1 and Chop2). The Chop1 amplifier usually takes a thermal
sensor input and converts or regulates the input to a linear
voltage output. The OUT1 (Pin 4) voltage is proportional to the
object temperature. The OUT1 (Pin 4) voltage is fed into the
compensation amplifier (Chop2) and compared with a temperature setpoint voltage, creating an error voltage that is proportional
to the difference. When using the Chop2 amplifier, a PID
network is recommended, as shown in Figure 12.
The maximum voltage across the TEC and current flowing
through the TEC is to be set using the VLIM (Pin 31) and
ILIMC (Pin 1)/ILIMH (Pin 32). Additional details are in the
Maximum TEC Voltage Limit section and the Maximum TEC
Current Limit section.
5Ω
0.1µF
AVDD
0.1µF
PVDD
VREF
LPGATE
VLIM
LFB
10kΩ
10kΩ
8.2kΩ
ILIMC
LNGATE
ILIMH
CS
10kΩ
SFB
SYNCI/SD
17.8kΩ
OUT1
10kΩ
VDD
COMPOSC
10kΩ
60µF
SPGATE
IN2N
27nF
TEC
IN1P
IN1N
THERMISTOR
0.1µF
COMPSW
10kΩ
7.68kΩ
RSENSE
10kΩ
8.2kΩ
17.8kΩ
VDD
3.0V TO 5.5V
0.1µF
30.1kΩ
10µF
TEMPERATURE SET INPUT
SW
1kΩ
3.3µH
OUT2
SNGATE
IN2P
SYNCO
NC
PHASE
NC
TEC VOLTAGE OUTPUT
VTEC
TEC CURRENT OUTPUT
ITEC
SS/SB
TMPGD
FREQ
40µF
AGND
PGND
NC = NO CONNECT
Figure 12. Typical Application Circuit 1
Rev. C | Page 11 of 18
118kΩ
04663-012
0.1µF
TEMP GOOD INDICATOR
ADN8831
Data Sheet
OSCILLATOR CLOCK FREQUENCY
Connecting Multiple ADN8831 Devices
The ADN8831 has an internal oscillator to generate the switching
frequency for the output stage. This oscillator can be set in either
free-run mode or synchronized to an external clock signal.
Connecting SYNCO (Pin 15) to the SYNCI/SD pin of another
ADN8831 allows for multiple ADN8831 devices to work
together using a single clock. Multiple ADN8831 devices can be
driven from a single master ADN8831 device, by connecting the
SYNCO pin of the master device to each slave SYNCI/SD pin,
or by daisy-chaining by connecting the SYNCO pin of each
device to the SYNCI/SD pin of the next device. When multiple
ADN8831 devices are clocked at the same frequency, the phase is
to be adjusted to reduce power supply ripple.
Free-Run Operation
The switching frequency is set by a single resistor connected
from FREQ (Pin 13) to ground. Table 5 shows RFREQ for some
common switching frequencies. For free-run operation, connect
SYNCI/SD (Pin 16) and COMPOSC (Pin 17) to PVDD (Pin 18).
Table 5. Switching Frequencies vs. RFREQ
ADN8831
RFREQ
484 kΩ
249 kΩ
168 kΩ
118 kΩ
MASTER
VDD
COMPOSC
118kΩ
FREQ
VDD
SYNCI/SD
PHASE
NC
SYNCO
Higher switching frequencies reduce the voltage ripple across the
TEC. However, high switching frequencies create more power
dissipation in the external transistors due to the more frequent
charging and discharging of the transistor gate capacitances.
10kΩ
VDD
1nF
ADN8831
SLAVE
ADN8831
COMPOSC
VDD
COMPOSC
FREQ
1kΩ
1MΩ
RFREQ
FREQ
VDD
PHASE
VPHASE
04663-013
SYNCI/SD
SYNCI/SD
1nF
ADN8831
Figure 13. Free-Run Mode
SLAVE
External Clock Operation
COMPOSC
The switching frequency of the ADN8831 can be synchronized
with an external clock. Connect the clock signal to SYNCI/SD
(Pin 16) and connect COMPOSC (Pin 17) to an R-C network. This
network compensates a PLL to lock on to the external clock.
FREQ
SYNCI/SD
1nF
COMPOSC
FREQ
SYNCI/SD
1kΩ
Figure 14. Synchronize to an External Clock
0.1µF
1MΩ
VPHASE
OSCILLATOR CLOCK PHASE
1MΩ
EXT. CLOCK
SOURCE
PHASE
1kΩ
Figure 15. Multiple ADN8831 Devices Driven from a Master Clock
0.1µF
04663-014
ADN8831
0.1µF
04663-015
fSWITCH
250 kHz
500 kHz
750 kHz
1 MHz
Adjust the oscillator clock phase using a simple resistor divider
at PHASE (Pin 10). Phase adjustment allows two or more
ADN8831 devices to operate from the same clock frequency
and not have all outputs switched simultaneously. This avoids
the potential of an excessive power supply ripple.
To ensure the correct operation of the oscillator, VPHASE is to
remain in the range of 100 mV to 2.4 V. PHASE (Pin 10) is
internally biased at 1.2 V. If PHASE (Pin 10) remains open, the
clock phase is set at 180° as the default.
Rev. C | Page 12 of 18
Data Sheet
ADN8831
TEMPERATURE LOCK INDICATOR
Current Monitor
The TMPGD (Pin 11) outputs a logic high when the OUT1 (Pin 4)
voltage reaches the IN2P (Pin 5) temperature setpoint (TEMPSET)
voltage. The TMPGD has a detection range of ±25 mV and a
10 mV typical hysteresis. This allows direct interfacing either to
the microcontrollers or to the supervisory circuitry.
ITEC (Pin 29) is an analog voltage output pin with a voltage
proportional to the actual current through the TEC. A center
ITEC voltage of 1.25 V corresponds to 0 A through the TEC.
The output voltage is calculated using the following equation:
SOFT START ON POWER-UP
The equivalent TEC current is calculated using the following
equation:
The ADN8831 can be programmed to ramp up for a specified
time after the power supply is turned on or after the SD pin is
deasserted. This feature, called soft start, is useful for gradually
increasing the duty cycle of the PWM amplifier. The soft start
time is set with a single capacitor connected from SS (Pin 14) to
ground. The capacitor value is calculated by the following
equation:
τ SS = 150 × C SS
where:
CSS is the value of the capacitor in microfarads.
τSS is the soft start time in milliseconds.
VITEC = 1.25 V + 25 × (VLFB − VCS )
I TEC =
VITEC − 1.25 V
25 × RSENSE
MAXIMUM TEC VOLTAGE LIMIT
The maximum TEC voltage is set by applying a voltage at
VLIM (Pin 31) to protect the TEC. This voltage can be set with
a resistor divider or a DAC. The voltage limiter operates in
bidirectional TEC voltage, and cooling and heating voltage.
Using a DAC
SHUTDOWN MODE
The shutdown mode sets the ADN8831 into an ultralow current
state. The current draw in shutdown mode is typically 8 µA.
The shutdown input, SD (Pin 16), is active low. To shut down
the device, drive SD to logic low. Once a logic high is applied,
the ADN8331 is reactivated after the time delay set by the soft
start circuitry. Refer to the Soft Start on Power-Up section for
more details.
STANDBY MODE
The ADN8831 has a standby mode that deactivates a MOSFET
driver stage. The current draw for the ADN8831 in standby
mode is less than 2 mA. The standby input SS/SB (Pin 14) is
active low. After applying a logic high, the ADN8331 reactivates
following the delay. In standby mode, only SYNCO (Pin 15) has
a clock output. All the other function blocks are powered off.
VTEC ( MAX ) = 5 × VVLIM
where:
VTEC (MAX) is the maximum TEC voltage.
VVLIM is the voltage applied at VLIM (Pin 31).
Using a Resistor Divider
Separate voltage limits are set using a resistor divider. The
internal current sink circuitry connected to VLIM (Pin 31) draws
a current when the ADN8831 drives the TEC in a heating
direction, which lowers the voltage at VLIM (Pin 31). The
current sink is not active when the TEC is driven in a cooling
direction; therefore, the TEC heating voltage limit is always
lower than the cooling voltage limit.
TEC VOLTAGE/CURRENT MONITOR
VREF
ADN8831
VLIM
VLIM
The TEC real time voltage and current are detectable at VTEC
(Pin 30) and ITEC (Pin 29), respectively.
Voltage Monitor
RA
RB
ISINK
FREQ
VTEC (Pin 30) is an analog voltage output pin with a voltage
proportional to the actual voltage across the TEC. A center
VTEC voltage of 1.25 V corresponds to 0 V across a TEC. The
output voltage is calculated using the following equation:
VVTEC = 1.25 V + 0.25 × (VLFB − VSFB )
Rev. C | Page 13 of 18
RFREQ
Figure 16. Using a Resistor Divider
04663-016
To set a soft start time of 15 ms, CSS is to equal 0.1 μF.
Both the cooling and heating voltage limits are set at the same
levels when a voltage source directly drives VLIM (Pin 31).
The maximum TEC voltage is calculated using the following
equation:
ADN8831
Data Sheet
The sink current is set by the resistor connected from FREQ
(Pin 13) to ground. The sink current is calculated using the
following equation:
I SINK =
1.25 V
RFREQ
MAXIMUM TEC CURRENT LIMIT
To protect the TEC, separate maximum TEC current limits in
cooling and heating directions are set by applying a voltage at
ILIMC (Pin 1) and ILIMH (Pin 32). Maximum TEC currents
are calculated using the following equations:
where:
ISINC is the sink current at VLIM (Pin 31).
RFREQ is the resistor connected at FREQ (Pin 13).
I TEC ,MAX ,COOL =
I TEC ,MAX ,HEAT =
The cooling and heating limits are calculated using the
following equations:
VVLIM ,COOL =
VREF × R B
RA + RB
VVLIM ,HEAT = VVLIM ,COOL − I SINK × R A R B
Rev. C | Page 14 of 18
VILIMC − 1.25 V
25 × RSENSE
1.25 V − VILIMH
25 × RSENSE
Data Sheet
ADN8831
APPLICATIONS INFORMATION
PID COMPENSATOR
AMPLIFIER
AV = Z2/Z1
THERMISTOR INPUT
AMPLIFIER
AV = RFB/(RTH + RX) – RFB/R
MOSFET DRIVER
AV = 5
SFB
SPGATE
PWM
IN1P
+
Chop1
IN1N –
IN2P
+
IN2N
Chop2
–
OUT1
SNGATE
LPF
TEC
OUT2
CONTROL
LPGATE
LINEAR
LNGATE
LFB
17.68kΩ
R
7.68kΩ
RX
2
3
4
VREF /2
RTH
5
6
7
VTEMPSET
RFB
Z1
Z2
VOUT1
VOUT2
04663-017
VREF
(10kΩ @ 25°C)
Figure 17. Signal Flow Block Diagram
SIGNAL FLOW
The ADN8831 integrates two auto-zero amplifiers defined
as the Chop1 amplifier and the Chop2 amplifier. Both of the
amplifiers can be used as standalone amplifiers, therefore, the
implementation of temperature control can vary. Figure 17
shows the signal flow through the ADN8831, and a typical
implementation of the temperature control loop using the Chop1
amplifier and the Chop2 amplifier.
In Figure 17, the Chop1 amplifier and the Chop2 amplifier are
configured as the thermistor input amplifier and the PID
compensation amplifier, respectively. The thermistor input
amplifier gains the thermistor voltage then outputs to the PID
compensation amplifier. The PID compensation amplifier then
compensates a loop response over the frequency domain.
The output from the compensation loop at OUT2 is fed to the
linear MOSFET gate driver. The voltage at LFB is fed with OUT2
into the PWM MOSFET gate driver. Including the external
transistors, the gain of the differential output section is fixed at 5.
For details on the output drivers, see the MOSFET Driver
Amplifier section.
THERMISTOR SETUP
The thermistor has a nonlinear relationship to temperature; near
optimal linearity over a specified temperature range can be
achieved with the proper value of RX placed in series with the
thermistor. First, the resistance of the thermistor must be
known, where
R LOW RTH @ TLOW
R MID RTH @ TMID
R HIGH RTH @ THIGH
TLOW and THIGH are the endpoints of the temperature range and
TMID is the average. In some cases, with only B constant available ,
RTH is calculated using the following equation:
1
1
RTH R R expB
T TR
where:
RTH is a resistance at T[K].
RR is a resistance at TR[K].
RX is calculated using the following equation:
R
R
R MID R HIGH 2R LOW R HIGH
R X LOW MID
R
LOW R HIGH 2 R MID
THERMISTOR AMPLIFIER (Chop1)
The Chop1 amplifier can be used as a thermistor input amplifier.
In Figure 17, the output voltage is a function of the thermistor
temperature. The voltage at OUT1 is expressed as
RFB
V
R
VOUT1
FB 1 REF
R
2
RTH R X
where:
RTH is a thermistor.
RX is a compensation resistor.
R is calculated using the following equation:
R R X RTH @ 25C
VOUT1 is centered around VREF/2 at 25°C. With the typical
values shown in Figure 17, an average temperature-to-voltage
coefficient is −25 mV/°C at a range of +5°C to +45°C.
Rev. C | Page 15 of 18
ADN8831
Data Sheet
2.5
f 0 dB
VOUT1 (V)
2.0
1
80 TECGAIN
2R3C1
To ensure stability, the unity-gain crossover frequency is to be
lower than the thermal time constant of the TEC and thermistor.
However, this thermal time constant is sometimes unspecified
making it difficult to characterize. There are many texts written
on loop stabilization, and it is beyond the scope of this data
sheet to discuss all methods and trade offs in optimizing
compensation networks.
1.5
1.0
0.5
04663-018
0
–15
ADN8831
5
25
45
+
CHOP2
–
65
TEMPERATURE(°C)
Figure 18. VOUT1 vs. Temperature
4
PID COMPENSATION AMPLIFIER (Chop2)
5
IN2P
6
IN2N
7
OUT2
VTEMPSET
R3
R2
R1
C2
C1
04663-019
Use the Chop2 amplifier as the PID compensation amplifier.
The voltage at OUT1 feeds into the PID compensation amplifier.
The frequency response of the PID compensation amplifier is
dictated by the compensation network. Apply the temperature
set voltage at IN2P. In Figure 17, the voltage at OUT2 is calculated using the following equation:
CF
Figure 19. Implementing a PID Compensation Loop
Z2
(VOUT1 VTEMPSET )
Z1
A typical compensation network for temperature control of
a laser module is a PID loop consisting of a very low frequency
pole and two separate zeros at higher frequencies. Figure 19
shows a simple network for implementing PID compensation.
To reduce the noise sensitivity of the control loop, an additional
pole is added at a higher frequency than the zeros. The bode
plot of the magnitude is shown in Figure 20. The unity-gain
crossover frequency of the feedforward amplifier is calculated
using the following equation:
0dB
R1
R2 || R3
R1
R3
1
2πR3C1
1
2πR1C1
1
2πC2 (R2 + R3)
FREQUENCY (Hz log scale)
1
2πR3C2
04663-020
The user sets the exact compensation network. This network
varies from a simple integrator to PI, PID, or any other type of
network. The user also determines the type of compensation
and component values because they are dependent on the thermal
response of the object and the TEC. One method for empirically
determining these values is to input a step function to IN2P,
therefore changing the target temperature, and adjusting the
compensation network to minimize the settling time of the TEC
temperature.
MAGNITUDE (log scale)
VOUT2 VTEMPSET
OUT1
Figure 20. Bode Plot for PID Compensation
With an ADN8831-EVALZ board, AN-695, an application note
shows how to determine the PID network components for a
stable TEC subsystem performance.
Rev. C | Page 16 of 18
Data Sheet
ADN8831
MOSFET DRIVER AMPLIFIER
5.0
LFB (V)
The ADN8831 has two separate MOSFET drivers: a switched
output or pulse-width modulated (PWM) amplifier, and a high
gain linear amplifier. Each amplifier has a pair of outputs that drive
the gates of external MOSFETs which, in turn, drive the TEC as
shown in Figure 17. A voltage across the TEC is monitored via
SFB (Pin 23) and LFB (Pin 27). Although both MOSFET drivers
achieve the same result, to provide constant voltage and high
current, their operation is different. The exact equations for the
two outputs are
2.5
0
SFB (V)
5.0
VLFB = VB − 40(VOUT2 − 1.25)
2.5
0
VSFB = VLFB + 5(VOUT2 − 1.25)
where:
VOUT2 is the voltage at OUT2 (Pin 7).
VB is determined by VDD as
5.0
2.5
VB = 2.5 V[VDD > 4.0 V]
The voltage at OUT2 (Pin 7) is determined by the compensation
network that receives temperature set voltage and thermistor
voltage fed by the input amplifier. VLFB has a low limit of 0 V
and an upper limit of VDD. Figure 21 shows the graphs of these
equations.
Rev. C | Page 17 of 18
0
–2.5
04663-021
VTEC (V)
LFB-SFB
VB = 1.5 V[VDD < 4.0 V]
–5.0
0
0.25
0.75
1.25
1.75
2.25
OUT2 (V)
Figure 21. OUT2 Voltage vs. TEC Voltage
2.75
ADN8831
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
25
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
32
24
1
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
PKG-003898
SEATING
PLANE
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
8
9
16
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD
09-12-2018-A
PIN 1
INDICATOR
AREA
5.10
5.00 SQ
4.90
Figure 22. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm× 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADN8831ACPZ-R2
ADN8831ACPZ-REEL7
ADN8831-EVALZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2005–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04663-0-9/19(C)
Rev. C | Page 18 of 18
Package Option
CP-32-7
CP-32-7
工商网监
湘ICP备2023018690号
