Data Sheet
Ultracompact, 1 A Thermoelectric Cooler
(TEC) Driver for Digital Control Systems
ADN8833
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VTEC
TEC CURRENT
AND VOLTAGE
SENSE AND LIMIT
VLIM/SD
ILIM
The ADN8833 is a monolithic H-bridge TEC driver with
integrated 1 A power MOSFETs. It has a linear power stage with
the linear driver (LDR) output and a pulse-width modulation
(PWM) power stage with the SW output. Depending on the
control voltage at the CONT input, the ADN8833 drives current
through a TEC to settle the temperature of a laser diode or a passive
component attached to the TEC module to the programmed
target temperature.
The control voltage applied to the CONT input is generated by a
digital-to-analog converter (DAC) closing the digital proportional,
integral, derivative (PID) loop of temperature control system.
LDR
CONTROLLER
PWM
POWER
STAGE
TEC temperature control
Optical modules
Optical fiber amplifiers
Optical networking systems
Instruments requiring TEC temperature control
1
LINEAR
POWER
STAGE
PVIN
CONT
VOLTAGE
REFERENCE
GENERAL DESCRIPTION
VDD
ADN8833
APPLICATIONS
1
ITEC
AGND
VREF
SW
OSCILLATOR
SFB
EN/SY
PGNDx
12909-001
Patented high efficiency single inductor architecture
Integrated low RDSON MOSFETs for TEC driver
TEC voltage and current operation monitoring
No external sense resistor required
Independent TEC heating and cooling current limit settings
Programmable maximum TEC voltage
2 MHz PWM driver switching frequency
External synchronization
Digital thermal control loop compatible
2.50 V reference output with 1% accuracy
Available in a 25-ball, 2.5 mm × 2.5 mm WLCSP or in a
24-lead, 4 mm × 4 mm LFCSP
Figure 1.
The internal 2.5 V reference voltage provides a 1% accurate
output that is used to bias a voltage divider network to program the
maximum TEC current and voltage limits for both the heating
and cooling modes. It can also be a reference voltage for the DAC
and the temperature sensing circuit, including a thermistor bridge
and an analog-to-digital converter (ADC).
Table 1. TEC Family Models
Model
ADN8831
ADN8833
MOSFET
Discrete
Integrated
Thermal Loop
Digital/analog
Digital
ADN8834
Integrated
Digital/analog
Package
LFCSP (CP-32-7)
WLCSP (CB-25-7),
LFCSP (CP-24-15)
WLCSP (CB-25-7),
LFCSP (CP-24-15)
Product is covered by US Patent No. 6,486,643.
Rev. B
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ADN8833
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
TEC Voltage/Current Monitor ................................................. 15
Applications ....................................................................................... 1
Maximum TEC Voltage Limit .................................................. 15
Functional Block Diagram .............................................................. 1
Maximum TEC Current Limit ................................................. 15
General Description ......................................................................... 1
Applications Information .............................................................. 16
Revision History ............................................................................... 2
Typical Application with Digital PID Using a DAC .............. 16
Specifications..................................................................................... 3
Thermistor Setup........................................................................ 16
Absolute Maximum Ratings............................................................ 6
MOSFET Driver Amplifiers ...................................................... 16
Thermal Resistance ...................................................................... 6
PWM Output Filter Requirements .......................................... 17
ESD Caution .................................................................................. 6
Input Capacitor Selection .......................................................... 18
Pin Configurations and Function Descriptions ........................... 7
Power Dissipation....................................................................... 18
Typical Performance Characteristics ............................................. 8
PCB Layout Guidelines .................................................................. 20
Detailed Functional Block Diagram ............................................ 12
Block Diagrams and Signal Flow ............................................. 20
Theory of Operation ...................................................................... 13
Guidelines for Reducing Noise and Minimizing Power Loss .... 20
Digital PID Control .................................................................... 13
Example PCB Layout Using Two Layers ................................. 21
Powering the Driver ................................................................... 13
Outline Dimensions ....................................................................... 23
Enable and Shutdown ................................................................ 14
Ordering Guide .......................................................................... 23
Oscillator Clock Frequency ....................................................... 14
Soft Start on Power-Up .............................................................. 14
REVISION HISTORY
8/2018—Rev. A to Rev. B
Added Patent Information .............................................................. 1
8/2015—Rev. 0 to Rev. A
Added 24-Lead LFCSP....................................................... Universal
Changes to Features Section and Table 1 ...................................... 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 6
Added Figure 3; Renumbered Sequentially ................................. 7
Changes to Figure 11 ........................................................................ 9
Changes to Figure 18 and Figure 19 ............................................. 10
Changes to Figure 23 ...................................................................... 12
Changes to Powering the Driver Section and Figure 24 Caption... 13
Change to Soft Start on Power-Up Section ................................. 14
Changes to Table 7 .......................................................................... 17
Added Table 8; Renumbered Sequentially .................................. 18
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide ......................................................... 23
4/2015—Revision 0: Initial Version
Rev. B | Page 2 of 23
Data Sheet
ADN8833
SPECIFICATIONS
VIN = 2.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA =25°C for typical specifications, unless
otherwise noted.
Table 2.
Parameter
POWER SUPPLY
Driver Supply Voltage
Controller Supply Voltage
Supply Current
Shutdown Current
Undervoltage Lockout (UVLO)
UVLO Hysteresis
REFERENCE VOLTAGE
LINEAR OUTPUT
Output Voltage
Low
High
Maximum Source Current
Maximum Sink Current
On Resistance
P-MOSFET
N-MOSFET
Leakage Current
P-MOSFET
N-MOSFET
Linear Amplifier Gain
LDR Short-Circuit Threshold
Hiccup Cycle
PWM OUTPUT
Output Voltage
Low
High
Maximum Source Current
Maximum Sink Current
On Resistance
P-MOSFET
N-MOSFET
Symbol
Test Conditions/Comments
Min
VPVIN
VPVINL, VPVINS
VVDD
IVDD
ISD
VUVLO
UVLOHYST
VVREF
WLCSP
LFCSP
2.7
2.7
2.7
VLDR
PWM not switching
EN/SY = AGND or VLIM/SD = AGND
VVDD rising
IVREF = 0 mA to 10 mA
2.45
80
2.475
Typ
Max
Unit
2.1
350
2.55
90
2.50
5.5
5.5
5.5
3.5
700
2.65
100
2.525
V
V
V
mA
µA
V
mV
V
1.0
V
V
A
A
35
44
50
55
31
40
45
50
50
60
65
75
50
55
70
80
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
0.1
0.1
40
2.2
−2.2
15
10
10
µA
µA
V/V
A
A
ms
ILDR = 0 A
0
VPVIN
ILDR_SOURCE
ILDR_SINK
RDS_PL(ON)
RDS_NL(ON)
ILDR_P_LKG
ILDR_N_LKG
ALDR
ILDR_SH_GNDL
ILDR_SH_PVIN
THICCUP
VSFB
ISW_SOURCE
ISW_SINK
RDS_PS(ON)
RDS_NS(ON)
TJ = −40°C to +125°C
TJ = −40°C to +125°C
ILDR = 0.6 A
WLCSP, VPVIN = 5.0 V
WLCSP, VPVIN = 3.3 V
LFCSP, VPVIN = 5.0 V
LFCSP, VPVIN = 3.3 V
WLCSP, VPVIN = 5.0 V
WLCSP, VPVIN = 3.3 V
LFCSP, VPVIN = 5.0 V
LFCSP, VPVIN = 3.3 V
LDR short to PGNDL, enter hiccup
LDR short to PVIN, enter hiccup
1.0
ISFB = 0 A
TJ = −40°C to +125°C
TJ = −40°C to +125°C
ISW = 0.6 A
WLCSP, VPVIN = 5.0 V
WLCSP, VPVIN = 3.3 V
LFCSP, VPVIN = 5.0 V
LFCSP, VPVIN = 3.3 V
WLCSP, VPVIN = 5.0 V
WLCSP, VPVIN = 3.3 V
LFCSP, VPVIN = 5.0 V
LFCSP, VPVIN = 3.3 V
Rev. B | Page 3 of 23
0.06 × VPVIN
0.93 × VPVIN
1.0
47
60
60
70
40
45
45
55
1.0
V
V
A
A
65
80
80
95
60
65
75
85
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
ADN8833
Parameter
Leakage Current
P-MOSFET
N-MOSFET
SW Node Rise Time 1
PWM Duty Cycle 2
SFB Input Bias Current
PWM OSCILLATOR
Internal Oscillator Frequency
EN/SY Input Voltage
Low
High
External Synchronization Frequency
Synchronization Pulse Duty Cycle
EN/SY Rising to PWM Rising Delay
EN/SY to PWM Lock Time
EN/SY Input Current
Pull-Down Current
DRIVER CONTROL INPUT
Input Voltage Range
Input Resistance
Input Capacitance1
TEC CURRENT LIMIT
ILIM Input Voltage Range
Cooling
Heating
Current-Limit Threshold
Cooling
Heating
ILIM Input Current
Heating
Cooling
Cooling to Heating Current Detection
Threshold
TEC VOLTAGE LIMIT
Voltage Limit Gain
VLIM/SD Input Voltage Range1
VLIM/SD Input Current
Cooling
Heating
TEC CURRENT MEASUREMENT (WLCSP)
Current Sense Gain
Data Sheet
Symbol
Test Conditions/Comments
ISW_P_LKG
ISW_N_LKG
tSW_R
DSW
ISFB
CSW = 1 nF
fOSC
EN/SY high
VEN/SY_ILOW
VEN/SY_IHIGH
fSYNC
DSYNC
tSYNC_PWM
tSY_LOCK
IEN/SY
Min
1.85
10
10
1
93
2
µA
µA
ns
%
µA
2.0
2.15
MHz
0.8
V
V
MHz
%
ns
Cycles
µA
µA
3.25
90
Number of SYNC cycles
0.3
0.3
1.3
0.2
10
0.5
0.5
VVREF
V
kΩ
pF
VVREF − 0.2
1.2
V
V
2.02
0.52
V
V
+0.2
42.5
µA
µA
mA
40
40
VILIMC_TH
VILIMH_TH
VITEC = 0.5 V
VITEC = 2 V
1.98
0.48
IILIMH
IILIMC
ICOOL_HEAT_TH
Sourcing current
−0.2
37.5
AVLIM
VVLIM
(VLDR − VSFB)/VVLIM
IILIMC
IILIMH
VOUT2 < VVREF/2
VOUT2 > VVREF/2, sinking current
RCS
VPVIN = 3.3 V
VPVIN = 5 V
700 mA ≤ ILDR ≤ 1 A, VPVIN = 3.3 V
800 mA ≤ ILDR ≤ 1 A, VPVIN = 5 V
VPVIN = 3.3 V, cooling, VVREF/2 + ILDR × RCS
VPVIN = 3.3 V, heating, VVREF/2 − ILDR × RCS
VPVIN = 5 V, cooling, VVREF/2 + ILDR × RCS
VPVIN = 5 V, heating, VVREF/2 − ILDR × RCS
VITEC_@_700_mA
VITEC_@_−700_mA
VITEC_@_800_mA
VITEC_@_−800_mA
0.1
0.1
1
50
VILIMC
VILIMH
ITEC Voltage Accuracy
Unit
2.1
1.85
10
0
ILDR_ERROR
Max
6
VCONT
RCONT
CCONT
Current Measurement Accuracy
Typ
Rev. B | Page 4 of 23
2.0
0.5
40
40
0.2
2
VVDD/2
V/V
V
−0.2
8
+0.2
12.2
µA
µA
+10
+10
1.779
0.971
1.846
0.905
V/A
V/A
%
%
V
V
V
V
10
0.525
0.535
−10
−10
1.455
0.794
1.510
0.739
1.618
0.883
1.678
0.822
Data Sheet
Parameter
TEC CURRENT MEASUREMENT (LFCSP)
Current Sense Gain
Test Conditions/Comments
RCS
VPVIN = 3.3 V
VPVIN = 5 V
700 mA ≤ ILDR ≤ 1 A, VPVIN = 3.3 V
800 mA ≤ ILDR ≤ 1 A, VPVIN = 5 V
VPVIN = 3.3 V, cooling, VVREF/2 + ILDR × RCS
VPVIN = 3.3 V, heating, VVREF/2 − ILDR × RCS
VPVIN = 5 V, cooling, VVREF/2 + ILDR × RCS
VPVIN = 5 V, heating, VVREF/2 − ILDR × RCS
ITEC = 0 A
ILDR = 0 A
ILDR_ERROR
ITEC Voltage Accuracy
VITEC_@_700_mA
VITEC_@_−700_mA
VITEC_@_800_mA
VITEC_@_−800_mA
VITEC
VITEC
IITEC
VTEC Output Voltage Range
VTEC Bias Voltage
Maximum VTEC Output Current
INTERNAL SOFT START
Soft Start Time
VLIM/SD SHUTDOWN
VLIM/SD Low Voltage Threshold
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
2
Symbol
Current Measurement Accuracy
ITEC Voltage Output Range
ITEC Bias Voltage
Maximum ITEC Output Current
TEC VOLTAGE MEASUREMENT
Voltage Sense Gain
Voltage Measurement Accuracy
1
ADN8833
AVTEC
VVTEC_@_1_V
VVTEC
VVTEC_B
RVTEC
VLDR − VSFB = 1 V, VVREF/2 + AVTEC ×
(VLDR − VSFB)
VLDR = VSFB
tSS
Min
Typ
Max
Unit
+15
+15
1.861
1.015
1.921
0.955
VVREF − 0.05
1.285
+2
V/A
V/A
%
%
V
V
V
V
V
V
mA
0.25
1.50
0.26
1.525
V/V
V
1.250
2.625
1.285
+2
V
V
mA
0.525
0.525
−15
−15
1.374
0.750
1.419
0.705
0
1.225
−2
0.24
1.475
0.005
1.225
−2
1.618
0.883
1.678
0.830
1.250
150
VVLIM/SD_THL
ms
0.07
TSHDN_TH
TSHDN_HYS
170
17
This specification is guaranteed by design.
This specification is guaranteed by characterization.
Rev. B | Page 5 of 23
V
°C
°C
ADN8833
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
PVIN to PGNDL (WLCSP)
PVIN to PGNDS (WLCSP)
PVINL to PGNDL (LFCSP)
PVINS to PGNDS (LFCSP)
LDR to PGNDL (WLCSP)
LDR to PGNDL (LFCSP)
SW to PGNDS
SFB to AGND
AGND to PGNDL
AGND to PGNDS
VLIM/SD to AGND
ILIM to AGND
VREF to AGND
VDD to AGND
EN/SY to AGND
ITEC to AGND
VTEC to AGND
Maximum Current
VREF to AGND
ITEC to AGND
VTEC to AGND
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages, and is
based on a 4-layer standard JEDEC board.
Rating
−0.3 V to +5.75 V
−0.3 V to +5.75 V
−0.3 V to +5.75 V
−0.3 V to +5.75 V
−0.3 V to VPVIN
−0.3 V to VPVINL
−0.3 V to +5.75 V
−0.3 V to VVDD
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to VVDD
−0.3 V to VVDD
−0.3 V to +3 V
−0.3 V to +5.75 V
−0.3 V to VVDD
−0.3 V to +5.75 V
−0.3 V to +5.75 V
Table 4.
Package Type
25-Ball WLCSP
24-Lead LFCSP
ESD CAUTION
20 mA
50 mA
50 mA
125°C
−65°C to +150°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 6 of 23
θJA
48
37
θJC
0.6
1.65
Unit
°C/W
°C/W
Data Sheet
ADN8833
5
PGNDL
PGNDL
DNC
DNC
DNC
18 PGNDL
DNC 1
A
CONT 2
17 LDR
VLIM/SD 3
ILIM 4
ADN8833
16 PVINL
TOP VIEW
(Not to Scale)
15 PVINS
VDD 5
C
PVIN
PVIN
ITEC
CONT
ILIM
14 SW
VREF 6
13 PGNDS
2.54mm
ITEC 11
VLIM/
SD
PGNDS 12
DNC
SFB 10
DNC
VTEC 9
LDR
AGND 7
LDR
EN/SY 8
B
NOTES
1. DNC = DO NOT CONNECT. DO NOT
CONNECT TO THESE PINS.
2. EXPOSED PAD. SOLDER TO THE ANALOG
GROUND PLANE ON THE BOARD
D
SW
VTEC
SW
EN/SY
12909-100
4
20 DNC
3
19 PGNDL
2
22 DNC
1
21 DNC
24 DNC
ADN8833
TOP VIEW
(Not to Scale)
23 DNC
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD
0.5mm
PITCH
E
PGNDS
SFB
PGNDS
AGND
VREF
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
12909-002
2.54mm
Figure 3. LFCSP Pin Configuration (Top View)
Figure 2. WLCSP Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.
WLCSP LFCSP
A1, A2
18, 19
A3 to
1, 20 to
A5, B3, 24
B4
B1, B2
17
B5
3
Mnemonic
PGNDL
DNC
Description
Power Ground of the Linear TEC Driver.
Do Not Connect. Do not connect to these pins.
LDR
VLIM/SD
Output of the Linear TEC Driver.
Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage limits. When this pin is
pulled low, the device shuts down.
Power Input for the TEC Driver.
Power input for the linear TEC driver
Power input for the PWM TEC driver
TEC Current Output.
Control Input of the TEC Driver. Apply a control signal from the DAC to this pin to close the thermal loop.
Current Limit. This pin sets the TEC cooling and heating current limits.
Switch Node Output of the PWM TEC Driver.
TEC Voltage Output.
Enable/Synchronization. Set this pin high to enable the device. An external synchronization clock input
can be applied to this pin.
Power for the Driver Circuits.
Power Ground of the PWM TEC Driver.
Feedback of the PWM TEC Driver Output.
Signal Ground.
2.5 V Reference Output.
Exposed Pad. Solder to the analog ground plane on the board.
C1, C2
N/A1
N/A1
C3
C4
C5
D1, D2
D3
D4
N/A 1
16
15
11
2
4
14
9
8
PVIN
PVINL
PVINS
ITEC
CONT
ILIM
SW
VTEC
EN/SY
D5
E1, E2
E3
E4
E5
N/A1
5
12, 13
10
7
6
0
VDD
PGNDS
SFB
AGND
VREF
EP
1
N/A means not applicable.
Rev. B | Page 7 of 23
ADN8833
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
100
100
VIN = 3.3V
VIN = 5V
90
80
70
70
60
50
40
50
40
30
30
20
20
10
10
0
0.5
1.0
TEC CURRENT (A)
1.5
0
0
1.0
MAXIMUM TEC CURRENT (A)
1.4
80
70
60
50
40
30
1.2
1.0
0.8
0.6
0.4
20
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
0.2
10
0
0.5
1.0
1.5
TEC CURRENT (A)
0
2.7
12909-004
0
1.5
Figure 7. Efficiency vs. TEC Current at VIN = 3.3 V with Different Loads in
Heating Mode
VIN = 3.3V
VIN = 5V
90
0.5
TEC CURRENT (A)
Figure 4. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Cooling Mode
with 2 Ω Load
100
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE AT PVIN (V)
Figure 5. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Heating Mode
with 2 Ω Load
12909-107
0
EFFICIENCY (%)
60
12909-106
EFFICIENCY (%)
80
12909-003
EFFICIENCY (%)
90
Figure 8. Maximum TEC Current vs. Input Voltage at PVIN (VIN = 3.3 V),
Without Voltage and Current Limit in Cooling Mode
100
1.4
80
EFFCIENCY(%)
70
60
50
40
30
20
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
0
0
0.5
1.0
TEC CURRENT (A)
1.5
1.0
0.8
0.6
0.4
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
0.2
0
2.7
12909-105
10
1.2
3.0
3.5
4.0
4.5
INPUT VOLTAGE AT PVIN (V)
Figure 6. Efficiency vs. TEC Current at VIN = 3.3 V with Different Loads in
Cooling Mode
5.0
5.5
12909-108
MAXIMUM TEC CURRENT (A)
90
Figure 9. Maximum TEC Current vs. Input Voltage at PVIN (VIN = 3.3 V),
Without Voltage and Current Limit in Heating Mode
Rev. B | Page 8 of 23
Data Sheet
ADN8833
20
0.8
0.6
0.2
0
–0.2
–0.4
–0.6
–1.0
–50
0
50
100
AMBIENT TEMPERATURE (°C)
150
12909-111
–0.8
Figure 10. VREF Error vs. Ambient Temperature
–5
–10
–15
–1.0
–0.5
0
0
–0.05
–0.10
–0.15
0
1
2
3
4
5
6
7
8
9
10
LOAD CURRENT AT VREF (mA)
Figure 11. VREF Load Regulation
10
5
0
–5
–10
–15
VTEC VOLTAGE READING ERROR (%)
15
10
5
0
–5
–10
–15
1.5
15
2.0
2.5
VIN = 3.3V
VIN = 5V
10
5
0
–5
–10
–15
–20
–2.5
12909-010
TEC CURRENT (A)
1.5
Figure 14. VTEC Voltage Reading Error vs. TEC Voltage in Cooling Mode
20
1.0
1.0
TEC VOLTAGE (V)
VIN = 3.3V
VIN = 5V
0.5
VIN = 3.3V
VIN = 5V
–20
0.5
12909-101
–0.20
15
12909-011
VTEC VOLTAGE READING ERROR (%)
VREF (%)
0
Figure 13. ITEC Current Reading Error vs. TEC Current in Cooling Mode
0.05
ITEC CURRENT READING ERROR (%)
5
20
0.10
0
10
TEC CURRENT (A)
VIN = 3.3V, ITEC = 0A
VIN = 3.3V, ITEC = 0.5A, COOLING
VIN = 3.3V, ITEC = 0.5A, HEATING
VIN = 5V, ITEC = 0A
VIN = 5V, ITEC = 0.5A, COOLING
VIN = 5V, ITEC = 0.5A, HEATING
0.15
–20
VIN = 3.3V
VIN = 5V
–20
–1.5
0.20
20
15
–2.0
–1.5
TEC VOLTAGE (V)
Figure 12. ITEC Current Reading Error vs. TEC Current in Heating Mode
–1.0
–0.5
12909-014
VREF ERROR (%)
0.4
NO LOAD
NO LOAD
NO LOAD
5mA LOAD
5mA LOAD
5mA LOAD
ITEC CURRENT READING ERROR (%)
VIN = 2.7V AT
VIN = 3.3V AT
VIN = 5.5V AT
VIN = 2.7V AT
VIN = 3.3V AT
VIN = 5.5V AT
12909-013
1.0
Figure 15. VTEC Voltage Reading Error vs. TEC Voltage in Heating Mode
Rev. B | Page 9 of 23
ADN8833
Data Sheet
T
SW
EN
3
3
TEC CURRENT
4
LDO (TEC+)
LDO (TEC–)
1
PWM (TEC+)
PWM (TEC–)
CH1 1V
CH2 1V
CH4 500mA Ω
CH3 2V
M20.0ms
A CH3
T
40ms
800mV
Figure 16. Typical Enable Waveforms in Cooling Mode, VIN = 3.3 V,
Load = 2 Ω, TEC Current = 1 A
CH1 20mV BW CH2 20mV
CH3 2.0V BW
B
W
M400ns
T
0.0s
A CH3
1.00V
12909-102
1
12909-121
2
Figure 18. Typical Switch and Voltage Ripple Waveforms in Cooling Mode,
VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A
T
EN
SW
3
3
TEC CURRENT
4
LDO (TEC+)
1
PWM (TEC–)
PWM (TEC–)
2
CH3 2V
M20.0ms
A CH3
T
40ms
800mV
Figure 17. Enable Waveforms in Heating Mode, VIN = 3.3 V,
Load = 2 Ω, TEC Current = 1 A
CH1 20mV BW CH2 20mV
CH3 2.0V BW
B
W M400ns
T
0.0s
A CH3
1.00V
12909-103
CH1 1V
CH2 1V
CH4 500mA Ω
12909-122
LDO (TEC+)
2
Figure 19. Typical Switch and Voltage Ripple Waveforms in Heating Mode,
VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A
Rev. B | Page 10 of 23
Data Sheet
ADN8833
LDO (TEC+)
PWM (TEC–)
TEC CURRENT
TEC CURRENT
4
4
PWM (TEC–)
LDO (TEC+)
1
CH2 500mV
M200ms
A CH4
T
–28.000ms
–108mA
CH1 500mV
CH4 200mA Ω
Figure 20. Cooling to Heating Transition
TEC CURRENT
PWM (TEC–)
LDO (TEC+)
M10ms
A CH4
T
5.4ms
–8mA
12909-119
1
CH2 500mV
M10ms
A CH4
T
5.4ms
12mA
Figure 22. Zero Crossing TEC Current Zoom in from Cooling to Heating
4
CH1 500mV
CH3 300mA Ω
CH2 500mV
12909-120
CH1 500mV
CH4 200mA Ω
12909-118
1
Figure 21. Zero Crossing TEC Current Zoom in from Heating to Cooling
Rev. B | Page 11 of 23
ADN8833
Data Sheet
DETAILED FUNCTIONAL BLOCK DIAGRAM
VTEC
ITEC
ADN8833
VDD
VREF
TEC DRIVER
LINEAR POWER
STAGE
COOLING
VDD
5kΩ
2.5V
BAND GAP
VOLTAGE
REFERENCE
HEATING
20kΩ
5kΩ
1.25V
20kΩ
1.25V
PVIN
1.25V
TEC CURRENT SENSE
20kΩ
–
+
LDR
VB = 2.5V AT VDD > 4.0V
VB = 1.5V AT VDD < 4.0V
VB
SFB
TEC
VOLTAGE
SENSE
VC
AGND
2kΩ
80kΩ
LDR
+
–
VB
LINEAR
AMPLIFIER
PGNDL
VB
PGNDL
80kΩ
1.25V
20kΩ
20kΩ
400kΩ
SFB
PWM POWER
STAGE
100kΩ
VC
20kΩ
CONT
PWM
MODULATOR
20kΩ
20kΩ
40µA
VB
COOLING
HEATING
OSCILLATOR
SW
CLK
PGNDS
SHUTDOWN
10µA
VHIGH ≥ 2.1V
VLOW ≤ 0.8V
ITEC
TEC
CURRENT
LIMIT
0.07V
VLIM/SD
DEGLITCH
SHUTDOWN
ILIM
Figure 23. Detailed Functional Block Diagram of the ADN8833 in the WLCSP
Rev. B | Page 12 of 23
PGNDS
EN/SY
12909-016
CLK
PWM
MOSFET
DRIVER
PWM
ERROR
AMPLIFIER
VDD
TEC VOLTAGE
LIMIT AND INTERNAL
SOFT START
PVIN
Data Sheet
ADN8833
THEORY OF OPERATION
The ADN8833 is a single chip TEC driver that sets and
stabilizes a TEC temperature. A control voltage from a DAC
applied to the CONT input of the ADN8833 corresponds to the
temperature setpoint of the target object attached to the TEC. The
ADN8833 controls an internal FET H-bridge whereby the
direction of the current fed through the TEC can be either
positive (for cooling mode) to pump heat away from the object
attached to the TEC, or negative (for heating mode), to pump heat
into the object attached to the TEC.
For additional details, see the Maximum TEC Voltage Limit
section and the Maximum TEC Current Limit section.
The objective temperature is measured with a thermal sensor
attached to the TEC and the sensed temperature (voltage) is fed
back to an ADC to close digital thermal control loop of the TEC.
For the best overall stability, couple the thermal sensor close to the
TEC. In most laser diode modules, a TEC and a NTC thermistor
are already mounted in the same package to regulate the laser
diode temperature.
POWERING THE DRIVER
The TEC is differentially driven in an H-bridge configuration. The
ADN8833 drives its internal MOSFET transistors to provide the
TEC current. To further improve the power efficiency of the
system, only one side of the H-bridge uses a PWM driver. Only one
inductor and one capacitor are required to filter out the switching
frequency. The other side of the H-bridge uses a linear output
without requiring any additional circuitry. This proprietary configuration allows the ADN8833 to provide efficiency of >90%. For
most applications, a 1 μH inductor, a 10 μF capacitor, and a
switching frequency of 2 MHz maintain less than 1% of the worstcase output voltage ripple across a TEC.
The maximum voltage across the TEC and the current flowing
through the TEC are set by using the VLIM/SD and ILIM pins.
The maximum cooling and heating currents can be set
independently to allow asymmetric heating and cooling limits.
The ADN8833 is used in a software controlled PID loop. An
amplifier conditions the signal from the thermistor and connects
to an external temperature measurement ADC.
The signal from an external DAC that controls the temperature
setpoint is applied to the CONT input pin.
The ADN8833 operates at an input voltage range of 2.7 V to
5.5 V that is applied to the VDD pin and the PVIN pin for the
WLCSP (or the PVINS pin and PVINL pin for the LFCSP). The
VDD pin is the input power for the driver and internal reference.
The PVIN input power pins are combined for both the linear
and the switching driver. Apply the same input voltage to all
power input pins: VDD and PVIN. In some circumstances, an RC
low-pass filter can be optionally added between the PVIN for
the WLCSP (PVINS and PVINL for the LFCSP) and VDD pins
to prevent high frequency noise from entering VDD, as shown
in Figure 24. The capacitor and resistor values are typically 10 Ω
and 100 nF, respectively.
When configuring power supply to the ADN8833, keep in mind
that at high current loads, the input voltage may drop
substantially due to a voltage drop on the wires between the
front-end power supply and the PVIN for the WLCSP (PVINS
and PVINL for the LFCSP) pin. Leave a proper voltage margin
when designing the front-end power supply to maintain the
performance. Minimize the trace length from the power supply
to the PVIN for the WLVSP (PVINS and PVINL for the LFCSP)
pin to help mitigate the voltage drop.
COOLING AND HEATING
TEC CURRENT LIMITS
EN
2.5V VREF
TEC
VOLTAGE
LIMIT
RC1
EN/SY
CVDD
0.1µF
VDD
RBP
VIN
2.7V TO 5.5V
R
PVIN
CIN
10µF
LDR
CL_OUT
0.1µF
ADC
CONT
TEC CURRENT READBACK
TEC VOLTAGE READBACK
RX
ITEC
VTEC
ADN8833
TEC
+
NTC
RTH
PGNDL
VREF
–
AGND
SFB
TEMPERATURE
READBACK
THERMISTER
L = 1µH
PGNDS
SW
FSW = 2MHz
CSW_OUT
10µF
12909-017
CVREF
0.1µF
ILIM
VLIM/SD
TEC DRIVER CONTROL
2.5V VREF
2.5V VREF
RC2
RV1
RV2
2.5V VREF
DAC
DIGITAL PID CONTROL
Figure 24. TEC Driver in a Digital Temperature Control Loop (WLCSP)
Rev. B | Page 13 of 23
ADN8833
Data Sheet
ENABLE AND SHUTDOWN
To enable the ADN8833, apply a logic high voltage to the EN/SY
pin while the voltage at the VLIM/SD pin is above the maximum
shutdown threshold of 0.07 V. If either the EN/SY pin voltage is
set to logic low or the VLIM/SD voltage is below 0.07 V, the driver
goes into an ultralow current state. The current drawn in
shutdown mode is 350 µA typically. Most of the current is
consumed by the VREF circuit block, which is always on even
when the device is disabled or shut down. The device can also
be enabled when an external synchronization clock signal is
applied to the EN/SY pin and the voltage at VLIM/SD input is
above 0.07 V. Table 6 shows the combinations of the two input
signals that are required to enable the ADN8833.
from each other by placing an inverter at one of the EN/SY pins,
as shown in Figure 26.
ADN8833
EXTERNAL CLOCK
SOURCE
EN/SY
AGND
ADN8833
Table 6. Enable Pin Combinations
1
Driver
Enabled
Enabled
No effect1
No effect1
≤0.07 V
Shutdown
Shutdown
Shutdown
EN/SY
AGND
12909-020
VLIM/SD Input
>0.07 V
>0.07 V
Figure 26. Multiple ADN8833 Devices Driven from a Master Clock
SOFT START ON POWER-UP
No effect means this signal has no effect in shutting down or in enabling the
device.
OSCILLATOR CLOCK FREQUENCY
The ADN8833 has an internal oscillator that generates a 2.0 MHz
switching frequency for the PWM output stage. This oscillator is
active when the enabled voltage at the EN/SY pin is set to a logic
level higher than 2.1 V and the VLIM/SD pin voltage is greater than
the shutdown threshold of 0.07 V.
External Clock Operation
The PWM switching frequency of the ADN8833 can be
synchronized to an external clock from 1.85 MHz to 3.25 MHz
applied to the EN/SY input pin as shown on Figure 25.
ADN8833
EXTERNAL CLOCK
SOURCE
EN/SY
12909-019
AGND
The ADN8833 has an internal soft start circuit that generates a
ramp with a typical 150 ms profile to minimize inrush current
during power-up. The settling time and the final voltage across
the TEC depends on the TEC voltage required by the control
voltage of voltage loop. The higher the TEC voltage is, the
longer it requires to be built up.
When the ADN8833 is first powered up, the linear side discharges
the output of any prebias voltage. As soon as the prebias is eliminated, the soft start cycle begins. During the soft start cycle, both the
PWM and linear outputs track the internal soft start ramp until
they reach midscale, where the control voltage, VC, is equal to the
bias voltage, VB. From the midscale voltage, the PWM and linear
outputs are then controlled by VC and diverge from each other
until the required differential voltage is developed across the TEC
or the differential voltage reaches the voltage limit. The voltage
developed across the TEC depends on the control point at that
moment in time. Figure 27 shows an example of the soft start in
cooling mode. Note that, as both the LDR and SFB voltages increase with the soft start ramp and approach VB, the ramp slows
down to avoid possible current overshoot at the point where the
TEC voltage starts to build up.
LDR
Figure 25. Synchronize to an External Clock
REACH
VOLTAGE LIMIT
Connecting Multiple ADN8833 Devices
Multiple ADN8833 devices can be driven from a single master
clock signal by connecting the external clock source to the
EN/SY pin of each slave device. The input ripple can be greatly
reduced by operating the ADN8833 devices 180° out of phase
TEC VOLTAGE
BUILDS UP
SFB
VB
DISCHARGE
PREBIAS
SOFT-START
BEGINS
TIME
Figure 27. Soft Start Profile in Cooling Mode
Rev. B | Page 14 of 23
12909-021
EN/SY Input
>2.1 V
Switching between high
>2.1 V and low < 0.8 V
4.0 V
TLOW and THIGH are the endpoints of the temperature range and
TMID is the average. In some cases, with only the β constant
available, calculate RTH using the following equation:
1 1
RTH = RR expβ −
T TR
The compensation network that receives the temperature set
voltage and the thermistor voltage fed by the input amplifier
determines the voltage at CONT. VLDR and VSFB have a low limit of
0 V and an upper limit of VVDD. Figure 31, Figure 32, and Figure
33 show the graphs of these equations.
where:
RTH is a resistance at T (K).
RR is a resistance at TR (K).
Calculate RX using the following equation:
R
R
+ R MID R HIGH − 2R LOW R HIGH
R X = LOW MID
R
LOW + R HIGH − 2 R MID
Rev. B | Page 16 of 23
Data Sheet
ADN8833
7.5
Inductor Selection
VSYS = 5.0V
VSYS = 3.3V
The inductor selection determines the inductor current ripple
and loop dynamic response. Larger inductance results in smaller
current ripple and slower transient response as smaller inductance
results in the opposite performance. To optimize the performance, a trade-off must be made between transient response
speed, efficiency, and component size. Calculate the inductor
value with the following equation:
LDR (V)
5.0
2.5
0
–2.5
0
0.25
0.75
1.25
1.75
2.25
2.75
CONT (V)
12909-024
L=
Figure 31. LDR Voltage vs. CONT Voltage
7.5
VSYS = 5.0V
VSYS = 3.3V
SFB (V)
2.5
–2.5
0.75
1.25
1.75
2.25
2.75
CONT (V)
12909-025
0
0.25
Figure 32. SFB Voltage vs. CONT Voltage
+5.0
VSYS = 5.0V
VSYS = 3.3V
+2.5
VTEC (V)
LDR – SFB
where:
VSW_OUT is the PWM amplifier output.
fSW is the switching frequency (2 MHz by default).
∆IL is the inductor current ripple.
A 1 µH inductor is typically recommended to allow reasonable
output capacitor selection while maintaining a low inductor
current ripple. If lower inductance is required, a minimum inductor
value of 0.68 µH is suggested to ensure that the current ripple is set
to a value between 30% and 40% of the maximum load current,
which is 1.5 A.
5.0
0
VSW _ OUT × (VIN – VSW _ OUT )
VIN × f SW × ∆I L
Except for the inductor value, the equivalent dc resistance (DCR)
inherent in the metal conductor is also a critical factor for inductor
selection. The DCR accounts for most of the power loss on the
inductor by DCR× IOUT2. Using an inductor with high DCR
degrades the overall efficiency significantly. In addition, there is
a conduct voltage drop across the inductor because of the DCR.
When the PWM amplifier is sinking current in cooling mode, this
voltage drives the minimum voltage of the amplifier higher than
0.06 × VIN by at least tenth of millivolts. Similarly, the maximum
PWM amplifier output voltage is lower than 0.93 × VIN. This
voltage drop is proportional to the value of DCR and it reduces
the output voltage range at the TEC.
When selecting an inductor, ensure that the saturation current
rating is higher than the maximum current peak to prevent
saturation. In general, ceramic multilayer inductors are suitable for
low current applications due to small size and low DCR. When the
noise level is critical, a shielded ferrite inductor may be used to
reduce the electromagnetic interference (EMI).
0
–5.0
0
0.25
0.75
1.25
1.75
2.25
CONT (V)
2.75
12909-026
–2.5
Figure 33. TEC Voltage vs. CONT Voltage
Table 7. Recommended Inductors
Vendor
Toko
PWM OUTPUT FILTER REQUIREMENTS
A type three compensator internally compensates the PWM
amplifier. As the poles and zeros of the compensator are designed
by assuming the resonance frequency of the output LC tank
being 50 kHz, the selection of the inductor and the capacitor
must follow this guideline to ensure system stability.
Taiyo
Yuden
Murata
Rev. B | Page 17 of 23
Value
1.0 µH ± 20%,
2.7 A (typical)
1.0 µH ± 20%,
2.2 A (typical)
1.0 µH ± 20%,
2.3 A (typical)
Device No.
DFE201612P-H-1R0M
Footprint
(mm)
2.0 × 1.6
MAKK2016T1R0M
2.0 × 1.6
LQM2MPN1R0MGH
2.0 × 1.6
ADN8833
Data Sheet
Capacitor Selection
PWM Regulator Power Dissipation
The output capacitor selection determines the output voltage
ripple, transient response, as well as the loop dynamic response
of the PWM amplifier output. Use the following equation to
select the capacitor:
The PWM power stage is configured as a buck regulator and
its dominant power dissipation (PPWM) includes power switch
conduction losses (PCOND), switching losses (PSW), and transition
losses (PTRAN). Other sources of power dissipation are usually
less significant at the high output currents of the application
thermal limit and can be neglected in approximation.
C=
VSW _ OUT × (VIN – VSW _ OUT )
VIN × 8 × L × ( f SW )2 × ∆VOUT
Note that the voltage caused by the product of current ripple, ΔIL,
and the capacitor equivalent series resistance (ESR) also add up
to the total output voltage ripple. Selecting a capacitor with low
ESR can increase overall regulation and efficiency performance.
Table 8. Recommended Capacitors
Vendor
Murata
Murata
Taiyo
Yuden
Value
10 µF ±
10%, 10 V
10 µF ±
20%, 10 V
10 µF ±
20%, 10 V
Device No.
ZRB18AD71A106KE01L
Footprint
(mm)
1.6 × 0.8
GRM188D71A106MA73
1.6 × 0.8
LMK107BC6106MA-T
1.6 × 0.8
INPUT CAPACITOR SELECTION
On the PVIN pin, the amplifiers require an input capacitor to
decouple the noise and to provide the transient current to maintain
stable input and output voltage. A 10 µF ceramic capacitor rated
at 10 V is the minimum recommended value. Increasing the
capacitance reduces the switching ripple that couples into the
power supply but increases the capacitor size. Because the current
at the input terminal of the PWM amplifier is discontinuous, a
capacitor with low effective series inductance (ESL) is preferred
to reduce voltage spikes.
In most applications, a decoupling capacitor is used in parallel
with the input capacitor. The decoupling capacitor is usually a
100 nF ceramic capacitor with very low ESR and ESL, which
provides better noise rejection at high frequency bands.
An RC low-pass filter can be optionally added between the PVIN
and VDD pins to prevent high frequency noise from entering
VDD, as shown in Figure 30. The capacitor and resistor values
are typically 10 Ω and 100 nF, respectively.
POWER DISSIPATION
This section provides guidelines to calculate the power
dissipation of ADN8833. Approximate the total power
dissipation in the device by
PLOSS = PPWM + PLINEAR
where:
PLOSS is the total power dissipation in the ADN8833.
PLINEAR is the power dissipation in the linear regulator.
Estimate the power dissipation of the buck regulator by
PLOSS = PCOND + PSW + PTRAN
Conduction Loss (PCOND)
The conduction loss consists of two parts: inductor conduction
loss (PCOND_L) and power switch conduction loss(PCOND_S).
PCOND = PCOND_L + PCOND_S
Inductor conduction loss is proportional to the DCR of the
output inductor, L. Using an inductor with low DCR enhances
the overall efficiency performance. Use the following equation
to estimate the inductor conduction loss:
PCOND_L = DCR× IOUT2
Power switch conduction losses are caused by the flow of the
output current through both the high-side and low-side power
switches, each of which has its own internal on resistance (RDSON).
Use the following equation to estimate the amount of power
switch conduction loss:
PCOND_S = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT2
where:
RDSON_HS is the on resistance of the high-side MOSFET.
D is the duty cycle (D = VOUT/VIN).
RDSON_LS is the on resistance of the low-side MOSFET.
Switching Loss (PSW)
Switching losses are associated with the current drawn by the
driver to turn the power devices on and off at the switching
frequency. Each time a power device gate is turned on or off,
the driver transfers a charge from the input supply to the gate,
and then from the gate to ground. Use the following equation
to estimate the switching loss:
PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW
where:
CGATE_HS is the gate capacitance of the high-side MOSFET.
CGATE_LS is the gate capacitance of the low-side MOSFET.
fSW is the switching frequency.
For the ADN8833, the total of (CGATE_HS + CGATE_LS) is
approximately 1 nF.
Rev. B | Page 18 of 23
Data Sheet
ADN8833
Transition Loss (PTRAN)
Linear Regulator Power Dissipation
Transition losses occur because the high-side MOSFET cannot
turn on or off instantaneously. During a switch node transition,
the MOSFET provides all the inductor current. The source-todrain voltage of the MOSFET is half the input voltage, resulting
in power loss. Transition losses increase with both load and input
voltage and occur twice for each switching cycle. Use the following
equation to estimate the transition loss:
The power dissipation of the linear regulator is given by the
following equation:
PTRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW
where:
tR is the rise time of the switch node.
tF is the fall time of the switch node.
PLINEAR = [(VIN − VOUT) × IOUT] + (VIN × IGND)
where:
VIN and VOUT are the input and output voltages of the linear
regulator.
IOUT is the load current of the linear regulator.
IGND is the ground current of the linear regulator.
Power dissipation due to the ground current is generally small
and can be ignored for the purposes of this calculation.
For the ADN8833, tR and tF are both approximately 1 ns.
Rev. B | Page 19 of 23
ADN8833
Data Sheet
PCB LAYOUT GUIDELINES
SOURCE OF
ELECTRICAL
POWER
TEMPERATURE
ERROR
COMPENSATION
TEC
DRIVER
TEMPERATURE
SIGNAL
CONDITIONING
TEC
CURRENT
LIMITING
TEC
VOLTAGE
SENSING
OBJECT
THERMOELECTRIC
COOLER
TEMPERATURE
(TEC)
SENSOR
TEC
CURRENT
SENSING
12909-035
TARGET
TEMPERATURE
TEC
VOLTAGE
LIMITING
Figure 34. System Block Diagram
BLOCK DIAGRAMS AND SIGNAL FLOW
The ADN8833 integrates analog signal conditioning blocks, a
load protection block, and a TEC driver power stage all in a single
IC. To achieve the best possible circuit performance, attention
must be paid to keep noise of the power stage from contaminating
the sensitive analog conditioning and protection circuits. In
addition, the layout of the power stage must be performed such
that the IR losses are minimized to obtain the best possible
electrical efficiency. The system block diagram of the ADN8833 is
shown in Figure 34.
GUIDELINES FOR REDUCING NOISE AND
MINIMIZING POWER LOSS
Each printed circuit board (PCB) layout is unique because of the
physical constraints defined by the mechanical aspects of a given
design. In addition, several other circuits work in conjunction
with the TEC driver; these circuits have their own layout requirements, so there are always compromises that must be made for a
given system. However, to minimize noise and keep power losses
to a minimum during the PCB layout process, observe the
following guidelines.
General PCB Layout Guidelines
Switching noise can interfere with other signals in the system;
therefore, the switching signal traces must be placed away from
the power stage to minimize the effect. If possible, place the
ground plate between the small signal layer and power stage layer
as a shield.
Supply voltage drop on traces is also an important consideration
because it determines the voltage headroom of the TEC driver at
high currents. For example, if the supply voltage from the frontend system is 3.3 V, and the voltage drop on the traces is 0.5 V,
PVIN sees only 2.8 V, which limits the maximum voltage of the
linear regulator as well as the maximum voltage across the TEC.
To mitigate the voltage waste on traces and impedance
interconnection, place the ADN8833 and the input decoupling
components close to the supply voltage terminal. This placement
not only improves the system efficiency, but also provides better
regulation performance at the output.
To prevent noise signal from circulating through ground plates,
reference all of the sensitive analog signals to AGND and connect
AGND to PGNDS using only a single point connection. This
ensures that the switching currents of the power stage do not flow
into the sensitive AGND node.
PWM Power Stage Layout Guidelines
The PWM power stage consists of a MOSFET pair that forms a
switch mode output that switches current from PVIN to the load
via an LC filter. The ripple voltage on the PVIN pin is caused by
the discontinuous current switched by the PWM side MOSFETs.
This rapid switching causes voltage ripple to form at the PVIN
input, which must be filtered using a bypass capacitor. Place a 10 µF
capacitor as close as possible to the PVIN pin to connect PVIN to
PGNDS. Because the 10 µF capacitor is sometimes bulky and has
higher ESR and ESL, a 100 nF decoupling capacitor is usually
used in parallel with it, placed between PVIN and PGNDS.
Because the decoupling is part of the pulsating current loop, which
carries high di/dt signals, the traces must be short and wide to
minimize the parasitic inductance. As a result, this capacitor is
usually placed on the same side of the board as the ADN8833 to
ensure short connections. If the layout requires that 10 µF capacitor be on the opposite side of the PCB, use multiple vias to reduce
via impedance.
The layout around the SW node is also critical because it switches
between PVIN and ground rapidly, which makes this node a
strong EMI source. Keep the copper area that connects the SW
node to the inductor small to minimize parasitic capacitance
between the SW node and other signal traces. This helps
minimize noise on the SW node due to excessive charge injection.
However, in high current applications, the copper area may be
increased reasonably to provide heat sink and to sustain high
current flow.
Connect the ground side of the capacitor in the LC filter as close
as possible to PGNDS to minimize the ESL in the return path.
Rev. B | Page 20 of 23
Data Sheet
ADN8833
Linear Power Stage Layout Guidelines
Place a 100 nF capacitor that connects from PVIN to PGNDL as
close as possible to the PVIN pin.
The linear power stage consists of a MOSFET pair that forms a
linear amplifier, which operates in linear mode for very low
output currents, and changes to fully enhanced mode for
greater output currents.
EXAMPLE PCB LAYOUT USING TWO LAYERS
Figure 35, Figure 36, and Figure 37 show an example ADN8833
WLCSP PCB layout that uses two layers. This layout example
achieves a small solution size of approximately 18 mm2 with all
of the conditioning circuitry and PID included. Using more layers
and blind vias allows the solution size to be reduced even further
because more of the discrete components can relocate to the
bottom side of the PCB.
Because the linear power stage does not switch currents rapidly
like the PWM power stage, it does not generate noise currents.
However, the linear power stage still requires a minimum amount
of bypass capacitance to decouple its input.
UNITS = (mm)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
PGND
CONNECT TO GROUND PLANE
0.5
ITEC
TEC+
1.0
PGNDL
NC
NC
NC
TEMPSET
0201
0201
20
CL_OUT
0201
PGNDL
LDR
L
R
LDR
NC
VLIM
LIM /
SD
NC
R V1
CIN_L
TEC–
1.5
PVIN
0201
PVIN
VIN
R V2
ILIM
LIM
CO
ONT
ONT
CONT
ITEC
TEC
EC
AGND
0201
PGNDS
PGNDS
RBP
BP
V
R
RE
EF
E
VREF
AGND
GN
SFB
R C2
0201
0201
02
20
CVDD
0201
02
20
2
201
01
0402
04
402
40
0201
0201
20
CIN_S
PGNDS
PGNDS
0201
VD
VDD
DD
EN
N/SY
EN/SY
VTE
V
VTEC
E
R BP
3.0
CVREF
0201
CSW_OUT
CONNECT AGND TO
PGNDS ONLY AT A
SINGLE POINT
AS A STAR
CONNECTION
0402
CONNECT TO GROUND PLANE
12909-036
UNITS = (mm)
2.5
R C1
SW
SW
CVDD
L
2.0
0805
VTEC
CBULK
BU
ULK
VIN
3.5
Figure 35. Example PCB Layout Using Two Layers (Top and Bottom Layers)
Rev. B | Page 21 of 23
ADN8833
Data Sheet
UNITS = (mm)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
PGND
CONNECT TO GROUND PLANE
0.5
PGNDL
NC
NC
NC
CL_OUT
0201
ITEC
TEC+
PGNDL
1.0
TEMPSET
LDR
LDR
NC
VL M/
VLIM
SD
NC
RV1
CIN_L
TEC-
1.5
0201
PV N
PVIN
PV N
PVIN
C
ITEC
CO
ONT
O
NT
CONT
RV2
ILIM
LIM
AGND
0201
VIN
RC1
2.0
UNITS = (mm)
L
SW
SW
0805
VTEC
VTEC
C
EN
N/SY
Y
0201
VDD
VD
DD
CIN_S
RC2
CVDD
0201
2.5
PGNDS
PGNDS
SFB
SF
AGND
AGN
AG
GND
D
VREF
VREF
VRE
RBP
3.0
CVREF
0201
CSW_OUT
0402
12909-037
CONNECT TO GROUND PLANE
3.5
Figure 36. Example PCB Layout Using Two Layers (Top Layer Only)
UNITS = (mm)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
PGND
CONNECT TO GROUND PLANE
1.0
TEMPSET
0201
TEC+
0201
ITEC
CL_OUT
0.5
TEC–
C IN_L
1.5
AGND
RB
BP
R BP
3.0
CONNECT TO GROUND PLANE
3.5
Figure 37. Example PCB Layout Using Two Layers (Bottom Layer Only)
Rev. B | Page 22 of 23
12909-038
UNITS = (mm)
2.5
0201
C VDD
0201
201
C IN_S
C VDD
0201
0402
0
2.0
VTEC
C BULK
U
VIN
Data Sheet
ADN8833
OUTLINE DIMENSIONS
2.58
2.54 SQ
2.50
5
BOTTOM VIEW
(BALL SIDE UP)
2
3
4
1
A
BALL A1
IDENTIFIER
2.00
REF
B
C
0.50
BSC
D
E
TOP VIEW
(BALL SIDE DOWN)
0.660
0.600
0.540
0.390
0.360
0.330
END VIEW
COPLANARITY
0.05
PKG-003121
0.360
0.320
0.280
0.270
0.240
0.210
06-07-2013-A
SEATING
PLANE
Figure 38. 25-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-25-7)
Dimensions shown in millimeters
PIN 1
INDICATOR
0.30
0.25
0.18
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
TOP VIEW
0.80
0.75
0.70
PKG-004273
Model 1
ADN8833ACBZ-R7
ADN8833CB-EVALZ
ADN8833ACPZ-R2
ADN8833ACPZ-R7
ADN8833CP-EVALZ
1
2
7
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
Figure 39. 24-Lead Lead-frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-15)
Dimensions shown in millimeters
Temperature Range2
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
6
12
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
ORDERING GUIDE
0.50
0.40
0.30
PIN 1
INDICATOR
24
19
18
12-03-2013-A
4.10
4.00 SQ
3.90
Package Description
25-Ball Wafer Level Chip Scale Package [WLCSP]
25-Ball WLCSP Evaluation Board: ±1 A TEC Current Limit, 3 V TEC Voltage Limit
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead LFCSP Evaluation Board: ±1 A TEC Current Limit, 3 V TEC Voltage Limit
Z = RoHS Compliant Part.
Operating junction temperature range. The ambient operating temperature range is −40°C to +85°C.
©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12909-0-8/18(B)
Rev. B | Page 23 of 23
Package
Option
CB-25-7
CP-24-15
CP-24-15
工商网监
湘ICP备2023018690号
