FEATURES
FUNCTIONAL BLOCK DIAGRAM
Patented high efficiency single inductor architecture
Integrated low RDSON MOSFETs for the TEC controller
TEC voltage and current operation monitoring
No external sense resistor required
Independent TEC heating and cooling current limit settings
Programmable maximum TEC voltage
2.0 MHz PWM driver switching frequency
External synchronization
Two integrated, zero drift, rail-to-rail chopper amplifiers
Capable of NTC or RTD thermal sensors
2.50 V reference output with 1% accuracy
Temperature lock indicator
Available in a 25-ball, 2.5 mm × 2.5 mm WLCSP or in a
24-lead, 4 mm × 4 mm LFCSP
VDD
VLIM/
SD ILIM VTEC ITEC
ERROR
AMP
IN1P
TEC DRIVER
TEC CURRENT
AND VOLTAGE
SENSE AND LIMIT
IN1N
PVIN
LINEAR
POWER
STAGE
OUT1
COMP
AMP
IN2P
CONTROLLER
SW
IN2N
PWM
POWER
STAGE
OUT2
VOLTAGE
REFERENCE
AGND
SFB
OSCILLATOR
APPLICATIONS
TEC temperature control
Optical modules
Optical fiber amplifiers
Optical networking systems
Instruments requiring TEC temperature control
LDR
VREF
EN/SY
PGNDx
12954-001
Data Sheet
Ultracompact, 1.5 A Thermoelectric Cooler
(TEC) Controller
ADN8834
Figure 1.
GENERAL DESCRIPTION
The ADN88341 is a monolithic TEC controller with an integrated
TEC controller. It has a linear power stage, a pulse-width
modulation (PWM) power stage, and two zero-drift, rail-to-rail
operational amplifiers. The linear controller works with the PWM
driver to control the internal power MOSFETs in an H-bridge
configuration. By measuring the thermal sensor feedback
voltage and using the integrated operational amplifiers as a
proportional integral differential (PID) compensator to condition
the signal, the ADN8834 drives current through a TEC to settle
the temperature of a laser diode or a passive component attached
to the TEC module to the programmed target temperature.
The ADN8834 supports negative temperature coefficient (NTC)
thermistors as well as positive temperature coefficient (PTC)
resistive temperature detectors (RTD). The target temperature is
set as an analog voltage input either from a digital-to-analog
converter (DAC) or from an external resistor divider.
1
The temperature control loop of the ADN8834 is stabilized by
PID compensation utilizing the built in, zero drift chopper
amplifiers. The internal 2.50 V reference voltage provides a 1%
accurate output that is used to bias a thermistor temperature
sensing bridge as well as a voltage divider network to program
the maximum TEC current and voltage limits for both the heating
and cooling modes. With the zero drift chopper amplifiers,
extremely good long-term temperature stability is maintained via
an autonomous analog temperature control loop.
Table 1. TEC Family Models
Device No.
ADN8831
ADN8833
MOSFET
Discrete
Integrated
Thermal Loop
Digital/analog
Digital
ADN8834
Integrated
Digital/analog
Package
LFCSP (CP-32-7)
WLCSP (CB-25-7),
LFCSP (CP-24-15)
WLCSP (CB-25-7),
LFCSP (CP-24-15)
Product is covered by U.S. Patent No. 6,486,643.
Rev. B
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ADN8834
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
TEC Voltage/Current Monitor ................................................. 16
Applications ....................................................................................... 1
Maximum TEC Voltage Limit .................................................. 16
Functional Block Diagram .............................................................. 1
Maximum TEC Current Limit ................................................. 17
General Description ......................................................................... 1
Applications Information .............................................................. 18
Revision History ............................................................................... 2
Signal Flow .................................................................................. 18
Specifications..................................................................................... 3
Thermistor Setup........................................................................ 18
Absolute Maximum Ratings ............................................................ 6
Thermistor Amplifier (Chopper 1).......................................... 19
Thermal Resistance ...................................................................... 6
PID Compensation Amplifier (Chopper 2)............................ 19
ESD Caution .................................................................................. 6
MOSFET Driver Amplifiers...................................................... 20
Pin Configurations and Function Descriptions ........................... 7
PWM Output Filter Requirements .......................................... 20
Typical Performance Characteristics ............................................. 8
Input Capacitor Selection .......................................................... 21
Detailed Functional Block Diagram ............................................ 12
Power Dissipation....................................................................... 21
Theory of Operation ...................................................................... 13
PCB Layout Guidelines .................................................................. 23
Analog PID Control ................................................................... 14
Block Diagrams and Signal Flow ............................................. 23
Digital PID Control .................................................................... 14
Guidelines for Reducing Noise and Minimizing Power Loss .... 23
Powering the Controller ............................................................ 14
Example PCB Layout Using Two Layers ................................. 24
Enable and Shutdown ................................................................ 15
Outline Dimensions ....................................................................... 27
Oscillator Clock Frequency ....................................................... 15
Ordering Guide .......................................................................... 27
Temperature Lock Indicator (LFCSP Only) ........................... 15
Soft Start on Power-Up .............................................................. 15
REVISION HISTORY
9/18—Rev. A to Rev. B
Added Patent Information............................................................... 1
8/15—Rev. 0 to Rev. A
Added 24-Lead LFCSP....................................................... Universal
Changes to Features Section and Table 1 ...................................... 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 6
Added Figure 3; Renumbered Sequentially .................................. 7
Changes to Figure 13 ........................................................................ 9
Changes to Figure 23 and Figure 24............................................. 11
Changes to Figure 25 ...................................................................... 12
Changes to Powering the Controller Section and Figure 27
Caption ............................................................................................ 14
Change to Soft Start on Power-Up Section ................................. 15
Change to Figure 33 ....................................................................... 18
Changes to Table 7.......................................................................... 21
Added Table 8; Renumbered Sequentially .................................. 21
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
4/15—Revision 0: Initial Version
Rev. B | Page 2 of 27
Data Sheet
ADN8834
SPECIFICATIONS
VIN = 2.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless
otherwise noted.
Table 2.
Parameter
POWER SUPPLY
Driver Supply Voltage
Controller Supply Voltage
Supply Current
Shutdown Current
Undervoltage Lockout (UVLO)
UVLO Hysteresis
REFERENCE VOLTAGE
LINEAR OUTPUT
Output Voltage
Low
High
Maximum Source Current
Symbol
VPVIN
VVDD
IVDD
ISD
VUVLO
UVLOHYST
VVREF
PWM not switching
EN/SY = AGND or VLIM/SD = AGND
VVDD rising
VLDR
ILDR = 0 A
ILDR_SOURCE
ILDR_SINK
On Resistance
P-MOSFET
RDS_PL(ON)
N-MOSFET
RDS_NL(ON)
Hiccup Cycle
PWM OUTPUT
Output Voltage
Low
High
Maximum Source Current
Min
Typ
Max
Unit
3.3
350
2.55
90
2.50
5.5
5.5
5
700
2.65
100
2.525
V
V
mA
µA
V
mV
V
1.5
1.2
V
V
A
A
A
A
35
44
50
55
31
40
45
50
50
60
65
75
50
55
70
80
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
0.1
0.1
40
2.2
−2.2
15
10
10
µA
µA
V/V
A
A
ms
2.7
2.7
IVREF = 0 mA to 10 mA
2.45
80
2.475
0
VPVIN
Maximum Sink Current
Leakage Current
P-MOSFET
N-MOSFET
Linear Amplifier Gain
LDR Short-Circuit Threshold
Test Conditions/Comments
ILDR_P_LKG
ILDR_N_LKG
ALDR
ILDR_SH_GNDL
ILDR_SH_PVIN(L)
THICCUP
VSFB
TJ = −40°C to +105°C
TJ = −40°C to +125°C
TJ = −40°C to +105°C
TJ = −40°C to +125°C
ILDR = 0.6 A
WLCSP, VPVIN = 5.0 V
WLCSP, VPVIN = 3.3 V
LFCSP, VPVIN = 5.0 V
LFCSP, VPVIN = 3.3 V
WLCSP, VPVIN = 5.0 V
WLCSP, VPVIN = 3.3 V
LFCSP, VPVIN = 5.0 V
LFCSP, VPVIN = 3.3 V
1.5
1.2
LDR short to PGNDL, enter hiccup
LDR short to PVIN, enter hiccup
ISFB = 0 A
1.5
1.2
V
V
V
A
A
A
A
65
80
80
95
mΩ
mΩ
mΩ
mΩ
0.06 × VPVIN
0.93 × VPVIN
ISW_SOURCE
Maximum Sink Current
ISW_SINK
On Resistance
P-MOSFET
RDS_PS(ON)
TJ = −40°C to +105°C
TJ = −40°C to +125°C
TJ = −40°C to +105°C
TJ = −40°C to +125°C
ISW = 0.6 A
WLCSP, VPVIN = 5.0 V
WLCSP, VPVIN = 3.3 V
LFCSP, VPVIN = 5.0 V
LFCSP, VPVIN = 3.3 V
Rev. B | Page 3 of 27
1.5
1.2
47
60
60
70
ADN8834
Parameter
N-MOSFET
Leakage Current
P-MOSFET
N-MOSFET
SW Node Rise Time 1
PWM Duty Cycle 2
SFB Input Bias Current
PWM OSCILLATOR
Internal Oscillator Frequency
EN/SY Input Voltage
Low
High
External Synchronization Frequency
Synchronization Pulse Duty Cycle
EN/SY Rising to PWM Rising Delay
EN/SY to PWM Lock Time
EN/SY Input Current
Pull-Down Current
ERROR/COMPENSATION AMPLIFIERS
Input Offset Voltage
Input Voltage Range
Common-Mode Rejection Ratio (CMRR)
Output Voltage
High
Data Sheet
Symbol
RDS_NS(ON)
Test Conditions/Comments
WLCSP, VPVIN = 5.0 V
WLCSP, VPVIN = 3.3 V
LFCSP, VPVIN = 5.0 V
LFCSP, VPVIN = 3.3 V
ISW_P_LKG
ISW_N_LKG
tSW_R
DSW
ISFB
CSW = 1 nF
fOSC
EN/SY high
VEN/SY_ILOW
VEN/SY_IHIGH
fSYNC
DSYNC
tSYNC_PWM
tSY_LOCK
IEN/SY
VOS1
VOS2
VCM1, VCM2
CMRR1, CMRR2
Min
Typ
40
45
45
55
Max
60
65
75
85
Unit
mΩ
mΩ
mΩ
mΩ
0.1
0.1
1
10
10
1
93
2
µA
µA
ns
%
µA
2.0
2.15
MHz
0.8
V
V
MHz
%
ns
Cycles
µA
µA
6
1.85
2.1
1.85
10
3.25
90
50
Number of SYNC cycles
0.3
0.3
VCM1 = 1.5 V, VOS1 = VIN1P − VIN1N
VCM2 = 1.5 V, VOS2 = VIN2P − VIN2N
10
10
0
VCM1, VCM2 = 0.2 V to VVDD − 0.2 V
VOH1, VOH2
10
0.5
0.5
100
100
VVDD
120
V
VVDD −
0.04
Low
Power Supply Rejection Ratio (PSRR)
Output Current
Gain Bandwidth Product1
TEC CURRENT LIMIT
ILIM Input Voltage Range
Cooling
VOL1, VOL2
PSRR1, PSRR2
IOUT1, IOUT2
GBW1, GBW2
VILIMC
1.3
Heating
Current-Limit Threshold
Cooling
Heating
ILIM Input Current
Heating
Cooling
Cooling to Heating Current Detection
Threshold
TEC VOLTAGE LIMIT
Voltage Limit Gain
VLIM/SD Input Voltage Range1
VLIM/SD Input Current
Cooling
Heating
VILIMH
0.2
10
mV
dB
mA
MHz
VVREF −
0.2
1.2
V
V
2.02
0.52
V
V
+0.2
42.5
µA
µA
mA
120
Sourcing and sinking
VOUT1,VOUT2 = 0.5 V to VVDD − 1 V
5
2
VILIMC_TH
VILIMH_TH
VITEC = 0.5 V
VITEC = 2 V
1.98
0.48
IILIMH
IILIMC
ICOOL_HEAT_TH
Sourcing current
−0.2
37.5
AVLIM
VVLIM
(VDRL − VSFB)/VVLIM
IILIMC
IILIMH
VOUT2 < VVREF/2
VOUT2 > VVREF/2, sinking current
2.0
0.5
40
40
2
0.2
Rev. B | Page 4 of 27
−0.2
8
µV
µV
V
dB
10
VVDD/2
V/V
V
+0.2
12.2
µA
µA
Data Sheet
Parameter
TEC CURRENT MEASUREMENT (WLCSP)
Current Sense Gain
ADN8834
Symbol
Test Conditions/Comments
RCS
VPVIN = 3.3 V
VPVIN = 5 V
700 mA ≤ ILDR ≤ 1.5 A, VPVIN = 3.3 V
800 mA ≤ ILDR ≤ 1.5 A, VPVIN = 5 V
VPVIN = 3.3 V, cooling, VVREF/2 +
ILDR × RCS
VPVIN = 3.3 V, heating, VVREF/2 −
ILDR × RCS
VPVIN = 5 V, cooling, VVREF/2 + ILDR × RCS
VPVIN = 5 V, heating, VVREF/2 − ILDR × RCS
Current Measurement Accuracy
ILDR_ERROR
ITEC Voltage Accuracy
VITEC_@_700_mA
VITEC_@_−700_mA
VITEC_@_800_mA
VITEC_@_−800_mA
TEC CURRENT MEASUREMENT (LFCSP)
Current Sense Gain
RCS
Current Measurement Accuracy
ILDR_ERROR
ITEC Voltage Accuracy
VITEC_@_700_mA
VITEC_@_−700_mA
VITEC_@_800_mA
VITEC_@_−800_mA
ITEC Voltage Output Range
VITEC
ITEC Bias Voltage
Maximum ITEC Output Current
TEC VOLTAGE MEASUREMENT
Voltage Sense Gain
Voltage Measurement Accuracy
VITEC
IITEC
VTEC Output Voltage Range
VTEC Bias Voltage
Maximum VTEC Output Current
TEMPERATURE GOOD (LFCSP Only)
TMPGD Low Output Voltage
TMPGD High Output Voltage
TMPGD Output Low Impedance
TMPGD Output High Impedance
High Threshold
Low Threshold
INTERNAL SOFT START
Soft Start Time
VLIM/SD SHUTDOWN
VLIM/SD Low Voltage Threshold
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1
2
AVTEC
VVTEC_@_1_V
VVTEC
VVTEC_B
RVTEC
VTMPGD_LO
VTMPGD_HO
RTMPGD_LOW
RTMPGD_LOW
VOUT1_THH
VOUT1_THL
VPVIN = 3.3 V
VPVIN = 5 V
700 mA ≤ ILDR ≤ 1 A, VPVIN = 3.3 V
800 mA ≤ ILDR ≤ 1 A, VPVIN = 5 V
VPVIN = 3.3 V, cooling, VVREF/2 + ILDR ×
RCS
VPVIN = 3.3 V, heating, VVREF/2 − ILDR ×
RCS
VPVIN = 5 V, cooling, VVREF/2 + ILDR ×
RCS
VPVIN = 5 V, heating, VVREF/2 − ILDR ×
RCS
ITEC = 0 A
ILDR = 0 A
VLDR – VSFB = 1 V, VVREF/2 + AVTEC ×
(VLDR – VSFB)
VLDR = VSFB
No load
No load
IN2N tied to OUT2, VIN2P = 1.5 V
IN2N tied to OUT2, VIN2P = 1.5 V
tSS
Min
Typ
Max
Unit
V/A
V/A
%
%
V
0.525
0.535
−10
−10
1.597
1.618
+10
+10
1.649
0.846
0.883
0.891
V
1.657
0.783
1.678
0.822
1.718
0.836
V
V
V/A
V/A
%
%
V
0.525
0.525
−15
−15
1.374
1.618
+15
+15
1.861
0.750
0.883
1.015
V
1.419
1.678
1.921
V
0.705
0.830
0.955
V
VVREF −
0.05
1.285
+2
V
V
mA
0
1.210
−2
1.250
0.24
1.475
0.25
1.50
0.26
1.525
V/V
V
1.250
2.625
1.285
+2
V
V
mA
0.4
V
V
Ω
Ω
V
V
0.005
1.225
−2
2.0
1.40
25
50
1.54
1.46
1.56
150
VVLIM/SD_THL
ms
0.07
TSHDN_TH
TSHDN_HYS
170
17
This specification is guaranteed by design.
This specification is guaranteed by characterization.
Rev. B | Page 5 of 27
V
°C
°C
ADN8834
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
PVIN to PGNDL (WLCSP)
PVIN to PGNDS (WLCSP)
PVINL to PGNDL (LFCSP)
PVINS to PGNDS (LFCSP)
LDR to PGNDL (WLCSP)
LDR to PGNDL (LFCSP)
SW to PGNDS
SFB to AGND
AGND to PGNDL
AGND to PGNDS
VLIM/SD to AGND
ILIM to AGND
VREF to AGND
VDD to AGND
IN1P to AGND
IN1N to AGND
OUT1 to AGND
IN2P to AGND
IN2N to AGND
OUT2 to AGND
EN/SY to AGND
ITEC to AGND
VTEC to AGND
Maximum Current
VREF to AGND
OUT1 to AGND
OUT2 to AGND
ITEC to AGND
VTEC to AGND
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Rating
−0.3 V to +5.75 V
−0.3 V to +5.75 V
−0.3 V to +5.75 V
−0.3 V to +5.75 V
−0.3 V to VPVIN
−0.3 V to VPVINL
−0.3 V to +5.75 V
−0.3 V to VVDD
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to VVDD
−0.3 V to VVDD
−0.3 V to +3 V
−0.3 V to +5.75 V
−0.3 V to VVDD
−0.3 V to VVDD
−0.3 V to +5.75 V
−0.3 V to VVDD
−0.3 V to VVDD
−0.3 V to +5.75 V
−0.3 V to VVDD
−0.3 V to +5.75 V
−0.3 V to +5.75 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages, and is
based on a 4-layer standard JEDEC board.
Table 4.
Package Type
25-Ball WLCSP
24-Lead LFCSP
ESD CAUTION
20 mA
50 mA
50 mA
50 mA
50 mA
125°C
−65°C to +150°C
260°C
Rev. B | Page 6 of 27
θJA
48
37
θJC
0.6
1.65
Unit
°C/W
°C/W
Data Sheet
ADN8834
PGNDL
OUT1
IN1P
IN2P
18 PGNDL
IN2N 1
OUT2 2
LDR
B
LDR
IN1N
VLIM/
SD
IN2N
17 LDR
VLIM/SD 3
ADN8834
16 PVINL
ILIM 4
TOP VIEW
(Not to Scale)
15 PVINS
VDD 5
14 SW
VREF 6
D
SW
SW
VTEC
EN/SY
VDD
2.54mm
ITEC 11
ILIM
PGNDS 12
OUT2
SFB 10
ITEC
VTEC 9
PVIN
AGND 7
PVIN
EN/SY 8
C
13 PGNDS
NOTES
1. EXPOSED PAD. SOLDER TO THE ANALOG
GROUND PLANE ON THE BOARD.
12954-200
PGNDL
20 TMPGD
5
19 PGNDL
4
22 IN1N
3
21 OUT1
2
24 IN2P
A
1
23 IN1P
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
0.5mm
PITCH
E
PGNDS
PGNDS
SFB
AGND
VREF
2.54mm
12954-002
ADN8834
TOP VIEW
(BALLS ON THE BOTTOM SIDE)
Figure 3. LFCSP Pin Configuration (Top View)
Figure 2. WLCSP Pin Configuration (Top View)
Table 5. Pin Function Descriptions
WLCSP
A1, A2
N/A1
A3
A4
A5
B1, B2
B3
B4
B5
Pin No.
LFCSP
18, 19
20
21
23
24
17
22
1
3
C1, C2
N/A1
N/A1
C3
C4
C5
D1, D2
D3
D4
N/A1
16
15
11
2
4
14
9
8
PVIN
PVINL
PVINS
ITEC
OUT2
ILIM
SW
VTEC
EN/SY
D5
E1, E2
E3
E4
E5
N/A1
5
12, 13
10
7
6
0
VDD
PGNDS
SFB
AGND
VREF
EPAD
1
Mnemonic
PGNDL
TMPGD
OUT1
IN1P
IN2P
LDR
IN1N
IN2N
VLIM/SD
Description
Power Ground of the Linear TEC Controller.
Temperature Good Output.
Output of the Error Amplifier.
Noninverting Input of the Error Amplifier.
Noninverting Input of the Compensation Amplifier.
Output of the Linear TEC Controller.
Inverting Input of the Error Amplifier.
Inverting Input of the Compensation Amplifier.
Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage limits. When this pin
is pulled low, the device shuts down.
Power Input for the TEC Controller.
Power Input for the Linear TEC Driver.
Power Input for the PWM TEC Driver.
TEC Current Output.
Output of the Compensation Amplifier.
Current Limit. This pin sets the TEC cooling and heating current limits.
Switch Node Output of the PWM TEC Controller.
TEC Voltage Output.
Enable/Synchronization. Set this pin high to enable the device. An external synchronization
clock input can be applied to this pin.
Power for the Controller Circuits.
Power Ground of the PWM TEC Controller.
Feedback of the PWM TEC Controller Output.
Signal Ground.
2.5 V Reference Output.
Exposed Pad. Solder to the analog ground plane on the board.
N/A means not applicable.
Rev. B | Page 7 of 27
ADN8834
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
90
80
70
70
EFFICIENCY (%)
80
60
50
40
50
40
30
30
20
20
10
10
0
0.5
1.0
1.5
TEC CURRENT (A)
0
1.4
MAXIMUM TEC CURRENT (A)
80
70
60
50
40
30
1.2
1.0
0.8
0.6
0.4
20
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
0.2
10
0
0.5
1.0
1.5
TEC CURRENT (A)
0
2.7
12954-004
0
1.5
1.0
Figure 7. Efficiency vs. TEC Current at VIN = 3.3 V with Different Loads in
Heating Mode
VIN = 3.3V
VIN = 5V
90
0.5
TEC CURRENT (A)
Figure 4. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Cooling Mode
with 2 Ω Load
100
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
0
12954-003
0
EFFICIENCY (%)
60
12954-106
90
EFFICIENCY (%)
100
VIN = 3.3V
VIN = 5V
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE AT PVIN (V)
Figure 5. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Heating Mode
with 2 Ω Load
12954-107
100
Figure 8. Maximum TEC Current vs. Input Voltage at PVIN (VIN = 3.3 V),
Without Voltage and Current Limit in Cooling Mode
100
1.4
90
EFFCIENCY(%)
70
60
50
40
30
20
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
0
0
0.5
1.0
TEC CURRENT (A)
1.0
0.8
0.6
0.4
LOAD = 2Ω
LOAD = 3Ω
LOAD = 4Ω
LOAD = 5Ω
0.2
1.5
0
2.7
12954-105
10
1.2
3.0
3.5
4.0
4.5
INPUT VOLTAGE AT PVIN (V)
Figure 6. Efficiency vs. TEC Current at VIN = 3.3 V with Different Loads in
Cooling Mode
5.0
5.5
12954-108
MAXIMUM TEC CURRENT (A)
80
Figure 9. Maximum TEC Current vs. Input Voltage at PVIN (VIN = 3.3 V),
Without Voltage and Current Limit in Heating Mode
Rev. B | Page 8 of 27
Data Sheet
ADN8834
0.20
T
T
T
T
T
0.08
0.06
= 15°C
= 25°C
= 35°C
= 45°C
= 55°C
VIN = 3.3V,
VIN = 3.3V,
VIN = 3.3V,
VIN = 5.0V,
VIN = 5.0V,
VIN = 5.0V,
0.15
0.10
0.04
0.05
VREF (%)
0.02
0
–0.02
COOLING
HEATING
0
–0.05
–0.10
–0.15
20
40
60
80
100
120
140
160
180
200
–0.20
0
0.08
0.06
20
= 15°C
= 25°C
= 35°C
= 45°C
= 55°C
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
0
20
40
60
80
100
120
140
160
180
200
TIME (Seconds)
Figure 11. Thermal Stability over Ambient Temperature at VIN = 3.3 V,
VTEMPSET = 1.5 V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
7
8
9
10
10
5
0
–5
–10
–15
0
0.5
1.0
1.5
Figure 14. ITEC Current Reading Error vs. TEC Current in Cooling Mode
ITEC CURRENT READING ERROR (%)
0.8
6
VIN = 3.3V
VIN = 5V
20
NO LOAD
NO LOAD
NO LOAD
5mA LOAD
5mA LOAD
5mA LOAD
5
TEC CURRENT (A)
1.0
VIN = 2.7V AT
VIN = 3.3V AT
VIN = 5.5V AT
VIN = 2.7V AT
VIN = 3.3V AT
VIN = 5.5V AT
4
15
–20
12954-110
–0.10
3
Figure 13. VREF Load Regulation
ITEC CURRENT READING ERROR (%)
T
T
T
T
T
2
LOAD CURRENT AT VREF (mA)
Figure 10. Thermal Stability over Ambient Temperature at VIN = 3.3 V,
VTEMPSET = 1 V
0.10
1
12954-201
0
12954-010
–0.08
TIME (Seconds)
15
VIN = 3.3V
VIN = 5V
10
5
0
–5
–10
–15
–1.0
–50
0
50
100
AMBIENT TEMPERATURE (°C)
150
12954-111
–0.8
–20
–1.5
–1.0
–0.5
TEC CURRENT (A)
0
12954-013
TEMPOUT [VOUT1] VOLTAGE ERROR (%)
COOLING
HEATING
–0.06
–0.10
VREF ERROR (%)
ITEC = 0A
ITEC = 0.5A,
ITEC = 0.5A,
ITEC = 0A
ITEC = 0.5A,
ITEC = 0.5A,
–0.04
12954-109
TEMPOUT [VOUT1] VOLTAGE ERROR (%)
0.10
Figure 15. ITEC Current Reading Error vs. TEC Current in Heating Mode
Figure 12. VREF Error vs. Ambient Temperature
Rev. B | Page 9 of 27
ADN8834
Data Sheet
VIN = 3.3V
VIN = 5V
15
10
5
TEC CURRENT
0
4
PWM (TEC–)
–5
–10
LDO (TEC+)
–20
0.5
1.0
1.5
2.0
2.5
TEC VOLTAGE (V)
Figure 16. VTEC Voltage Reading Error vs. TEC Voltage in Cooling Mode
B
M10ms
A CH4
T
5.4ms
W
–8mA
Figure 19. Zero Crossing TEC Current Zoom in from Heating to Cooling
VIN = 3.3V
VIN = 5V
15
10
5
TEC CURRENT
0
4
PWM (TEC–)
–5
–10
LDO (TEC+)
–15
–20
–2.5
–2.0
–1.5
–1.0
–0.5
TEC VOLTAGE (V)
Figure 17. VTEC Voltage Reading Error vs. TEC Voltage in Heating Mode
CH1 500mV BW CH2 500mV
CH3 200mA Ω BW
B
M10ms
A CH4
T
5.4ms
W
12mA
12954-120
1
12954-014
Figure 20. Zero Crossing TEC Current Zoom in from Cooling to Heating
LDO (TEC+)
EN
3
PWM (TEC–)
TEC CURRENT
TEC CURRENT
4
4
LDO (TEC–)
PWM (TEC+)
1
B
W
M200ms
A CH4
T
–28.000ms
–108mA
1
12954-118
CH1 500mV BW CH2 500mV
CH4 200mA Ω BW
CH1 1V BW CH2 1V
CH4 500mA Ω BW
Figure 18. Cooling to Heating Transition
B
W
CH3 2V
B
W
M20.0ms
A CH3
T
40ms
800mV
Figure 21. Typical Enable Waveforms in Cooling Mode,
VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A
Rev. B | Page 10 of 27
12954-121
VTEC VOLTAGE READING ERROR (%)
20
CH1 500mV BW CH2 500mV
CH3 300mA Ω BW
12954-120
1
–15
12954-011
VTEC VOLTAGE READING ERROR (%)
20
Data Sheet
ADN8834
EN
SW
3
3
TEC CURRENT
4
LDO (TEC+)
1
PWM (TEC–)
PWM (TEC–)
2
CH1 1V W CH2 1V
CH4 500mA Ω BW
B
W
CH3 2V
B
W
M20.0ms
A CH3
T
40ms
800mV
CH1 20mV BW CH2 20mV
CH3 2.0V BW
Figure 22. Typical Enable Waveforms in Heating Mode,
VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A
3
LDO (TEC+)
1
PWM (TEC–)
W
M400ns
T
0.0s
A CH3
1.00V
2.50GS/s
12954-202
2
B
W
M400ns
T
0.0s
A CH3
1.00V
2.50GS/s
Figure 24. Typical Switch and Voltage Ripple Waveforms in Heating Mode,
VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A
SW
CH1 20mV BW CH2 20mV
CH3 2.0V BW
B
12954-203
B
12954-122
LDO (TEC+)
2
Figure 23. Typical Switch and Voltage Ripple Waveforms in Cooling Mode
VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A
Rev. B | Page 11 of 27
ADN8834
Data Sheet
DETAILED FUNCTIONAL BLOCK DIAGRAM
VTEC
ITEC
ADN8834
VDD
VREF
TEC DRIVER
LINEAR POWER
STAGE
COOLING
VDD
5kΩ
2.5V
BAND GAP
VOLTAGE
REFERENCE
HEATING
20kΩ
5kΩ
1.25V
20kΩ
1.25V
PVIN
1.25V
TEC CURRENT SENSE
20kΩ
–
+
LDR
VB = 2.5V AT VDD > 4.0V
VB = 1.5V AT VDD < 4.0V
TEC
VOLTAGE
SENSE
VB
SFB
VC
AGND
TEMPERATURE
ERROR
AMPLIFIER
2kΩ
80kΩ
LDR
+
–
VB
LINEAR
AMPLIFIER
IN1P
PGNDL
VB
PGNDL
IN1N
80kΩ
OUT1
1.25V
20kΩ
20kΩ
400kΩ
SFB
PWM POWER
STAGE
100kΩ
COMPENSATION
AMPLIFIER
VC
20kΩ
IN2P
PWM
MODULATOR
20kΩ
IN2N
20kΩ
OUT2
TEC VOLTAGE
LIMIT AND INTERNAL
SOFT START
40µA
VB
COOLING
HEATING
PWM
MOSFET
DRIVER
PWM
ERROR
AMPLIFIER
VDD
OSCILLATOR
SW
CLK
PGNDS
SHUTDOWN
10µA
VHIGH ≥ 2.1V
VLOW ≤ 0.8V
ITEC
TEC
CURRENT
LIMIT
0.07V
VLIM/SD
DEGLITCH
SHUTDOWN
ILIM
Figure 25. Detailed Functional Block Diagram of the ADN8834 for the WLCSP
Rev. B | Page 12 of 27
PGNDS
EN/SY
12954-018
CLK
PVIN
Data Sheet
ADN8834
THEORY OF OPERATION
The ADN8834 drives its internal MOSFET transistors to provide
the TEC current. To provide good power efficiency and zero
crossing quality, only one side of the H-bridge uses a PWM
driver. Only one inductor and one capacitor are required to filter
out the switching frequency. The other side of the H-bridge uses a
linear output without requiring any additional circuitry. This proprietary configuration allows the ADN8834 to provide efficiency of
>90%. For most applications, a 1 µH inductor, a 10 μF capacitor,
and a switching frequency of 2 MHz maintain less than 1% of the
worst-case output voltage ripple across a TEC.
The ADN8834 is a single chip TEC controller that sets and
stabilizes a TEC temperature. A voltage applied to the input of
the ADN8834 corresponds to the temperature setpoint of the target
object attached to the TEC. The ADN8834 controls an internal
FET H-bridge whereby the direction of the current fed through
the TEC can be either positive (for cooling mode), to pump
heat away from the object attached to the TEC, or negative (for
heating mode), to pump heat into the object attached to the TEC.
Temperature is measured with a thermal sensor attached to the
target object and the sensed temperature (voltage) is fed back to
the ADN8834 to complete a closed thermal control loop of the
TEC. For the best overall stability, couple the thermal sensor
close to the TEC. In most laser diode modules, a TEC and a
NTC thermistor are already mounted in the same package to
regulate the laser diode temperature.
The maximum voltage across the TEC and the current flowing
through the TEC are set by using the VLIM/SD and ILIM pins.
The maximum cooling and heating currents can be set independently to allow asymmetric heating and cooling limits. For
additional details, see the Maximum TEC Voltage Limit section
and the Maximum TEC Current Limit section.
The TEC is differentially driven in an H-bridge configuration.
TEC
CURRENT
ENABLE/
SYNC
TEC
VOLTAGE
SHUTDOWN
ITEC
EN/SY
VTEC
VDD
CVDD
0.1µF R
BP
VIN
2.7V TO 5.5V
VLIM/SD
TEC
VOLTAGE
LIMIT
RV2
RV1
TEC
CURRENT
LIMITS
RC2
LDR
CL_OUT
0.1µF
ADN8834
RB
–
SFB
AGND
RFB
RTH
THERMISTER
+
PGNDL
CVREF
0.1µF
NTC
TEC
L = 1µH
IN2P
IN1P
IN1N
OUT1
IN2N
RI
RD CD
OUT2
SW
PGNDS
CSW_OUT
10µF
R P CI
CF
12954-019
RA
TEMP
SET
RX
CIN
10µF
ILIM
RC1
VREF
R
PVIN
Figure 26. Typical Application Circuit with Analog PID Compensation in a Temperature Control Loop
Rev. B | Page 13 of 27
ADN8834
Data Sheet
ANALOG PID CONTROL
The Chopper 2 amplifier is used as a buffer for the external
DAC, which controls the temperature setpoint. Connect the
DAC to IN2P and short the IN2N and OUT2 pins together. See
Figure 27 for an overview of how to configure the ADN8834
external circuitry for digital PID control.
The ADN8834 integrates two self-correcting, auto-zeroing
amplifiers (Chopper 1 and Chopper 2). The Chopper 1 amplifier
takes a thermal sensor input and converts or regulates the input
to a linear voltage output. The OUT1 voltage is proportional to
the object temperature. The OUT1 voltage is fed into the
compensation amplifier (Chopper 2) and is compared with a
temperature setpoint voltage, which creates an error voltage that is
proportional to the difference. For autonomous analog temperature
control, Chopper 2 can be used to implement a PID network as
shown in Figure 27 to set the overall stability and response of the
thermal loop. Adjusting the PID network optimizes the step
response of the TEC control loop. A compromised settling time
and the maximum current ringing become available when this
adjustment is done. To adjust the compensation network, see
the PID Compensation Amplifier (Chopper 2) section.
POWERING THE CONTROLLER
The ADN8834 operates at an input voltage range of 2.7 V to
5.5 V that is applied to the VDD pin and the PVIN pin for the
WLCSP (the PVINS pin and PVINL pin for the LFCSP. The
VDD pin is the input power for the driver and internal reference.
The PVIN input power pins are combined for both the linear
and the switching driver. Apply the same input voltage to all power
input pins: VDD and PVIN. In some circumstances, an RC lowpass filter can be added optionally between the PVIN for the
WLCSP (PVINS and PVINL for the LFCSP) and VDD pins to
prevent high frequency noise from entering VDD, as shown in
Figure 27. The capacitor and resistor values are typically 10 Ω
and 100 nF, respectively.
DIGITAL PID CONTROL
The ADN8834 can also be configured for use in a software
controlled PID loop. In this scenario, the Chopper 1 amplifier
can either be left unused or configured as a thermistor input
amplifier connected to an external temperature measurement
analog-to-digital converter (ADC). For more information, see
the Thermistor Amplifier (Chopper 1) section. If Chopper 1 is
left unused, tie IN1N and IN1P to AGND.
When configuring power supply to the ADN8834, keep in mind
that at high current loads, the input voltage may drop substantially
due to a voltage drop on the wires between the front-end power
supply and the PVIN for the WLCSP (PVINS and PVINL for
the LFCSP) pin. Leave a proper voltage margin when designing
the front-end power supply to maintain the performance.
Minimize the trace length from the power supply to the PVIN
for the WLCSP (PVINS and PVINL for the LFCSP) pin to help
mitigate the voltage drop.
ENABLE
COOLING AND HEATING
TEC CURRENT LIMITS
2.5V VREF
TEC
VOLTAGE
LIMIT
2.5V VREF
RC1
RV1
RC2
CVDD
0.1µF
ILIM
EN/SY
VDD
VLIM/SD
RV2
PVIN
CIN
10µF
LDR
CL_OUT
0.1µF
VIN
2.7V TO 5.5V
IN2P
TEC CURRENT READBACK
TEC VOLTAGE READBACK
ITEC
ADN8834
VTEC
TEC
+
PGNDL
2.5V VREF
VREF
R
RA
–
CVREF
0.1uF
AGND
IN1P
IN1N
RX
L = 1µH
OUT1
IN2N OUT2
RB
RFB
NTC
RTH
SFB
SW
PGNDS
FSW = 2MHz
CSW_OUT
10µF
THERMISTER
2.5V VREF
TEMPERATURE
READBACK
ADC
Figure 27. TEC Controller in a Digital Temperature Control Loop (WLCSP)
Rev. B | Page 14 of 27
12954-020
DAC
TEMPERATURE SET
RBP
Data Sheet
ADN8834
ENABLE AND SHUTDOWN
Connecting Multiple ADN8834 Devices
To enable the ADN8834, apply a logic high voltage to the
EN/SY pin while the voltage at the VLIM/SD pin is above the
maximum shutdown threshold of 0.07 V. If either the EN/SY
pin voltage is set to logic low or the VLIM/SD voltage is below
0.07 V, the controller goes into an ultralow current state. The
current drawn in shutdown mode is 350 µA typically. Most of
the current is consumed by the VREF circuit block, which is
always on even when the device is disabled or shut down. The
device can also be enabled when an external synchronization
clock signal is applied to the EN/SY pin, and the voltage at
VLIM/SD input is above 0.07 V. Table 6 shows the combinations
of the two input signals that are required to enable the ADN8834.
Multiple ADN8834 devices can be driven from a single master
clock signal by connecting the external clock source to the
EN/SY pin of each slave device. The input ripple can be greatly
reduced by operating the ADN8834 devices 180° out of phase
from each other by placing an inverter at one of the EN/SY pins,
as shown in Figure 29.
ADN8834
EXTERNAL CLOCK
SOURCE
AGND
Table 6. Enable Pin Combinations
1
VLIM/SD Input
>0.07 V
>0.07 V
Controller
Enabled
Enabled
No effect1
No effect1
≤0.07 V
Shutdown
Shutdown
Shutdown
ADN8834
EN/SY
AGND
12954-022
EN/SY Input
>2.1 V
Switching between high
>2.1 V and low < 0.8 V
4.0 V
0.75
1.25
Figure 39. TEC Voltage vs. OUT2 Voltage
VB = 1.5 V for VVDD < 4.0 V
0.25
0.75
OUT2 (V)
where:
VOUT2 is the voltage at OUT2.
VB is determined by VVDD as
0
0.25
12954-032
VLDR = VB − 40(VOUT2 − 1.25 V)
VSW _ OUT × (VIN – VSW _ OUT )
VIN × f SW × ∆I L
where:
VSW_OUT is the PWM amplifier output.
fSW is the switching frequency (2 MHz by default).
∆IL is the inductor current ripple.
A 1 µH inductor is typically recommended to allow reasonable
output capacitor selection while maintaining a low inductor current
ripple. If lower inductance is required, a minimum inductor value
of 0.68 µH is suggested to ensure that the current ripple is set to
a value between 30% and 40% of the maximum load current,
which is 1.5 A.
Except for the inductor value, the equivalent dc resistance (DCR)
inherent in the metal conductor is also a critical factor for
inductor selection. The DCR accounts for most of the power loss
on the inductor by DCR × IOUT2. Using an inductor with high
DCR degrades the overall efficiency significantly. In addition,
there is a conduct voltage drop across the inductor because of
the DCR. When the PWM amplifier is sinking current in cooling
mode, this voltage drives the minimum voltage of the amplifier
higher than 0.06 × VIN by at least tenth of millivolts. Similarly, the
maximum PWM amplifier output voltage is lower than 0.93 × VIN.
Rev. B | Page 20 of 27
Data Sheet
ADN8834
This voltage drop is proportional to the value of the DCR and it
reduces the output voltage range at the TEC.
When selecting an inductor, ensure that the saturation current
rating is higher than the maximum current peak to prevent saturation. In general, ceramic multilayer inductors are suitable for low
current applications due to small size and low DCR. When the
noise level is critical, use a shielded ferrite inductor to reduce the
electromagnetic interference (EMI).
Table 7. Recommended Inductors
Vendor
Toko
Taiyo
Yuden
Murata
Value
1.0 µH ± 20%,
2.6 A (typical)
1.0 µH ± 20%,
2.2 A (typical)
1.0 µH ± 20%,
2.3 A (typical)
Device No.
DFE201612R-H-1R0M
Footprint
2.0 × 1.6
MAKK2016T1R0M
2.0 × 1.6
LQM2MPN1R0MGH
2.0 × 1.6
Capacitor Selection
The output capacitor selection determines the output voltage
ripple, transient response, as well as the loop dynamic response
of the PWM amplifier output. Use the following equation to
select the capacitor:
C=
VSW _ OUT × (VIN – VSW _ OUT )
Taiyo
Yuden
PLOSS = PPWM + PLINEAR
where:
PLOSS is the total power dissipation in the ADN8834.
PLINEAR is the power dissipation in the linear regulator.
PWM Regulator Power Dissipation
The PWM power stage is configured as a buck regulator and
its dominant power dissipation (PPWM) includes power switch
conduction losses (PCOND), switching losses (PSW), and transition
losses (PTRAN). Other sources of power dissipation are usually
less significant at the high output currents of the application
thermal limit and can be neglected in approximation.
Use the following equation to estimate the power dissipation of
the buck regulator:
PLOSS = PCOND + PSW + PTRAN
Conduction Loss (PCOND)
The conduction loss consists of two parts: inductor conduction
loss (PCOND_L) and power switch conduction loss (PCOND_S).
PCOND = PCOND_L + PCOND_S
Table 8. Recommended Capacitors
Murata
This section provides guidelines to calculate the power
dissipation of the ADN8834. Approximate the total power
dissipation in the device by
VIN × 8 × L × ( f SW )2 × ∆VOUT
Note that the voltage caused by the product of current ripple,
ΔIL, and the capacitor equivalent series resistance (ESR) also
add up to the total output voltage ripple. Selecting a capacitor
with low ESR can increase overall regulation and efficiency
performance.
Vendor
Murata
POWER DISSIPATION
Value
10 µF ±
10%, 10 V
10 µF ±
20%, 10 V
10 µF ±
20%, 10 V
Device No.
ZRB18AD71A106KE01L
Footprint
(mm)
1.6 × 0.8
GRM188D71A106MA73
1.6 × 0.8
LMK107BC6106MA-T
1.6 × 0.8
INPUT CAPACITOR SELECTION
Inductor conduction loss is proportional to the DCR of the output
inductor, L. Using an inductor with low DCR enhances the overall
efficiency performance. Estimate inductor conduction loss by
PCOND_L = DCR × IOUT2
Power switch conduction losses are caused by the flow of the
output current through both the high-side and low-side power
switches, each of which has its own internal on resistance (RDSON).
Use the following equation to estimate the amount of power
switch conduction loss:
PCOND_S = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT2
where:
RDSON_HS is the on resistance of the high-side MOSFET.
D is the duty cycle (D = VOUT/VIN).
RDSON_LS is the on resistance of the low-side MOSFET.
On the PVIN pin, the amplifiers require an input capacitor
to decouple the noise and to provide the transient current to
maintain a stable input and output voltage. A 10 µF ceramic
capacitor rated at 10 V is the minimum recommended value.
Increasing the capacitance reduces the switching ripple that
couples into the power supply but increases the capacitor size.
Because the current at the input terminal of the PWM amplifier
is discontinuous, a capacitor with low effective series inductance
(ESL) is preferred to reduce voltage spikes.
In most applications, a decoupling capacitor is used in parallel
with the input capacitor. The decoupling capacitor is usually a
100 nF ceramic capacitor with very low ESR and ESL, which
provides better noise rejection at high frequency bands.
Rev. B | Page 21 of 27
ADN8834
Data Sheet
Switching Loss (PSW)
Use the following equation to estimate the transition loss:
Switching losses are associated with the current drawn by the
controller to turn the power devices on and off at the switching
frequency. Each time a power device gate is turned on or off,
the controller transfers a charge from the input supply to the
gate, and then from the gate to ground. Use the following
equation to estimate the switching loss:
PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW
PTRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW
where:
tR is the rise time of the switch node.
tF is the fall time of the switch node.
For the ADN8834, tR and tF are both approximately 1 ns.
Linear Regulator Power Dissipation
The power dissipation of the linear regulator is given by the
following equation:
where:
CGATE_HS is the gate capacitance of the high-side MOSFET.
CGATE_LS is the gate capacitance of the low-side MOSFET.
fSW is the switching frequency.
PLINEAR = [(VIN − VOUT) × IOUT] + (VIN × IGND)
For the ADN8834, the total of (CGATE_HS + CGATE_LS) is
approximately 1 nF.
Transition Loss (PTRAN)
Transition losses occur because the high-side MOSFET cannot
turn on or off instantaneously. During a switch node transition,
the MOSFET provides all the inductor current. The source-todrain voltage of the MOSFET is half the input voltage, resulting
in power loss. Transition losses increase with both load and input
voltage and occur twice for each switching cycle.
where:
VIN and VOUT are the input and output voltages of the linear
regulator.
IOUT is the load current of the linear regulator.
IGND is the ground current of the linear regulator.
Power dissipation due to the ground current is generally small
and can be ignored for the purposes of this calculation.
Rev. B | Page 22 of 27
Data Sheet
ADN8834
PCB LAYOUT GUIDELINES
SOURCE OF
ELECTRICAL
POWER
TEMPERATURE
ERROR
COMPENSATION
TEC
DRIVER
TEMPERATURE
SIGNAL
CONDITIONING
TEC
CURRENT
LIMITING
OBJECT
THERMOELECTRIC
COOLER
TEMPERATURE
(TEC)
SENSOR
TEC
CURRENT
SENSING
12954-033
TARGET
TEMPERATURE
TEC
VOLTAGE
SENSING
TEC
VOLTAGE
LIMITING
Figure 40. System Block Diagram
BLOCK DIAGRAMS AND SIGNAL FLOW
The ADN8834 integrates analog signal conditioning blocks, a
load protection block, and a TEC controller power stage all in a
single IC. To achieve the best possible circuit performance,
attention must be paid to keep noise of the power stage from
contaminating the sensitive analog conditioning and protection
circuits. In addition, the layout of the power stage must be
performed such that the IR losses are minimized to obtain the
best possible electrical efficiency.
The system block diagram of the ADN8834 is shown in Figure 40.
GUIDELINES FOR REDUCING NOISE AND
MINIMIZING POWER LOSS
Each printed circuit board (PCB) layout is unique because of
the physical constraints defined by the mechanical aspects of a
given design. In addition, several other circuits work in conjunction
with the TEC controller; these circuits have their own layout
requirements, so there are always compromises that must be
made for a given system. However, to minimize noise and keep
power losses to a minimum during the PCB layout process,
observe the following guidelines.
General PCB Layout Guidelines
Switching noise can interfere with other signals in the system;
therefore, the switching signal traces must be placed away from
the power stage to minimize the effect. If possible, place the
ground plate between the small signal layer and power stage
layer as a shield.
Supply voltage drop on traces is also an important consideration
because it determines the voltage headroom of the TEC controller
at high currents. For example, if the supply voltage from the frontend system is 3.3 V, and the voltage drop on the traces is 0.5 V,
PVIN sees only 2.8 V, which limits the maximum voltage of the
linear regulator as well as the maximum voltage across the TEC. To
mitigate the voltage waste on traces and impedance interconnection, place the ADN8834 and the input decoupling components
close to the supply voltage terminal. This placement not only
improves the system efficiency but also provides better regulation
performance at the output.
To prevent noise signal from circulating through ground plates,
reference all of the sensitive analog signals to AGND and connect
AGND to PGNDS using only a single point connection. This
ensures that the switching currents of the power stage do not
flow into the sensitive AGND node.
PWM Power Stage Layout Guidelines
The PWM power stage consists of a MOSFET pair that forms a
switch mode output that switches current from PVIN to the load
via an LC filter. The ripple voltage on the PVIN pin is caused by
the discontinuous current switched by the PWM side MOSFETs.
This rapid switching causes voltage ripple to form at the PVIN
input, which must be filtered using a bypass capacitor. Place a 10 µF
capacitor as close as possible to the PVIN pin to connect PVIN to
PGNDS. Because the 10 µF capacitor is sometimes bulky and has
higher ESR and ESL, a 100 nF decoupling capacitor is usually
used in parallel with it, placed between PVIN and PGNDS.
Because the decoupling is part of the pulsating current loop,
which carries high di/dt signals, the traces must be short and
wide to minimize the parasitic inductance. As a result, this
capacitor is usually placed on the same side of the board as the
ADN8834 to ensure short connections. If the layout requires
that a 10 µF capacitor be on the opposite side of the PCB, use
multiple vias to reduce via impedance.
The layout around the SW node is also critical because it switches
between PVIN and ground rapidly, which makes this node a
strong EMI source. Keep the copper area that connects the SW
node to the inductor small to minimize parasitic capacitance
between the SW node and other signal traces. This helps minimize
noise on the SW node due to excessive charge injection. However,
in high current applications, the copper area may be increased
reasonably to provide heat sink and to sustain high current flow.
Connect the ground side of the capacitor in the LC filter as close as
possible to PGNDS to minimize the ESL in the return path.
Rev. B | Page 23 of 27
ADN8834
Data Sheet
Linear Power Stage Layout Guidelines
Place the thermistor conditioning and PID circuit components
close to each other near the inputs of Chopper 1 and Chopper 2.
Avoid crossing paths between the amplifier circuits and the
power stages to prevent noise pickup on the sensitive nodes.
Always reference the thermistor to AGND to have the cleanest
connection to the amplifier input and to avoid any noise or
offset build up.
The linear power stage consists of a MOSFET pair that forms a
linear amplifier, which operates in linear mode for very low output
currents, and changes to fully enhanced mode for greater
output currents.
Because the linear power stage does not switch currents rapidly
like the PWM power stage, it does not generate noise currents.
However, the linear power stage still requires a minimum
amount of bypass capacitance to decouple its input.
EXAMPLE PCB LAYOUT USING TWO LAYERS
Figure 41, Figure 42, and Figure 43 show an example ADN8834
PCB layout that uses two layers. This layout example achieves a
small solution size of approximately 20 mm2 with all of the
conditioning circuitry and PID included. Using more layers and
blinds via allows the solution size to be reduced even further
because more of the discrete components can relocate to the
bottom side of the PCB.
Place a 100 nF capacitor that connects from PVIN to PGNDL as
close as possible to the PVIN pin.
Placing the Thermistor Amplifier and PID Components
The thermistor conditioning and PID compensation amplifiers
work with very small signals and have gain; therefore, attention
must be paid when placing the external components with these
circuits.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
RD
0201
RFB
0.5
0201
0
CD
CF
RX
0201
0201
0201
RI
RP
0201
0201
CI
NTC
AGND
R
0402
0201
PGND
CONNECT TO GROUND PLANE
1.0
1.5
PGNDL
P
N L
OUT
UT 1
1P
IN
N1
P
0201
2P
IN
N2
P
RB
0201
020
0
02
2
201
20
01
0
1
0201
ITEC
TEC+
RA
PGNDL
P
NDL
CL_OUT
0201
TEMPSET
LDR
L
R
LDR
LD
L
D
DR
R
1N
IN
N1
N
VLIM
IM /
SD
2N
IN
N2
N
RV1
CIN_L
TEC–
2.0
PVIN
VI
0201
PVIN
VI
ITEC
TEC
EC
OUT
UT 2
RV2
ILIM
LIM
0201
CIN_S
PG
PGN
P
PGNDS
GN
N
NDS
DS
S
P
PGNDS
GN
ND
NDS
DS
S
CVDD
SFB
AGND
GN
0201
VD
VDD
DD
D
RC2
RBP
BP
EN/SY
EN
N /SY
0201
0201
02
20
VTEC
V
TE
0201
02
20
2
201
01
020
02
0201
20
01
1
04
402
4
0
0402
SW
SW
VREF
V
R
RE
E
EF
RBP
3.5
CVREF
0201
CSW_OUT
0402
CONNECT TO GROUND PLANE
4.0
Figure 41. Example PCB Layout Using Two Layers (Top and Bottom Layers)
Rev. B | Page 24 of 27
CONNECT AGND
TO PGNDS ONLY AT A
SINGLE POINT AS A
STAR CONNECTION
12954-034
UNITS = (mm)
3.0
RC1
SW
S
W
CVDD
L
2.5
0805
VTEC
CBU
BULK
ULK
VIN
Data Sheet
ADN8834
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
RD
0201
RFB
0.5
0201
0
CD
CF
RX
0201
0201
0201
RI
RP
0201
0201
CI
R
0402
NTC
AGND
0201
PGND
CONNECT TO GROUND PLANE
1.0
ITEC
TEC+
RA
PGN L
PGNDL
PGN L
PGNDL
IN
N 1P
IN1P
UT 1
OUT
IN2
IN
2P
IN2P
CL_OUT
0201
TEMPSET
1.5
RB
0201
IN1
N 1N
IN1N
LIM /
VLIM
SD
IN2
N 2N
IN2N
CIN_L
TEC–
2.0
0201
VI
PVIN
VI
PVIN
RV1
0201
TE
ITEC
UT 2
OUT
IL
LIM
M
ILIM
RV2
0201
VIN
RC1
2.5
3.5
0805
CVDD
0201
RC2
0201
SF
SFB
AGND
GN
VR
RE
E
EF
F
VREF
CVREF
0201
CSW_OUT
0402
CONNECT TO GROUND PLANE
4.0
Figure 42. Example PCB Layout Using Two Layers (Top Layer Only)
Rev. B | Page 25 of 27
12954-035
UNITS = (mm)
3.0
VD
D
VDD
EN
N /SY
EN/SY
VTEC
L
VTEC
ADN8834
Data Sheet
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
NTC
0.5
PGND
TEMPSET
AGND
CONNECT TO GROUND PLANE
1.0
ITEC
1.5
0201
TEC+
CIN_L
TEC–
2.0
RBP
RBP
3.5
CONNECT TO GROUND PLANE
4.0
Figure 43. Example PCB Layout Using Two Layers (Bottom Layer Only)
Rev. B | Page 26 of 27
12954-036
UNITS = (mm)
0201
CVDD
201
0201
CIN_S
3.0
CVDD
0201
2.5
0402
0
VTEC
CBULK
UL
VIN
Data Sheet
ADN8834
OUTLINE DIMENSIONS
2.58
2.54 SQ
2.50
5
BOTTOM VIEW
(BALL SIDE UP)
2
3
4
1
A
BALL A1
IDENTIFIER
2.00
REF
B
C
0.50
BSC
D
E
TOP VIEW
(BALL SIDE DOWN)
0.660
0.600
0.540
0.390
0.360
0.330
END VIEW
COPLANARITY
0.05
PKG-003121
0.360
0.320
0.280
0.270
0.240
0.210
06-07-2013-A
SEATING
PLANE
Figure 44. 25-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-25-7)
Dimensions shown in millimeters
PIN 1
INDICATOR
0.30
0.25
0.18
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PKG-004273
SEATING
PLANE
PIN 1
INDICATOR
24
19
18
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
12-03-2013-A
4.10
4.00 SQ
3.90
Figure 45. 24-Lead Lead-frame Chip Scale Package [LFCSP_WQ]
(CP-24-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADN8834ACBZ-R7
ADN8834CB-EVALZ
ADN8834ACPZ-R2
ADN8834ACPZ-R7
ADN8834CP-EVALZ
ADN8834MB-EVALZ
1
2
Temperature Range 2
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
25-Ball Wafer Level Chip Scale Package [WLCSP]
25-Ball WLCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead LFCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit
Mother Evaluation Board of the ADN8834 for PID tuning
Z = RoHS Compliant Part.
Operating junction temperature range. The ambient operating temperature range is −40°C to +85°C.
©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12954-0-9/18(B)
Rev. B | Page 27 of 27
Package
Option
CB-25-7
CP-24-15
CP-24-15
工商网监
湘ICP备2023018690号
