Ultracompact, 3 A
Thermoelectric Cooler (TEC) Controller
ADN8835
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD
VLIM/
SD ILIM VTEC ITEC
PVINx
ADN8835
ERROR
AMP
IN1P
TEC DRIVER
TEC CURRENT
AND VOLTAGE
SENSE AND LIMIT
IN1N
LINEAR
POWER
STAGE
OUT1
TMPGND
COMP
AMP
IN2P
CONTROLLER
SW
IN2N
PWM
POWER
STAGE
OUT2
APPLICATIONS
TEC temperature control
Optical modules
Optical fiber amplifiers
Optical networking systems
Instruments requiring TEC temperature control
LDR
AGND
VOLTAGE
REFERENCE
OSCILLATOR
VREF
EN/SY
PGNDx
SFB
14174-001
High efficiency single inductor architecture
Integrated low RDSON MOSFETs for the TEC controller
TEC voltage and current operation monitoring
No external sense resistor required
Independent TEC heating and cooling current-limit settings
Programmable maximum TEC voltage
2.0 MHz (typical) PWM driver switching frequency
External synchronization
Two integrated, zero-drift, rail-to-rail chopper amplifiers
Compatible with NTC or RTD thermal sensors
2.50 V reference output with 1% accuracy
Temperature lock indicator
Available in a 36-lead, 6 mm × 6 mm LFCSP
Figure 1.
GENERAL DESCRIPTION
The ADN88351 is a monolithic TEC controller with an integrated
TEC controller. It has a linear power stage, a pulse-width
modulation (PWM) power stage, and two zero-drift, rail-to-rail
chopper amplifiers. The linear controller works with the PWM
driver to control the internal power MOSFETs in an H bridge
configuration. By measuring the thermal sensor feedback
voltage and using the integrated operational amplifiers as a
proportional integral differential (PID) compensator to condition
the signal, the ADN8835 drives current through a TEC to settle
the temperature of a laser diode or a passive component attached
to the TEC module to the programmed target temperature.
The ADN8835 supports negative temperature coefficient
(NTC) thermistors as well as positive temperature coefficient
(PTC) resistive temperature detectors (RTDs). The target
temperature is set as an analog voltage input either from a
digital-to-analog converter (DAC) or from an external resistor
divider.
1
The temperature control loop of the ADN8835 is stabilized by
PID compensation utilizing the built in, zero-drift chopper
amplifiers. The internal 2.50 V reference voltage provides a 1%
accurate output that biases a thermistor temperature sensing
bridge as well as a voltage divider network to program the
maximum TEC current and voltage limits for both the heating and
cooling modes. With the zero-drift chopper amplifiers, excellent
long-term temperature stability is maintained via an autonomous
analog temperature control loop.
Table 1. TEC Family Models
Device No.
ADN8831
ADN8833
MOSFET
Discrete
Integrated
Thermal Loop
Digital/analog
Digital
ADN8834
Integrated
Digital/analog
ADN8835
Integrated
Digital/analog
Package
LFCSP (CP-32-7)
WLCSP (CB-25-7),
LFCSP (CP-24-15)
WLCSP (CB-25-7),
LFCSP (CP-24-15)
LFCSP (CP-36-5)
Product is covered by U.S. Patent No. 6,486,643.
Rev. B
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ADN8835
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
TEC Voltage/Current Monitor ................................................. 16
Applications ....................................................................................... 1
Maximum TEC Voltage Limit .................................................. 16
Functional Block Diagram .............................................................. 1
Maximum TEC Current Limit ................................................. 16
General Description ......................................................................... 1
Applications Information .............................................................. 18
Revision History ............................................................................... 2
Signal Flow .................................................................................. 18
Detailed Functional Block Diagram .............................................. 3
Thermistor Setup........................................................................ 18
Specifications..................................................................................... 4
Thermistor Amplifier (Chopper 1).......................................... 19
Absolute Maximum Ratings............................................................ 7
PID Compensation Amplifier (Chopper 2)............................ 19
Thermal Resistance ...................................................................... 7
MOSFET Driver Amplifiers...................................................... 20
Maximum Power Dissipation ..................................................... 7
PWM Output Filter Requirements .......................................... 20
ESD Caution .................................................................................. 7
Input Capacitor Selection .......................................................... 21
Pin Configuration and Function Descriptions ............................. 8
Power Dissipation....................................................................... 21
Typical Performance Characteristics ............................................. 9
Thermal Consideration ............................................................. 22
Theory of Operation ...................................................................... 13
PCB Layout Guidelines .................................................................. 23
Analog PID Control ................................................................... 14
Block Diagrams and Signal Flow ............................................. 23
Digital PID Control .................................................................... 14
Guidelines for Reducing Noise and Minimizing Power Loss23
Powering the Controller ............................................................ 14
Example PCB Layout Using Two Layers ................................. 24
Enable and Shutdown ................................................................ 15
Outline Dimensions ....................................................................... 27
Oscillator Clock Frequency ....................................................... 15
Ordering Guide .......................................................................... 27
Temperature Lock Indicator ..................................................... 15
Soft Start on Power-Up .............................................................. 15
REVISION HISTORY
9/2018—Rev. A to Rev. B
Added Patent Information................................................................. 1
Changes to Specifications, Table 2, Voltage Measurement
Accuracy Parameter ......................................................................... 6
5/2017—Rev. 0 to Rev. A
Changes to PID Compensation Amplifier (Chopper 2) Section... 18
Changes to Ordering Guide .......................................................... 26
12/2016—Revision 0: Initial Version
Rev. B | Page 2 of 27
Data Sheet
ADN8835
DETAILED FUNCTIONAL BLOCK DIAGRAM
TMPGD
VTEC
ITEC
ADN8835
VDD
VREF
TEC DRIVER
LINEAR POWER
STAGE
COOLING
VDD
5kΩ
2.5V
BAND GAP
VOLTAGE
REFERENCE
HEATING
20kΩ
5kΩ
1.25V
20kΩ
1.25V
PVINL
1.25V
TEC CURRENT SENSE
20kΩ
–
+
LDR
VB = 2.5V AT VDD > 4.0V
VB = 1.5V AT VDD < 4.0V
TEC
VOLTAGE
SENSE
VB
SFB
VC
AGND
TEMPERATURE
ERROR
AMPLIFIER
2kΩ
80kΩ
LDR
+
–
VB
LINEAR
AMPLIFIER
IN1P
PGNDL
VB
PGNDL
IN1N
80kΩ
OUT1
1.25V
20kΩ
20kΩ
400kΩ
SFB
PWM POWER
STAGE
100kΩ
COMPENSATION
AMPLIFIER
VC
20kΩ
IN2P
PWM
MODULATOR
20kΩ
IN2N
20kΩ
OUT2
40µA
VB
COOLING
HEATING
OSCILLATOR
SW
CLK
PGNDS
SHUTDOWN
10µA
VHIGH ≥ 2.1V
VLOW ≤ 0.8V
ITEC
TEC
CURRENT
LIMIT
0.07V
VLIM/SD
DEGLITCH
SHUTDOWN
ILIM
EN/SY
Figure 2. Detailed Functional Block Diagram of the ADN8835
Rev. B | Page 3 of 27
PGNDS
14174-002
CLK
PWM
MOSFET
DRIVER
PWM
ERROR
AMPLIFIER
VDD
TEC VOLTAGE
LIMIT AND INTERNAL
SOFT START
PVINS
ADN8835
Data Sheet
SPECIFICATIONS
VIN = 2.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless
otherwise noted.
Table 2.
Parameter
POWER SUPPLY
Driver Supply Voltage
Controller Supply Voltage
Supply Current
Shutdown Current
Undervoltage Lockout (UVLO)
UVLO Hysteresis
REFERENCE VOLTAGE
LINEAR OUTPUT
Output Voltage
Low
High
Maximum Source Current
Maximum Sink Current
On Resistance
P-MOSFET
N-MOSFET
Leakage Current
P-MOSFET
N-MOSFET
Linear Amplifier Gain
LDR Short-Circuit Threshold
Hiccup Cycle
PWM OUTPUT
Output Voltage
Low
High
Maximum Source Current
Maximum Sink Current
On Resistance
P-MOSFET
N-MOSFET
Leakage Current
P-MOSFET
N-MOSFET
SW Node Rise Time 1
PWM Duty Cycle 2
SFB Input Bias Current
PWM OSCILLATOR
Internal Oscillator Frequency
Symbol
Test Conditions/Comments
VPVIN
VVDD
IVDD
ISD
VUVLO
UVLOHYST
VVREF
PWM not switching
EN/SY = AGND or VLIM/SD = AGND
VVDD rising
VLDR
ILDR = 0 A
Min
Typ
Max
Unit
3.3
350
2.55
90
2.50
5.5
5.5
5
700
2.65
100
2.525
V
V
mA
µA
V
mV
V
3.5
V
V
A
A
50
55
45
50
70
85
80
90
mΩ
mΩ
mΩ
mΩ
0.1
0.1
40
4
−4
15
10
10
µA
µA
V/V
A
A
ms
2.7
2.7
IVREF = 0 mA to 10 mA
2.45
80
2.475
0
VPVIN
ILDR_SOURCE
ILDR_SINK
RDS_PL(ON)
RDS_NL(ON)
ILDR_P_LKG
ILDR_N_LKG
ALDR
ILDR_SH_GNDL
ILDR_SH_PVIN(L)
tHICCUP
VSFB
3.5
ILDR = 1.5 A
VPVIN = 5.0 V
VPVIN = 3.3 V
VPVIN = 5.0 V
VPVIN = 3.3 V
LDR short to PGNDL, enter hiccup
LDR short to PVIN, enter hiccup
ISFB = 0 A
3.5
V
V
V
A
A
60
70
45
55
85
100
85
95
mΩ
mΩ
mΩ
mΩ
0.1
0.1
1
10
10
1
93
2
µA
µA
ns
%
µA
2.0
2.15
MHz
0.06 × VPVIN
0.93 × VPVIN
ISW_SOURCE
ISW_SINK
3.5
ISW = 1.5 A
VPVIN = 5.0 V
VPVIN = 3.3 V
VPVIN = 5.0 V
VPVIN = 3.3 V
ISW_P_LKG
ISW_N_LKG
tSW_R
DSW
ISFB
CSW = 1 nF
fOSC
EN/SY high
RDS_PS(ON)
RDS_NS(ON)
6
Rev. B | Page 4 of 27
1.85
Data Sheet
Parameter
EN/SY Input Voltage
Low
High
External Synchronization Frequency
Synchronization Pulse Duty Cycle
EN/SY Rising to PWM Rising Delay
EN/SY to PWM Lock Time
EN/SY Input Current
Pull-Down Current
ERROR/COMPENSATION AMPLIFIERS
Input Offset Voltage
Input Voltage Range
Common-Mode Rejection Ratio (CMRR)
Output Voltage
High
ADN8835
Symbol
VEN/SY_ILOW
VEN/SY_IHIGH
fSYNC
DSYNC
tSYNC_PWM
tSY_LOCK
IEN/SY
VOS1
VOS2
VCM1, VCM2
CMRR1, CMRR2
Test Conditions/Comments
Min
Typ
2.1
1.85
10
Max
Unit
0.8
V
V
MHz
%
ns
Cycles
µA
µA
3.25
90
50
Number of sync cycles
0.3
0.3
VCM1 = 1.5 V, VOS1 = VIN1P − VIN1N
VCM2 = 1.5 V, VOS2 = VIN2P − VIN2N
10
10
0
VCM1, VCM2 = 0.2 V to VVDD − 0.2 V
VOH1, VOH2
11
0.5
0.5
100
100
VVDD
120
VVDD −
0.04
Low
Power Supply Rejection Ratio (PSRR)
Output Current
Gain Bandwidth Product1
TEC CURRENT LIMIT
ILIM Input Voltage Range
Cooling
VOL1, VOL2
PSRR1, PSRR2
IOUT1, IOUT2
GBW1, GBW2
VILIMC
1.3
Heating
Current-Limit Threshold
Cooling
Heating
ILIM Input Current
Heating
Cooling
Cooling to Heating Current Detection
Threshold
TEC VOLTAGE LIMIT
Voltage Limit Gain
VLIM/SD Input Voltage Range1
VLIM/SD Input Current
Cooling
Heating
TEC CURRENT MEASUREMENT
Current Sense Gain
Current Measurement Accuracy
ITEC Voltage Accuracy
ITEC Voltage Output Range
VILIMH
0.2
ITEC Bias Voltage
Maximum ITEC Output Current
TEC VOLTAGE MEASUREMENT
Voltage Sense Gain
VITEC_B
IITEC
V
10
mV
dB
mA
MHz
VVREF −
0.2
1.2
V
V
2.02
0.52
V
V
+0.2
42.5
µA
µA
mA
120
Sourcing and sinking
VOUT1, VOUT2 = 0.5 V to VVDD − 1 V
5
2
VILIMC_TH
VILIMH_TH
VITEC = 0.5 V
VITEC = 2 V
1.98
0.48
IILIMH
IILIMC
ICOOL_HEAT_TH
Sourcing current
−0.2
37.5
2.0
0.5
40
40
AVLIM
VVLIMC, VVLIMH
(VDRL − VSFB)/VVLIM
2
IILIMC
IILIMH
VOUT2 < VVREF/2
VOUT2 > VVREF/2, sinking current
−0.2
8
RCS
ILDR_ERROR
VITEC_AT_1_A
VITEC
1 A ≤ ILDR ≤ 3 A
Cooling, VVREF/2 + ILDR × RCS
ITEC = 0 A
15
1.493
0
ILDR = 0 A
1.210
−2
1.250
0.24
0.25
0.2
10
VVDD/2
V/V
V
+0.2
12
µA
µA
0.285
AVTEC
Rev. B | Page 5 of 27
µV
µV
V
dB
1.535
V/A
%
V
V
15
1.577
VVREF −
0.05
1.285
+2
V
mA
0.26
V/V
ADN8835
Data Sheet
Parameter
Voltage Measurement Accuracy
Symbol
VVTEC_AT_1_V
VTEC Output Voltage Range
VTEC Bias Voltage
Maximum VTEC Output Current
TEMPERATURE GOOD
TMPGD Output Voltage
Low
High
TMPGD Output Impedance
Low
High
Threshold
High
Low
INTERNAL SOFT START
Soft Start Time
VLIM/SD SHUTDOWN
Low Voltage Threshold
THERMAL SHUTDOWN
Threshold
Hysteresis
VVTEC
VVTEC_B
RVTEC
1
2
Test Conditions/Comments
VLDR − VSFB = 1 V, VVREF/2 + AVTEC ×
(VLDR − VSFB)
VLDR = VSFB
Min
1.475
Typ
1.50
Max
1.525
Unit
V
0.005
1.225
−2
1.250
2.625
1.285
+2
V
V
mA
0.4
V
V
No load
VTMPGD_LO
VTMPGD_HO
2.0
RTMPGD_LOW
RTMPGD_LOW
25
50
Ω
Ω
IN2N tied to OUT2, VIN2P = 1.5 V
VOUT1_THH
VOUT1_THL
1.40
tSS
1.54
1.46
1.56
150
VVLIM/SD_THL
ms
0.07
TSHDN_TH
TSHDN_HYS
170
17
This specification is guaranteed by design.
This specification is guaranteed by characterization.
Rev. B | Page 6 of 27
V
V
V
°C
°C
Data Sheet
ADN8835
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages, and is
based on a 4-layer standard JEDEC board.
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VPVINL
−0.3 V to +6 V
−0.3 V to VVDD
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to VVDD
−0.3 V to VVDD
−0.3 V to +3 V
−0.3 V to +6 V
−0.3 V to VVDD
−0.3 V to VVDD
−0.3 V to +6 V
−0.3 V to VVDD
−0.3 V to VVDD
−0.3 V to +6 V
−0.3 V to VVDD
−0.3 V to +6 V
−0.3 V to +6 V
Table 4. Thermal Resistance
Package Type
36-Lead LFCSP
θJA
33
ΨJT
1.2
ΨJB
12.3
Unit
°C/W
MAXIMUM POWER DISSIPATION
The maximum power that the ADN8835 can dissipate is limited
by the associated rise in junction temperature. The maximum
safe junction temperature for a plastic encapsulated device is
determined by the glass transition temperature of the plastic,
approximately 125°C. Exceeding this limit may cause a shift in
parametric performance or device failure.
The driver stage of the ADN8835 is designed for maximum
load current capability. To ensure proper operation, it is
necessary to observe the corresponding maximum power
derating curves.
3.5
TJ = 125°C
20 mA
50 mA
50 mA
50 mA
50 mA
125°C
−65°C to +150°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
3.0
2.5
2.0
1.5
1.0
0.5
0
30
40
50
60
70
80
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. B | Page 7 of 27
14174-003
MAXIMUM POWER DISSIPATION (W)
Parameter
PVINL to PGNDL
PVINS to PGNDS
LDR to PGNDL
SW to PGNDS
SFB to AGND
AGND to PGNDL
AGND to PGNDS
VLIM/SD to AGND
ILIM to AGND
VREF to AGND
VDD to AGND
IN1P to AGND
IN1N to AGND
OUT1 to AGND
IN2P to AGND
IN2N to AGND
OUT2 to AGND
EN/SY to AGND
ITEC to AGND
VTEC to AGND
Maximum Current
VREF to AGND
OUT1 to AGND
OUT2 to AGND
ITEC to AGND
VTEC to AGND
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
ADN8835
Data Sheet
36
35
34
33
32
31
30
29
28
DNC
DNC
IN2P
IN1P
IN1N
OUT1
TMPGD
PGNDL
PGNDL
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
ADN8835
TOP VIEW
(Not to Scale)
27
26
25
24
23
22
21
20
19
LDR
LDR
PVINL
PVINL
PVINS
PVINS
SW
SW
DNC
NOTES
1. DO NOT CONNECT. LEAVE THESE PINS PIN FLOATING.
2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE
ANALOG GROUND PLANE ON THE BOARD.
14174-004
DNC
DNC
AGND
EN/SY
VTEC
SFB
ITEC
PGNDS
PGNDS
10
11
12
13
14
15
16
17
18
DNC
DNC
IN2N
OUT2
VLIM/SD
ILIM
VDD
VREF
DNC
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
0
1, 2, 9, 10, 11, 19,
35, 36
3
4
5
Mnemonic
EPAD
DNC
Description
Exposed Pad. Solder the exposed pad to the analog ground plane on the board.
Do Not Connect. Leave these pins floating.
IN2N
OUT2
VLIM/SD
6
7
8
12
13
ILIM
VDD
VREF
AGND
EN/SY
14
15
16
17, 18
20, 21
22, 23
24, 25
26, 27
28, 29
30
31
32
33
34
VTEC
SFB
ITEC
PGNDS
SW
PVINS
PVINL
LDR
PGNDL
TMPGD
OUT1
IN1N
IN1P
IN2P
Inverting Input of the Compensation Amplifier.
Output of the Compensation Amplifier.
Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage limits. When this pin is pulled
low, the device shuts down.
Current Limit. This pin sets the TEC cooling and heating current limits.
Power for the Controller Circuits.
2.5 V Reference Output.
Signal Ground.
Enable/Synchronization. Set this pin high to enable the device. An external synchronization clock input
can be applied to this pin.
TEC Voltage Output.
Feedback of the PWM TEC Controller Output.
TEC Current Output.
Power Ground of the PWM TEC Controller.
Switch Node Output of the PWM TEC Controller.
Power Input for the PWM TEC Driver.
Power Input for the Linear TEC Driver.
Output of the Linear TEC Controller.
Power Ground of the Linear TEC Controller.
Temperature Good Output.
Output of the Error Amplifier.
Inverting Input of the Error Amplifier.
Noninverting Input of the Error Amplifier.
Noninverting Input of the Compensation Amplifier.
Rev. B | Page 8 of 27
Data Sheet
ADN8835
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
90
90
80
80
70
70
EFFICIENCY (%)
60
50
40
30
60
50
40
30
20
20
LOAD = 2Ω
LOAD = 1Ω
LOAD = 0.5Ω
0
0
0.5
1.0
1.5
2.0
2.5
3.0
TEC CURRENT (A)
VIN = 5V
VIN = 3.3V
10
0
14174-007
10
Figure 5. Efficiency vs. TEC Current at VIN = 3.3 V at Various Loads in Cooling
Mode
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TEC CURRENT (A)
14174-006
EFFICIENCY (%)
TA = 25°C, unless otherwise noted.
Figure 8. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Heating Mode
with 1 Ω Load
3.0
100
90
2.5
EFFICIENCY (%)
70
60
50
40
30
20
0
0.5
1.0
1.5
2.0
2.5
3.0
TEC CURRENT (A)
1.0
Figure 6. Efficiency vs. TEC Current at VIN = 3.3 V at Various Loads in Heating
Mode
LOAD = 2Ω
LOAD = 1Ω
LOAD = 0.5Ω
0
2.7
14174-008
0
1.5
0.5
LOAD = 2Ω
LOAD = 1Ω
LOAD = 0.5Ω
10
2.0
3.7
14174-009
MAXIMUM TEC CURRENT (A)
80
4.7
INPUT VOLTAGE AT PVIN (V)
Figure 9. Maximum TEC Current vs. Input Voltage at PVIN at Various Loads,
Without Voltage and Current Limit
0.20
100
90
0.15
80
0.10
VREF ERROR (%)
EFFICIENCY (%)
70
60
50
40
0.05
0
–0.05
30
–0.10
20
–0.15
0
0.5
1.0
1.5
2.0
TEC CURRENT (A)
2.5
3.0
3.5
Figure 7. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Cooling Mode
with 1 Ω Load
Rev. B | Page 9 of 27
–0.20
2.5
NO LOAD
5mA LOAD
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
Figure 10. VREF Line Regulation
5.5
6.0
14174-010
0
14174-005
VIN = 5V
VIN = 3.3V
10
ADN8835
Data Sheet
1.0
0.6
0.4
0.02
0.2
VREF (%)
0.04
0
–0.02
0
–0.2
–0.04
–0.4
–0.06
–0.6
–0.08
–0.8
–0.10
0
20
40
60
80
100
120
140
160
180
200
TIME (Seconds)
–1.0
0
1
Figure 11. Thermal Stability (TEMPOUT) Voltage Error at Various Ambient
Temperatures, VIN = 3.3 V, VTEMPSET = 1 V
ITEC CURRENT READING ERROR (%)
0.02
0
–0.02
–0.04
–0.06
–0.08
0
20
40
60
80
100
120
140
160
180
200
TIME (Seconds)
–5
–10
–15
VIN = 5V
VIN = 3.3V
0.5
1.0
1.5
2.0
2.5
3.0
20
NO LOAD
NO LOAD
NO LOAD
5mA LOAD
5mA LOAD
5mA LOAD
ITEC CURRENT READING ERROR (%)
VIN = 5.5V AT
VIN = 3.3V AT
VIN = 2.7V AT
VIN = 5.5V AT
VIN = 3.3V AT
VIN = 2.7V AT
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–50
0
Figure 15. ITEC Current Reading Error vs. TEC Current in Cooling Mode
0
50
100
AMBIENT TEMPERATURE (°C)
150
14174-013
VREF ERROR (%)
0.4
5
TEC CURRENT (A)
1.0
0.6
10
0
Figure 12. Thermal Stability (TEMPOUT) Voltage Error at Various Ambient
Temperatures, VIN = 3.3 V, VTEMPSET = 1.5 V
0.8
5
15
–20
14174-012
TEMPOUT (VOUT1) VOLTAGE ERROR (%)
0.04
–0.10
4
20
TA = 55°C
TA = 45°C
TA = 35°C
TA = 25°C
TA = 15°C
0.06
3
Figure 14. VREF Load Regulation
0.10
0.08
2
LOAD CURRENT AT VREF (mA)
14174-015
0.06
VIN = 5V, ITEC = 0.5A, HEATING
VIN = 5V, ITEC = 0A
VIN = 5V, ITEC = 0.5A, COOLING
VIN = 3.3V, ITEC = 0.5A, HEATING
VIN = 3.3V, ITEC = 0.0A
VIN = 3.3V, ITEC = 0.5A, COOLING
0.8
15
10
5
0
–5
–10
–15
VIN = 5V
VIN = 3.3V
–20
0
0.5
1.0
1.5
2.0
2.5
3.0
TEC CURRENT (A)
Figure 16. ITEC Current Reading Error vs. TEC Current in Heating Mode
Figure 13. VREF Error vs. Ambient Temperature
Rev. B | Page 10 of 27
14174-016
0.08
14174-014
TA = 55°C
TA = 45°C
TA = 35°C
TA = 25°C
TA = 15°C
14174-011
TEMPOUT (VOUT1) VOLTAGE ERROR (%)
0.10
Data Sheet
ADN8835
20
T
VTEC VOLTAGE READING ERROR (%)
15
LDO (TEC+)
10
5
4
0
TEC CURRENT
PWM (TEC–)
–5
1
–10
–15
0
1
2
3
4
TEC VOLTAGE (V)
Figure 17. VTEC Voltage Reading Error vs. TEC Voltage in Cooling Mode
CH1 1.00V BW CH2 1.00V BW
CH4 500mA Ω BW
20.0mA
1.0MS/s
1M POINTS
Figure 20. Zero-Crossing TEC Current Zoom In from Heating to Cooling
20
T
15
LDO (TEC+)
10
5
4
0
PWM (TEC–)
TEC CURRENT
–5
1
–10
–15
1
2
3
4
TEC VOLTAGE (V)
Figure 18. VTEC Voltage Reading Error vs. TEC Voltage in Heating Mode
CH1 1.00V BW CH2 1.00V BW
CH4 500mA Ω BW
M20.0ms
CH4
T
15.8000ms
20.0mA
5.0MS/s
1M POINTS
14174-021
0
14174-018
VIN = 5V
VIN = 3.3V
–20
Figure 21. Zero-Crossing TEC Current Zoom In from Cooling to Heating
T
ENABLE
LDO (TEC+)
3
TEC
CURRENT
4
PWM
(TEC–)
4
TEC CURRENT
LDO (TEC+)
1
PWM (TEC–)
CH1 1.00V BW CH2 1.00V BW
CH4 500mA Ω BW
M200ms
CH4
–500mA
500kS/s 1M POINTS
CH1 2.00V
CH3 5.00V
Figure 19. Cooling to Heating Transition
B
W
B
W
CH2 1.00V BW
CH4 1.00A Ω BW
M40.0ms
CH3
1.60V
2.50MS/s
T
79.6000ms
1M POINTS
Figure 22. Typical Enable Waveforms in Cooling Mode,
VIN = 5 V, Load = 1 Ω, TEC Current = 2 A
Rev. B | Page 11 of 27
14174-022
2
14174-019
VTEC VOLTAGE READING ERROR (%)
M20.0ms
CH4
T
15.1000ms
14174-020
–20
14174-017
VIN = 5V
VIN = 3.3V
ADN8835
Data Sheet
T
SW
T
ENABLE
3
3
TEC CURRENT
4
LDO (TEC+)
1
PWM (TEC–)
PWM (TEC–)
2
2
M40.0ms
CH3
1.90V
2.50MS/s
T
79.6000ms
1M POINTS
CH1 20.0mV BW CH2 20.0mV BW M400ns
CH3
2.24V
2.50GS/s
CH3 2.00V
T
4.0000ns
1M POINTS
Figure 23. Typical Enable Waveforms in Heating Mode,
VIN = 5 V, Load = 1 Ω, TEC Current = 2 A
SW
Figure 25. Typical Switch and Voltage Ripple Waveforms in Heating Mode,
VIN = 5 V, Load = 1 Ω, TEC Current = 2 A
T
3
LDO (TEC+)
1
PWM (TEC–)
14174-024
2
CH1 20.0mV BW CH2 20.0mV BW M400ns
CH3
2.24V
2.50GS/s
CH3 2.00V
T
4.0000ns
1M POINTS
14174-025
CH1 2.00V BW CH2 2.00V BW
CH3 5.00V BW CH4 1.00A Ω BW
14174-023
LDO (TEC+)
Figure 24. Typical Switch and Voltage Ripple Waveforms in Cooling Mode
VIN = 5 V, Load = 1 Ω, TEC Current = 2 A
Rev. B | Page 12 of 27
Data Sheet
ADN8835
THEORY OF OPERATION
The ADN8835 drives its internal MOSFET transistors to provide
the TEC current. To provide good power efficiency and zerocrossing quality, only one side of the H bridge uses a PWM
driver. Only one inductor and one capacitor are required to filter
out the switching frequency. The other side of the H bridge uses a
linear output without requiring any additional circuitry. This proprietary configuration allows the ADN8835 to provide efficiency of
>90%. For most applications, a 1 µH inductor, a 10 μF capacitor,
and a switching frequency of 2.0 MHz maintain less than 1% of the
worst-case output voltage ripple across a TEC.
The ADN8835 is a single-chip TEC controller that sets and
stabilizes a TEC temperature. A voltage applied to the input of
the ADN8835 corresponds to the temperature setpoint of the
target object attached to the TEC. The ADN8835 controls an
internal FET H bridge whereby the direction of the current fed
through the TEC can be either positive (for cooling mode) to
pump heat away from the object attached to the TEC, or
negative (for heating mode) to pump heat into the object attached
to the TEC.
Temperature is measured with a thermal sensor attached to the
target object, and the sensed temperature (voltage) is fed back
to the ADN8835 to complete a closed thermal control loop of
the TEC. For the best overall stability, couple the thermal sensor
close to the TEC. In most laser diode modules, a TEC and a
NTC thermistor are already mounted in the same package to
regulate the laser diode temperature.
The maximum voltage across the TEC and the current flowing
through the TEC are set by using the VLIM/SD and ILIM pins.
The maximum cooling and heating currents can be set independently to allow asymmetric heating and cooling limits. For
additional details, see the Maximum TEC Voltage Limit section
and the Maximum TEC Current Limit section.
The TEC is differentially driven in an H bridge configuration.
TEC
CURRENT
ENABLE/
SYNC
TEC
VOLTAGE
SHUTDOWN
EN/SY
ITEC
TMPGD
VTEC
VLIM/SD
TEC
CURRENT
LIMITS
PVINL
PVINS
TEC
VOLTAGE
LIMIT
RV2
RV1
RC2
CIN
10µF
LDR
ADN8835
RB
CL_OUT
0.1µF
–
SFB
AGND
RFB
RTH
THERMISTOR
+
PGNDL
CVREF
0.1µF
NTC
TEC
L = 1µH
IN2P
IN1P
IN1N
OUT1
IN2N
RI
RD CD
OUT2
SW
PGNDS
CSW_OUT
10µF
R P CI
CF
14174-026
RA
TEMP
SET
RX
VIN
2.7V TO 5.5V
ILIM
RC1
VREF
R
VDD
CVDD
0.1µF R
BP
Figure 26. Typical Application Circuit with Analog PID Compensation in a Temperature Control Loop
Rev. B | Page 13 of 27
ADN8835
Data Sheet
The Chopper 2 amplifier is used as a buffer for the external
DAC, which controls the temperature setpoint. Connect the
DAC to IN2P and short the IN2N and OUT2 pins together. See
Figure 27 for an overview of how to configure the ADN8835
external circuitry for digital PID control.
ANALOG PID CONTROL
The ADN8835 integrates two self correcting, auto-zeroing
amplifiers (Chopper 1 and Chopper 2). The Chopper 1 amplifier
takes a thermal sensor input and converts or regulates the input
to a linear voltage output. The OUT1 voltage is proportional to the
object temperature. The OUT1 voltage is fed into the compensation amplifier (Chopper 2) and is compared with a temperature
setpoint voltage, which creates an error voltage that is proportional to the difference. For autonomous analog temperature
control, Chopper 2 can implement a PID network as shown in
Figure 26 to set the overall stability and response of the thermal
loop. Adjusting the PID network optimizes the step response of
the TEC control loop. A compromised settling time and the
maximum current ringing become available when this
adjustment is done. To adjust the compensation network, see
the PID Compensation Amplifier (Chopper 2) section.
POWERING THE CONTROLLER
The ADN8835 operates at an input voltage range of 2.7 V to
5.5 V that is applied to the PVINS pins and PVINL pins. The
VDD pin is the input power for the driver and internal reference.
The PVINS and the PVINL input power pins are for the PWM
driver and the linear driver, respectively. Apply the same input
voltage to all power input pins. In some circumstances, an RC
low-pass filter can be added between the PVINS/PVINL and
the VDD pins to prevent high frequency noise from entering
VDD, as shown in Figure 27. The capacitor and resistor values
are typically 10 Ω and 0.1 µF, respectively.
When configuring the power supply to the ADN8835, keep in
mind that at high current loads, the input voltage may drop
substantially due to a voltage drop on the wires between the
front-end power supply and the PVINS and the PVINL pins.
Leave a proper voltage margin when designing the front-end
power supply to maintain the performance. Minimize the trace
length from the power supply to the PVINS and the PVINL
pins to help mitigate the voltage drop.
DIGITAL PID CONTROL
The ADN8835 can also be configured for use in a software
controlled PID loop. In this scenario, the Chopper 1 amplifier
can either be left unused or configured as a thermistor input
amplifier connected to an external temperature measurement
analog-to-digital converter (ADC). For more information, see
the Thermistor Amplifier (Chopper 1) section. If Chopper 1 is
left unused, tie IN1N and IN1P to AGND.
ENABLE
COOLING AND HEATING
TEC CURRENT LIMITS
2.5V VREF
TEC
VOLTAGE
LIMIT
2.5V VREF
RC1
RV1
RC2
CVDD
0.1µF
TMPGD
ILIM
EN/SY
PVINL
PVINS
VLIM/SD
RV2
RBP
VIN
2.7V TO 5.5V
CIN
10µF
IN2P
TEC CURRENT READBACK
TEC VOLTAGE READBACK
ITEC
LDR
ADN8835
VTEC
CL_OUT
0.1µF
TEC
+
PGNDL
2.5V VREF
VREF
R
RA
–
CVREF
0.1uF
AGND
IN1P
IN1N
RX
L = 1µH
OUT1
IN2N OUT2
RB
RFB
NTC
RTH
SFB
SW
PGNDS
FSW = 2MHz
CSW_OUT
10µF
THERMISTOR
2.5V VREF
TEMPERATURE
READBACK
ADC
Figure 27. TEC Controller in a Digital Temperature Control Loop
Rev. B | Page 14 of 27
14174-027
DAC
TEMPERATURE SET
VDD
Data Sheet
ADN8835
Connecting Multiple ADN8835 Devices
To enable the ADN8835, apply a logic high voltage to the
EN/SY pin while the voltage at the VLIM/SD pin is above the
maximum shutdown threshold of 0.07 V. If either the EN/SY pin
voltage is set to logic low or the VLIM/SD voltage is below 0.07 V,
the controller goes into an ultralow current state. The current
drawn in shutdown mode is 350 µA typically. Most of the current
is consumed by the VREF circuit block, which is always on even
when the device is disabled or shut down. The device can also
be enabled when an external synchronization clock signal is
applied to the EN/SY pin, and the voltage at VLIM/SD input is
above 0.07 V. Table 6 shows the combinations of the two input
signals that are required to enable the ADN8835.
ADN8835
EXTERNAL CLOCK
SOURCE
AGND
ADN8835
EN/SY
AGND
Table 6. Enable Pin Combinations
EN/SY Input
>2.1 V
Switching Between High
(>2.1 V) and Low (0.07 V
Controller
Enabled
Enabled
No effect1
No effect1
≤0.07 V
Shutdown
Shutdown
Shutdown
No effect means this signal has no effect in shutting down or in enabling the
device.
OSCILLATOR CLOCK FREQUENCY
The ADN8835 has an internal oscillator that generates a 2.0 MHz
switching frequency for the PWM output stage. This oscillator is
active when the enabled voltage at the EN/SY pin is set to a logic
level higher than 2.1 V and the VLIM/SD pin voltage is greater
than the shutdown threshold of 0.07 V.
External Clock Operation
The PWM switching frequency of the ADN8835 can be synchronized to an external clock from 1.85 MHz to 3.25 MHz, applied
to the EN/SY input pin, as shown on Figure 28.
ADN8835
EXTERNAL CLOCK
SOURCE
EN/SY
14174-028
AGND
Figure 28. Synchronize to an External Clock
EN/SY
14174-029
ENABLE AND SHUTDOWN
Multiple ADN8835 devices can be driven from a single master
clock signal by connecting the external clock source to the
EN/SY pin of each slave device. The input ripple can be greatly
reduced by operating the ADN8835 devices 180° out of phase from
each other and placing an inverter at one of the EN/SY pins, as
shown in Figure 29.
Figure 29. Multiple ADN8835 Devices Driven from a Master Clock
TEMPERATURE LOCK INDICATOR
The TMPGD pin outputs logic high when the temperature
error amplifier output voltage, VOUT1, reaches the IN2P
temperature setpoint (TEMPSET) voltage. The TMPGD pin has a
detection range between 1.46 V and 1.54 V of VOUT1 and hysteresis.
The TMPGD function allows direct interfacing either to the
microcontrollers or to the supervisory circuitry.
SOFT START ON POWER-UP
The ADN8835 has an internal soft start circuit that generates a
ramp with a typical 150 ms profile to minimize inrush current
during power-up. The settling time and the final voltage across
the TEC depends on the TEC voltage required by the control
voltage of voltage loop. The higher the TEC voltage is, the longer it
requires to increase.
When the ADN8835 is first powered up, the linear side discharges
the output of any prebias voltage. As soon as the prebias is eliminated, the soft start cycle begins. During the soft start cycle, both
the PWM and linear outputs track the internal soft start ramp
until they reach midscale, where the control voltage, VC, is equal
to the bias voltage, VB. From the midscale voltage, the PWM and
linear outputs are then controlled by VC and diverge from each
other until the required differential voltage is developed across
the TEC or the differential voltage reaches the voltage limit. The
voltage developed across the TEC depends on the control point
at that moment in time. Figure 30 shows an example of the soft
start profile in cooling mode. Note that, as both the LDR and SFB
voltages increase with the soft start ramp and approach VB, the
ramp slows to avoid possible current overshoot at the point
where the TEC voltage starts to increase.
Rev. B | Page 15 of 27
ADN8835
Data Sheet
LDR
REACH
VOLTAGE LIMIT
CLK
SFB
TEC VOLTAGE
BUILDS UP
TEC VOLTAGE
LIMIT AND
INTERNAL
SOFT START
VB
HEATING
SOFT START
BEGINS
TIME
DISABLE
RV1
Figure 30. Soft Start Profile in Cooling Mode
10µA
VLIM/SD
TEC VOLTAGE/CURRENT MONITOR
RV2
The TEC real-time voltage and current are detectable at VTEC
and ITEC, respectively.
Voltage Monitor
VTEC is an analog voltage output pin with a voltage proportional
to the actual voltage across the TEC. A center VTEC voltage of
1.25 V corresponds to 0 V across the TEC. Convert the voltage
at VTEC and the voltage across the TEC using the following
equation:
SW OPEN = VVLIMC
SW CLOSED = VVLIMH
14174-031
DISCHARGE
PREBIAS
14174-030
VREF
Figure 31. Using a Resistor Divider to Set the TEC Voltage Limit
Calculate the cooling and heating limits using the following
equations:
VVLIMC = VREF × RV2/(RV1 +RV2)
where VREF = 2.5 V.
VVLIMH = VVLIMC − ILIMH × RV1||RV2
where ILIMH = 10 µA.
VVTEC = 1.25 V + 0.25 × (VLDR − VSFB)
VTEC_MAX_COOLING = VVLIMC × AVLIM
Current Monitor
ITEC is an analog voltage output pin with a voltage proportional
to the actual current through the TEC. A center ITEC voltage of
1.25 V corresponds to 0 A through the TEC. Convert the
voltage at ITEC and the current through the TEC using the
following equations:
VITEC_COOLING = 1.25 V + ILDR × RCS
where the current sense gain (RCS) is 0.285 V/A.
where AVLIM = 2 V/V.
VTEC_MAX_HEATING = VVLIMH × AVLIM
MAXIMUM TEC CURRENT LIMIT
To protect the TEC, separate maximum TEC current limits in
cooling and heating directions are set by applying a voltage
combination at the ILIM pin.
Using a Resistor Divider to Set the TEC Current Limit
VITEC_HEATING = 1.25 V − ILDR × RCS
MAXIMUM TEC VOLTAGE LIMIT
The maximum TEC voltage is set by applying a voltage divider
at the VLIM/SD pin to protect the TEC. The voltage limiter
operates bidirectionally and allows the cooling limit to be
different from the heating limit.
Using a Resistor Divider to Set the TEC Voltage Limit
Separate voltage limits are set using a resistor divider. The
internal current sink circuitry connected to VLIM/SD draws a
current when the ADN8835 drives the TEC in a heating direction,
which lowers the voltage at VLIM/SD. The current sink is not
active when the TEC is driven in a cooling direction; therefore,
the TEC heating voltage limit is always lower than the cooling
voltage limit.
The internal current sink circuitry connected to ILIM draws a
40 µA current when the ADN8835 drives the TEC in a cooling
direction, which allows a high cooling current. Use the following
equations to calculate the maximum TEC currents:
VILIMH = VREF × RC2/(RC1 +RC2)
where VREF = 2.5 V.
VILIMC = VILIMH + ILIMC × RC1||RC2
where ILIMC = 40 µA.
ITEC _ MAX _ COOLING =
VILIMC − 1.25 V
RCS
where RCS = 0.285 V/A.
ITEC _ MAX _ HEATING =
1.25 V − VILIMH
RCS
VILIMH must not exceed 1.2 V and VILIMC must be more than
1.3 V to leave proper margins between the heating and the
cooling modes.
Rev. B | Page 16 of 27
Data Sheet
ADN8835
Figure 32. Using a Resistor Divider to Set the TEC Current Limit
VDD
40µA
VREF
COOLING
–
RC1
ITEC
RC2
+
TEC
CURRENT
LIMIT
SW OPEN = VILIMH
SW CLOSED = VILIMC
14174-032
ILIM
Rev. B | Page 17 of 27
ADN8835
Data Sheet
APPLICATIONS INFORMATION
TEC DRIVER
LINEAR POWER
STAGE
VIN
PVINL
–
+
TEC CURRENT SENSE
LDR
LDR
TEMPERATURE ERROR
AMPLIFIER
PID COMPENSATION
AMPLIFIER
AV = RFB/(RTH + RX) – RFB/R
AV = Z2/Z1
CHOPPER 1
CHOPPER 2
+
–
LINEAR
AMPLIFIER
PGNDL
TEC
+
PGNDL
–
IN2P
IN1P
OUT2
OUT1
IN1N
IN2N
SFB
CONTROL
PWM POWER
STAGE
VIN
PVINS
PWM
MODULATOR
PWM
MOSFET
DRIVER
SW
OSCILLATOR
R
OUT2
IN2N
IN2P
OUT1
VREF
IN1N
IN1P
PGNDS
PGNDS
VTEMPSET
VREF /2
Z1
RFB
Z2
RX
VOUT1
VOUT2
14174-033
RTH
Figure 33. Signal Flow Block Diagram
SIGNAL FLOW
The ADN8835 integrates two auto-zero amplifiers, defined as
the Chopper 1 amplifier and the Chopper 2 amplifier. Both of the
amplifiers can be used as standalone amplifiers; therefore, the
implementation of temperature control can vary. Figure 33
shows the signal flow through the ADN8835, and a typical
implementation of the temperature control loop using the
Chopper 1 amplifier and the Chopper 2 amplifier.
In Figure 33, the Chopper 1 and Chopper 2 amplifiers are configured as the thermistor input amplifier and the PID compensation
amplifier, respectively. The thermistor input amplifier amplifies
the thermistor voltage, and then outputs to the PID compensation amplifier. The PID compensation amplifier then compensates
a loop response over the frequency domain.
The output from the compensation loop at OUT2 is fed to the linear
MOSFET gate driver. The voltage at LDR is fed with OUT2 into
the PWM MOSFET gate driver. Including the internal transistors,
the gain of the differential output section is fixed at 5. For details
on the output drivers, see the MOSFET Driver Amplifier section.
THERMISTOR SETUP
The thermistor has a nonlinear relationship to temperature; near
optimal linearity over a specified temperature range can be achieved
with the proper value of a compensation resistor, RX, placed in
series with the thermistor.
First, the resistance of the thermistor must be known, where
•
•
•
RLOW = RTH at TLOW
RMID = RTH at TMID
RHIGH = RTH at THIGH
TLOW and THIGH are the endpoints of the temperature range and
TMID is the average. In some cases, with only the β constant
available, calculate RTH using the following equation:
Rev. B | Page 18 of 27
1
1
RTH = RR exp β −
T TR
Data Sheet
ADN8835
Z1 is the combination of RI, RD, and CD (see Figure 35).
Z2 is the combination of RP, CI, and CF (see Figure 35).
where:
RTH is a resistance at T (K).
RR is a resistance at TR (K).
Calculate RX using the following equation:
R
+ R MID RHIGH − 2RLOW RHIGH
R
R X = LOW MID
RLOW + RHIGH − 2R MID
The user sets the exact compensation network. This network
varies from a simple integrator to proportional integral (PI), PID,
or any other type of network. The user also determines the type of
compensation and component values because they are dependent
on the thermal response of the object and the TEC. One method to
empirically determine these values is to input a step function to
IN2P (thus changing the target temperature), and adjust the
compensation network to minimize the settling time of the TEC
temperature.
THERMISTOR AMPLIFIER (CHOPPER 1)
The Chopper 1 amplifier can be used as a thermistor input
amplifier. In Figure 33, the output voltage is a function of the
thermistor temperature. The voltage at OUT1 is expressed as:
V
RFB
R
VOUT1 =
− FB + 1 × REF
2
R
RTH + R X
where:
RFB is the feedback resistor.
RTH is a thermistor.
RX is a compensation resistor.
Calculate R using the following equation:
R = RX + RTH_AT_25°C
VOUT1 is centered around VVREF/2 at 25°C. An average temperature
to voltage coefficient is −25 mV/°C at a range of 5°C to 45°C.
A typical compensation network for temperature control of a laser
module is a PID loop consisting of a very low frequency pole and
two separate zeros at higher frequencies. Figure 35 shows a simple
network for implementing PID compensation. To reduce the noise
sensitivity of the control loop, an additional pole is added at a higher
frequency than that of the zeros. The bode plot of the magnitude is
shown in Figure 36. Use the following equation to calculate the
unity-gain crossover frequency of the feedforward amplifier:
2.5
f 0dB =
where TECGAIN is the symbolic gain of the TEC module.
VOUT1 (V)
2.0
1.5
1.0
5
25
45
65
TEMPERATURE (°C)
14174-034
0.5
0
–15
RFB
R
1
×
− FB × TECGAIN
2πR I C I RTH + R X
R
Figure 34. VOUT1 vs. Temperature
PID COMPENSATION AMPLIFIER (CHOPPER 2)
Use the Chopper 2 amplifier as the PID compensation amplifier.
The voltage at OUT1 feeds into the PID compensation amplifier.
The frequency response of the PID compensation amplifier is
dictated by the compensation network. Apply the temperature
set voltage at IN2P. In Figure 39, the voltage at OUT2 is
calculated using the following equation:
VOUT2 = VTEMPSET −
TECGAIN is critical to the mathematical design of the PID
loop. However, the thermal time constant of the TEC module is
usually unspecified, making it difficult to characterize
TECGAIN as well as the feedback transfer function. In this
case, the PID loop can be determined empirically by tuning the
components step by step. There are many documents written on
loop stabilization, and it is beyond the scope of this data sheet to
discuss all methods and trade-offs for optimizing compensation
networks.
VOUT1 is a convenient measure to gauge the thermal instability of
the system, which is also known as TEMPOUT. If the thermal loop
is in steady state, the TEMPOUT voltage equals the TEMPSET
voltage, meaning that the temperature of the controlled object
equals the target temperature.
Z2
(V − V
)
Z1 OUT1 TEMPSET
where:
VTEMPSET is the temperature setpoint voltage to the IN2P pin.
Rev. B | Page 19 of 27
ADN8835
Data Sheet
7.5
ADN8835
VVDD = 5.0V
VVDD = 3.3V
CHOPPER 2
IN2N
RP
RI
VTEMPSET
RD
CD
OUT2
2.5
CI
CF
PID COMPENSATOR
0
Figure 35. Implementing a PID Compensation Loop
–2.5
0
0.25
0.75
1.25
1.75
2.25
2.75
Figure 37. LDR Voltage vs. OUT2 Voltage
7.5
0dB
VVDD = 5.0V
VVDD = 3.3V
RP
RD || RI
5.0
SFB (V)
RP
RI
1
2π × RICI
1
2π × RPCI
1
1
2π × CD (RD + RI) 2π × RICD
FREQUENCY (Hz Log Scale)
2.5
14174-036
MAGNITUDE (Log Scale)
OUT2 (V)
14174-037
OUT1
14174-035
IN2P
LDR (V)
5.0
0
–2.5
MOSFET DRIVER AMPLIFIERS
0
0.25
0.75
1.25
1.75
2.25
2.75
OUT2 (V)
VLDR = VB − 80(VOUT2 − 1.25 V)
Figure 38. SFB Voltage vs. OUT2 Voltage
5.0
VVDD = 5.0V
VVDD = 3.3V
2.5
VTEC (V)
LDR – SFB
The ADN8835 has two separate MOSFET drivers: a switched
output or PWM amplifier, and a high gain linear amplifier. Each
amplifier has a pair of outputs that drive the gates of the internal
MOSFETs, which, in turn, drive the TEC as shown in Figure 33. A
voltage across the TEC is monitored via the SFB and LDR pins.
Although both MOSFET drivers achieve the same result, to
provide constant voltage and high current, their operation is
different. The exact equations for the two outputs are
14174-038
Figure 36. Bode Plot for PID Compensation
VSFB = VLDR + 5(VOUT2 − 1.25 V)
0
where:
VOUT2 is the voltage at OUT2.
VB is determined by VVDD as
–5.0
0
0.25
0.75
1.25
1.75
2.25
OUT2 (V)
VB = 1.5 V for VVDD < 4.0 V
2.75
14174-039
–2.5
Figure 39. TEC Voltage (LDR – SFB) vs. OUT2 Voltage
VB = 2.5 V for VVDD > 4.0 V
The compensation network that receives the temperature set voltage
and the thermistor voltage fed by the input amplifier determines
the voltage at OUT2. VLDR and VSFB have a low limit of 0 V and
an upper limit of VVDD. Figure 37, Figure 38, and Figure 39
show the graphs of these equations.
PWM OUTPUT FILTER REQUIREMENTS
A Type III compensator internally compensates the PWM
amplifier. Because the poles and zeros of the compensator are
designed and fixed by assuming the resonance frequency of the
output LC tank is 50 kHz, the selection of the inductor and the
capacitor must follow this guideline to ensure system stability.
Rev. B | Page 20 of 27
Data Sheet
ADN8835
Inductor Selection
Capacitor Selection
The inductor selection determines the inductor current ripple and
loop dynamic response. Larger inductance results in smaller
current ripple and slower transient response because smaller
inductance results in the opposite performance. To optimize the
performance, the trade-off must be made between transient
response speed, efficiency, and component size. Calculate the
inductor value with the following equation:
The output capacitor selection determines the output voltage
ripple, transient response, as well as the loop dynamic response
of the PWM amplifier output. Use the following equation to
select the capacitor:
L=
VSW _ OUT × (VIN – VSW _ OUT )
VIN × f SW × ∆I L
where:
VSW_OUT is the PWM amplifier output.
fSW is the switching frequency (2 MHz by default).
∆IL is the inductor current ripple.
Except for the inductor value, the equivalent dc resistance (DCR)
inherent in the metal conductor is also a critical factor for
inductor selection. The DCR accounts for most of the power loss
on the inductor by DCR × IOUT2. Using an inductor with high
DCR degrades the overall efficiency significantly. In addition,
there is a conduct voltage drop across the inductor because of
the DCR. When the PWM amplifier is sinking current in cooling
mode, this voltage drives the minimum voltage of the amplifier
higher than 0.06 × VPVIN by at least tenth of millivolts. Similarly, the
maximum PWM amplifier output voltage is lower than 0.93 ×
VPVIN.
This voltage drop is proportional to the value of the DCR, and
reduces the output voltage range at the TEC.
When selecting an inductor, ensure that the saturation current
rating is higher than the maximum current peak to prevent saturation. In general, ceramic multilayer inductors are suitable for low
current applications due to small size and low DCR. When the
noise level is critical, use a shielded ferrite inductor to reduce the
electromagnetic interference (EMI).
Table 7. Recommended Inductors
Murata
Value
1.0 μH ±
20%
1.0 μH ±
20%
VSW _ OUT × (VIN – VSW _ OUT )
VIN × 8 × L × ( f SW )2 × ∆VOUT
Note that the voltage caused by the product of current ripple,
ΔIL, and the capacitor equivalent series resistance (ESR) also
add up to the total output voltage ripple. Selecting a capacitor
with low ESR can increase overall regulation and efficiency
performance.
Table 8. Recommended Output Capacitors
A 1 µH inductor is typically recommended to allow reasonable
output capacitor selection while maintaining a low inductor
current ripple. If lower inductance is required, a minimum
inductor value of 0.68 µH is suggested to ensure that the current
ripple is set to a value between 30% and 40% of the maximum
load current.
Vendor
Coilcraft
C=
Device No.
XFL4020-102MEB
Footprint (mm)
4.3 × 4.3
DFE252012P-1R0M
2.5 × 2.0
Vendor
Murata
Murata
Taiyo
Yuden
Value
10 µF ±
10%, 10 V
10 µF ±
20%, 10 V
10 µF ±
20%, 10 V
Device No.
ZRB18AD71A106KE01L
Footprint
(mm)
1.6 × 0.8
GRM188D71A106MA73
1.6 × 0.8
LMK107BC6106MA-T
1.6 × 0.8
INPUT CAPACITOR SELECTION
On the PVIN pin, the amplifiers require an input capacitor
to decouple the noise and to provide the transient current to
maintain a stable input and output voltage. A 10 µF ceramic
capacitor rated at 10 V is the minimum recommended value.
Increasing the capacitance reduces the switching ripple that
couples into the power supply but increases the capacitor size.
Because the current at the input terminal of the PWM amplifier
is discontinuous, a capacitor with low effective series inductance
(ESL) is preferred to reduce voltage spikes.
In most applications, a decoupling capacitor is used in parallel
with the input capacitor. The decoupling capacitor is usually a
100 nF ceramic capacitor with very low ESR and ESL, which
provides better noise rejection at high frequency bands.
POWER DISSIPATION
This section provides guidelines to calculate the power
dissipation of the ADN8835. Approximate the total power
dissipation in the device by
PLOSS = PPWM + PLINEAR
where:
PPWM is the power dissipation in the PWM regulator.
PLOSS is the total power dissipation in the ADN8835.
PLINEAR is the power dissipation in the linear regulator.
PWM Regulator Power Dissipation
The PWM power stage is configured as a buck regulator and
its dominant power dissipation (PPWM) includes power switch
Rev. B | Page 21 of 27
ADN8835
Data Sheet
conduction losses (PCOND), switching losses (PSW), and transition
losses (PTRAN). Other sources of power dissipation are usually
less significant at the high output currents of the application
thermal limit and can be neglected in approximation.
Use the following equation to estimate the power dissipation of
the buck regulator:
PLOSS = PCOND + PSW + PTRAN
Conduction Loss (PCOND)
The conduction loss consists of two parts: inductor conduction
loss (PCOND_L) and power switch conduction loss (PCOND_S).
PCOND = PCOND_L + PCOND_S
Inductor conduction loss is proportional to the DCR of the output
inductor, L. Using an inductor with low DCR enhances the overall
efficiency performance. Estimate inductor conduction loss by
PCOND_L = DCR × IOUT2
Power switch conduction losses are caused by the flow of the
output current through both the high-side and low-side power
switches, each of which has its own internal on resistance (RDSON).
Use the following equation to estimate the amount of power
switch conduction loss:
PCOND_S = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT2
where:
RDSON_HS is the on resistance of the high-side MOSFET.
D is the duty cycle (D = VOUT/VIN).
RDSON_LS is the on resistance of the low-side MOSFET.
drain voltage of the MOSFET is half the input voltage, resulting
in power loss. Transition losses increase with both load and input
voltage and occur twice for each switching cycle.
Use the following equation to estimate the transition loss:
PTRAN = 0.5 × VPVIN × IOUT × (tR + tF) × fSW
where:
VPVIN is the voltage at PVIN.
IOUT is the output current of the PWM regulator.
tR is the rise time of the switch node.
tF is the fall time of the switch node.
Linear Regulator Power Dissipation
In the ADN8835, the output voltage of linear regulator is
typically tied either to ground or VIN. The main power
dissipation in this case comes from the conduction loss of the
FETs and thus is quite low. When the load is light and the linear
regulator must operate in a linear region, the power dissipation
can be calculated using the following equation:
PLINEAR = ((VIN − VOUT) × IOUT) + (VIN × IGND)
where:
VIN and VOUT are the input and output voltages of the linear
regulator.
IOUT is the load current of the linear regulator.
IGND is the ground current of the linear regulator.
Power dissipation due to the ground current is generally small
and can be ignored for the purposes of this calculation.
THERMAL CONSIDERATION
Switching Losses (PSW)
Switching losses are associated with the current drawn by the
controller to turn the power devices on and off at the switching
frequency. Each time a power device gate is turned on or off,
the controller transfers a charge from the input supply to the
gate, and then from the gate to ground. Use the following
equation to estimate the switching loss:
PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW
where:
CGATE_HS is the gate capacitance of the high-side MOSFET.
CGATE_LS is the gate capacitance of the low-side MOSFET.
fSW is the switching frequency.
For the ADN8835, the total of CGATE_HS + CGATE_LS is
approximately 1 nF.
To ensure that the ADN8835 operates below the maximum
junction temperature even at high load, careful attention must
be paid to provide a lower θJA value of the device. Typical
techniques for enhancing heat dissipation include using larger
copper layer and vias on the printed circuit board (PCB) and
adding a heat sink.
The ADN8835 LFCSP package has a large exposed pad (EPAD)
at the bottom that must be soldered to the analog ground plane
on the board. The majority of the heat of the device dissipates
through the EPAD. Therefore, the copper layer connected to the
EPAD as well as the vias on it must be optimized to conduct the
heat effectively. It is recommended to use at least a 6 × 6 via
array and distribute them evenly on the EPAD. Generally, it is
more effective to increase the number of vias than to increase
the diameter of the via within a limited area.
Transition Losses (PTRAN)
Transition losses occur because the high-side MOSFET cannot
turn on or off instantaneously. During a switch node transition,
the MOSFET provides all the inductor current. The source to
Rev. B | Page 22 of 27
Data Sheet
ADN8835
PCB LAYOUT GUIDELINES
TARGET
TEMPERATURE
TEC
VOLTAGE
SENSING
TEC
VOLTAGE
LIMITING
TEMPERATURE
ERROR
COMPENSATION
TEC
DRIVER
TEMPERATURE
SIGNAL
CONDITIONING
TEC
CURRENT
LIMITING
OBJECT
THERMOELECTRIC
COOLER
TEMPERATURE
(TEC)
SENSOR
TEC
CURRENT
SENSING
14174-040
SOURCE OF
ELECTRICAL
POWER
Figure 40. System Block Diagram
BLOCK DIAGRAMS AND SIGNAL FLOW
The ADN8835 integrates analog signal conditioning blocks, a
load protection block, and a TEC controller power stage, all in a
single IC. To achieve the best possible circuit performance,
attention must be paid to keep the noise of the power stage from
contaminating the sensitive analog conditioning and protection
circuits. In addition, the layout of the power stage must be
performed such that the IR losses are minimized to obtain the
best possible electrical efficiency.
The system block diagram of the ADN8835 is shown in Figure 40.
GUIDELINES FOR REDUCING NOISE AND
MINIMIZING POWER LOSS
Each PCB layout is unique because of the physical constraints
defined by the mechanical aspects of a given design. In addition,
several other circuits work in conjunction with the TEC
controller; these circuits have their own layout requirements.
Therefore, there are always compromises that must be made for a
given system. However, to minimize noise and keep power losses
to a minimum during the PCB layout process, observe the
following guidelines.
General PCB Layout Guidelines
Switching noise can interfere with other signals in the system;
therefore, the switching signal traces must be placed away from
the power stage to minimize the effect. If possible, place the
ground plate between the small signal layer and power stage
layer as a shield.
Supply voltage drop on traces is also an important consideration
because it determines the voltage headroom of the TEC controller
at high currents. For example, if the supply voltage from the frontend system is 3.3 V, and the voltage drop on the traces is 0.5 V,
PVIN sees only 2.8 V, which limits the maximum voltage of the
linear regulator as well as the maximum voltage across the TEC. To
mitigate the voltage waste on traces and impedance interconnection, place the ADN8835 and the input decoupling components
close to the supply voltage terminal. This placement not only
improves the system efficiency but also provides better regulation
performance at the output.
To prevent the noise signal from circulating through the ground
plates, reference all of the sensitive analog signals to AGND and
connect AGND to PGNDS using only a single-point connection.
This connection ensures that the switching currents of the power
stage do not flow into the sensitive AGND node.
PWM Power Stage Layout Guidelines
The PWM power stage consists of a MOSFET pair that forms a
switch mode output that switches current from PVINS to the
load via an LC filter. The ripple voltage on the PVINS pin is
caused by the discontinuous current switched by the PWM side
MOSFETs. This rapid switching causes voltage ripple to form at
the PVINS input, which must be filtered using a bypass capacitor. Place a 10 µF capacitor as close as possible to the PVINS pin
to connect PVINS to PGNDS. Because the 10 µF capacitor is
sometimes bulky and has higher ESR and ESL, a 100 nF decoupling capacitor is usually used in parallel with it, placed between
PVINS and PGNDS.
Because the decoupling is part of the pulsating current loop,
which carries high di/dt signals, the traces must be short and
wide to minimize the parasitic inductance. As a result, this
capacitor is usually placed on the same side of the board as the
ADN8835 to ensure short connections. If the layout requires
that a 10 µF capacitor be on the opposite side of the PCB, use
multiple vias to reduce via impedance.
The layout around the SW node is also critical because it switches
between PVINS and ground rapidly, which makes this node a
strong EMI source. Keep the copper area that connects the SW
node to the inductor small to minimize parasitic capacitance
between the SW node and other signal traces. The small copper
area helps minimize noise on the SW node due to excessive
charge injection. However, in high current applications, the
copper area can be increased reasonably to provide a heat sink
and to sustain high current flow.
Rev. B | Page 23 of 27
ADN8835
Data Sheet
must be paid when placing the external components with these
circuits.
Connect the ground side of the capacitor in the LC filter as close as
possible to PGNDS to minimize the ESL in the return path.
Place the thermistor conditioning and PID circuit components
close to each other near the inputs of Chopper 1 and Chopper 2.
Avoid crossing paths between the amplifier circuits and the
power stages to prevent noise pickup on the sensitive nodes.
Always reference the thermistor to AGND to have the cleanest
connection to the amplifier input and to avoid any noise or
offset buildup.
Linear Power Stage Layout Guidelines
The linear power stage consists of a MOSFET pair that forms a
linear amplifier, which operates in linear mode for very low output
currents, and changes to fully enhanced mode for greater
output currents.
EXAMPLE PCB LAYOUT USING TWO LAYERS
Because the linear power stage does not switch currents rapidly
like the PWM power stage, it does not generate noise currents.
However, the linear power stage still requires a minimum
amount of bypass capacitance to decouple its input.
Figure 41, Figure 42, and Figure 43 show an example ADN8835
PCB layout that uses two layers. This layout example achieves a
small solution size of approximately 20 mm2 with all of the
conditioning circuitry and PID included. Using more layers and
blinds via allows the solution size to be reduced even further
because more of the discrete components can relocate to the
bottom side of the PCB.
Place a 100 nF capacitor that connects from PVINL to PGNDL
as close as possible to the PVINL pin.
Placing the Thermistor Amplifier and PID Components
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
The thermistor conditioning and PID compensation amplifiers
work with very small signals and have gain; therefore, attention
RD
0201
R FB
0201
RX
0201
R
0201
RB
0201
1.0
RA
0201
0
CD
0201
CF
0201
RI
0201
RP
0201
CI
NTC
0402
2.0
TEMPSE T
LDR
C L_OUT
0201
PGNDL
PGNDL
DNC
TMPGD
OUT1
IN1N
IN1P
IN2P
DNC
3.0
DNC
PGND
IN2N
PVINL
OUT2
0402
040
02
IIN
C PV INS
1616
DNC
L
PGNDS
PGNDS
C VREF
0201
8.0
ITEC
SW
SFB
VREF
DNC
VTEC
SW
AGND
PVINS
DNC
ILIM
VDD
DNC
R C2
0201
R C1
0201
7.0
VIN
PVINS
C PVINS
0201
VLIM/SD
6.0
TEC–
PVINL
ADN8835
EN/SY
R V1
0201
R V2
0201
5.0
LDR
C PVINL
0201
TEC+
4.0
DNC
AGND
10.0
0402
14174-041
ITEC
C SW_OUT
C VDD
0201
9.0
R BP
0201
VTEC
UNITS = (mm)
Figure 41. Example PCB Layout Using Two Layers (Top and Bottom Layers)
Rev. B | Page 24 of 27
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
ADN8835
0
Data Sheet
RD
0201
R FB
0201
RX
0201
R
0201
RB
0201
1.0
RA
0201
0
CD
0201
CF
0201
RI
0201
RP
0201
CI
NTC
0402
2.0
TEMPSE T
LDR
C L_OUT
0201
PGNDL
PGNDL
DNC
TMPGD
OUT1
IN1N
IN1P
IN2P
DNC
3.0
DNC
PGND
TEC+
DNC
LDR
IN2N
PVINL
OUT2
PVINL
ADN8835
DNC
L
PGNDS
8.0
C VREF
0201
DNC
PGNDS
SW
ITEC
VREF
SFB
SW
VTEC
VDD
AGND
PVINS
DNC
7.0
VIN
PVINS
ILIM
DNC
R C2
0201
R C1
0201
6.0
TEC–
1616
VLIM/SD
EN/SY
R V1
0201
5.0
R V2
0201
4.0
AGND
10.0
0402
14174-042
ITEC
C SW_OUT
C VDD
0201
9.0
R BP
0201
VTEC
UNITS = (mm)
Figure 42. Example PCB Layout Using Two Layers (Top Layer Only)
Rev. B | Page 25 of 27
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
Data Sheet
0
ADN8835
RD
0201
R FB
0201
RX
0201
R
0201
RB
0201
1.0
RA
0201
0
NTC
2.0
TEMPSE T
PGNDL
PGNDL
DNC
TMPGD
OUT1
IN1N
IN1P
IN2P
DNC
3.0
DNC
PGND
LDR
LDR
IN2N
PVINL
OUT2
PVINL
ADN8835
8.0
PGNDS
C VREF
0201
DNC
PGNDS
VIN
0402
C PV INS
SW
ITEC
VREF
SFB
SW
VTEC
VDD
AGND
PVINS
DNC
7.0
ILIM
DNC
R C2
0201
R C1
0201
6.0
TEC–
PVINS
C PVINS
0201
VLIM/SD
EN/SY
R V1
0201
R V2
0201
5.0
DNC
C PVINL
0201
TEC+
4.0
DNC
AGND
9.0
10.0
14174-043
ITEC
R BP
0201
VTEC
UNITS = (mm)
Figure 43. Example PCB Layout Using Two Layers (Bottom Layer Only)
Rev. B | Page 26 of 27
Data Sheet
ADN8835
OUTLINE DIMENSIONS
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
0.30
0.23
0.18
PIN 1
INDICATOR
28
36
27
1
0.50
BSC
4.80
4.70 SQ
4.60
EXPOSED
PAD
9
19
0.80
0.75
0.70
SIDE VIEW
PKG-005013
SEATING
PLANE
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
18
10
BOTTOM VIEW
4.00 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-4
12-01-2015-A
TOP VIEW
0.45
0.40
0.35
Figure 44. 36-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.75 mm Package Height
(CP-36-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADN8835ACPZ-R7
ADN8835CP-EVALZ
ADN8834MB-EVALZ3
Temperature
Range2
−40°C to +125°C
Package Description
36-Lead Lead Frame Chip Scale Package [LFCSP]
36-Lead LFCSP Evaluation Board: 3 A (Source/Sink) TEC Current Limit, 5 V TEC
Voltage Limit
Evaluation Board
Z = RoHS Compliant Part.
Operating junction temperature range. The ambient operating temperature range is −40°C to +85°C.
3
The ADN8834MB-EVALZ evaluation board can be used with the ADN8835CP-EVALZ to evaluate the ADN8835 product.
1
2
©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14174-0-9/18(B)
Rev. B | Page 27 of 27
Package
Option
CP-36-5
