ADP1031ACPZ-1-R7

Three-Channel, Isolated Micropower Management Unit with Seven Digital Isolators ADP1031 Data Sheet TYPICAL APPLICATION CIRCUIT Wide input supply voltage range: 4.5 V to 60 V Integrated flyback power switch Generates isolated, independent bipolar outputs and factory programmable buck output VOUT1: 21 V, 24 V or 6 V to 28 V VOUT2: 5.15 V, 5.0 V, or 3.3 V VOUT3: −24 V to −5 V Uses a 1:1 ratio transformer for simplified transformer design Peak current limiting and OVP for flyback, buck, and inverting regulators Precision enable input and power-good output Adjustable switching frequency via SYNC input Internal compensation and soft start control per regulator High speed, low propagation delay, SPI signal isolation channels Three, 100 kbps general-purpose isolated data channels 9 mm × 7 mm LFCSP form factor enables small overall solution size −40°C to +125°C operating junction temperature range Conforms to CISPR11 Class B radiated emission limits Safety and regulatory approvals (pending) UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A 300 V rms basic insulation between slave, master, and field power domains (IEC 61010-1, pending) VDE certificate of conformity DIN V VDE 0884-10 (VDE 0884-10):2006-12 VIORM = 565 VPEAK APPLICATIONS Industrial automation and process control Instrumentation and data acquisition systems Data and power isolation GENERAL DESCRIPTION The ADP1031 is a high performance, isolated micropower management unit (PMU) that combines an isolated flyback dc-to-dc regulator, an inverting dc-to-dc regulator, and a buck dc-to-dc regulator, providing three isolated power rails. Additionally, the ADP1031 contains four, high speed, serial peripheral interface (SPI) isolation channels and three generalpurpose isolators for channel to channel applications where low power dissipation and small solution size is required. Rev. A VINP 4.5V TO 60V 1:1 Tx1 SWP VINP CIN R3 R2 PGNDP VOUT1 6V TO 28V D1 RFT1 CFLYBK RFB1 FB1 SGND2 VOUT1 ADP1031 VOUT2 SW2 CBUCK L1 VOUT3 –24V TO –5V PGNDP GNDP VOUT3 SLEW FB3 SW3 ISOLATED GPIO CHANNELS AND SPI INTERFACE RFB3 L2 RFT3 CINV ISOLATED GPIO CHANNELS AND SPI INTERFACE PWRGD MVDD 2.3V TO 5.5V VOUT2 3.3V, 5V, 5.15V SYNC EN SVDD2 R1 SGND2 MVDD C3 SVDD 1.8V TO 5.5V SVDD1 C1 MGND SGND1 C4 16434-101 FEATURES Figure 1. Operating over an input voltage range of +4.5 V to +60 V, the ADP1031 generates isolated output voltages of +6 V to +28 V (adjustable version) or+ 21 V and +24 V (fixed versions) for VOUT1, factory programmable voltages of +5.15 V, +5.0 V, or +3.3 V for VOUT2, and an adjustable output voltages of −24 V to −5 V for VOUT3. By default, the ADP1031 flyback regulator operates at a 250 kHz switching frequency and the buck and inverting regulators operate at 125 kHz. All three regulators are phase shifted relative to each other to reduce electromagnetic interference (EMI). The ADP1031 can be driven by an external oscillator in the range of 350 kHz to 750 kHz to ease noise filtering in sensitive applications. The digital isolators integrated in the ADP1031 use Analog Devices, Inc., iCoupler® chip scale transformer technology, optimized for low power and low radiated emissions. The ADP1031 is available in a 9 mm × 7 mm, 41-lead LFCSP and is rated for a −40°C to +125°C operating junction temperature range. COMPANION PRODUCTS Analog Output DAC: AD5758 Precision Data Acquisition Subsystem: AD7768-1 Additional companion products on the ADP1031 product page Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP1031 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Buck Regulator ........................................................................... 25  Applications ....................................................................................... 1  Inverting Regulator .................................................................... 26  General Description ......................................................................... 1  Power Good ................................................................................ 26  Typical Application Circuit ............................................................. 1  Power-Up Sequence ................................................................... 26  Companion Products ....................................................................... 1  Oscillator and Synchronization ................................................ 26  Revision History ............................................................................... 2  Thermal Shutdown .................................................................... 27  Specifications..................................................................................... 3  Data Isolation .............................................................................. 27  Regulatory Information ............................................................... 7  Applications Information .............................................................. 29  Electromagnectic Compatibility................................................. 8  Component Selection ................................................................ 29  Insulation and Safety Related Specifications ............................ 8  Flyback Regulator Components Selection .............................. 30  DIN V VDE 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 9  Buck Regulator Components Selection ................................... 33  Absolute Maximum Ratings.......................................................... 10  Insulation Lifetime ..................................................................... 34  Thermal Resistance .................................................................... 10  Thermal Analysis ....................................................................... 35  ESD Caution ................................................................................ 10  Typical Application Circuit ....................................................... 36  Pin Configuration and Function Descriptions ........................... 11  PCB Layout Considerations .......................................................... 37  Typical Performance Characteristics ........................................... 13  Outline Dimensions ....................................................................... 38  Theory of Operation ...................................................................... 23  Ordering Guide .......................................................................... 38  Inverting Regulator Component Selection ............................. 33  Flyback Regulator ....................................................................... 24  REVISION HISTORY 12/2019—Rev. 0 to Rev. A Changes Table 9 .............................................................................. 11 Changes to Figure 48 and Figure 51 ............................................. 20 Changes to Figure 52 to Figure 57 ................................................ 21 Changes to Figure 58 to Figure 63 ................................................ 22 Changes to Insulation Lifetime Section ....................................... 34 Added Surface Tracking Section, Insulation Wear Out Section, Equation 1 and Equation 2; Renumbered Sequentially, Calculation and Use of Parameters Example Section, and Figure 75; Renumbered Sequentially ............................................................. 35 Changes to Figure 76...................................................................... 36 Updated Outline Dimensions ....................................................... 38 Changes to Ordering Guide .......................................................... 38 1/2019—Revision 0: Initial Version Rev. A | Page 2 of 38 Data Sheet ADP1031 SPECIFICATIONS VINP voltage (VINP) = 24 V, MVDD voltage (VMVDD) = 3.3 V, SVDDx voltage (VSVDDx) = 3.3 V, VOUT1 voltage (VOUT1) = 24 V, VOUT2 voltage (VOUT2) = 5.15 V, VOUT3 voltage (VOUT3) = −15 V, and TA = 25°C for typical specifications. Minimum and maximum specification apply over the entire operating range of 4.5 V ≤ VINP ≤ 60 V, 2.3 V ≤ VMVDD ≤ 5.5 V, 1.8 V ≤ VSVDDx ≤ 5.5 V, and −40°C ≤ TJ ≤ +125°C, unless otherwise noted. Table 1. Parameter INPUT SUPPLY VOLTAGE RANGE VINP MVDD SVDDx OUTPUT POWER AND EFFICIENCY Total Output Power Symbol Min VINP VMVDD VSVDDx 4.5 2.3 1.8 SPI Low Power Mode SVDD1 SPI Active Mode SPI Low Power Mode SVDD2 UVLO VINP Rising Threshold Falling Threshold Hysteresis MVDD Rising Threshold Falling Threshold Hysteresis Unit 60 5.5 5.5 V V V Test Conditions/Comments Applies to SVDD1 and SVDD2 Transformer = 750316743 VOUT1 current (IOUT1) = 70 mA, VOUT2 current (IOUT2) = 7 mA, VOUT3 current (IOUT3) = −0.3 mA IOUT1 = 20 mA, IOUT2 = 7 mA, IOUT3 = −0.3 mA IOUT1 = 70 mA, IOUT2 = 7 mA, IOUT3 = −0.3 mA IOUT1 = 20 mA, IOUT2 = 7 mA, IOUT3 = −0.3 mA IOUT1 = 70 mA, IOUT2 = 7 mA, IOUT3 = −0.3 mA IOUT1 = 20 mA, IOUT2 = 7 mA, IOUT3 = −0.3 mA mW 520 mW 88.8 % 84.8 % 216.5 mW 93.1 mW IQ_VINP 1.77 mA ISHDN_VINP 125 175 µA Normal operation, VOUT1, VOUT2, VOUT3 = no load EN voltage (VEN) = 0 V IQ_MVDD (SPI_ACTIVE) 4.1 9.2 1.6 1.6 6.5 14 2.5 2.5 mA mA mA mA VIx 1 = logic low, MSS = logic low VIx1 = logic high, MSS = logic low VIx1 = logic low, MSS = logic high VIx1 = logic high, MSS = logic high 1.8 5.7 1.8 1.8 39 2 2.7 8.6 2.7 2.7 85 2.5 mA mA mA mA µA mA VIx1 = logic low, SSS = logic low VIx1 = logic high, SSS = logic low VIx1 = logic low, SSS = logic high VIx1 = logic high, SSS = logic high VIx1 = logic low VIx1 = logic high 4.49 4.29 4.44 4.34 100 V V mV 2.28 1.9 2.14 2 140 V V mV Power Dissipation Shutdown Current MVDD SPI Active Mode Max 1720 Efficiency QUIESCENT CURRENT VINP Operating Current Typ IQ_MVDD (SPI_LOWPWR) IQ_SVDD1 (SPI_ACTIVE) IQ_SVDD1 (SPI_LOWPWR) IQ_SVDD2 Relative to PGNDP VUVLO_FLYBACK (RISE) VUVLO_FLYBACK (FALL) Relative to MGND VUVLO_MVDD (RISE) VUVLO_MVDD (FALL) Rev. A | Page 3 of 38 ADP1031 Parameter THERMAL SHUTDOWN Threshold Hysteresis PRECISION ENABLE Rising Input Threshold Input Hysteresis Leakage Current POWER GOOD Power-Good Threshold Flyback Regulator Lower Limit Upper Limit Buck Regulator Lower Limit Upper Limit Inverting Regulator Lower Limit Upper Limit Glitch Rejection Output Voltage Logic High Logic Low SLEW Voltage Level Threshold Slow Slew Rate Normal Slew Rate Input Current Slow Slew Rate Normal Slew Rate Fast Slew Rate CLOCK SYNCHRONIZATION SYNC Input Input Clock Range Minimum On Pulse Width Minimum Off Pulse Width High Logic Low Logic Leakage Current FLYBACK REGULATOR Output Voltage Range Data Sheet Symbol Min TSHDN THYS VEN_RISING VEN_HYST Max 150 15 1.10 Unit 1.135 100 0.03 1.20 0.5 V mV µA 87.5 90 92.5 % VPG_FYLBACK_UL 107.5 110 112.5 % VPG_BUCK_LL VPG_BUCK_UL 87.5 107.5 90 110 92.5 112.5 % % VPG_INVERTER_LL VPG_INVERTER_UL 87.5 107.5 90 110 1.36 92.5 112.5 % % µs VPWRGD_OH VMVDD − 0.4 VPWRGD_OL −1 V IPWRGD = 1 mA 0.8 V V VOUT1 (ADJ) µA µA µA Slew voltage (VSLEW) = 0 V to 0.8 V VSLEW = 2 V to VINP SLEW pin not connected 0.4 1 kHz ns ns V V µA SYNC voltage (VSYNC) = VSVDDx 28 V +1.5 V V % 750 0.005 6 24 21 −1.5 Rev. A | Page 4 of 38 Glitch of ±15% of the typical output 0.4 10 +1 350 100 150 1.3 Fixed and adjustable output versions Fixed and adjustable output versions PWRGD current (IPWRGD) = −1 mA −10 fSYNC tSYNC_MIN_ON tSYNC_MIN_OFF VH (SYNC) VL (SYNC) VEN = VINP V 2 −1 Test Conditions/Comments °C °C VPG_FLYBACK_LL VOUT1 (FIXED) VOUT1 (FIXED) Output Voltage Accuracy Typ ADP1031ACPZ-1, ADP1031ACPZ-2, and ADP1031ACPZ-3 ADP1031ACPZ-4 ADP1031ACPZ-5 Fixed output options Data Sheet Parameter Feedback Voltage Feedback Voltage Accuracy Feedback Bias Current Load Regulation ADP1031 IFB1 (ΔVFB1/VFB1)/ΔIOUT1 −0.0005 Unit V % µA %/mA Line Regulation (ΔVOUT1/VOUT1)/ΔVINP 0.0003 %/V Power Field Effect Transistor (FET) On Resistance Current-Limit Threshold SWP Leakage Current SWP Capacitance Switching Frequency RON (FLYBACK) 3 Ω CSWP fSW (FLYBACK) 235 Minimum On Time Minimum Off Time Soft Start Timer Severe Overvoltage Threshold tSS (FLYBACK) SOVPFLYBACK 29.4 Severe Overvoltage Hysteresis BUCK REGULATOR Output Voltage Symbol VFB1 Min −1.5 ILIM (FLYBACK) 280 Current-Limit Threshold SW2 Leakage Current P Type Metal-Oxide Semiconductor (PMOS) N Type Metal-Oxide Semiconductor (NMOS) Switching Frequency Minimum On Time Soft Start Timer Active Pull-Down Resistor INVERTING REGULATOR Output Voltage Range Feedback Voltage Feedback Voltage Accuracy Feedback Bias Current Load Regulation Line Regulation Power FET On Resistance Max +1.5 0.05 300 0.03 50 250 fSYNC/2 425 220 8 30 320 0.5 265 30.6 mA µA pF kHz kHz ns ns ms V Test Conditions/Comments Adjustable output options IOUT1 = 4 mA to 24 mA, IOUT2 = 10 mA, IOUT3 = −1 mA VINP = 16 V to 32 V, IOUT1 = 20 mA, IOUT2 = 10 mA, IOUT3 = −1 mA SWP current (ISWP) = 100 mA SWP voltage (VSWP) = 60 V SYNC = low or high SYNC = external clock Flyback regulator stops switching until the overvoltage is removed SOVPFLYBACK_HYST 500 mV VOUT2 5.15 V 5.0 3.3 +1.5 V V % −0.0005 0.0004 1 2.5 300 320 %/mA %/V Ω Ω mA 0.03 0.5 µA VSW2 = 0 V 0.03 0.5 µA VSW2 = 28 V 125 fSYNC/4 200 8 1.7 132.5 kHz kHz ns ms kΩ SYNC = low or high SYNC = external clock Output Voltage Accuracy Load Regulation Line Regulation Power FET On Resistance Typ 0.8 −1.5 (ΔVOUT2/VOUT2)/ΔIOUT2 (ΔVOUT2/VOUT2)/ΔVOUT1 RON_NFET (BUCK) RON_PFET (BUCK) ILIM (BUCK) fSW (BUCK) 280 117.5 tSS (BUCK) RPD (BUCK) VOUT3 VFB3 −24 −5 IFB3 (ΔVFB3/VFB3)/ΔIOUT3 −0.01 V V % µA %/mA (ΔVOUT3/VOUT3)/ΔVOUT1 RON_NFET (INVERTER) RON_PFET (INVERTER) 0.0005 1.45 2.2 %/V Ω Ω 0.8 −1.5 +1.5 0.05 Rev. A | Page 5 of 38 ADP1031ACPZ-1, ADP1031ACPZ-4, and ADP1031ACPZ-5 ADP1031ACPZ-2 ADP1031ACPZ-3 IOUT2 = 10 mA, applies to all models IOUT2 = 2 mA to 50 mA VOUT1 = 6 V to 28 V, IOUT2 = 7 mA SW2 current (ISW2) = 100 mA ISW2 = 100 mA 1.23 V < VOUT1 < 4.5 V In reference to VOUT3 Adjustable output option IOUT3 = 1 mA to 15 mA VOUT1 = 6 V to 28 V, IOUT3 = −15 mA SW3 current (ISW3) = 100 mA ISW3 = 100 mA ADP1031 Parameter Current-Limit Threshold SW3 Leakage Current PMOS NMOS Switching Frequency Minimum On Time Soft Start Timer Active Pull-Down Resistor ISOLATORS, DC SPECIFICATIONS MCK, MSS, MO, SO, MGPI1, MGPI2, SGPI3 Input Threshold Logic High Logic Low Input Current SCK, SSS, SI, MI Output Voltage Logic High Logic Low Data Sheet Symbol ILIM (INVERTER) fSW (INVERTER) Min 280 117.5 tSS (INVERTER) RPD (INVERTER) VIH Typ 300 Max 320 Unit mA Test Conditions/Comments 0.03 0.03 125 fSYNC/4 178 8 350 0.5 0.5 132.5 µA µA kHz kHz ns ms Ω VSW3 = −24 V VSW3 = 24 V SYNC = low or high SYNC = external clock V VxVDD = VMVDD or VSVDDx V VxVDD = VMVDD or VSVDDx µA 0 V ≤ VINPUT ≤ VxVDD V IOx 2 = −20 µA, VIx = VIxH 3 V IOx2 = −2 mA, VIx = VIxH3 V V IOx2 = 20 µA, VIx = VIxL 4 IOx2 = 2 mA, VIx = VIxL4 V IOx2 = −20 µA, VIx = VIxH3 V IOx2 = −500 µA, VIx = VIxH3 0.7 × VxVDD 0.3 × VxVDD +1 VIL II −1 VOH VxVDD − 0.1 VxVDD − 0.4 VOL 0.15 SGPO1, SGPO2, MGPO3 Output Voltage Logic High Logic Low VOH ISOLATORS, SWITCHING SPECIFICATION MCK, MSS, MO, SO SPI Clock Rate VxVDD − 0.1 VxVDD − 0.4 VOL SCK, SI, MI Tristate Leakage 0.15 0.1 0.4 V V IOx2 = 20 µA, VIx = VIxL4 IOx2 = 500 µA, VIx = VIxL4 0.01 0.01 1 1 µA µA MSS = logic high VOx 5 = VxVDD 16.6 MHz 100 125 ns 0.25 6.5 ns ns 0.5 0.5 5.5 4 ns ns −1 −1 SPIMCK Latency Input Pulse Width Input Pulse Width Distortion Channel Matching Codirectional Opposing Direction tPW tPWD tPSKCD tPSKOD 0.1 0.4 1.23 V < VOUT1 < 4.5 V 17 Rev. A | Page 6 of 38 Delay from MSS going low to the first data out is valid Within PWD limit |tPLH − tPHL| Data Sheet ADP1031 Parameter Propagation Delay Symbol tPHL, tPLH Min Jitter Typ Max Unit 7 7 7 8.5 620 100 11 12 15 12 ns ns ns ns ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms 440 80 290 60 410 110 MGPI1, MGPI2, SGPI3 Data Rate Input Pulse Width Propagation Delay Jitter ISOLATORS AC SPECIFICATIONS General-Purpose Input/Output (GPIO) Output Rise Time/Fall Time SPI Output Rise Time/Fall Time Common-Mode Transient Immunity 6 100 tPW tPHL, tPLH 10 14 19.5 Test Conditions/Comments 50% input to 50% output VMVDD = 5 V, VSVDD1 = 5 V VMVDD = 3.3V, VSVDD1 = 5 V VMVDD = 3.3 V, VSVDD1 = 3.3 V VMVDD = 2.3 V, VSVDD1 = 1.8 V VMVDD = 5 V, VSVDD1 = 5 V VMVDD = 5 V, VSVDD1 = 5 V VMVDD = 3.3 V, VSVDD1 = 5 V VMVDD = 3.3 V, VSVDD1 = 5 V VMVDD = 3.3 V, VSVDD1 = 3.3 V VMVDD = 3.3 V, VSVDD1 = 3.3 V VMVDD = 2.3 V, VSVDD1 = 1.8 V VMVDD = 2.3 V, VSVDD1 = 1.8 V kbps µs µs µs Within PWD limit 50% input to 50% output tR/tF 2.5 ns 10% to 90% tR/tF |CM| 2 100 ns kV/µs 10% to 90% VIx is the Channel x logic input, where Channel x can be MCK, MO, SO, MGPI1, MGPI2, or MGPI3. IOx is the output current of the pin. 3 VIxH is the input side, logic high. 4 VIxL is the input side, logic low. 5 VOx is the voltage where the output is pulled. 6 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 MVDD and/or SVDDx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 REGULATORY INFORMATION See Table 8 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross isolation waveforms and insulation levels. Table 2. Safety Certifications UL (Pending) Recognized Under UL 1577 Component Recognition Program CSA (Pending) Approved under CSA Component Acceptance Notice 5A VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 2500 V rms Single Protection CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1+A2: basic insulation at 300 V rms (424 VPEAK) Basic insulation, 565 VPEAK CSA 61010-1-12 and IEC 61010-1 third edition: basic insulation at 300 V rms mains, 300 V rms (424 VPEAK) secondary Rev. A | Page 7 of 38 ADP1031 Data Sheet ELECTROMAGNECTIC COMPATIBILITY Table 3. Regulatory Body SGS-CCSR Standard CISPR11 Class B Comment Tested using the system board with the AD5758 INSULATION AND SAFETY RELATED SPECIFICATIONS Table 4. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Field Power Domain to Master Domain Value 2500 Unit V rms Test Conditions/Comments 1-minute duration 2.15 mm min Field Power Domain to Slave Domain 2.15 mm min Master Domain to Slave Domain 2.15 mm min Measured from field power pins and pads to master pins and pads, shortest distance through air Measured from field power pins and pads to slave pins and pads, shortest distance through air Measured from master pins and pads to slave pins and pads, shortest distance through air Minimum External Tracking (Creepage) Field Power Domain to Master Domain 2.15 mm min Field Power Domain to Slave Domain 2.15 mm min Master Domain to Slave Domain 2.15 mm min 18 >400 II µm min V Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Material Group Symbol CTI Rev. A | Page 8 of 38 Measured from field power pins and pads to master pins and pads, shortest distance path along body Measured from field power pins and pads to slave pins and pads, shortest distance path along body Measured from master pins and pads to slave pins and pads, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303, Part 1 Material group (DIN VDE 0110, 1/89, Table 1) Data Sheet ADP1031 DIN V VDE 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS Table 5. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input to Output Test Voltage, Method B1 Test Conditions/Comments VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC Input to Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety Limiting Values Maximum Junction Temperature Total Power Dissipation at 25°C Insulation Resistance at TS VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 2) VIO = 500 V Symbol Characteristic Unit VIORM Vpd (m) I to III I to II I to I 40/105/21 2 565 1060 VPEAK VPEAK Vpd (m) 847 VPEAK 678 VPEAK VIOTM VIOSM 3537 4000 VPEAK VPEAK TS PS RS 150 2.48 >109 °C W Ω 3.0 SAFE LIMITING POWER (W) 2.5 2.0 1.5 1.0 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 16434-102 0.5 Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10 Rev. A | Page 9 of 38 ADP1031 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6. Parameter VINP to PGNDP SWP to VINP SLEW to GNDP EN to GNDP VOUT1 to SGND2 FB1 to SGND2 VOUT1 to VOUT3 SW2 to SGND2 VOUT2 to SGND2 SW3 to SGND2 VOUT3 to SGND2 FB3 to VOUT3 SVDD1 to SGND1 SVDD2 to SGND2 SSS, SCK, SI, SO to SGND1 SGPO1, SGPO2, SGPI3 to SGND2 SYNC to SGND2 MVDD to MGND MSS, MCK, MO, MI to MGND MGPI1, MGPI2, MGPO3 to MGND PWRGD to MGND Common-Mode Transients Operating Junction Temperature Range1 Storage Temperature Range Lead Temperature Soldering Conditions 1 Rating 61 V VINP + 70 V or 110 V, whichever is lower −0.3 V to VINP + 0.3 V −0.3 V to +61 V 35 V −0.3 V to VOUT1 + 0.3 V 61 V −0.3 V to VOUT1 + 0.3 V 6V VOUT3 − 0.3 V to VOUT1 + 0.3 V −26 V to +0.3 V +3.3 V to −0.3 V 6.0 V 6.0 V −0.3 V to SVDD1 + 0.3 V −0.3 V to SVDD2 + 0.3 V −0.3 V to +6 V 6.0 V −0.3 V to MVDD + 0.3 V −0.3 V to MVDD + 0.3 V −0.3 V to MVDD + 0.3 V ±100 kV/µs −40°C to +125°C −65°C to +150°C JEDEC industry standard JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. θJA is the natural convection, junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is measured at the top of the package and is independent of the PCB. The ΨJT value is appropriate for calculating junction to case temperature in the application. Table 7. Thermal Resistance Package Type1, 2, 3, 4 CP-41-1 θJA 50.4 θJC 33.1 ΨJT 25 Unit °C/W 9 mm × 7 mm LFCSP with omitted pins for isolation purposes. Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with 19 thermal vias. See JEDEC JESD-51. 3 Case temperature was measured at the center of the package. 4 Board temperature was measured near Pin 1. 1 2 ESD CAUTION Power dissipated on chip must be derated to keep the junction temperature below 125°C. Table 8. Maximum Continuous Working Voltage1 Parameter 60 Hz AC Voltage DC Voltage 1 2 3 Value 300 V rms 424 VPEAK Constraint 20-year lifetime at 0.1% failure rate, zero average voltage Limited by the creepage of the package, Pollution Degree 2, Material Group II2, 3 See the Insulation Lifetime section for more details. Other pollution degree and material group requirements yield a different limit. Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards. Rev. A | Page 10 of 38 Data Sheet ADP1031 MI 1 MSS 2 MGND 3 33 GNDP 32 SLEW 31 EN 41 40 39 38 37 36 35 34 MO MCK MVDD MGPO3 MGPI2 MGPI1 PWRGD MGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS M FP EPGNDM EPGNDP 30 VINP 29 SWP 28 PGNDP ADP1031 TOP VIEW (Not to Scale) 4 5 6 7 EPGND2 S 27 26 25 24 SGND2 DNC DNC DNC NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. EPGNDP IS INTERNALLY CONNECTED TO PGNDP, EPGNDM IS INTERNALLY CONNECTED TO MGND, AND EPGND2 IS INTERNALLY CONNECTED TO SGND. 16434-002 SI SCK SVDD1 FB3 VOUT3 SW3 SYNC VOUT2 SGND2 SW2 VOUT1 FB1 SVDD2 SGPI3 SGPO2 SGPO1 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SGND2 SGND1 SSS SO Figure 3. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 Mnemonic MI Isolation Domain Master Direction Output 2 MSS Master Input 3 4 5 6 MGND SGND2 SGND1 SSS Master Slave Slave Slave Return Return Return Output 7 SO Slave Input 8 SI Slave Output 9 SCK Slave Output 10 SVDD1 Slave Power 11 12 13 14 FB3 VOUT3 SW3 SYNC Slave Slave Slave Slave Not applicable Power Not applicable Input 15 16 VOUT2 SGND2 Slave Slave Power Return 17 18 SW2 VOUT1 Slave Slave Not applicable Power 19 20 FB1 SVDD2 Slave Slave Power Description SPI Data Output from the Slave MI and SO Line. This pin is paired with SO. On the slave domain, SO drives this pin. SPI Slave Select Input from the Master Controller. This pin is paired with SSS. On the slave domain, this pin drives SSS. This signal uses an active low logic. Master Domain Signal Ground Connection. Slave Domain Ground Connection. This pin can be left unconnected. Slave Domain SPI Isolator Ground. SPI Slave Select Output. This pin is paired with MSS. On the master domain, MSS drives this pin. SPI Data Input Going to the Master MI and SO Line. This pin is paired with MI. On the master domain, this pin drives MI. SPI Data Output from the Master MO and SI Line. This pin is paired with MO. On the master domain, MO drives this pin. SPI Clock Output from the Master. This pin is paired with MCK. On the master domain, MCK drives this pin. SPI Isolator Power Supply. Connect a 100 nF decoupling capacitor from SVDD1 to SGND1. Inverting Regulator Feedback Pin. Inverting Regulator Output and Overvoltage Sense. Inverting Regulator Switch Node. SYNC Pin. To synchronize the switching frequency, connect the SYNC pin to an external clock at twice the required switching frequency. Do not leave this pin floating. Connect a 100 kΩ pull-down resistor to SGND2. Buck Regulator Output Feedback. Slave Power Ground. Ground return for inverting and buck regulator output capacitors. Buck Regulator Switch Node. Flyback Regulator Output and Overvoltage Sense. This pin is the input to the buck and inverting regulators. Feedback Node for the Flyback Regulator. GPIO Isolators Power Supply. Connect a 100 nF decoupling capacitor from SVDD2 to SGND2. Rev. A | Page 11 of 38 ADP1031 Data Sheet Pin No. 21 22 23 24 25 26 27 28 29 30 Mnemonic SGPI3 SGPO2 SGPO1 DNC DNC DNC SGND2 PGNDP SWP VINP Isolation Domain Slave Slave Slave Slave Slave Slave Slave Field power Field power Field power Direction Input Output Output Not applicable Not applicable Not applicable Return Return Not applicable Power 31 EN Field power Input 32 SLEW Field power Input 33 34 35 GNDP MGND PWRGD Field power Master Master Return Return Return 36 37 38 39 MGPI1 MGPI2 MGPO3 MVDD Master Master Master Master Input Input Output Power 40 MCK Master Input 41 MO Master Input EPGNDP EPGNDM EPGND2 Field power Master Slave Return Return Return Description General-Purpose Input 3. This pin is paired with MGPO3. General-Purpose Output 2. This pin is paired with MGPI2. General-Purpose Output 1. This pin is paired with MGPI1. Do Not Connect. Do not connect to this pin. Do Not Connect. Do not connect to this pin. Do Not Connect. Do not connect to this pin. Slave Domain Ground Connection. This pin can be left unconnected. Ground Return for Flyback Regulator Power Supply. Flyback Regulator Switching Node. Primary side transformer connection. Flyback Regulator Supply Voltage. Connect a minimum of 3.3 µF capacitor from VINP to PGNDP. Precision Enable. Compare the EN pin to an internal precision reference to enable the flyback regulator output. Flyback Regulator Slew Rate Control. The SLEW pin sets the slew rate for the SWP driver. For the fastest slew rate (best efficiency), leave the SLEW pin open. For the normal slew rate, connect the SLEW pin to VINP. For the slowest slew rate (best EMI performance), connect the SLEW pin to GNDP. Field Power Signal Ground Connection. Master Domain Power Ground Connection. Power Good. This pin indicates when the secondary side supplies are within their programmed range. General-Purpose Input 1. This pin is paired with SGPO1. General-Purpose Input 2. This pin is paired with SGPO2. General-Purpose Output 3. This pin is paired with SGPI3. Master Domain Power. Connect a 100 nF decoupling capacitor from MVDD to MGND. SPI Clock Input from the Master Controller. Paired with SCK. On the slave domain, this pin drives SCK. SPI Data Input Going to Slave MO and SI Line. Paired with SI. On the slave domain, this pin drives SI. PGNDP Exposed Pad. This pad is internally connected to PGNDP. MGND Exposed Pad. This pad is internally connected to MGND. SGND Exposed Pad. This pad is internally connected to SGND. Rev. A | Page 12 of 38 Data Sheet ADP1031 TYPICAL PERFORMANCE CHARACTERISTICS 100 450 POWER DISSIPATION (mW) 90 70 60 VINP = 5V VINP = 12V VINP = 18V VINP = 24V VINP = 32V VINP = 60V 10 20 30 40 50 60 70 80 90 100 Figure 4. Overall Efficiency at Various Input Voltages, TA = +25°C, VOUT1 = +24 V, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA, Using a Würth Elektronik 750316743 Transformer 0 POWER DISSIPATION (mW) 60 50 VINP = 5V VINP = 12V VINP = 18V VINP = 24V VINP = 32V VINP = 60V 0 10 20 30 40 50 60 70 80 90 100 IOUT1 (mA) Figure 5. Overall Efficiency at Various Input Voltages, TA = +25°C, VOUT1 = +21 V, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA, Using a Würth Elektronik 750316743 Transformer 350 70 60 50 40 50 VOUT1 = 21V (–40°C) VOUT1 = 21V (+25°C) VOUT1 = 21V (+125°C) 60 IOUT1 (mA) 70 80 90 100 90 100 150 100 0 10 20 30 40 50 60 70 80 90 100 VOUT1 = 24V (–40°C) VOUT1 = 24V (+25°C) VOUT1 = 24V (+125°C) VOUT1 = 21V (–40°C) VOUT1 = 21V (+25°C) VOUT1 = 21V (+125°C) 350 300 250 200 150 100 50 0 16434-005 30 80 Figure 8. Power Dissipation at Various Input Voltages, TA = +25°C, VOUT1 = +21 V, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA, Using a Würth Elektronik 750316743 Transformer POWER DISSIPATION (mW) 80 20 70 IOUT1 (mA) 90 10 60 200 400 0 50 250 450 VOUT1 = 24V (–40°C) VOUT1 = 24V (+25°C) VOUT1 = 24V (+125°C) 40 300 0 100 40 30 50 16434-004 40 20 VINP = 5V VINP = 12V VINP = 18V VINP = 24V VINP = 32V VINP = 60V 400 70 10 Figure 7. Power Dissipation at Various Input Voltages, TA = +25°C, VOUT1 = +24 V, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA, T Using a Würth Elektronik 750316743 Transformer 450 80 EFFICIENCY (%) 100 IOUT1 (mA) 90 EFFICIENCY (%) 150 0 100 30 200 50 IOUT1 (mA) 30 250 16434-006 0 300 16434-007 40 350 Figure 6. Overall Efficiency across Temperature, VINP = +24 V, VOUT1 = +21 V and VOUT1 = +24 V, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA, Using a Würth Elektronik 750316743 Transformer 0 10 20 30 40 50 60 IOUT1 (mA) 70 80 90 100 16434-008 50 16434-003 EFFICIENCY (%) 80 30 VINP = 5V VINP = 12V VINP = 18V VINP = 24V VINP = 32V VINP = 60V 400 Figure 9. Power Dissipation across Temperature, VINP = +24 V, VOUT1 = +21 V and VOUT1 = +24 V, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA, Using a Würth Elektronik 750316743 Transformer Rev. A | Page 13 of 38 ADP1031 Data Sheet 450 100 POWER DISSIPATION (mW) 90 70 60 BS64042CS YA9293-AL LPD5030-154MRB 750316743 750316566 WA8478-BE 0 10 20 30 40 50 60 70 80 90 100 Figure 10. Overall Efficiency using Various Transformers, TA = +25°C, VINP = +24 V, VOUT1 = +24 V, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA 200 150 100 0 0 10 POWER DISSIPATION (mW) 90 60 50 BS64042CS YA9293-AL LPD5030-154MRB 750316743 750316566 WA8478-BE 0 10 20 30 40 50 60 70 80 90 100 IOUT1 (mA) Figure 11. Overall Efficiency using Various Transformers, TA = +125°C, VINP = +24 V, VOUT1 = +24 V, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA 350 4 0 80 90 100 200 150 100 0 10 20 30 40 60 50 70 80 90 IOUT1 (mA) 100 Figure 14. Power Dissipation using Various Transformers, TA = +125°C, VINP = +24 V, VOUT1 = +24 V, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA VEN VINP VOUT1 2 VOUT2 3 VOUT3 4 0 PWRGD CH1 10.0V CH3 5.0V B B W W CH2 10.0V CH4 10.0V B B W W M4.00ms A CH1 T 14.000ms 3.60mA VOUT1 VOUT2 VOUT3 PWRGD CH1 5.00V CH3 2.00V Figure 12. Power-Up Sequence at VINP Rising, TA = +25°C, VINP = +24 V, VOUT1 = +24 V, IOUT1 = +20 mA, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA B B W W CH2 10.0V CH4 10.0V B B W W M4.00ms A CH1 T 12.0000ms 3.20V 16434-014 3 70 250 0 16434-011 2 60 300 1 1 50 50 16434-010 40 40 BS64042CS YA9293-AL LPD5030-154MRB 750316743 750316566 WA8478-BE 400 70 30 Figure 13. Power Dissipation using Various Transformers, TA = +25°C, VINP = +24 V, VOUT1 = +24 V, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA 450 80 20 IOUT1 (mA) 100 EFFICIENCY (%) 250 50 IOUT1 (mA) 30 300 16434-012 40 350 16434-013 50 16434-009 EFFICIENCY (%) 80 30 BS64042CS YA9293-AL LPD5030-154MRB 750316743 750316566 WA8478-BE 400 Figure 15. Power-Up Sequence at EN Rising, TA = +25°C, VINP = +24 V, VOUT1 = +24 V, IOUT1 = +20 mA, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA Rev. A | Page 14 of 38 Data Sheet ADP1031 VEN 1 VOUT1 VOUT3 PWRGD CH1 5.00V CH3 2.00V B B W W CH2 10.0V CH4 10.0V M4.00ms A CH1 T 12.0000ms B W B W 3.20V 16434-015 0 CH1 5.00V BW CH2 10.0V CH3 50.0mA BW Figure 16. Shutdown Sequence, TA = +25°C, VINP = +24 V, VOUT1 = +24 V, IOUT1 = +20 mA, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA 1.5 –40°C +25°C +125°C VARIATION FROM NOMINAL (%) 1.0 0.5 0 –0.5 –1.0 0 10 20 30 40 50 60 70 80 90 100 IOUT1 (mA) 0.2 –0.5 –1.0 0 0.5 10 20 30 40 50 60 70 80 90 100 VINP = 5V VINP = 12V VINP = 18V VINP = 24V VINP = 32V VINP = 60V 0.4 0.1 0 –0.1 –0.2 –0.3 –0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 10 20 30 40 50 60 IOUT1 (mA) 70 80 90 100 –0.5 16434-017 –0.5 0 IOUT1 (mA) VARIATION FROM NOMINAL (%) 0.3 0.5 Figure 20. Flyback Regulator Load Regulation Across Temperature, VINP = 24 V, VOUT1 = 21 V, Nominal = VOUT1 at 20 mA Load VINP = 5V VINP = 12V VINP = 18V VINP = 24V VINP = 32V VINP = 60V 0.4 3.20V –40°C +25°C +125°C 1.0 –1.5 Figure 17. Flyback Regulator Load Regulation Across Temperature, VINP = 24 V, VOUT1 = 24 V, Nominal = VOUT1 at 20 mA Load 0.5 W Figure 18. Flyback Regulator Load Regulation at Various Input Voltages, TA = 25°C, VOUT1 = 24 V, Nominal = VOUT1 at 20 mA Load 0 10 20 30 40 50 60 IOUT1 (mA) 70 80 90 100 16434-020 –1.5 M4.00ms A CH1 T 8.0400ms B Figure 19. Inrush Current, TA = +25°C, VINP = +24 V, VOUT1 = +24 V, IOUT1 = +20 mA, VOUT2 = +5.15 V, IOUT2 = +7 mA, VOUT3 = −15 V, IOUT3 = −0.3 mA 16434-016 VARIATION FROM NOMINAL (%) 1.5 ISWP 3 16434-018 4 16434-019 2 VARIATION FROM NOMINAL (%) VOUT1 2 VOUT2 3 VEN 1 Figure 21. Flyback Regulator Load Regulation at Various Input Voltages, TA = 25°C, VOUT1 = 21 V, Nominal = VOUT1 at 20 mA Load Rev. A | Page 15 of 38 ADP1031 1.5 –40°C +25°C +125°C 0.5 0 –0.5 –1.0 0 20 10 40 30 60 50 VINP (V) VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 160 0 –0.5 –1.0 100 = 6V = 15V = 21V = 24V = 28V 30 40 50 60 –40°C +25°C +105°C 90 80 70 100 80 60 60 50 40 30 40 20 20 10 10 15 20 25 30 35 40 45 50 0 16434-022 5 VINP (V) Figure 23. Flyback Regulator Maximum Output Current at Various Output Voltage, TA = 25°C, Using a Würth Elektronik 750316743 Transformer, Based on Target of 70% ILIM (FLYBACK) 1 20 Figure 25. Flyback Regulator Line Regulation Across Temperature, VOUT1 = 21 V, IOUT1 = 20 mA, Nominal = VOUT1 with VINP = 24 V 120 0 10 0 VINP (V) IOUT1 (MAX) (mA) IOUT1 (MAX) (mA) 140 0.5 –1.5 Figure 22. Flyback Regulator Line Regulation Across Temperature, VOUT1 = 24 V, IOUT1 = 20 mA, Nominal = VOUT1 with VINP = 24 V 180 1.0 5 10 15 20 25 30 VINP (V) 35 40 45 50 16434-025 –1.5 –40°C +25°C +125°C 16434-024 VARIATION FROM NOMINAL (%) 1.0 16434-021 VARIATION FROM NOMINAL (%) 1.5 Data Sheet Figure 26. Flyback Regulator Maximum Output Current across Temperature, VOUT1 = 24 V, Using a Würth Elektronik 750316743 Transformer, Based on Target of 70% ILIM (FLYBACK) VOUT1 1 VOUT1 ISWP 2 2 ISWP VSWP B W CH2 20.0mA BW 4.00µs A CH3 T 50.10% 48.0V 16434-124 CH1 20.0mV CH3 50.0V BW VSWP CH1 20.0mV CH3 20.0V BW Figure 24. Flyback Regulator Pulse Skipping Operation Showing Inductor Current (ISWP), Switch Node Voltage, and Output Ripple, TA = 25°C, VINP = 48 V, VOUT1 = 24 V, IOUT1 = 1 mA B W CH2 50.0mA BW 1.00µs A CH3 T 50.10% 48.0V 16434-127 3 3 Figure 27. Flyback Regulator Discontinuous Conduction Mode Operation Showing ISWP, Switch Node Voltage, and Output Ripple, TA = 25°C, VINP = 24 V, VOUT1 = 24 V, IOUT1 = 10 mA Rev. A | Page 16 of 38 Data Sheet 1 ADP1031 VOUT1 1 2 VEN VOUT1 ISWP 2 3 ISWP VSWP VSWP CH1 50.0mV CH3 20.0V BW B W CH2 100mA B W 1.00µs A CH3 T 50.10% 48.0V CH1 5.00V CH3 200mA Figure 28. Flyback Regulator Continuous Conduction Mode Operation Showing ISWP, Switch Node Voltage, and Output Ripple, TA = 25°C, VINP = 24 V, VOUT1 = 24 V, IOUT1 = 50 mA 2 W W CH2 10.0V CH4 20.0V M1.00ms A CH1 T 2.01000ms B W B W 3.20V Figure 31. Flyback Regulator Short-Circuit Current Limit During Startup, VINP = 24 V, VOUT1 = SGND2, TA = 25°C IOUT1 VINP 1 B B 16434-030 4 16434-128 3 1 VOUT1 2 VOUT1 VSWP VSWP 3 CH2 2.00V B W B M4.00ms A CH1 T 11.929ms B W W 15.4V CH1 20.0mA BW CH2 2.00V CH3 20.0V BW Figure 29. Flyback Regulator Line Transient Response, VINP = 6 V to 20 V Step, VOUT1 = 24 V, IOUT1 = 20 mA, TA = 25°C B W M4.00ms A CH1 T 11.9000ms 16.8mA 16434-031 CH1 10.0V CH3 20.0V 16434-028 3 Figure 32. Flyback Regulator Load Transient Response, VINP = 24 V, VOUT1 = 24 V, IOUT1 = 1 mA to 20 mA Step, TA = 25°C VINP 1 VOUT1 2 2 VSWP IOUT1 VOUT1 VSWP 1 3 B W B CH2 200mV W B W M4.00ms A CH1 T 11.9290ms 6.64V CH1 50.0mA CH3 50.0V Figure 30. Flyback Regulator Line Transient Response, VINP = 6 V to 7 V Step, VOUT1 = 24 V, IOUT1 = 20 mA, TA = 25°C Rev. A | Page 17 of 38 B B W W CH2 2.00V B W M4.00ms A CH1 T 11.9000ms 35.0mA 16434-032 CH1 1.00V CH3 20.0V 16434-029 3 Figure 33. Flyback Regulator Load Transient Response, VINP = 32 V, VOUT1 = 24 V, IOUT1 = 1 mA to 50 mA Step, TA = 25°C ADP1031 1.5 DEVIATION FROM NOMINAL (%) 1.0 0.5 0 –0.5 –1.0 –1.5 0 10 20 30 50 40 IOUT2 (mA) 1.0 0.5 0 –0.5 –1.0 –1.5 5 10 15 20 25 30 VOUT1 (V) Figure 34. Buck Regulator Load Regulation Across Temperature, VOUT1 = 24 V, VOUT2 = 5.15 V, Nominal = VOUT2 at 10 mA IOUT2 1 –40°C +25°C +125°C 16434-137 –40°C +25°C +125°C 16434-134 DEVIATION FROM NOMINAL (%) 1.5 Data Sheet Figure 37. Buck Regulator Line Regulation Across Temperature, VOUT2 = 5.15 V, IOUT2 = 7 mA, Nominal = VOUT2 at 24 VOUT1 VOUT2 VOUT2 1 ISW2 2 VSW2 3 CH1 10.0mV Ω BW CH2 20.0mA BW CH3 10.0V BW M10.0µs A CH3 T 700.000ns 20.4V 16434-034 3 CH1 50.0mV Ω BW CH2 100mA CH3 10.0V BW Figure 35. Buck Regulator Pulse Skipping Operation Showing Inductor Current 2 (IL2), Switch Node Voltage, and Output Ripple, TA = 25°C, VOUT1 = 24 V, VOUT2 = 5.15 V, IOUT2 = 0.3 mA 1 2 VSW2 B W M2.00µs A CH3 T –40.000ns 3.80V 16434-037 2 ISW2 Figure 38. Buck Regulator Discontinuous Conduction Mode Operation Showing IL2, Switch Node Voltage, and Output Ripple, TA = 25°C, VOUT1 = 21 V, VOUT2 = 5.15 V, IOUT2 = 50 mA VOUT2 1 ISW2 2 VOUT2 ISW2 VSW2 CH1 20.0mV Ω BW CH2 50.0mA BW CH3 10.0V BW M2.00µs A CH3 T 40.0000ns 16.0V 16434-035 3 VSW2 CH1 1.00V Ω BW CH3 10.0V BW Figure 36. Buck Regulator Discontinuous Conduction Mode Operation Showing IL2, Switch Node Voltage, and Output Ripple, TA = 25°C, VOUT1 = 21 V, VOUT2 = 5.15 V, IOUT2 = 7 mA CH2 200mA B W M200µs A CH2 T 595.000µs 164mA 16434-038 3 Figure 39. Buck Regulator Short-Circuit Current Limit During Startup, VOUT1 = 24 V, VOUT2 = SGND2, TA = 25°C Rev. A | Page 18 of 38 Data Sheet ADP1031 IOUT2 IOUT2 1 1 VOUT2 2 VOUT2 2 VSW2 VSW2 W M2.00ms A CH1 T 5.92000ms 4.30mA CH1 5.00mA BW CH2 500mV CH3 10.0V BW DEVIATION FROM NOMINAL (%) 0.5 0 –0.5 –1.0 –1.5 0 5 10 15 20 25 30 IOUT3 (mA) 4.30mA 0.5 0 –0.5 –1.0 5 10 15 20 25 30 VOUT1 (V) Figure 44. Inverting Regulator Line Regulation Across Temperature, VOUT3 = −15 V, IOUT3 = −7 mA, Nominal = VOUT3 at +24 VOUT1 Figure 41. Inverting Regulator Load Regulation Across Temperature, VOUT1 = +24 V, VOUT3 = −15 V, Nominal = VOUT3 at −7 mA IOUT3 1 M2.00ms A CH1 T 5.92000ms –40°C +25°C +125°C 1.0 –1.5 16434-142 DEVIATION FROM NOMINAL (%) 1.5 –40°C +25°C +125°C 1.0 W Figure 43. Buck Regulator Load Transient Response, VOUT1 = 21 V, VOUT2 = 5.15 V, IOUT2 = 0.3 mA to 7 mA Step, TA = 25°C Figure 40. Buck Regulator Load Transient Response, VOUT1 = 24 V, VOUT2 = 5.15 V, IOUT2 = 0.3 mA to 7 mA Step, TA = 25°C 1.5 B 16434-145 B 16434-042 CH1 5.00mA BW CH2 500mV CH3 10.0V BW 16434-043 3 3 VOUT3 VOUT3 1 2 ISW3 ISW3 2 VSW3 B W M10.0µs A CH2 T 595.000µs 36.0mA CH1 20mV BW CH2 100mA CH3 10.0V BW Figure 42. Inverting Regulator Pulse Skipping Operation Showing Inductor Current (IL3), Switch Node Voltage, and Output Ripple, TA = +25°C, VOUT1 = +24 V, VOUT3 = −6 V, IOUT3 = −0.3 mA B W M2.00µs A CH2 T 595.000µs 36.0mA 16434-046 CH1 10mV BW CH2 20.0mA CH3 10.0V BW 16434-045 3 3 VSW3 Figure 45. Inverting Regulator Discontinuous Conduction Operation Showing IL3, Switch Node Voltage, and Output Ripple, TA = +25°C, VOUT1 = +24 V, VOUT3 = −15 V, IOUT3 = −7 mA Rev. A | Page 19 of 38 ADP1031 Data Sheet VOUT3 1 ISW3 2 VOUT3 1 ISW3 2 VSW3 VSW3 CH1 50mV BW CH2 100mA CH3 10.0V BW B W M2.00µs A CH2 T 595.000µs 36.0mA 16434-048 3 CH1 1.00V BW CH2 200mA CH3 10.0V BW Figure 46. Inverting Regulator Discontinuous Conduction Operation Showing IL3, Switch Node Voltage, and Output Ripple, TA = +25°C, VOUT1 = +24 V, VOUT3 = −15 V, IOUT3 = −20 mA M200µs A CH2 T 698.000µs 60.0mA IOUT3 1 VOUT3 2 W Figure 49. Inverting Regulator Short-Circuit Current Limit During Startup, VOUT1 = +24 V, VOUT3 = SGND2, TA = +25°C IOUT3 1 B 16434-049 3 VOUT3 2 VSW3 VSW3 B B W CH2 200mV B W W M2.00ms A CH1 T 6.0100ms 4.40mA 16434-151 CH1 5.00mA CH3 20.0V CH1 5.00mA CH3 20.0V Figure 47. Inverting Regulator Load Transient Response, VOUT1 = +24 V, VOUT3 = −15 V, IOUT2 = −0.3 mA to −7 mA Step, TA = +25°C 10 VMVDD = 2.5V, VSVDD1 = 1.8V VMVDD = 3.3V, VSVDD1 = 3.3V VMVDD = 5.0V, VSVDD1 = 5.0V 8 8 6 6 4 2 CH2 500mV B W M2.00ms A CH1 T 6.0100ms 4.40mA VMVDD = 2.5V, VMVDD = 3.3V, VMVDD = 5.0V, VSVDD1 = 1.8V VSVDD1 = 3.3V VSVDD1 = 5.0V 4 0 10 20 30 40 50 60 DATA RATE (Mbps) 70 80 90 100 0 0 10 20 30 40 50 60 DATA RATE (Mbps) Figure 48. MVDD Supply Current (IMVDD) per SPI Input vs. Data Rate at Various Supply Voltages, MSS Is Low, Clock Signal Applied on Single SPI Channel, Other Input Channels Tied Low 70 80 90 100 16434-256 2 16434-253 0 W W Figure 50. Inverting Regulator Load Transient Response, VOUT1 = +6 V, VOUT3 = −15 V, IOUT2 = −0.3 mA to −7 mA Step, TA = +25°C ISVDD1 (mA) IMVDD (mA) 10 B B 16434-154 3 3 Figure 51. SVDD1 Supply Current (ISVDD1) per SPI Input vs. Data Rate at Various Supply Voltages, SSS Is Low, Clock Signal Applied on Single SPI Channel, Other Input Channels Tied Low Rev. A | Page 20 of 38 Data Sheet 14 12 10 10 ISVDD1 (mA) 12 8 6 8 6 4 4 2 2 0 0 10 20 30 40 50 VMVDD = 2.5V, VSVDD1 = 1.8V VMVDD = 3.3V, VSVDD1 = 3.3V VMVDD = 5.0V, VSVDD1 = 5.0V 14 60 70 80 90 100 DATA RATE (Mbps) 0 16434-254 IMVDD (mA) 16 VMVDD = 2.5V, VSVDD1 = 1.8V VMVDD = 3.3V, VSVDD1 = 3.3V VMVDD = 5.0V, VSVDD1 = 5.0V 0 10 20 30 40 50 60 70 80 90 100 DATA RATE (Mbps) Figure 52. IMVDD per SPI Output vs. Data Rate at Various Supply Voltages, MSS Is Low, Clock Signal Applied on Single SPI Channel, Other Input Channels Tied Low 16434-257 16 ADP1031 Figure 55. ISVDD1 vs. Data Rate at Various Supply Voltages, SSS Is Low, Clock Signal Applied on Single SPI Channel, Other Input Channels Tied Low 10 VMVDD = 2.5V, VSVDD1 = 1.8V VMVDD = 3.3V, VSVDD1 = 3.3V VMVDD = 5.0V, VSVDD1 = 5.0V VMVDD = 2.5V, VSVDD1 = 1.8V VMVDD = 3.3V, VSVDD1 = 3.3V VMVDD = 5.0V, VSVDD1 = 5.0V IMVDD (mA) ISVDD1 (mA) 8 6 4 –25 0 25 50 75 100 125 TEMPERATURE (°C) 0 –50 16434-258 –50 Figure 53. IMVDD vs. Temperature at Various Supply Voltages, MSS Is Low, Data Rate = 10 Mbps on All SPI Channels –25 0 25 50 75 100 125 TEMPERATURE (°C) 16434-261 2 Figure 56. ISVDD1 vs. Temperature at Various Supply Voltages, SSS Is Low, Data Rate = 10 Mbps on All SPI Channels VMVDD = 2.5V, VSVDD1 = 1.8V VMVDD = 3.3V, VSVDD1 = 3.3V VMVDD = 5.0V, VSVDD1 = 5.0V –25 0 25 50 TEMPERATURE (°C) 75 100 125 Figure 54. SPI Channels Propagation Delay (tPLH) vs. Temperature at Various Supply Voltages –50 –25 0 25 50 TEMPERATURE (°C) 75 100 125 16434-162 –50 16434-159 PROPAGATION DELAY, tPLH (ns) PROPAGATION DELAY, tPHL (ns) VMVDD = 2.5V, VSVDD1 = 1.8V VMVDD = 3.3V, VSVDD1 = 3.3V VMVDD = 5.0V, VSVDD1 = 5.0V Figure 57. SPI Channels Propagation Delay (tPLH) vs. Temperature at Various Supply Voltages Rev. A | Page 21 of 38 ADP1031 4.0 Data Sheet VMVDD = 2.5V, VSVDD2 = 1.8V VMVDD = 3.3V, VSVDD2 = 3.3V VMVDD = 5.0V, VSVDD2 = 5.0V VMVDD = 2.5V, VSVDD2 = 1.8V VMVDD = 3.3V, VSVDD2 = 3.3V VMVDD = 5.0V, VSVDD2 = 5.0V 3.5 2.5 ISVDD2 (µA) IMVDD (mA) 3.0 2.0 1.5 1.0 0 40 20 60 80 100 DATA RATE (kbps) Figure 58. IMVDD vs. Data Rate on All GPIO Channels at Various Supply Voltages, MSS Is High 4.0 3.5 0 20 40 60 DATA RATE (kbps) 80 100 16434-163 0 16434-260 0.5 Figure 61. SVDD2 Supply Current (ISVDD2) vs. Data Rate on All GPIO Channels at Various Supply Voltages, MSS Is High VMVDD = 2.5V, VSVDD2 = 1.8V VMVDD = 3.3V, VSVDD2 = 3.3V VMVDD = 5.0V, VSVDD2 = 5.0V VMVDD = 2.5V, VSVDD2 = 1.8V VMVDD = 3.3V, VSVDD2 = 3.3V VMVDD = 5.0V, VSVDD2 = 5.0V 2.5 ISVDD2 (µA) IMVDD (mA) 3.0 2.0 1.5 1.0 0 25 50 75 100 125 TEMPERATURE (°C) Figure 59. IMVDD vs. Temperature at Various Supply Voltages, MSS Is Low, Data Rate = 40 kbps on All GPIO Channels 10 10 9 7 6 5 4 3 2 25 50 75 100 125 VMVDD = 2.5V, VSVDD2 = 1.8V VMVDD = 3.3V, VSVDD2 = 3.3V VMVDD = 5.0V, VSVDD2 = 5.0V 8 7 6 5 4 3 2 1 1 –25 0 25 50 TEMPERATURE (°C) 75 100 125 0 –50 16434-265 0 –50 0 Figure 62. ISVDD2 vs. Temperature at Various Supply Voltages, SSS Is Low, Data Rate = 40 kbps on All GPIO Channels VSVDD2 = 1.8V VSVDD2 = 3.3V VSVDD2 = 5.0V 8 –25 TEMPERATURE (°C) PROPAGATION DELAY, tPHL (µs) PROPAGATION DELAY, tPLH (µs) 9 V MVDD = 2.5V, V MVDD = 3.3V, V MVDD = 5.0V, –50 16434-166 –25 Figure 60. GPIO Channels Propagation Delay (tPLH) vs. Temperature at Various Supply Voltages –25 0 25 50 TEMPERATURE (°C) 75 100 125 16434-267 0 –50 16434-264 0.5 Figure 63. GPIO Channels Propagation Delay (tPHL) vs. Temperature at Various Supply Voltages Rev. A | Page 22 of 38 Data Sheet ADP1031 THEORY OF OPERATION isolators in a 41-lead LFCSP package for channel to channel isolated applications where power dissipation and board space are at a premium. The ADP1031 is a high performance, isolated micro PMU that combines an isolated flyback regulator, an inverting regulator, and a buck regulator, providing three isolated power rails. Additionally, the ADP1031 includes seven low power digital D1 VOUT1 RFT1 Tx1 1:1 RFB1 SWP FB1 FLYBACK CONTROLLER VINP FEEDBACK AND OVER VOLTAGE CONTROL VOUT1 PG1 SYNC ÷2 PLL VINP R5 R6 HIGH EFFICIENCY BUCK GNDP PGNDP L1 SW3 INVERTING SWITCHING REGULATOR C1 CBUCK SW2 PG2 SLEW MVDD VOUT2 VOUT2 ÷2 EN MVDD RFT3 FB3 VOUT3 PG3 MGND L2 PWRGD CINV RFB3 VOUT3 SVDD2 SVDD2 SGND2 C3 PWRGD MGPO3 MGPI2 CONTROL BLOCK CONTROL BLOCK SGPI3 SGPO2 SGPO1 MGPI1 SVDD1 SVDD1 MSS ENCODE DECODE SSS MCK ENCODE DECODE SCK MO ENCODE DECODE SI MI DECODE ENCODE C4 SO SGND1 MGND NOTES 1. CFLYBK IS THE FLYBACK REGULATOR OUTPUT CAPACITOR VALUE. 2. CBUCK IS THE BUCK REGULATOR OUTPUT CAPACITOR VALUE. 3. CINV IS THE INVERTING REGULATOR OUTPUT CAPACITOR VALUE. Figure 64. Simplified Block Diagram Rev. A | Page 23 of 38 16434-268 CIN CFLYBK ADP1031 Data Sheet FLYBACK REGULATOR Flyback Undervoltage Lockout (UVLO) Flyback Regulator Operation The UVLO circuitry monitors the VINP pin voltage level. If the input voltage drops below the VUVLO_FLYBACK (FALL) threshold, the flyback regulator turns off. After the VINP pin voltage rises above the VUVLO_FLYBACK (RISE) threshold, the soft start period initiates, and the flyback regulator enables. Traditionally, in an isolated flyback regulator, a discrete optocoupler is used in the feedback path to transmit the signal from the secondary side to the primary side. However, the current transfer ratio (CTR) of the optocouplers degrades over time and over temperature. Therefore, the optocoupler must be replaced every 5 years to 10 years. The ADP1031 eliminates the use of an optocoupler and the associated problems by integrating Analog Devices iCoupler technology for feedback, thus reducing system cost, PCB area, and complexity while improving system reliability without the issue of CTR degradation. A flyback transformer with a single primary and secondary winding is used. This configuration is possible because iCoupler technology is used to send an isolated control signal to the primary side controller so that a primary sense winding is not required. In addition, because the secondary and tertiary rails are generated using high efficiency switching regulators, extra secondary windings are not required. This approach offers a number of advantages over an alternative multiwinding solution, such as the following: • • • • A smaller transformer solution size due to a lower number of turns required on the core and a fewer number of pins. Each output can be independently set—the multitap approach requires a custom multitap transformer for different output voltage combinations. Outputs are more accurate because the outputs do not rely on the discrete ratios between the transformer windings. Output accuracy is unaffected by load changes on each rail. Power Saving Mode (PSM) During light load operation, the regulators can skip pulses to maintain output voltage regulation. Therefore, no minimum load is required. Skipping pulses increases the device efficiency but results in larger output ripple. Flyback Regulator Precision Enable Control The flyback regulator in the ADP1031 features a precision enable circuit with an accurate reference voltage. If the voltage at the EN pin rises above the VEN_RISING threshold, the flyback regulator soft start period initiates, and the regulator enables. If the EN pin voltage falls below the VEN_RISING − VEN_HYST threshold, the flyback regulator turns off. Flyback Regulator Soft Start The flyback regulator includes a soft start function that limits the inrush current from the supply and ramps up the output voltage in a controlled manner. The flyback regulator soft start period initiates when the voltage at the EN pin rises above the VEN_RISING threshold. Flyback Slew Rate Control The flyback regulator employs programmable output driver slew rate control circuitry. This circuitry adjusts the slew rate of the switching node as shown in Figure 65, where lower EMI and reduced ringing can be achieved at slightly lower efficiency operation and vice versa. To program the slew rate, connect the SLEW pin to the VINP pin for normal mode, to the GNDP pin for slow mode, or leave it open for fast mode. Note that slew rate control causes a trade-off between efficiency and low EMI. FASTEST SLOWEST 16434-051 The flyback regulator in the ADP1031 generates an isolated output supply rail that can be programmed from 6 V to 28 V for the adjustable output version or 21 V and 24 V for the factory programmable fixed output versions. The flyback regulator adopts current mode control, resulting in a fast inner current controlled loop that regulates the peak inductor current and a slower outer loop via an isolated iCoupler channel that adjusts the current controlled loop to define a regulated output voltage. When the high voltage switch is on, the diode on the secondary side of the transformer is reverse biased, which causes an increase in the current in the primary inductance of the transformer and is stored as energy. When the switch turns off, the diode becomes forward biased and energy stored in the transformer is transferred to the load. Figure 65. Switching Node at Various Slew Rate Settings Table 10. Slew Rate Settings SLEW Pin Connection GNDP VINP Unconnected Rev. A | Page 24 of 38 Slew Rate Slow Normal Fast Comment Lowest EMI Optimized efficiency and EMI Highest efficiency Data Sheet ADP1031 Flyback Regulator Overcurrent Protection Buck Regulator UVLO The flyback regulator features a current-limit function that senses the forward current in the switching metal-oxide semiconductor field effect transistor (MOSFET) on a cycle by cycle basis. If the current exceeds the ILIM (FLYBACK) threshold, the switch turns off. The step-down regulator of theADP1031 features an internal undervoltage lockout circuit that monitors the input voltage to the regulator or VOUT1. If the voltage at VOUT1 drops below the internal threshold level of 4.5 V, the regulator turns off. If the output at VOUT1 rises above the internal threshold, the regulator soft start period initiates, and the regulator enables. Flyback Regulator Overvoltage Protection The flyback regulator of the ADP1031 implements a number of OVP methods to detect and prevent an overvoltage condition on the flyback regulator output, such as the following: • • • If the voltage on the FB1 pin exceeds VFB1 by 10% for the adjustable output version, or the VOUT1 pin exceeds the factory programmed VOUT1 by 10% for the fixed output version, an OVP fault will be detected, which prevents the flyback regulator switch from turning on. The flyback regulator primary switch stays off until the OVP condition is no longer present. If communication across the isolation barrier from the secondary controller to the primary controller fails, the flyback regulator shuts down and a new soft start power-up cycle initiates. If the voltage on the output of the flyback regulator exceeds the severe overvoltage threshold (SOVPFLYBACK), the primary controller does not turn on the primary side switch. The flyback regulator primary switch stays off until the voltage on the VOUT1 pin falls below the SOVPFLYBACK − SOVPFLYBACK_HYST threshold. BUCK REGULATOR Buck Regulator Operation The step-down, dc-to-dc (or buck) regulator in the ADP1031 uses a current mode controlled scheme, operating at a fixed frequency set by an internal oscillator. Current mode uses a fast inner current-controlled loop to regulate peak inductor current and a slower outer loop to adjust the current loop to regulate the output voltage. At the start of each oscillator cycle, the highside MOSFET switch turns on, applying the input voltage to one end of the inductor, which normally causes the buck regulator inductor current (IL_BUCK) to increase until the current sense signal crosses the peak inductor current threshold that turns off the MOSFET switch. The error amplifier output sets this threshold. During the high-side MOSFET off time, the inductor current declines through the low-side MOSFET switch until either the next oscillator clock pulse starts a new cycle that results in continuous conduction mode (CCM) operation, or the inductor current reaches zero, the low-side MOSFET switch is turned off, and the control system waits for the next oscillator clock pulse to start a new cycle, resulting in discontinuous mode (DCM) operation. Under light load conditions, the regulator can skip pulses to maintain regulation and increase power conversion efficiency. Buck Regulator Soft Start The step-down regulator in the ADP1031 includes soft start circuitry that ramps the output voltage in a controlled manner during start-up, thereby limiting the inrush current. Buck Regulator Current-Limit Protection The step-down regulator in the ADP1031 includes a currentlimit protection circuit to limit the amount of forward current through the high-side MOSFET switch. The inductor peak current is monitored cycle by cycle to detect an overload condition. When the overload condition occurs, the currentlimit protection limits the peak inductor current to ILIM (BUCK), resulting in a drop in the output voltage. Buck Regulator OVP The step-down regulator of the ADP1031 features an OVP circuit that monitors the output voltage. If the voltage on the VOUT2 pin exceeds the nominal output voltage by 10%, the step-down, dc-to-dc regulator stops switching until the voltage falls below the threshold again. Buck Regulator Active Pull-Down Resistor The buck regulator has an active pull-down resistor that discharges the output capacitor when the output of VOUT1 is between 1.23 V and 4.5 V. The pull-down resistor connects between VOUT2 and SGND2. Rev. A | Page 25 of 38 ADP1031 Data Sheet INVERTING REGULATOR POWER GOOD Inverting Regulator Operation The ADP1031 provides a push pull, power-good output to indicate when the three isolated output voltage rails are valid. The PWRGD pin pulls high when the voltages on the three supplies are within the respective power-good threshold limits. The inverting, dc-to-dc regulator in the ADP1031 uses a current mode controlled scheme, operating at a fixed frequency set by an internal oscillator. Current mode uses a fast inner current controlled loop to regulate the peak inductor current and a slower outer loop to adjust the current loop to regulate the output voltage. At the start of each oscillator cycle, the high-side MOSFET switch turns on, applying the input voltage to one end of the inductor, which normally causes the inverting regulator inductor current (IINV_INDUCTOR) to increase until the current sense signal crosses the peak inductor current threshold that turns off the MOSFET switch. The error amplifier output sets this threshold. During the high-side MOSFET off time, the inductor current declines through the low-side MOSFET switch until either the next oscillator clock pulse starts a new cycle, which results in CCM operation, or the inductor current reaches zero, the low-side MOSFET switch is turned off, and the control system waits for the next oscillator clock pulse to start a new cycle, resulting in DCM operation. Under light load conditions, the regulator can skip pulses to maintain regulation and increase power conversion efficiency. POWER-UP SEQUENCE The power-up sequence is as follows (see Figure 66): 1. The flyback regulator powers up first (see 1 in Figure 66). 2. When VOUT1 rises above the lower power-good threshold (VPG_FLYBACK_LL), the buck regulator turns on (see 2 in Figure 66). 3. When the buck regulator output (VOUT2) rises above the lower power-good threshold (VPG_BUCK_LL), the inverting regulator turns on (see 3 in Figure 66). 4. PWRGD is driven high when the inverting regulator output (VOUT3) is below the power-good threshold, VPG_INVERTER_LL (see 4 in Figure 66). 5. If any of the three analog supplies move outside the powergood threshold ranges, PWRGD drives low after a short deglitch delay (see 5 in Figure 66). VOUT1 VPG_FLYBACK_U L Inverting Regulator UVLO VPG_FLYBACK_L L The inverting, dc-to-dc regulator of the ADP1031 features an internal UVLO circuit that monitors the input voltage to the regulator or VOUT1. If the voltage at VOUT1 drops below the internal threshold level of 4.5 V, the regulator turns off. If the output of VOUT1 rises above the internal threshold, the regulator soft start period initiates, and the regulator enables. VINP 2 VOUT2 VPG_BUCK_LL 1 3 0V Inverting Regulator Soft Start VOUT3 The inverting, dc-to-dc regulator in the ADP1031 includes soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. VPG_INVERTER_L L Inverting Regulator Current-Limit Protection 4 HIGH PWRGD 16434-052 The inverting, dc-to-dc regulator in the ADP1031 includes a current-limit protection circuit to limit the amount of forward current through the high-side MOSFET switch. The inductor peak current is monitored cycle by cycle to detect an overload condition. When the overload condition occurs, the current-limit protection limits the peak inductor current to ILIM (INVERTER), resulting in a drop in the output voltage. 5 LOW Figure 66. Power-Up Sequencing and PWRGD OSCILLATOR AND SYNCHRONIZATION Inverting Regulator Active Pull-Down Resistor A phase-locked loop (PLL)-based oscillator generates the internal clock for the flyback, buck, and inverter regulators and offers an internally generated frequency or external clock synchronization. Connect the SYNC pin as describe in Table 11 to configure the switching frequency. For external synchronization, connect the SYNC pin to a suitable clock source. The PLL locks to an input clock within the range specified by fSYNC. Table 11. Sync Pin Functionality The inverting regulator has an active pull-down resistor that discharges the output capacitor when the output of VOUT1 is between 1.23 V and 4.5 V. The pull-down resistor connects between VOUT3 and SGND2. SYNC Pin State, fSYNC Low or High 350 kHz to 750 kHz Inverting Regulator OVP The inverting, dc-to-dc regulator of the ADP1031 features an OVP circuit that monitors the voltage on the FB3 pin. If the voltage on this pin falls below VFB3 by 10%, the inverting regulator stops switching until the voltage rises above the threshold again. Rev. A | Page 26 of 38 Switching Frequency (fSW) Flyback Buck Inverter 250 kHz 125 kHz 125 kHz fSYNC ÷ 2 fSYNC ÷ 4 fSYNC ÷ 4 Data Sheet ADP1031 THERMAL SHUTDOWN The datapaths are SPI mode agnostic. The CLK and MO/SI SPI datapaths are optimized for propagation delay and channel to channel matching. The MI/SO SPI datapath is optimized for propagation delay. The device does not synchronize to the clock channels. Therefore, there are no constraints on the clock polarity or timing with respect to the data lines. If the ADP1031 junction temperature rises above TSHDN, the thermal shutdown circuit turns the flyback regulator off. Extreme junction temperatures can be the result of prolonged high current operation, poor circuit board design, and/or high ambient temperatures. When thermal shutdown occurs, hysteresis is included so that the ADP1031 does not return to operation until the on-chip temperature drops below TSHDN − THYS. When resuming from thermal shutdown, the ADP1031 performs a soft start. DATA ISOLATION High Speed SPI Channels The ADP1031 has four high speed channels. The first three, CLK, MI/SO, and MO/SI (the slash indicates the connection of the input and output forming a datapath across the isolator that corresponds to an SPI bus signal) are optimized for low propagation delay. With a maximum propagation delay of 15 ns, the ADP1031 supports read and write clock rates up to 16.6 MHz in the standard 4-wire SPI. However, the total round trip delay of the system determines the maximum clock rate and is less than that value. The relationship between the SPI signal paths, the ADP1031 pin mnemonics, and the data directions are detailed in Table 12. Table 12. Correspondence of the Pin Mnemonics to the SPI Signal Path Names SPI Signal Path CLK MO/SI MI/SO SS Master Side MCK MO MI MSS Data Direction → → ← → MSS ENCODE DECODE SSS MCK ENCODE DECODE SCK MO ENCODE DECODE SI MI DECODE ENCODE SO Slave Side SCK SI SO SSS 16434-053 SS (slave select bar) is an active low signal. To save power in a multichannel system, SS puts the other SPI isolator channels in a low power state when the channels are not in use (SS = high), and these channels are only active when required, which is when SS is low. The clock and data channels are gated to the SS as shown in Figure 67. However, this power saving mode adds 100 ns of latency. This latency is the time required for the internal circuitry to wake up from the low power state and to start transmitting data to the isolation barrier. Conversely, the latency is the delay from the falling edge of MSS to the first clock edge or data edge that appears on the slave side, as shown in Figure 68. Figure 67. iCoupler Gating SPI ACTIVATION (LATENCY) SPI TRANSMIT MSS SSS tP1 tPW tP2 MCK, MO, SO tP3 SCK, SI, MI LATENCY = MSS FALLING EDGE TO SCK, SI, MI STARTS SENDING DATA (EXIT TO HIGH IMPEDANCE MODE). t PW = MCK, MO, SO PULSE WIDTH. t P1 = MSS TO SSS PROPAGATION DELAY. t P2 = MCK TO SCK, MO TO SI, SO TO MI PROPAGATION DELAY. t P3 = MSS RISING EDGE TO SCK, SI, MI RETURN TO HIGH IMPEDANCE STATE. SAME AS t P1. Figure 68. SPI Isolators Timing Diagram Rev. A | Page 27 of 38 16434-054 HIGH IMPEDANCE ADD A PULL HIGH OR PULL LOW RESISTOR TO HAVE A KNOWN STATE WHEN MSS IS HIGH. ADP1031 Data Sheet MSS MSS1 SCK MCK MCK MO MO CHANNEL 1 SI SO MI MI The MI, SCK, and SI outputs are also tristated when MSS is high (see Table 13) to allow a more flexible design and to avoid the requirement for external multiplexing of MI in a multichannel system. Figure 69 shows how the SPI busses from multiple ADP1031 devices can be connected together. SSS Table 13. SPI MSS Gating MSS2 MSS SSS Parameter MSS High MSS Low MCK SCK SSS High Low SCK Tristate MCK SI Tristate MO MI Tristate SO MO CHANNEL 2 SO MI MCK MO CHANNEL 3 MI GPIO Data Channels SO The general-purpose data channels are provided as space-saving isolated datapaths where timing is not critical. The dc value of all low speed general-purpose inputs, on a given side of the device, are sampled simultaneously, packetized, and shifted across a single isolation coil. The process is then reversed by reading the inputs on the opposite side of the device, packetizing the inputs and sending these inputs back for similar processing. Because of the sampled nature of this process, the generalpurpose data channels exhibit a sampling uncertainty that resembles 19.5 µs peak jitter. SCK MCK MO SI SSS MSS MSS4 SCK Connect a pull-up or pull-down resistor to MI, SCK, and SI to pull these pins to the desired logic state when MSS is high. SSS MSS MSS3 SI CHANNEL 4 SI SO 16434-055 MI TO CHANNEL 5 THROUGH CHANNEL 8 For proper operation of the GPIO channels, refer to Table 14. Power both MVDD and SVDD2 within the specified input voltage range for these pins. Figure 69. Multichannel SPI Muxing Scheme Table 14. Truth Table for GPIO Channels MVDD State Unpowered Powered Powered Powered Powered SVDD2 State Powered Unpowered Powered Powered Powered to Unpowered xGPIx Don’t care Don’t care High Low Don’t care MGPOx Low Low High Low Hold SGPOx Low Low High Low Low Powered to Unpowered Powered Don’t care Low Hold Rev. A | Page 28 of 38 Test Conditions/Comments During startup During startup Normal operation Normal operation Hold means that the current state of the outputs are preserved Hold means that the current state of the outputs are preserved Data Sheet ADP1031 APPLICATIONS INFORMATION COMPONENT SELECTION As with the flyback regulator, calculate the value of the top resistor for the target VOUT3 by the following equation: Feedback Resistors The ADP1031 provides an adjustable output voltage for both flyback and inverting regulators. An external resistor divider sets the output voltage where the divider output must equal the appropriate feedback reference voltage, VFB1 or VFB3. To limit the output voltage accuracy degradation due to the feedback bias current, ensure that the current through the divider is at least 10 times IFB1 or IFB3. The recommended RFB1 and RFB3 values are in the range of 50 kΩ to 250 kΩ to minimize the output voltage error due to the bias current and to lessen the power dissipation across the feedback resistors. The external feedback resistors are not required for the fixed output versions because the feedback resistors are already inside the chip. RFT1 Tx1 SWP VINP VOUT1 6V TO 28V D1 RFB1 SGND2 VOUT1 FB1 FLYBACK Set the positive output for the flyback regulator by VOUT1 = VFB1 × (1 + (RFT1/RFB1)) where: VOUT1 is the flyback output voltage. VFB1 is the flyback feedback voltage. RFT1 is the feedback resistor from VOUT1 to FB1. RFB1 is the feedback resistor from FB1 to SGND2. Conversely, calculate the value of the top resistor for the target VOUT1 by: RFT1 = RFB1 × ((VOUT1/VFB1) − 1) VOUT3 –24V TO –5V FB3 SW3 RFB3 L2 100µH RFT3 CINV 4.7µF SGND2 16434-074 INVERTER Desired Output Voltage (V) ±6 ±9 ±12 ±15 ±24 +28 RFT1/RFT3 (MΩ) 0.715 1.24 1.54 2.15 3.48 3.4 Flyback/Inverting Regulator RFB1/RFB3 Calculated Output (kΩ) Voltage (V) 110 ±6.000 121 ±8.998 110 ±12.000 121 ±15.015 120 ±24.000 100 +28.000 Capacitor Selection Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with voltage ratings of 25 V to 50 V (depending on output) are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. Figure 70. Flyback Regulator Output Voltage Setting VOUT3 Table 15. Recommended Feedback Resistor Values Higher output capacitor values reduce the output voltage ripple and improve the load transient response. When choosing this value, it is also important to account for the loss of capacitance due to the output voltage dc bias. CFLYBK 4.7µF 16434-073 1:1 VINP RFT3 = RFB3 × ((VOUT3/VFB3) − 1) Figure 71. Inverting Regulator Output Voltage Setting Set the negative output for the inverting regulator by VOUT3 = VFB3 × (1 + (RFT3/RFB3)) where: VOUT3 is the inverting regulator output voltage (negative sign disregarded). VFB3 is the inverting regulator feedback voltage in reference to VOUT3. RFT3 is the feedback resistor from FB3 to SGND2. RFB3 is the feedback resistor from VOUT3 to FB3. Calculate the worst case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage using the following equation: CEFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) × (1 − Tolerance) where: CEFFECTIVE is the effective capacitance at the operating voltage. CNOMINAL is the nominal capacitance shown in this data sheet. TEMPCO is the worst case capacitor temperature coefficient. DCBIASCO is the dc bias derating at the output voltage. Tolerance is the worst case component tolerance. To guarantee the performance of the device, it is imperative to evaluate the effects of dc bias, temperature, and tolerances on the behavior of the capacitors for each application. Capacitors with lower effective series resistance (ESR) and effective series inductance (ESL) are preferred to minimize voltage ripple. Rev. A | Page 29 of 38 ADP1031 Data Sheet FLYBACK REGULATOR COMPONENTS SELECTION Primary Inductance Input Capacitor The ADP1031 operates with a transformer with an inductance in the 80 µH to 560 µH range. However, it is recommended to choose an inductance value that results in the flyback output voltage (VOUT1) divided by the transformer primary inductance being less than or equal to 140,000 to maintain control loop stability. VOUT1/LPRI ≤ 140,000 where: VOUT1 is the flyback regulator output voltage. LPRI is the primary side inductance of the transformer. An input capacitor must be placed between the VINP pin and ground. Ceramic capacitors greater than or equal to 3.3 µF over temperature and voltage are recommended. The input capacitor reduces the input voltage ripple caused by the switching current. Place the input capacitor as close as possible to the VINP and PGNDP pins to reduce input voltage spikes. The voltage rating of the input capacitor must be greater than the maximum input voltage. Output Capacitor Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to the output voltage dc bias. A 4.7 µF capacitor is recommended as a balance between performance and size. Ripple Current vs. Capacitor Value The output capacitor value must be chosen to minimize the output voltage ripple while considering the increase in size and cost of a larger capacitor. Use the following equation to calculate the output capacitance: COUT = (LPRI × ISWP2)/(2 × VOUT1 × ΔVOUT1) where: COUT is the capacitance of the flyback output capacitor. LPRI is the primary inductance of the transformer. ISWP is the peak switch current. VOUT1 is the flyback regulator output voltage. ΔVOUT1 is the allowable flyback regulator output ripple. Schottky Diode A Schottky diode with low junction capacitance is recommended for D1. At higher output voltages and especially at higher switching frequencies, the junction capacitance is a significant contributor to efficiency. Choose an output diode with a forward current rating (IF) that is greater than the maximum load requirement and with a reverse voltage rating (VR) that is greater than the summation of the maximum supply voltage (VINP (MAX)) and the maximum output voltage (VOUT1 (MAX)). Transformer The transformer used with the ADP1031 is an important component within the system, in terms of efficiency and maximum output power capability. Analog Devices worked with a number of leading magnetic component suppliers to develop a number of transformer designs for use with the ADP1031. These designs are listed in Table 16. A number of factors must be taken into account when designing a transformer for use with the ADP1031. Turn Ratio The ADP1031 requires the use of a transformer with a primary to secondary turn ratio of 1:1 to start up properly. Using a transformer at the lower end of the inductance range may result in a smaller transformer but also reduces the output power capabilities due to larger ac ripple current through the transformer. Conversely, operating at higher inductance can result in higher output power at the expense of a potentially larger transformer. Flyback Transformer Saturation Current Do not exceed the saturation current of the transformer in operation or this may lead to much higher losses and overall lower system efficiency. Choose a transformer with a saturation current rating that is greater than the expected peak switch current (ISWP) across line and load conditions. Series Winding Resistance In power loss sensitive applications, keep the series resistance of the primary and secondary windings as low as possible to improve overall efficiency. Leakage Inductance and Clamping Circuits When choosing a transformer to operate with the ADP1031, minimize transformer leakage inductance. Leakage inductance causes a voltage spike to appear on the SWP node when the flyback regulator switch is off due to energy storage in the leakage inductance that is not transferred to the output. The voltage spike is more prominent at higher load currents and increases with higher leakage inductance. It is important to keep the voltage spikes lower than the voltage rating of the flyback switch that drives the SWP pin. Margin must be built in to any design to avoid exceeding this limit if no clamp or snubber circuit is used to protect the flyback switch. To estimate the leading voltage spike at the SWP pin when the switch turns off, use the following equation: VPEAK = IPEAK × (LLEAK/(CP + CSWP))1/2 + VINP + VOUT1 + VD where: VPEAK is the voltage spike amplitude. IPEAK is the peak current on the flyback switch. LLEAK is the leakage inductance of the transformer. CP is the parasitic capacitance of the transformer. CSWP is the capacitance on the flyback switch. VINP is the input supply voltage. VOUT1 is the output voltage of the flyback regulator. VD is the forward voltage drop across the rectifier diode. A snubber or clamp circuit can protect the flyback switch for cases where the leakage inductance is too high for application conditions. Two common types of clamping circuit are the Rev. A | Page 30 of 38 Data Sheet ADP1031 Tx1 1:1 VINP D1 VOUT1 VCLAMP VINP (MAX) Figure 74. Clamping Waveform Use the following equation to calculate the value of the clamping resistor for a given VCLAMP value: where: RCLAMP is the value of the clamping resistor. VCLAMP is the clamping voltage. VOUT1 is the output voltage of the flyback regulator. LLEAK is the leakage inductance of the transformer. IPEAK is the peak current on the flyback switch. fSW is the switching frequency of the flyback regulator. LLEAK SWP 16434-276 To calculate the power dissipation across the snubber resistor, use the following equation: PRCLAMP = (VCLAMP)2/(RCLAMP) Figure 72. Resistor, Capacitor, Diode Clamp Tx1 1:1 VINP ZCLAMP VOUT1 (MAX) + VINP (MAX) RCLAMP = (2 × VCLAMP × (VCLAMP − VOUT1))/(LLEAK × IPEAK2 × fSW) RCLAMP CCLAMP L PRI DCLAMP SWPVMAX 16434-278 resistor, capacitor, diode clamp shown in Figure 72 and the diode Zener diode clamp shown in Figure 73. The resistor, capacitor, diode clamp quickly dampens the voltage spike and provides improved EMI performance, and the diode Zener diode clamp can be used when the clamping level must be consistent and well defined. The diode Zener diode clamp has slightly higher power efficiency over the resistor, capacitor, diode clamp. However, the cost of the diode Zener diode clamp solution is typically higher than the resistor, capacitor, diode solution. D1 where PRCLAMP is the power dissipation across RCLAMP. Choose RCLAMP with power rating of about twice this value to have margin. VOUT1 LPRI Clamping Capacitor DCLAMP The clamping capacitor (CCLAMP) is used to minimize the voltage ripple level (VRIPPLE) superimposed in VCLAMP. Calculate the clamping capacitor by using the following equation for the desired VRIPPLE level and the calculated RCLAMP: LLEAK SWP 16434-277 CCLAMP = VCLAMP/(VRIPPLE × fSW × RCLAMP) Figure 73. Diode Zener Diode Clamp Clamping Resistor To calculate the clamping resistor (RCLAMP) value, the clamping voltage (VCLAMP) must be determined. The clamping voltage is the voltage on which any voltage spike that occurs on the flyback switch is clamped. Choose a clamping voltage (VCLAMP) that provides sufficient margin between the SWP maximum voltage rating (SWPVMAX) specified in the Absolute Maximum Ratings section and that also is greater than the summation of the maximum input supply (VINP (MAX)) and the maximum flyback output voltage (VOUT1 (MAX)) of the application as given by where: CCLAMP is the value of the clamping capacitor. VCLAMP is the clamping voltage. VRIPPLE is the voltage ripple superimposed in VCLAMP. A VRIPPLE of about 5% to 10% of VCLAMP is reasonable. fSW is the switching frequency of the flyback regulator. RCLAMP is the value of the clamping resistor. Clamping Diode Schottky diodes are typically the best choice. However, fast recovery diodes can also be used. The diode reverse voltage rating must be higher than the maximum SWP pin voltage rating. SWPVMAX > VINP (MAX) + VCLAMP > VINP (MAX) + VOUT1 (MAX) Rev. A | Page 31 of 38 ADP1031 Data Sheet Diode Zener Diode Clamp Maximum Output Current Calculation A Zener diode can replace the resistor, capacitor (RC) network on the resistor, capacitor, diode clamp when the clamping level must be consistent and well defined. Choose the Zener diode breakdown voltage to balance power loss and switch voltage protection. Calculate the Zener voltage by using the following equation: The maximum output power and current that can be achieved from the flyback output depends on a number of variables within the regulator. These variables include the transformer choice, the operating frequency, and the rectifier diode choice. The flyback regulator output is the supply to the buck regulator that drives VOUT2 and the inverting regulator that drives VOUT3. Determine the maximum output power capability by VZENER (MAX) ≤ SWPVMAX − VINP (MAX) where: VZENER (MAX) is the maximum Zener diode breakdown voltage or the Zener voltage, which can be the same as the clamping voltage, VCLAMP. SWPVMAX is the absolute maximum rating of the SWP pin. VINP (MAX) is the maximum input supply voltage. The power loss in the clamp determines the power requirement for the Zener diode. Use the following equation to calculate the Zener diode power dissipation: PZENER = (VZENER × LLEAK × IPEAK2 × fSW)/(2 × (VZENER − VOUT1)) where: PZENER is the Zener diode power dissipation. Choose a Zener diode with power rating higher than the calculated value. VZENER is the Zener diode breakdown voltage or the Zener voltage. LLEAK is the leakage inductance of the transformer. IPEAK is the peak current on the flyback switch. fSW is the switching frequency of the flyback regulator. VOUT1 is the output voltage of the flyback regulator. Ripple Current (IAC) vs. Inductance Calculate the ripple current by first determining the duty cycle in continuous conduction mode. PVOUT1 (MAX) = 0.5 × (IPEAK2 − (IPEAK − IAC/2)2) × LPRI × fSW × η where: PVOUT1 (MAX) is the maximum output power from VOUT1. IPEAK is the peak current on the flyback switch. IAC is the ripple current through the primary side of the transformer and flyback switch. LPRI is the primary side inductance of the transformer. fSW is the switching frequency of the flyback regulator. η is the expected efficiency of the flyback regulator. The lower limit of the flyback current-limit threshold, ILIM (FLYBACK), limits the maximum IPEAK. However, it is not recommended to operate at this level to avoid unwanted current-limit events due to variation in transformer inductance, efficiency, flyback switching frequency, and rectifier diode forward voltage drop. If the load on the flyback causes the current limit to trip, the output voltage may not regulate as expected. It is recommended to choose a peak operating current with built in margin for the variations mentioned or to calculate the maximum output power or output load using the worst case transformer inductance, efficiency, diode forward voltage drop, and flyback switching frequency. Calculate the maximum load current on VOUT1 by IVOUT1 (MAX) = PVOUT1 (MAX)/VOUT1 DCCM = (VOUT1 + VD)/(VOUT1 + VD + VINP) where: IVOUT1 (MAX) is the maximum output current from VOUT1. PVOUT1 (MAX) is the maximum output power from VOUT1. VOUT1 is the output voltage of the flyback regulator. where: DCCM is the duty cycle of the flyback switch. VOUT1 is the output voltage of the flyback regulator. VD is the forward voltage drop across the rectifier diode. VINP is the input supply voltage. Then, from the duty cycle, calculate the IAC in the flyback switch and transformer primary. IAC = (VINP × DCCM)/(fSW × LPRI) where: IAC is the ripple current through the primary side of the transformer and flyback switch. VINP is the input supply voltage. DCCM is the duty cycle of the flyback switch. fSW is the switching frequency of the flyback regulator. LPRI is the primary side inductance of the transformer. Rev. A | Page 32 of 38 Data Sheet ADP1031 BUCK REGULATOR COMPONENTS SELECTION Inductor The value of the inductor for the ADP1031 buck regulator affects the efficiency and the output voltage ripple. Larger value inductors typically improve efficiency. However, for a given package size, as load increases, the dc resistance (DCR) and core losses eventually have an increasing negative impact on efficiency. Using a smaller value inductor reduces output voltage ripple but can decrease the overall efficiency due to increased switching losses. Output Capacitor The output capacitor selection affects the output ripple voltage, load step transient, and the loop stability of the regulator. A 4.7 µF capacitor is recommended as a balance between performance and size, but a larger capacitor can be used to reduce output ripple. INVERTING REGULATOR COMPONENT SELECTION Inductor The value of the inductor for the ADP1031 inverting regulator affects the efficiency and output voltage ripple. Larger value inductors typically improve efficiency. However, for a given package size, as load increases, the DCR and core losses eventually have an increasing negative impact on efficiency. Using a smaller value inductor reduces output voltage ripple but can decrease the overall efficiency due to increased switching losses. Output Capacitor The output capacitor selection affects the output ripple voltage, load step transient, and the loop stability of the regulator. A minimum of 4.7 µF capacitor is recommended to maintain stability across VOUT1 and output load. Inverting Regulator Stability The ADP1031 inverting regulator uses internal compensation and operates with an inductance of 100 µH and a typical capacitance of 4.7 µF. Using different component values may result in instability of VOUT3, particularly if lower capacitance and smaller inductor values are used. Consult the factory for guidance. Operating the inverter with the recommended inductor and output capacitor, the output is stable from no load to a 15 mA load for any output from −24 V to −5 V. When increasing the load beyond 15 mA, it is recommended to use a larger output capacitor to stabilize the feedback loop, particularly for lower output voltages. Table 16. Transformer Selection Primary Part Number 750316743 750316566 WA8478-BE YA9293-AL BS64042CS LPD5030-154MRB Manufacturer Würth Elektronik Würth Elektronik Coilcraft Coilcraft Bourns Coilcraft Turns Ratio1 1:1 1:1 1:1 1:1 1:1 1:1 Inductance (µH) 280 150 275 300 270 150 Resistance (Ω) 1.1 1.65 1.2 1.15 1.4 2.43 Saturation Current2 (mA) 250 220 150 250 400 430 Isolation Voltage3 (V rms) 2000 2000 2250 2250 2200 Not applicable Isolation Type Basic Basic Basic Reinforced Basic Functional Size, Length × Width × Height, (mm) 8.26 × 8.6 × 9.65 7.0 × 6.91 × 7.8 7.25 × 7.85 × 7.0 10 × 12.07 × 5.97 10.5 × 9.8 × 11.0 4.8 × 4.8 × 2.9 Turns ratio between the primary and secondary coils. 20% drop from initial. 3 1 minute duration. 1 2 Table 17. Buck Regulator and Inverting Regulator Recommended Inductors Part Number 744043101 XFL3012-104MEB LQH3NPN101MMEL SRN3015-101M SRU2016-101Y XFL2006-104MEB 1 Manufacturer Würth Elektronik Coilcraft Murata Bourns Bourns Coilcraft Inductance (µH) 100 100 100 100 100 100 DC Resistance (Ω) 0.55 2.63 1.59 2.92 4.9 11.1 30% drop in inductance. Rev. A | Page 33 of 38 Saturation Current1 (mA) 290 280 260 270 150 115 Size, Length × Width × Height, (mm) 4.8 × 4.8 × 2.8 3.2 × 3.2 × 1.3 3 × 3 × 1.4 3 × 3 × 1.5 2.8 × 2.8 × 1.65 2 × 2 × 0.6 ADP1031 Data Sheet INSULATION LIFETIME Surface Tracking Surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. Safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material groups. Lower material group ratings are more resistant to surface tracking. Therefore, lower material group ratings provide adequate lifetime with smaller creepage. The minimum creepage for a given working voltage and material group is determined in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material group. The material group and creepage for the ADP1031 isolators are shown in Table 4. VRMS 2 − VDC 2 (2) V= AC RMS where: VRMS is the total rms working voltage. VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. Calculation and Use of Parameters Example The following example frequently arises in power conversion applications. Assume that the line voltage on one side of the isolation is 240 V ac rms and a 400 V dc bus voltage is present on the other side of the isolation barrier. The isolator material is polyimide. To establish the critical voltages in determining the creepage, clearance, and lifetime of a device, see Figure 75 and the following equations. VAC RMS VRMS VPEAK Insulation Wear Out VDC TIME The lifetime of insulation is determined by thickness, material properties, and the voltage stress applied. It is important to verify that the product lifetime is adequate at the application working voltage. The working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. The working voltage applicable to tracking is specified in most standards. Testing and modeling have shown that the primary driver of long-term degradation is displacement current in the polyimide insulation. This displacement current causes incremental damage to the insulation. The stress on the insulation can be broken down into broad categories: dc stress and ac component time varying voltage stress. DC stress causes very little insulation wear out because there is no displacement current. AC component time varying voltage stress causes insulation wear out. The ratings in certification documents are usually based on 60 Hz sinusoidal stress because this reflects isolation from line voltage. However, many practical applications have combinations of 60 Hz ac and dc across the barrier as shown in Equation 1. Because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as shown in Equation 2. For insulation wear out with the polyimide materials, the ac rms voltage determines the product lifetime. Figure 75. Critical Voltage Example The working voltage across the barrier from Equation 1 is VRMS = VAC RMS 2 + VDC 2 VRMS = 240 2 + 400 2 VRMS = 466 V This VRMS value is the working voltage and is used together with the material group and pollution degree when looking up the creepage required by a system standard. To determine if the lifetime is adequate, obtain the time varying portion of the working voltage. To obtain the ac rms voltage, use Equation 2. V= AC RMS VRMS 2 − VDC 2 VAC RMS = 466 2 − 400 2 VAC RMS = 240 V rms In this case, the ac rms voltage is simply the line voltage of 240 V rms. This calculation is more relevant when the waveform is not sinusoidal. The value is compared to the limits for working voltage in Table 8 for the expected lifetime, which is less than a Rev. A | Page 34 of 38 16434-375 The two types of insulation degradation of primary interest are breakdown along surfaces exposed to the air and insulation wear out. Surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. Insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-term insulation degradation. (1) or ISOLATION VOLTAGE All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation as well as on the materials and material interfaces. VRMS = VAC RMS 2 + VDC 2 Data Sheet ADP1031 60 Hz sine wave, and it is well within the limit for a 20-year service life. The dc working voltage limit is set by the creepage of the package as specified in IEC 60664-1. This value can differ for specific system level standards. THERMAL ANALYSIS For the purpose of thermal analysis, the ADP1031 die are treated as a thermal unit, with the highest junction temperature reflected in the θJA values from Table 7. The value of θJA is based on measurements taken with the devices mounted on a JEDEC standard, 4-layer board with fine width traces and still air. Under normal operating conditions, the ADP1031 operates at a full load across the full temperature range without derating the output current. However, following the recommendations in the PCB Layout Considerations section decreases thermal resistance to the PCB, allowing increased thermal margins in high ambient temperatures. Each switching regulator in the ADP1031 has a thermal shutdown circuit that turns off the dcto-dc converter and the outputs when a die temperature of approximately 150°C is reached. When the die cools below approximately 135°C, the ADP1031 dc-to-dc converter outputs turn on again. Rev. A | Page 35 of 38 ADP1031 Data Sheet TYPICAL APPLICATION CIRCUIT D1 1:1 BAT46W-7-F +24V VINP SWP CFLYBK 10µF 120kΩ FB1 SGND2 VOUT1 VINP 3.4MΩ CIN 4.7µF 232kΩ PGNDP SW2 PGNDP VOUT3 GNDP FB3 SLEW SW3 MVDD 100kΩ PGOOD FAULT LDAC ADuCM3029 RESET SYNC PWRGD MGPO3 MGPI2 SGPI3 MGND SGPO2 CS CLK MOSI MISO GND MGND SGND2 SVDD1 MVDD SGND1 MSS SSS SCK MCK SI MO MI MGND –12V 110kΩ 1.54MΩ CINV 10µF L2 100µH 100kΩ PGND 100nF SGPO1 SVDD2 MVDD L1 100µH CBUCK 10µF ADP1031 MGPI1 100nF VBAT +5.15V VOUT2 EN 100nF 100nF 100kΩ CLKOUT 100kΩ 100nF 100nF AVSS 47µH 100nF AVDD2 AVDD1 SW+ VLOGIC SCLK SDI +VSENSE CCOMP FAULT –VSENSE LDAC RESET DGND AD1 AD0 REFOUT REFIN RA RB 13.7kΩ DGND HART SIGNAL Figure 76. Typical Application Circuit for the ADP1031 Using the AD5758 Rev. A | Page 36 of 38 1kΩ VIOUT AD5758 SDO 100kΩ VDPC+ VLDO SYNC SO 2.2µF RLOAD 1kΩ CHART AGND AGND 16434-059 Tx1 750316743 3.48MΩ Data Sheet ADP1031 • • • • • • Keep the input bypass capacitor, CIN, close to the VINP pin and the PGNDP pin. Keep the high current switching paths as short as possible. These paths include the connections between the following: • CIN, VINP, the primary winding of the transformer, and PGNDP • VOUT1, CFLYBK, Diode 1 (D1), the secondary winding of the transformer, and SGND2 • VOUT2, SW2, Inductance 1 (L1), CBUCK, and SGND2 • VOUT3, SW3, Inductance 2 (L2), CINV, and SGND2 Keep high current traces as short and wide as possible to minimize parasitic series inductance, which causes spiking and EMI. Avoid routing high impedance traces near any node connected to the SWP, SW2, and SW3 pins or near the L1 and L2 inductors or the T1 transformer to prevent radiated switching noise injection. Place the feedback resistors as close to the FB1 and FB3 pins as possible to prevent high frequency switching noise injection. To minimize EMI, place the MVDD decoupling capacitor (C1) as close to the MVDD pin (Pin 39) and the MGND pin (Pin 3). • To minimize EMI, place the SVDD1 decoupling capacitor (C3) as close to the SVDD1 pin (Pin 10) and the SGND1 pin (Pin 5), and place the SVDD2 decoupling capacitor (C7) as close to the SVDD2 pin (Pin 20) and the SGND2 pin (Pin 16). Figure 77 shows a suggested top layer layout for the ADP1031. Rev. A | Page 37 of 38 18.8mm T1 D1 R9 R10 VINP VOUT1 PGNDP L1 CIN U1 C7 C3 MVDD CFLYBK VOUT2 L2 CBUCK VOUT3 C1 CINV 23mm To achieve optimum efficiency, proper regulation, strong stability, and low noise, a well designed PCB layout is required. Follow these guidelines when designing PCBs: R7 R8 Figure 77. Suggested Top Layer Layout 16434-060 PCB LAYOUT CONSIDERATIONS ADP1031 Data Sheet OUTLINE DIMENSIONS 0.50 BSC 7.10 7.00 6.90 TOP VIEW 31 PKG-005383 SEATING PLANE 0.30 0.25 0.20 0.35 0.30 0.25 41 1 *EXPOSED PAD *EXPOSED PAD 2.75 BSC 2.15 MIN 2.14 2.04 1.94 *EXPOSED PAD 0.45 0.40 0.35 (Pins 8-41) SIDE VIEW 3.88 3.78 3.68 30 24 1.00 0.95 0.90 2.15 MIN 1.72 1.62 1.52 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 23 BOTTOM VIEW 7.70 7.60 7.50 8 7 3.75 BSC 1.46 1.36 1.26 0.435 0.385 0.335 (Pins 1-7) * FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 09-05-2019-D 9.10 9.00 8.90 PIN 1 INDICATOR AREA Figure 78. 41-Lead Lead Frame Chip Scale Package [LFCSP] 9 mm × 7 mm Body and 0.95 mm Package Height (CP-41-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP1031ACPZ-1-R7 ADP1031ACPZ-2-R7 ADP1031ACPZ-3-R7 ADP1031ACPZ-4-R7 ADP1031ACPZ-5-R7 ADP1031CP-1-EVALZ ADP1031CP-2-EVALZ ADP1031CP-3-EVALZ ADP1031CP-4-EVALZ ADP1031CP-5-EVALZ 1 2 VOUT1 2 Adjustable Adjustable Adjustable 24 V 21 V Adjustable Adjustable Adjustable 24 V 21 V VOUT2 5.15 V 5V 3.3 V 5.15 V 5.15 V 5.15 V 5V 3.3 V 5.15 V 5.15 V VOUT3 Adjustable Adjustable Adjustable Adjustable Adjustable Adjustable Adjustable Adjustable Adjustable Adjustable Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 41-Lead LFCSP 41-Lead LFCSP 41-Lead LFCSP 41-Lead LFCSP 41-Lead LFCSP Evaluation Board for the ADP1031ACPZ-1 Evaluation Board for the ADP1031ACPZ-2 Evaluation Board for the ADP1031ACPZ-3 Evaluation Board for the ADP1031ACPZ-4 Evaluation Board for the ADP1031ACPZ-5 Z = RoHS Compliant Part. For other VOUT1 voltage options, contact Analog Devices local sales representatives for additional information. ©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16434-0-12/19(A) Rev. A | Page 38 of 38 Package Option CP-41-1 CP-41-1 CP-41-1 CP-41-1 CP-41-1