ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
UG-664
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
240 W Evaluation Board Kit for the ADP1050, Digital Controller for Isolated Power
Supply with PMBus Interface
FEATURES
GENERAL DESCRIPTION
Full support evaluation kit for the ADP1050
240 W full bridge topology
Input voltage range: 36 V dc to 75 V dc
Output voltage: 12 V dc
Nominal output current: 20 A
Synchronization as slave device
On-board tests for housekeeping functions
LED indicated key status
PMBus communication
Graphical user interface (GUI) software
The ADP1051-240-EVALZ evaluation board, together with
an ADP1050DC1-EVALZ daughter card, allows the user to
evaluate the ADP1050 in a power supply unit (PSU) environment. The boards are fully compatible with the ADP1050-51
GUI software. With the ADP-I2C-USB-Z USB-to-I2C connector
and the GUI software, the ADP1050 on the evaluation board
can be interfaced with a PC via a USB port.
The evaluation board allows the ADP1050 to be exercised
without the need for external components. The board is set up
to act as an isolated PSU, outputting a rated load of 12 V, 20 A
from a 36 V dc to 75 V dc source.
EVALUATION KIT CONTENTS
ADP1051-240-EVALZ evaluation board
ADP1050DC1-EVALZ daughter card
CD with ADP1050-51 GUI installer, ADP1050 data sheet,
ADP1051-240-EVALZ/ADP1050DC1-EVALZ (UG-664) user
guide, and schematics and bill of materials for the
ADP1051-240-EVALZ and ADP1050DC1-EVALZ
Multiple test points allow easy access to all critical points/pins.
Three LEDs give the user a direct visual indication of variations
in the board status, such as the system input voltage, PGOOD
output, and FLAGIN input.
Full performance details are provided in the ADP1050 data sheet,
which should be consulted in conjunction with this user guide.
ADDITIONAL EQUIPMENT/SOFTWARE NEEDED
ADP-I2C-USB-Z USB-to-I2C connector
ADP-I2C-USB-Z drivers CD
EVALUATION BOARD SETUP
ADP1051-240-EVALZ
VIN+
VOUT+
VOUT–
VIN–
ADP1050DC1-EVALZ
12085-001
PC
ADP-I2C-USB-Z
Figure 1. ADP1051-240-EVALZ Evaluation Board Setup with ADP1050DC1-EVALZ Daughter Card and ADP-I2C-USB-Z USB-to-I2C Interface
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. 0 | Page 1 of 44
UG-664
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
TABLE OF CONTENTS
Features .............................................................................................. 1
Evaluating the Board ...................................................................... 12
Evaluation Kit Contents ................................................................... 1
On/Off Control and Soft Start .................................................. 12
Additional Equipment/Software Needed ...................................... 1
PWM Settings ............................................................................. 18
General Description ......................................................................... 1
Digital Compensator and Load Transient Response ............. 19
Evaluation Board Setup ................................................................... 1
Input Voltage Settings ................................................................ 21
Revision History ............................................................................... 2
Output Voltage Settings ............................................................. 23
Evaluation Board Hardware ............................................................ 3
Input and Output Current Settings .......................................... 26
Overview........................................................................................ 3
Temperature Settings ................................................................. 27
Evaluation Board Characteristics ............................................... 5
Flags and Fault Response Configurations ............................... 28
Connectors .................................................................................... 5
Trimming..................................................................................... 29
Hardware Connection ................................................................. 6
Synchronization .......................................................................... 30
Evaluation Board GUI Software ..................................................... 8
Power Good Signal ..................................................................... 31
Overview........................................................................................ 8
Additional Graphs .......................................................................... 32
Downloading the GUI ................................................................. 8
Schematics and Artwork ............................................................... 33
Installing the GUI ......................................................................... 8
ADP1051-240-EVALZ ............................................................... 33
Launching the GUI ...................................................................... 8
ADP1050DC1-EVALZ .............................................................. 39
Loading Command and Board Settings .................................... 9
Ordering Information .................................................................... 41
Getting Started ............................................................................ 11
Bill of Materials ........................................................................... 41
REVISION HISTORY
1/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
UG-664
EVALUATION BOARD HARDWARE
OVERVIEW
The ADP1051-240-EVALZ evaluation board can be used as
an evaluation tool for the ADP1050 and the ADP1051. The
ADP1051-240-EVALZ evaluation board and the ADP1050DC1EVALZ daughter card feature the ADP1050 in a dc-to-dc switching
power supply in full bridge topology with synchronous rectification.
Figure 2 shows a photograph of the evaluation board hardware.
Figure 4 shows a block diagram of the main components on the
board. The circuit is designed to provide a rated load of 12 V,
20 A from a dc input voltage source of 36 V dc to 75 V dc. The
ADP1050 provides functions such as output voltage regulation,
synchronization, prebias startup, and comprehensive protection.
The main transformer on the evaluation board breaks the
dc-to-dc power supply into primary side and secondary side,
creating isolation. On the primary side, the full bridge stage
switches and inverts the dc voltage derived from the input
terminals (J1 and J5) into ac voltage. The control signals for the
full bridge stage come from the ADP1050 through the digital
isolators (ADuM3210) and the half bridge drivers. There is
also a current transformer (CT) sensing and transmitting the
primary side current information to the ADP1050 on the
secondary side.
On the secondary side, the full wave synchronous rectifiers (SRs)
rectify the ac voltage to dc voltage. An LC filter smooths the
pulsated dc voltage. The output terminals, J2 and J6, are used
for the load connection.
An auxiliary power supply on the evaluation board is used to
generate a 10 V bias power on the primary side (10V_PRI) for
full bridge drivers, a 5 V bias power on the primary side
(5V_PRI) for the primary side power supply of the ADuM3210,
and a 10 V bias power on the secondary side (10V_SEC) for the
ADP3654 driver (see Figure 4). A 10 V bias power (10V_VCC) is
generated from an OR-diode network using a 10 V bias power on
the secondary side (10V_SEC) and a 5 V voltage source from
the USB-to-I2C connector (see Figure 4). This allows the GUI
access to the ADP1050 when the auxiliary power circuit is not
powered up. The ADP3303 LDO converts the 10V_VCC to a
3.3 V bias power on the secondary side (3V3_SEC) for the
ADP1050 and the secondary side power of the ADuM3210.
Alternatively, the auxiliary power input can also come from an
independent dc source through TP47 and TP50.
There are three blue LEDs on the evaluation board to provide the
status of the evaluation board. D7 indicates the input voltage
signal. D17 indicates the PGOOD output (PG/ALT pin output
signal). D18 indicates the FLAGIN signal.
There are three complete switches on the evaluation board. The
SW1 switch is used to control the voltage level of the hardware
CTRL pin. The SW2 and SW3 switches are used to change the
part operating state to master or slave when synchronization is
enabled.
The ADP1050DC1-EVALZ daughter card shown in Figure 3
can be plugged into the ADP1050/ADP1051 daughter card
connector (J8). It provides the signals that are used to regulate
the output voltage, limit the output current, and control the
on/off switch of the evaluation board. A 4-pin connector (J2) on
the daughter card is used for I2C/PMBus™ communication
through a USB-to-I2C connector, ADP-I2C-USB-Z. This allows
the GUI software to communicate with the evaluation board
through the USB port of the PC. If the J17 or J18 parallel
connector is connected, the GUI can visit all the evaluation
boards through a single USB-to-I2C connector. With this
interface, users can monitor and program the ADP1050.
Rev. 0 | Page 3 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
12085-002
UG-664
12085-003
Figure 2. ADP1051-240-EVALZ Evaluation Board
Figure 3. ADP1050DC1-EVALZ Daughter Card
FULL BRIDGE FETs
MAIN
TRANSFORMER
OUTPUT FILTER
SR FETs
VOUT (12V @ 20A)
VIN = 36V TO 75V
CT
ADP3654
HIP 2101
HIP 2101
ADuM3210
SR1/SR2
CS1
ON/OFF AND
UVP CONTROL
ADuM3210
OUTA/OUTB
ADuM3210
CTRL
OVP
VS+
ADP1050
VS–
AGND
AUX
TRANSFORMER
VDD
NCP1031
10V_PRI
SCL SDA
3V3_SEC
10V_SEC 10V_VCC
ADP3303
I2C
CONNECTOR
12085-004
5V_PRI
RTD ADD RES
Figure 4. Block Diagram of ADP1050 Evaluation Board System
Rev. 0 | Page 4 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
UG-664
EVALUATION BOARD CHARACTERISTICS
Table 1. Evaluation Board Characteristics
Parameter
INPUT VOLTAGE
OUTPUT VOLTAGE SETPOINT
VOUT Overvoltage Fault Limit (Default)
Output Voltage Ripple
OUTPUT CURRENT
IOUT Overcurrent Fault Limit (Default)
OPERATION TEMPERATURE
Symbol
VIN
VOUT
Min
36
Typ
48
12
14
200
IOUT
0
Overtemperature Fault Limit (Default)
EFFICIENCY
SWITCHING FREQUENCY
DIMENSION
Width
Length
Component Height
TOT_FAULT
η
fSW
25
25
25
110
94.5
120
W
L
H
210
110
40
Max
75
20
TA
50
85
Unit
V dc
V dc
V dc
mV
A
Test Conditions/Comments
°C
°C
°C
%
kHz
Natural convection
Airflow = 200 LFM or above
VIN = 48 V, VOUT = 12 V, IOUT = 20 A
VIN = 48 V, VOUT = 12 V, IOUT = 20 A
mm
mm
mm
CONNECTORS
ADP1050/ADP1051 Daughter Card Connector (J8)
The connections to the ADP1051-240-EVALZ evaluation board
are shown in Table 2. Table 3 and Table 4 show the details about
these connectors.
The connections to J8 are shown in Table 3.
Table 2. Evaluation Board Connections
Connector
J1
J5
J2
J6
J8
J15
J17
J18
1
Function
VIN+, dc input
VIN−, ground return for dc input
VOUT+, dc output
VOUT−, ground return for dc output
ADP1050/ADP1051 daughter card connector
Analog current share daughter card connector1
Parallel Connector 11
Parallel Connector 21
For ADP1051 only.
Table 3. J8 Connections
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function
10V_VCC
VS−
VS+
CS2−1
CS2+1
VF
CS1
SR1
SR2
OUTA
OUTB
OUTC2
OUTD3
SCL
SDA
CTRL
PG/ALT
SYNI/FLGI
3V3_SEC
AGND
RTD
OVP
For ADP1051 only. These pins are left unconnected for the ADP1050.
In the ADP1050DC1-EVALZ daughter card, this pin (OUTC) is connected to
the OUTB pin of the ADP1050.
3
In the ADP1050DC1-EVALZ daughter card, this pin (OUTD) is connected to
the OUTA pin of the ADP1050.
1
2
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ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
Daughter Card I2C/PMBus Connector (J2)
The connections to J2 in the ADP1050DC1-EVALZ daughter
card are shown in Table 4.
Table 4. J2 Connections
Pin
1
2
3
4
to ensure safety for the user. It is strongly advised to switch off
the evaluation board when it is not in use. A current-limit dc
source is recommended to use as the input.
Required Equipment
•
•
•
•
Function
5V
SCL
SDA
AGND
•
HARDWARE CONNECTION
•
Caution
•
12085-005
This evaluation board is supplied with high voltages and
currents. Take extreme caution, especially on the primary side,
DC power supply capable of 36 V dc to 75 V dc, 10 A output
Electronic load capable of 12 V, 25 A input
Oscilloscope capable of 500 MHz bandwidth or higher
PC with Microsoft Windows® XP (32-bit), Windows Vista
(32-bit), Windows 7 (32-bit), or Windows 8 (32-bit)
Precision digital multimeters (6-digit HP34401 or
equivalent)
Portable digital multimeters (fluke) for measuring up to
25 A dc current
ADP-I2C-USB-Z USB-to-I2C connector (see Figure 5)
available from Analog Devices, Inc.
Figure 5. ADP-I2C-USB-Z USB-to-I2C Interface Connector
Rev. 0 | Page 6 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
UG-664
Evaluation Board Configurations
Table 5. Jumpers Configuration
There are a series of jumpers used for ADP1051-240-EVALZ
hardware settings. All the jumper configurations have been
completed during the evaluation board assembly. Table 5 shows
the details of jumper configurations.
Jumper
JP1
JP2
JP3
T1 and T4 are current transformers for primary side current
sense. Typically, T4 is used while T1 is not connected by default.
JP4
Users do not need to complete any additional hardware
configuration unless special test items will be conducted.
Connecting the Hardware
Do not connect the ADP-I2C-USB-Z connector to the evaluation board until after the GUI software has been installed.
JP5
Figure 6 shows the test configuration of the evaluation board.
The digital multimeters are optional. An independent dc source
can be applied on TP47 and TP50 to generate all bias power
supplies even if the dc input is lower than 30 V. The board
evaluation can start when the dc input voltage is increased
from 0 V.
JP11
JP12
JP13
JP14
Function
Short this jumper to short R46. This jumper can be
used as a signal injection point during the control
loop test. It is open by default.
Short this jumper to short R53. It is open by default.
When SW1 is used to control the PSU, short this
jumper. It is shorted by default.
When multiple evaluation boards are connected in
parallel, proper configuration of this jumper allows a
single switch to control all evaluation boards. It is
shorted by default.
Short this jumper to configure the CTRL pin so that
the ADP1050 is in the off state. This jumper is open
by default.
This jumper is not used by the ADP1050.
This jumper is not used by the ADP1050.
This jumper is not used by the ADP1050.
This jumper is not used by the ADP1050.
20.00A
5.40A
I
ADP1051-240-EVALZ
COM
J18
COM
J2
J1
+
I
SW3
+
DC
POWER
SUPPLY
ELECTRONIC
LOAD
–
ADP1050DC1-EVALZ
J15
J2
J5
I
V
–
J8
TP47
COM
J6
JP4 SW1
TP50
J17
SW2
COM
I
V
12.00V
48.00V
MULTIMETER
MULTIMETER
ADP-I2C-USB-Z
12085-006
PC
Figure 6. Test Configuration for the Evaluation Board
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ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
EVALUATION BOARD GUI SOFTWARE
OVERVIEW
LAUNCHING THE GUI
The ADP1050-51 GUI is a free software tool for programming
and configuring the ADP1050 and ADP1051.
To launch the GUI, use the following steps:
1.
2.
The ADP1050-51 GUI setup file is included on the CD in the
ADP1050 evaluation kit.
Users can also visit http://www.analog.com/ADP1050 to obtain
the latest version of the GUI software.
3.
4.
INSTALLING THE GUI
Warning
Do not connect the USB cable to the evaluation board until the
software has been installed.
5.
Installation Steps
6.
To install the ADP1050-51 GUI software, use the following steps:
3.
4.
5.
6.
7.
8.
9.
Insert the CD.
Double-click the ADP1050-51 Setup.msi installation file
to start the installation.
Follow the prompts in subsequent windows (see Figure 7)
to install the software.
In the Total Phase USB Setup window, click Next.
Check I accept the terms in the License Agreement after
reading it. Then click Next.
Check the Install USB drivers option when the driver is
not installed. If the driver has been installed, clear the
Install USB drivers option. Then click Install.
After the installation, click Close to complete the driver
installation.
When the Adobe Flash Player Installer window appears,
check I have read and agree to the terms of the Flash
Player License Agreement after reading it. Then click
INSTALL. If a newer version of Adobe Flash Player is
already installed in the system, click Quit.
Click Close to exit the setup.
7.
8.
12085-007
1.
2.
Figure 7. GUI Installation
Rev. 0 | Page 8 of 44
Plug the ADP1050DC1-EVALZ daughter card into the
J8 connector.
Ensure that the CTRL switch (SW1) is turned to the off
position. The off position is the left side by default.
Plug the ADP-I2C-USB-Z connector into the USB port
in the PC.
If the Found New Hardware - Total Phase Aardvark
I2C/SPI Host Adapter message appears, the PC automatically installs the hardware driver. Wait until the installation
is finished. If this window does not appear, skip this step.
Connect the ADP-I2C-USB-Z connector to J2 on the
ADP1050DC1-EVALZ daughter card.
Double-click the ADP1050-51.exe file. The GUI software
should report that the ADP1050 has been detected on the
board, as shown in Figure 8.
Click Finish to proceed to the Monitor window (see
Figure 10).
Click Unlock the chip password (Button I in Figure 10)
and enter the chip password in the pop-up window that
appears. The default chip password is 0xFFFF. Press ENTER
after typing in the password to proceed to the Setup tab of
the main window, as shown in Figure 11.
12085-008
DOWNLOADING THE GUI
Figure 8. Getting Started—Device Detected on the Board
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
LOADING COMMAND AND BOARD SETTINGS
Default.50s file when specifying the folder, as shown in Figure 9.
Because the ADP1050 in the evaluation kit is preprogrammed
with the board and command settings, this step is optional.
12085-009
If the user wants to load the default command and board
settings file from a local folder, click Load Command and
Board settings from a .50s file to the ADP1050 device
(Button A in Figure 11) and select the ADP1050-240-EVALZ-
UG-664
Figure 9. Load Board and Command Settings File
Rev. 0 | Page 9 of 44
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ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
Table 6 shows a list of key buttons in the GUI.
Table 6. Key Buttons in the GUI
Button Letter
A
Button
Description
Load command and board settings from a .50s file to the ADP1050 device.
Save command and board settings from the ADP1050 device to a .50s file.
C
Generate a hexadecimal file of the command and board settings.
D
Access the EEPROM.
E
Scan for the ADP1050 device.
F
Open a spy window to monitor PMBus communication between the GUI and the ADP1050 device.
G
Program command and board settings into the EEPROM.
H
Unlock/lock the trim password.
I
Unlock/lock the chip password.
12085-010
B
Figure 10. Monitor Window in the GUI
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ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
GETTING STARTED
1.
2.
3.
4.
Connect a dc source (voltage range of 36 V dc to 75 V dc)
at the J1 and J5 input terminals, and connect an electronic
load at the J2 and J6 output terminals. See Figure 6 for the
correct configuration.
Connect the multimeters on the input terminals and
output terminals separately as shown in Figure 6.
Connect the voltage probes at different test points. Ensure
that differential probes are used and that the grounds of the
probes are isolated if the measurements are performed
simultaneously on the primary and secondary sides of the
transformer.
Turn the CTRL switch (SW1) to the on position.
The evaluation board is now up and running, and ready for
evaluation. The output should read 12 V dc.
After completing the programming of the ADP1050, click
Program command and board settings into the EEPROM
(Button G in Figure 11) to program the command and board
settings into the EEPROM if the user wants to save the settings
in the device. Moreover, the user can use the Save command
and board settings from the ADP1050 device to a .50s file
button (Button B in Figure 11) to generate a .50s file for the
command and board settings.
Software Main Window
Figure 11 shows the main window. There are four tabs in the
main window:
•
•
•
•
Setup tab: All the setting controls, including board and
command settings, can be accessed via this tab.
Monitor tab: The readings and flags are monitored in this tab.
Commands Access tab: This tab provides the command
maps for direct access.
Password Settings tab: The PMBus command WRITE_
PROTECT and chip password can be configured in this tab.
12085-011
After a successful startup, the PSU is in a steady state. The LEDs
of the board provide the status of the board. When D17 is turned
on, there are no faults detected. When a fault is detected, the
PGOOD LED is turned off, indicating that a flag has been
triggered. The Monitor tab of the main window in the GUI
displays the appropriate state of the PSU.
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Figure 11. Main Setup Window of the GUI (See Table 6)
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ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
EVALUATING THE BOARD
This ADP1050 evaluation kit allows the user to gain insight into
the flexibility offered by the extensive ADP1050 programming
options. The following sections provide an overview of the
options that are available to evaluate the key features of the
ADP1050.
ON/OFF CONTROL AND SOFT START
The turn-on delay time, turn-on rise time, and turn-off delay
time can be programmed in the Soft Start and Stop Settings
window (see Figure 13), accessed via the Setup tab. The
Additional Soft Start Settings window is shown in Figure 14.
12085-012
This section specifies the power-on control behavior, the poweroff control behavior, and the soft start timing of the PSU. By
default, the AND logic of the hardware CTRL pin logic and the
software OPERATION command are used to turn on the
ADP1050, as shown in the CTRL Settings window (see Figure 12),
accessed via the Setup tab. It is recommended that Switch SW1
be used to control the operation state of the PSU.
Figure 12. CTRL Settings Window
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12085-013
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
Figure 13. Soft Start and Stop Settings Window
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ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
12085-014
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Figure 14. Additional Soft Start Settings Window
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ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
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12085-015
12085-017
Figure 15 and Figure 16 show the results of a soft start at 0 A load and 20 A load, respectively. The soft start rise time is programmed to 10
ms. Figure 17 shows an example of a soft start with disabled synchronous rectifiers during the soft start ramp.
Figure 17. Soft Start with Disabled Synchronous Rectifiers
12085-016
Figure 15. Soft Start at 48 V DC Input, 0 A Load
Figure 16. Soft Start at 48 V DC Input, 20 A Load
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ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
Prebias Start-Up Function
The prebias start-up function provides the capability to start up
with a prebiased voltage on the output. To set up the prebias
start-up function, use the following steps:
2.
In the Additional Soft Start Settings window (see Figure 14),
enable the prebias start-up function and program the
appropriate nominal modulation value for prebias startup.
Select the type of prebias startup in the Feedforward
Selection window (see Figure 18):
•
If the closed-loop input voltage feedforward operation
is enabled and the input voltage information is available
for the ADP1050 before the PSU starts up, select the
•
A
B
C
12085-018
1.
•
Feed Forward always Activated option (Option A in
Figure 18).
If the closed-loop input voltage feedforward operation
is disabled and the input voltage information is available for the ADP1050 before the PSU starts up, select
the Feed Forward only during Startup option
(Option B in Figure 18).
If the closed-loop input voltage feedforward operation
is disabled and the input voltage information is not
available for the ADP1050 before the PSU starts up,
select the Feed Forward always Disabled option
(Option C in Figure 18).
Figure 18. Feedforward Selection Window
Rev. 0 | Page 16 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
Figure 19 and Figure 20 show the prebias start-up waveforms
when the Feed Forward always Activated option (Option A in
Figure 18) is selected.
UG-664
Because the input voltage cannot be sensed through the
transformer windings of the auxiliary power circuit in this
evaluation board, it is recommended that the Feed Forward
always Disabled option (Option C in Figure 18) be selected for
evaluation.
Other evaluation options include the following:
•
•
12085-019
•
•
12085-020
Figure 19. Prebias Startup at 36 V DC Input and Low Residual Voltage
Figure 20. Prebias Startup at 60 V DC Input and High Residual Voltage
Rev. 0 | Page 17 of 44
Program a different turn-on rise time in combination with
a different turn-on delay time (see Figure 13).
Select different flags to blank during the soft start ramp
(see Figure 14).
Choose different soft start gains to optimize the soft start
ramp (see Figure 14).
Enable the synchronous rectifier soft start and select a
different synchronous rectifier soft start speed (see Figure 14)
to prevent a glitch at the output voltage ramp.
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ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
PWM SETTINGS
The PWM timings for the primary side switches and the secondary
side synchronous rectifiers are programmed in the PWM SR
Settings window (see Figure 21), accessed via the Setup tab.
This window allows the programming of the switching
frequency, the rising edge and falling edge timings, the type of
modulating edge (rising edge or falling edge), the modulation
type (positive or negative), and the modulation limit. Figure 21
shows the gate drive signals at the output pins of the ADP1050.
The QA/QD, QB/QC, Q7/Q8, and Q3/Q4 switches on the
ADP1051-240-EVALZ evaluation board are driven separately
by PWM outputs OUTA, OUTB, SR1, and SR2.
•
•
•
•
•
Enable and disable the pulse skipping mode and measure
the standby power of the PSU.
Double the switching frequency from 120 kHz to 240 kHz.
The board is designed to operate at a switching frequency
of up to 240 kHz with airflow cooling.
Program an imbalance in the on time of the QA and QB
switches, and evaluate the volt-second balance control
function.
Run the software in simulation mode and program the
PWM settings for different topologies, such as hardswitched full bridge, half bridge, push-pull, two-switch
forward, or active clamp forward converters.
Align all synchronous rectifier edges to the OUTA and OUTB
edges and adjust the primary-secondary propagation delay
by programming the SR1 and SR2 delay.
12085-021
Although the switching frequency can be adjusted, the GUI
software does not account for the dead times. The PWM
timings must be programmed manually to guarantee normal
operation of the PWM outputs.
Additional PWM and synchronous rectifier evaluation options
include the following:
Figure 21. PWM SR Settings Window
Rev. 0 | Page 18 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
DIGITAL COMPENSATOR AND LOAD TRANSIENT
RESPONSE
The digital compensator can be configured by the Filter
Settings window (see Figure 22), accessed via the Setup tab.
The digital compensator can be changed by manipulating the
position of the poles and zeros in the s-domain.
error. The second pole can be placed anywhere, but ideally
should be placed at the ESR zero position. The third pole is
fixed at half the switching frequency.
Warning
Although varying the parameters of the compensator is possible
when the part is running, the wrong combination of parameters
may cause the system to become unstable.
12085-022
The digital compensator is a Type III compensator. The first
pole is placed at a dc position to eliminate the steady state
UG-664
Figure 22. Filter Settings Window
Rev. 0 | Page 19 of 44
UG-664
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
Control Loop Configuration
Transient Response for the Load Step
To configure the control loop, use the following steps:
A dynamic electronic load can be connected to the output of
the evaluation board to evaluate the load transient response.
Set up an oscilloscope to capture the transient waveforms of
the PSU output. Figure 24 and Figure 25 show examples of load
transient responses.
5.
40
200
32
160
Figure 24. Transient Response with Load Steps: 25% to 50% to 25%
120
24
MAGNITUDE (B ÷ A) (dB)
12085-024
4.
PHASE
16
80
40
8
MAGNITUDE
0
0
–8
–40
–16
–80
–24
–120
–32
–160
–40
100
1k
10k
FREQUENCY (Hz)
–200
100k
12085-025
3.
The user can vary the digital compensator via the GUI software
to change the transient response. This evaluation kit allows the
digital compensator to be easily programmed to optimize the
load transient response of the PSU.
PHASE (B – A) (Degrees)
2.
Make sure the board parameters are set correctly, including
the topology, the turn ratio of the main transformer, the
output LC filter parameters, and the output voltage sense
network parameters. Using this information, the GUI
software generates the bode plots of the power stage and
the output voltage sense network separately.
The switching frequency is determined in the PWM SR
Settings window. Changing the switching frequency
changes the low frequency gain and the third pole position.
The user can start to place the zeros and poles and can set
the low frequency gain and high frequency gain of the digital
compensator, based on the stability rules.
The GUI then displays the full loop gain crossover
frequency, the phase margin, the gain margin, and the
phase crossover frequency.
Using a loop analyzer, such as an AP300, the user can
verify the programmed control loop (an example is shown
in Figure 23). During the control loop test, the test signal
from the loop analyzer can be easily injected in JP1 of the
evaluation board.
12085-023
1.
Figure 23. Control Loop Test Using an AP300 Loop Analyzer
Rev. 0 | Page 20 of 44
Figure 25. Transient Response with Load Steps: 50% to 75% to 50%
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
INPUT VOLTAGE SETTINGS
input UVLO protection. Using the VIN Settings window (see
Figure 26), accessed via the Setup tab, the user can program the
VIN on and VIN off limits.
12085-026
If the input voltage can be sensed by ADP1050 before the PSU
is turned on (for example, the input voltage is sensed through
the transformer windings of the auxiliary power circuit), the
VIN on and VIN off limits can be programmed to control the
UG-664
Figure 26. VIN Settings Window
Rev. 0 | Page 21 of 44
UG-664
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
By selecting different input voltage feedforward options (labeled
A, B, and C in Figure 18) in the Feedforward Selection window,
the input voltage feedforward can be evaluated in different ways.
Figure 27 shows an input voltage transient response when the
feedforward is disabled (Option C—Feed Forward always
Disabled in Figure 18). Figure 28 shows an input voltage transient
response when the feedforward is enabled (Option A—Feed
Forward always Activated in Figure 18).
•
Apply a different input voltage compensation multiplier
(Register 0xFE59) to attain an accurate input voltage sense
at both no load and heavy load conditions.
Select the input voltage signal to trigger the VIN_LOW flag
or the VIN_UV_FAULT flag in the Feedforward Selection
window (see Figure 18).
Figure 27. Input Voltage Transient Response with Feedforward Disabled
12085-028
•
12085-027
Additional input voltage related evaluation options include the
following:
Figure 28. Input Voltage Transient Response with Feedforward Enabled
Rev. 0 | Page 22 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
OUTPUT VOLTAGE SETTINGS
can be accessed by clicking VOUT in the Settings tab of the
main window, and the window shown in Figure 30 can be
accessed by clicking Additional Settings in VOUT Settings
Window 1.
12085-029
The VOUT Settings windows (shown in Figure 29 and Figure 30)
set all the output voltage related parameters, such as the output
voltage settings, the output voltage transition rate (through the
VOUT_TRANSITION_RATE command), and the conditional
overvoltage protection setting. The window shown in Figure 29
UG-664
Figure 29. VOUT Settings Window 1
Rev. 0 | Page 23 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
12085-030
UG-664
Figure 30. VOUT Settings Window 2
Rev. 0 | Page 24 of 44
ADP1051-240EVALZ/ADP1050DC1-EVALZ
User Guide
UG-664
The ADP1050 also supports conditional output overvoltage
protection. The settings of conditional output overvoltage
protection can be accessed via VOUT Settings Window 2 (see
Figure 30). Figure 34 shows a result of conditional overvoltage
protection when the outputs of two evaluation boards are
connected to a common bus.
12085-031
Figure 31 and Figure 32 show the results of adjusting the output voltage when the VOUT transition rate is programmed as 3.125 µV/µs.
12085-033
Figure 31. VOUT Adjusted from 10 V to 12.5 V with 3.125 µV/µs Transition Rate
12085-034
12085-032
Figure 33. Overvoltage Protection Waveforms
Figure 32. VOUT Adjusted from 12.5 V to 10 V with 3.125 µV/µs Transition Rate
Figure 34. Conditional Overvoltage Protection with Two Evaluation Boards
Connected to a Common Bus
Output Overvoltage Protection
This test can be conducted in several ways. The simplest way is to
set the output voltage to a value higher than the VOUT overvoltage
fault limit (see VOUT_OV_FAULT_LIMIT in Figure 29).
Alternatively, the user can short the VS+ pin to AGND in the
ADP1050DC1-EVALZ daughter card to cause a fast output
overvoltage condition. The responses of the fault conditions can
be programmed in the Fault Response window (see the Flags
and Fault Response Configurations section and Figure 37).
Figure 33 shows an example of waveforms in response to an
output overvoltage condition.
Output Undervoltage Protection
This test can be done in several ways. The simplest way is to set
the output voltage to a value lower than the VOUT undervoltage
fault limit value (see VOUT_UV_FAULT_LIMIT in Figure 29).
Even a shorted load or an internal short (such as shorting of the
synchronous rectifiers) can cause an output undervoltage condition. The response of the fault condition can be programmed in
the Fault Response window (see the Flags and Fault Response
Configurations section and Figure 37).
Rev. 0 | Page 25 of 44
UG-664
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
INPUT AND OUTPUT CURRENT SETTINGS
The input and output current settings are accessed using the
CS1 and CS3 Settings window (see Figure 35), accessed via the
Setup tab. This window is used to program the CS1 cycle-by-cycle
current limiting, the input overcurrent fast fault protection, the
CS3 output overcurrent protection, and the volt-second balance
control.
CS1 Cycle-by-Cycle Current Limiting
This test can be conducted by shorting the load. Using the CS1
and CS3 Settings window (see Figure 35), the user can specify
the IIN overcurrent fast fault limit value to 2, 8, 16, 64, 128, 256,
512, or 1024. The fault response can be configured in the Fault
Response window (see the Flags and Fault Response Configurations
section and Figure 37).
Output Overcurrent Fast Fault Protection
(CS3 Overcurrent Protection)
This test can be conducted by applying an overload. Using the
CS1 and CS3 Settings window (see Figure 35), the user can
specify the CS3 overcurrent fast fault limit value. The fault
response can be configured by clicking CS3_OC_FAULT in the
Fault Response window (see the Flags and Fault Response
Configurations section and Figure 37).
12085-035
The leading edge blanking time, the leading edge blanking
reference, the debounce time, the PWM disabling selection,
and the matched cycle-by-cycle current limiting can be programmed in the CS1 and CS3 Settings window (see Figure 35).
Input Overcurrent Fast Fault Protection
(CS1 Overcurrent Protection)
Figure 35. CS1 and CS3 Settings Window
Rev. 0 | Page 26 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
TEMPERATURE SETTINGS
through the Temperature Settings window (see Figure 36). The
overtemperature hysteresis is the difference between the values
of the overtemperature fault limit and the overtemperature
warning limit.
12085-036
This test can be conducted by enclosing the evaluation board
in a thermal chamber at the desired ambient temperature to
simulate the operating condition. The user can program the
overtemperature fault limit and overtemperature warning limit
UG-664
Figure 36. Temperature Settings Window
Rev. 0 | Page 27 of 44
UG-664
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
FLAGS AND FAULT RESPONSE CONFIGURATIONS
The fault responses can be programmed in the Fault Response
window (see Figure 37), accessed via Setup tab. The state of
each fault can be monitored in the Monitor tab, as shown in
Figure 10. There are two groups of fault responses:
•
PMBus fault responses, including the VOUT overvoltage fault
response (VOUT_OV_FAULT_RESPONSE), the VOUT undervoltage fault response (VOUT_UV_FAULT_RESPONSE), and
the overtemperature fault response (OT_FAULT_RESPONSE).
Manufacturer specific fault responses, including the IIN
overcurrent fast fault response (IIN_OC_FAST_FAULT_
RESPONSE), the CS3 overcurrent fault response (CS3_OC_
FAULT_RESPONSE), the VIN undervoltage fault response
(VIN_UV_FAULT_RESPONSE), the flag input fault response
The user can test these responses by applying a fault condition.
By changing the settings of the debounce timing, delay timings,
and responses and reenable timings, the user can alter the
protection performance.
If there is a fault causing the power supply to be shut down and
a soft start is required because the PWM outputs are reenabled,
the first fault ID information is displayed in the Monitor tab.
The first flag ID register provides the user with more information
than a simple flag would and, therefore, helps facilitate fault
diagnoses.
12085-037
•
(FLAGIN_RESPONSE), and the VDD overvoltage fault
response (VDD_OV_RESPONSE). There is a global
reenabling timing for all manufacturer specific fault
responses.
Figure 37. Fault Response Window
Rev. 0 | Page 28 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
TRIMMING
This test allows the entire power supply to be calibrated and
trimmed digitally through the ADP1050 in the production
environment.
high enough accuracy (see the ADP1050 data sheet for details).
However, the ADP1050 can be retrimmed by the user to compensate for errors introduced by external components. All
trimming can be initiated from the Trim Settings window (see
Figure 38), accessed via the Setup tab.
12085-038
All the ADP1050 parts are factory calibrated. The trimming
is not needed if the voltage and current sense resistors have a
UG-664
Figure 38. Trimming Settings Window
Rev. 0 | Page 29 of 44
UG-664
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
SYNCHRONIZATION
To view the synchronization performance,
Synchronization as a Slave Device
•
•
•
•
Enable and disable synchronization.
Set different delays to see the phase shift between master
device and slave device.
Program a different phase capture range.
If the external clock signal is generated by a signal generator,
program the clock signal in sweep mode or burst mode to
see the synchronization locking or unlocking.
12085-039
This test can be done by applying an external clock signal to the
TP25 test point. Alternatively, an external clock signal (such as
an SYNO signal from the master device) can be applied to the
SYNC pin of the J17 or J18 connector. The synchronization
settings can be programmed in the Sync Settings window (see
Figure 39).
Figure 39. Sync Settings Window
Rev. 0 | Page 30 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
UG-664
POWER GOOD SIGNAL
12085-041
This test can be conducted by setting a fault condition, which is
used to trigger a PGOOD flag and to pull down the PG/ALT pin.
In the PGOOD Settings window (see Figure 41), program which
fault signal asserts the PGOOD flag. When a fault triggers the
PGOOD flag, the D17 LED turns off, indicating that the power
supply is not good. Figure 40 shows an example of a VOUT_UV_
FAULT flag triggering the PGOOD output (PG/ALT pin).
12085-040
Figure 40. A VOUT_UV_FAULT Flag to Trigger PGOOD Output
Figure 41. PGOOD Settings Window
Rev. 0 | Page 31 of 44
UG-664
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
ADDITIONAL GRAPHS
100
EFFICIENCY (%)
95
90
VIN = 36V DC
VIN = 48V DC
VIN = 60V DC
VIN = 75V DC
85
0
5
10
LOAD CURRENT (A)
15
20
Figure 45. Thermal Image at 60 V DC Input, 20 A Load, No Airflow
12085-046
12085-043
Figure 42. Efficiency Curve at 36 V DC, 48 V DC, 60 V DC, and 75 V DC Input
12085-045
75
12085-042
80
Figure 43. Thermal Image at 36 V DC Input, 20 A load, No Airflow
12085-044
Figure 46. Thermal Image at 75 V DC Input, 20 A Load, No Airflow
Figure 44. Thermal Image at 48 V DC Input, 20 A Load, No Airflow
Rev. 0 | Page 32 of 44
R14
30.1kΩ
1
SW2
DRIVE C
SW1
DRIVE A
BANANA
JACK
J5
VIN–
20mA/4.9V
D7
VIN+
BANANA
JACK
2
TP45
TP6
TP9
TP15
TP14
TP11
VIN–
+
220µF/100V
2
1
C2
220µF/100V
2
1
C1
+
C27
C22
C28
1µF/25V
R32
0Ω
C23
1µF/25V
R26
0Ω
1
2
3
4
0.1µF/25V
10V_PRI
1
2
3
4
3
DRIVE B
VDD
HB
HO
HS
VDD
HB
HO
HS
8
7
6
5
R6
2Ω
R30 0Ω
R27 0Ω
R36
NC
TP8
DRIVE B
R21
10kΩ
R19
2Ω
1
Q5
90A/100V/ 6.8mΩ
SW1
R7
10kΩ
1
Q1
90A/100V/ 6.8mΩ
T4
PA1005.100NL
2
NC
R37
R34 0Ω
R33 0Ω
L3
560nH/20A/3.4mΩ
D3
8
7
6
5
8
7
6
5
U2
DRIVE D
2Ω
R20
D10
1A/30V
U5
VDD1
VIA
VIB
GND1
VDD1
VIA
VIB
GND1
ISOLATION BARRIER
VDD2
VOA
VOB
GND2
ADUM3210BRZ
VDD2
VOA
VOB
GND2
1
2
3
4
1
2
3
4
R22
10kΩ
C85
C13
1
2
J12 JUMPER
NC
NC
2
R91 0Ω
R35 0Ω
R92 0Ω
TP39
GROUND TEST POINT
0
R93 0Ω
C30
0.1µF/25V
3V3_SEC
TP44
GROUND TEST POINT
0
C25
0.1µF/25V
3V3_SEC
FULL BRIDGE STAGE
1
2
R8
10kΩ
Q6
90A/100V/ 6.8mΩ
SW2
DRIVE C
R11
2Ω
1
Q2
90A/100V/ 6.8mΩ
D4
1A/30V
ADUM3210BRZ
D8
2A/100V
2A/100V
C29
0.1µF/25V
5V_PRI
C24
0.1µF/25V
5V_PRI
FULL BRIDGE MOSFET DRIVER CIRCUIT
LO
VSS
LI
HI
U4
HIP2101EIBZT
DRIVE D
1
DRIVE A
TP13
LO
VSS
LI
HI
8
7
6
5
D9
1A/30V
D2
1A/30V
U1
HIP2101EIBZT
TP45
GROUND TEST POINT
0.1µF/25V
10V_PRI
C18
C6
C17
C5
C4
C3
L1
1µH/32A/2mΩ
2.2µF/100V
1
2.2µF/100V
2.2µF/100V
2
1
2
J1
2.2µF/100V
2
1
1
2.2µF/100V
CS1+
PAD
NC
C64
NC
C67
8
6
5
1
2
NC
C65
NC
C68
3
2
3
NC
C66
NC
C69
1
2
1
2
CS+
3
4
7
CS–
1
8
6
5
3
2
3
2.2µF/100V
9
OUTD
OUTC
OUTB
OUTA
T1
NC
TP4
TR5
2
3
1
D33
1
D34
R25
2Ω
TP12
2
D5
3
R5
R2
2
2
3
SSR1
D11
1A/30V
TP30
10V_SEC
R9
2Ω
3
NC.
OUTA
VDD
OUTB
ADP3654
8
7
6
5
SW4
C70
R88 10kΩ
2
R100 10kΩ
R90 10kΩ
1
2
3
4
10nF
250V
R31
NC
3.6µH/24A/3.04mΩ
L2
R89 10kΩ
C71
NC
INA
PGND
INB
U3
10nF
250V
R103 10kΩ
1
TP42
R94 0Ω
R95 0Ω
SR2
SR1
TP7
R101 10kΩ
4.7µF/50V
C12
J3
2
R23
1
J4
0.002Ω
2
JUMPER
Short
JUMPER
Short
1
0.002Ω
R108 10kΩ
4.7µF/50V
R3
4.7µF/50V
C8
SR MOSFET DRIVER CIRCUIT
C26
1µF/25V
1A/30V
D6
R24 10kΩ
R96 10kΩ
2
JUMPER
Q7
90A/100V/ 6.8mΩ
2A/100V
2
2A/100V
1
J13
10kΩ
10kΩ
1A/30V
Q4
90A/100V/ 6.8mΩ
2
R4
2Ω
R109 10kΩ
4.7µF/50V
C9
D1
1A/30V
2
1
Q3
90A/100V/ 6.8mΩ
1
Q8
90A/100V/ 6.8mΩ
TP10
SSR2
SSR1
TP5
7
6
5
TP3
ERI 25 5-2-2
3
4
1
2
T2
SW3
TR3
R1
2Ω
1
2
CS2+_H
C14
SSR2
1
CS1–
1
1
2
1
1
2
R104 10kΩ
PAD
1
+
Vo-
Vo+
SW4
PGND
10V_SEC
5V_PRI
10V_PRI
AGND
Vin-
Vin+
1
J2
BANANA
JACK
Vo–
Vo+
SW4
PGND
10V_SEC
5V_PRI
10V_PRI
AGND
Vin–
Vin+
3V3_SEC
1
VO–
+
J6
BANANA
JACK
VO+
TP41
3V3_SEC
2
R97
10kΩ
9
470µF/35V
C10
4
7
PAD
2
1
Rev. 0 | Page 33 of 44
9
Figure 47. ADP1051-240-EVALZ Evaluation Board Schematic—Part I
2
1
R110 10kΩ
4.7µF/50V
C15
CS2–_L
1
2
CS2–_H
4.7µF/50V
C16
CS2+_L
470µF/35V
C11
TP1
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
UG-664
SCHEMATICS AND ARTWORK
ADP1051-240-EVALZ
12085-047
220Ω
2A/100V
0
C31
100nF/50V
1
2
3
4
5
6
7
8
9
10
11
OVP
RTD
AGND
3.3V
SYNI/FLGI
PG/ALT#
CTRL
SDA
SCL
OUTD3
OUTC2
ADP1051 SOCKET
10V_VCC
VS–
VS+
CS2–*
CS2+*
VF
CS1
SR1
SR2
OUTA
OUTB
J8
22
21
20
19
18
17
16
15
14
13
12
FEED FORWARD FILTER
0
C35
100pF/50V
0Ω
R54
OVP
RTD
AGND
3V3_SEC
FLAGIN
PGOOD
CTRL
SDA
SCL
OUTD3
OUTC2
TP19
R58
NC
C42
CS2 CURRENT SENSE
R57
0Ω
CS2–
R59
0Ω
CS2+
ADP1050/ADP1051
DAUGHTER CARD CONNECTOR
R60
NC
FOR ADP1051 ONLY. THESE PINS ARE LEFT UNCONNECTED FOR THE ADP1050.
2
IN THE ADP1050DC1-EVALZ DAUGHTER CARD, THIS PIN (OUTC) IS CONNECTED
TO THE OUTB PIN OF THE ADP1050.
3
IN THE ADP1050DC1-EVALZ DAUGHTER CARD, THIS PIN (OUTD) IS CONNECTED
TO THE OUTA PIN OF THE ADP1050.
1
10V_VCC
VS–
VS+
CS2–1
CS2+1
VF
CS1
SR1
SR2
OUTA
OUTB
SW4
CS2-_H
VF
2
PGOOD
0
0
t
RT1
100kΩ
RTD
CON8 SINGLE ROW
1
2
3
4
5
6
7
8
J15
CS1–
CS1+
CS–
NC
R98
10kΩ
0
0Ω
R123
3
Q9
2
BSS138
CS1 CURRENT SENSE
NC
R39
10Ω
IBUS
SYNC1
0
R40
10Ω
FLAGIN
R10
1kΩ
D16
D30
D29
D28
R74
1Ω
NC
NC
200mA/30V
CS1
OUTD
OUTC
OUTB
OUTA
100pF/50V
C34
200mA/30V
0
0
D39
200mA/30V
SYNC2
200mA/30V
D40
3V3_SEC
AGND
D44
1
2
8
7
4
6
J18
2
2
5
3
1
SW
SW3
SW
SW2
D43
200mA/30V
CTRL_1
SYNC2
SYNC1
0
2
SDA
SCL
TP18
TP17
R43
10Ω
R53
2
R52
NC
TP20
AGND
PGND
SYNO
FLAGIN
PGOOD
AGND
TP34
IBUS
SR1
10V_SEC
OUTD
OUTC
OUTB
OUTA
SR2
R49
NC
R47
0Ω
NC
C40
C38
NC
TEST POINT
AGND
PGND
TP35
TP25
TP21
TP39
TP49
TP48
Vo-
Vo+
TP33
TP29
TP28
TP27
TP26
TP24
TP23
OUTPUT VOLTAGE SENSE
OVP
SDA_FILTER
SCL_FILTER
10Ω
1
3V3_SEC
VF_ISHARE
VF_ISHARE
JP2 JUMPER
R48
0Ω
R105
0Ω
I2C/PMBUS FILTER
0
33pF/50V
C36
0
33pF/50V
R41
10Ω
NC
C41
NC
C39
NC
2
R46 10Ω
10V_VCC
JP1 JUMPER
1
200mA/70V
D14
R107
C32
TP22
VS-
VS+
10V_SEC
3V3_SEC
R45
4.7kΩ
R102
4.7kΩ
JP9
SHORTPIN
1
D52
200mA/30V
SDA_FILTER
200mA/30V
D51
AGND
10V_VCC
CTRL_1
SDA_FILTER
R99
1Ω
D45
200mA/30V
SCL_FILTER
200mA/30V
D46
CON8 SHROUDED
3
200mA/30V
IBUS
SYNC2
SCL_FILTER
1
3
PARALLELING CONNECTOR
100Ω
D31
200mA/30V
R38
1
2
JP14 JUMPER
JP13 JUMPER
1 SYNO
2
10V_VCC
CTRL_1
D36
200mA/30V
SYNC1
1
2
JP12 JUMPER
JP11 JUMPER
1 SYNO
2
SDA_FILTER
FLAGIN
OUTC
OUTD
FLAGIN
OUTC
OUTD
200mA/30V
D38
CON8 SHROUDED
8
7
4
2
6
J17
5
3
1
20mA/4.9V
D18
1kΩ
R56
TP16
SCL_FILTER
D37 200mA/70V
D15 NC
R140
D13
CURRENT SHARE CONNECTOR
CS+
10nF/50V
C72
FLAGIN/SYNC/RTD CIRCUIT
R50
16.5kΩ
20mA/4.9V
D17
1kΩ
R51
CS2+
CS210V_SEC
3V3_SEC
IBUS
VF_ISHARE
AGND
AGND
1
D12
CS2+_L
2
1
R106
CS2+_H
Rev. 0 | Page 34 of 44
CS2-_L
Figure 48. ADP1051-240-EVALZ Evaluation Board Schematic—Part II
1
UG-664
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
12085-048
TP37
JP5
VIN+_AUX
VIN+
TP50
TP47
C48
10nF/50V
JUMPER
R76
220Ω
TEST POINT
1
VEN
2
D32
2
2A/100V
1
D35
2
C62
220pF/100V
2A/100V
1
D21
200mA/70V
R68
8K2Ω
10kΩ
R64
1kΩ
C45
1µF/25V
D19
ZR431
0.1µF/100V
R81
1MΩ
C52
2.2µF/100V
Figure 49. ADP1051-240-EVALZ Evaluation Board Schematic—Part III
R87
36kΩ
R86
54.9kΩ
C56
1µF/25V
R72
5.1kΩ
Q10
800mA/60V
R65
5.1kΩ
10V_PRI
D25
500mA/100V
C49
2.2µF/100V
C50
1
2
R67
8
7
6
5
C59
1nF/50V
NCP1031DR2G
1
2
3
4
R78
20kΩ
C46
10nF/50V
VD GND
VCC CT
UV VFB
OV COM
U14
VEN
R69
1kΩ
C57
0.1µF/25V
R85
10kΩ
TP38
2A/100V
D24
8
7
6
5
3V3_SEC
TP40
680Ω
R82
2
1
0
C63
1000pF/2000V
PGND
7
5
C61
1µF/25V
5V_PRI
R83
680Ω
ISOLATION BARRIER
3
2
4
8
3
1
2
D22
1
2A/100V
2
10V_SEC
SW
SW1
JP3
JUMPER
T3
FLYBACK TRANSFORMER
1
2
D20
1A/30V
1
R77
10kΩ
0
C43
0.1µF/25V
0
R70
0Ω
D26
MMBZ5231BLT1G
VDD2
VOA
VOB
GND2
D23
200mA/200V
C51
470pF/250V
10V_PRI
R79
20kΩ
C55
390pF/50V
VDD1
VIA
VIB
GND1
U7
ADUM3210BRZ
ON/OFF AND UVP CIRCUIT
1
2
3
4
AUXILIARY POWER SUPPLY
C44
0.1µF/25V
R80 14kΩ
R84 5.1kΩ
R63
220kΩ
C60 10µF/16V
R66
100kΩ
10µF/16V
C58
1
2
6
VIN+
3
2
1
0
FLAGIN
JUMPER
JP4
10µF/16V
5V_PRI
1
Rev. 0 | Page 35 of 44
2
10µF/16V
C54
C53
5V_PRI
R111
NC
R71
C47
10nF/50V
220Ω
NC
D41
0
TP36
5.1kΩ
R75
CTRL
0Ω
R73
CTRL_1
MH1
R30-1011602
PGND
AGND
PGND
AGND
3V3_SEC
5V_PRI
10V_SEC
10V_PRI
VIN–
VIN+
MH3
R30-1011602
HEADERS
3V3_SEC
5V_PRI
10V_SEC
10V_PRI
VIN–
VIN+
MH2
R30-1011602
MH5
R30-1011602
MH4
R30-1011602
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
UG-664
12085-049
12085-050
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
Figure 50. PCB Layout, Silkscreen Layer
12085-051
UG-664
Figure 51. PCB Layout, Top Layer
Rev. 0 | Page 36 of 44
UG-664
12085-052
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
12085-053
Figure 52. PCB Layout, Layer 2
Figure 53. PCB Layout, Layer 3
Rev. 0 | Page 37 of 44
12085-054
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
Figure 54. PCB Layout, Layer 4
12085-055
UG-664
Figure 55. PCB Layout, Layer 5
Rev. 0 | Page 38 of 44
UG-664
12085-056
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
Figure 56. PCB Layout, Bottom Layout
ADP1050DC1-EVALZ
D1
BAV70WT1
10V_VDD
10V_VCC
C4
NC
10V_VDD
3.3V
R4
11K
U1
R3
NC
VSVS+
SDA
CTRL
PG/ALT#
FLAGIN
3.3V
AGND
RTD
OVP
CS1
8
SR1
5
C8
1uF
9
SR2
10
OUTA
C12
R9
1K
6
11
OUTB
12
OUTC
R17
7
0
8
13
OUTD
14
SCL
R18
9
0
10
15
SDA
16
PSON
17
PGOOD
18
FLAGIN
3.3V
19
20
OVP
1
2
VS-
VS+
U2
SR2
ADD
ADP1050
OUTA
RES
AGND
OUTB
SYNI/FLGI
R14
2.2K
VDD
20
19
R10
10K
18
R11
10K
17
16
J2
69167-104HLF
0
0.1% resistor
3.3V
C13
1uF
D2
BAV70WT1
0
10V_VDD
R12
2
C14
330nF
21
22
2
3
4
1
SCL
SDA
0
RTD
SR1
3.3V
R13
2.2K
4
0
3
100pF
VCORE
SCL
7
15
OUTD
#SD
GND
ADP3303-3.3
C10
1nF
PG/ALT#
OUTC
0
C11
100pF
CTRL
OUTB
5
6
14
OUTA
4
7
6
0
13
SR2
#ERR
NR
R8
11K
5
SR1
IN1
0
1K
VF
CS1
R7
CS1
VF
3
4
SDA
CS2+
C6
100nF
C7
1uF
IN2
OUT2
R6 19.1K
SCL
CS2-
R16
10
OUT1
8
VF
12
VS+
2
C9
100nF
R5
1K
1
11
VS-
2
C1
100nF3
C5 1nF
J1
10V_VCC
1
0
0
3.3V
R15
2.2K
12085-057
68683-411LF
RTD
OVP
Figure 57. ADP1050DC1-EVALZ Daughter Card Schematic
Rev. 0 | Page 39 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
12085-061
12085-058
UG-664
Figure 61. PCB Layout, Layer 3
12085-059
12085-062
Figure 58. PCB Layout, Silkscreen Layer
Figure 62. PCB Layout, Bottom Layer
12085-060
Figure 59. PCB Layout, Top Layer
Figure 60. PCB Layout, Layer 2
Rev. 0 | Page 40 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
UG-664
ORDERING INFORMATION
BILL OF MATERIALS
Table 7. ADP1051-240-EVALZ Evaluation Board
Qty
2
8
1
4
4
1
Reference Designator
C1, C2
C3, C4, C5, C6, C17,
C18, C49, C50
C8, C9, C12, C14,
C15, C16
C10, C11
C13, C85
C22, C26, C27,
C45, C56, C61
C23, C24, C25, C28, C29,
C30, C43, C44, C57
C31
C32, C36
C34, C35
C38, C39, C40, C41
C42
C46, C47, C48, C72
C51
C52
C53, C54, C58, C60
C55
C59
C62
C63
C64, C65, C66,
C67, C68, C69
C70, C71
D1, D2, D4, D5, D6,
D9, D10, D11, D20
D3, D8, D12, D22, D24,
D32, D33, D34, D35
D7, D17, D18
D13, D15
D14, D21, D37
D16, D28, D31, D36,
D38, D39, D40, D43,
D44, D45, D46, D51, D52
D19
D23
D25
D26
D29, D30, D41
JP1, JP2, JP3, JP4, JP5,
JP11, JP12, JP13, JP14
JP9
J1, J2, J5, J6
J3, J4, J12, J13
J8
1
2
1
1
J15
J17, J18
L1
L2
1
L3
6
2
2
6
9
1
2
2
4
1
4
1
1
4
1
1
1
1
6
2
9
9
3
2
3
13
1
1
1
1
3
9
Manufacturer
EEEFK2A221AM
C3225X7R2A225K
Part Number 1
Digi-Key
PCE4866TR-ND
445-4497-2-ND
Footprint
SMC-AEC-TG-K16
C1210
Description
Capacitor aluminum 220 µF 100 V 20% SMD
Capacitor 2.2 µF/100 V X7R 1210
GRM32ER71H475KA88
490-1864-2-ND
C1210
Capacitor ceramic 4.7 µF 50 V 10% X7R 1210
EEEFK1V471AQ
C3225X7R2A225K
C2012X7R1E105K
PCE4862TR-ND
445-4497-2-ND
445-1354-2-ND
AL_CAP_H13
C1210
C0805
Capacitor aluminum 470 µF 35 V 20% SMD
Capacitor ceramic 2.2 µF 100 V 10% X7R 1210
Capacitor ceramic 1 µF 25 V 10% X7R 0805
C1608X7R1E104K
445-1316-2-ND
C0603
Capacitor ceramic 0.1 µF 25 V 10% X7R 0603
C1608X7R1H104K
C1608COG1H330J
C1608COG1H101J
C1608COG1H102J
C1608X7R1H104K
C1608X7R1H103J
C1608C0G2E471J
C2012X7R2A104K
C3216X7R1C106K
C1608C0G1H391J
C1608COG1H102J
C1608COG2A221J
202S43W102KV4E
C3225X7R1H335K
445-1314-2-ND
445-1257-2-ND
445-1281-2-ND
445-1293-2-ND
445-1314-2-ND
445-5089-2-ND
445-2318-2-ND
445-1418-2-ND
445-4042-2-ND
445-1288-2-ND
445-1293-2-ND
445-2308-2-ND
709-1053-2-ND
445-3936-2-ND
C0603
C0603
C0603
C0603
C0603
C0603
C0603
C0805
C1206
C0603
C0603
C0603
C1812
C1210
Capacitor ceramic 0.1 µF 50 V 10% X7R 0603
Capacitor ceramic 33 pF 50 V 5% NP0 0603
Capacitor ceramic 100 pF 50 V 5% NP0 0603
Capacitor ceramic 1000 pF 50 V 5% NP0 0603
Capacitor ceramic 0.1 µF 50 V 10% X7R 0603
Capacitor ceramic 10 nF 50 V 5% X7R 0603
Capacitor ceramic 470 pF 250 V 5% NP0 0603
Capacitor ceramic 0.1 µF 100 V 10% X7R 0805
Capacitor ceramic 10 µF 16 V 10% X7R 1206
Capacitor ceramic 390 pF 50 V 5% NP0 0603
Capacitor ceramic 1 nF 50 V 5% NP0 0603
Capacitor ceramic 220 pF 100 V 5% NP0 0603
Capacitor ceramic 1 nF 2 kV 10% X7R 1812
Capacitor ceramic 3.3 µF 50 V 10% X7R 1210
C2012X7R2E103K
MBR130LSFT1G
445-2280-2-ND
MBR130LSFT1GOSTR-ND
C0805
SOD123
Capacitor ceramic 10 nF 250 V X7R 0805
Schottky diode 1 A 30 V SOD-123FL
MURA110T3G
MURA110T3GOSTR-ND
SMA
Diode ultrafast 2 A 100 V SMA
CMD15-21UBC/TR8
BAV99
BAV70WT1G
BAT42WS-7
L62206CT-ND
BAV99FSTR-ND
BAV70WT1GOSTR-ND
BAT42WSDITR-ND
D1206
SOT23
SOT323
SOD323
LED blue clear 1206 SMD
Diode ultrafast HI COND 70 V SOT-23
Diode switch dual CC 70 V SOT323
Schottky diode 30 V 200 MW SOD-323
ZR431F01TA
MMBD1504A
EGL34B-E3/83
MMBZ5231BLT1G
BAT42WS-7
STC02SYAN
ZR431F01TR-ND
MMBD1504ATR-ND
EGL34B-E3/83-ND
MMBZ5231BLT1GOSTR-ND
BAT42WSDITR-ND
S9000-ND
SOT23-IC
SOT23
DO-213AA
SOT23
SOD323
HEADER-SR-2
IC VREF shunt PREC ADJ SOT-23
Diode SS 200 V 200 MA SOT23
Diode 0.5 A 100 V 50 NS MELF
Diode Zener 5.1 V 225 MW SOT-23
Schottky diode 30 V 200 MW SOD-323
Connector jumper shorting tin
N/A
108-0740-001
N/A
TSW-111-14-T-D
N/A
J147-ND
N/A
SAM1058-11-ND
Short pin
B-JACK
PADJUMPER
HEADER-DR-22
PPC081LFBN-RC
75869-132LF
IHLP5050FDER1R0M01
#7443630420
LER-20-63
IHLP2525EZERR56M01
S4108-ND
609-3530-ND
541-1032-2-ND
N/A
N/A
IHLP2525EZERR56M01-ND
HEADER-I-SR-8
313-208-s2
IND-IHLP-5050FD
LER-20-63
Single connect point of AGND and PGND
Connector jack banana
Power connector jumper on PCB
Connector header 22 POS 0.100 dual tin 22
male pin 2.54
Single row 8 female pin 2.54 mm
Connector header 8 POS dual vertical PCB
Power inductor 1.0 µH 32 A SMD
Power inductor 4.2 µH 24 A 3.04 mΩ SMD
Power Inductor 3.6 µH 30 A 2.3 mΩ SMD
Power Inductor 0.56 µH 20 A SMD
Rev. 0 | Page 41 of 44
2525ez
UG-664
Qty
5
8
1
1
1
12
2
8
1
1
2
19
9
1
2
4
2
1
4
1
1
3
1
1
3
2
2
1
1
2
1
1
1
10
1
3
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
Reference Designator
MH1, MH2, MH3,
MH4, MH5
QA, QB, QC, QD,
Q3, Q4, Q7, Q8
Q9
Q10
RT1
Manufacturer
R30-1011602
R2, R5, R7, R8, R21,
R22, R24, R67, R77,
R85, R96, R98
R3, R23
R1, R4, R6, R9, R11,
R19, R20, R25
R10
R14
R26, R32
R27, R30, R33, R34,
R35, R47, R48, R54,
R57, R59, R70, R73,
R91, R92, R93, R94,
R95, R105, R123
R31, R36, R37, R49,
R58, R60, R107,
R111, R140
R38
R39, R40
R41, R43, R46, R53
R45, R102
R50
R51, R56, R64, R69
R52
R63
R65, R72, R75
R66
R68
R71, R76, R106
R74, R99
R78, R79
R80
R81
R82, R83
R84
R86
R87
R88, R89, R90, R100,
R101, R103, R104,
R108, R109, R110
R97
SW1, SW2, SW3
Part Number 1
Digi-Key
952-1492-ND
Footprint
MH
Description
Standoff HEX M3 THR Brass 16 mm
IPD068N10N3 G
IPD068N10N3 G-ND
DPAK
MOSFET N-CH 100 V 90 A TO252-3
BSS138
MMBT2907A
NCP15WF104F03RC
BSS138TR-ND
MMBT2907AFSTR-ND
490-4803-2-ND
SOT23
SOT23
R0402
CRCW060310K0JNTA
CRCW060310K0JNTA-ND
R0603
MOSFET N-CH 50 V 220 MA SOT-23
Transistor GP PNP AMP SOT-23
Thermistor 100 kΩ NTC 0402 SMD
resistance 1% beta
Resistor 10 kΩ 5% 1/10 W 0603 SMD
ERJ-M1WTF2M0U
CRCW08052R00JNEA
P2.0NDTR-ND
541-2.0ATR-ND
R2512
R0805
Resistor 0.002 Ω 1 W 1% 2512
Resistor 2 Ω 5% 1/8 W 0805 SMD
CRCW060310K0JNTA
CRCW120630K1FKEA
CRCW08050000Z0EA
CRCW06030000Z0EA
CRCW060310K0JNTA-ND
541-30.1KFTR-ND
541-0.0ATR-ND
541-0.0GTR-ND
R0603
R1206
R0805
R0603
Resistor 10 kΩ 5% 1/10 W 0603 SMD
Resistor 30.1 kΩ 1/4 W 1% 1206 SMD
Resistor 0.0 Ω 1/8 W 0805 SMD
Resistor 0.0 Ω 1/10 W 0603 SMD
CRCW06030000Z0EA
541-0.0GTR-ND
R0603
Resistor 0.0 Ω 1/10 W 0603 SMD
CRCW0603100RFKEA
CRCW080510R0FKEA
CRCW060310R0FKEA
CRCW06034K10JNEA
CRCW060316K5FKTA
CRCW06031K00FKEA
CRCW06031K00FKEA
CRCW0603220KFKEA
CRCW06035K10JNEA
CRCW0805100KJNEA
CRCW06038K20FKEA
CRCW0603220RJNEA
CRCW08051R00JNEA
CRCW080520R0JNEA
CRCW060314K0FKEA
CRCW08051M00FKEA
CRCW0805680RJNEA
CRCW06035K10FKEA
CRCW060354K9FKEA
CRCW060336K0FKEA
CRCW120620K0JNEA
541-100HCT-ND
541-10.0CTR-ND
541-10.0HTR-ND
541-4.7KGCT-ND
CRCW060316K5FKTA-ND
541-1.00KHCT-ND
541-1.00KHCT-ND
541-220KHTR-ND
541-5.1KGCT-ND
541-100KATR-ND
541-8.20KHCT-ND
541-220GCT-ND
541-1.0ATR-ND
541-20ACT-ND
541-14.0KHTR-ND
541-1.00MCTR-ND
541-680ACT-ND
541-5.10KHTR-ND
541-54.9KHTR-ND
541-36.0KHTR-ND
541-20KETR-ND
R0603
R0805
R0603
R0603
R0603
R0603
R0603
R0603
R0603
R0805
R0603
R0603
R0805
R0805
R0603
R0805
R0805
R0603
R0603
R0603
R1206
Resistor 100 Ω 1/10 W 1% 0603 SMD
Resistor 10.0 Ω 1/8 W 1% 0805 SMD
Resistor 10.0 Ω 1/10 W 1% 0603 SMD
Resistor 4.7 kΩ 1/10 W 5% 0603 SMD
Resistor 16.5 kΩ 1% 1/10 W 0603 SMD
Resistor 1.00 kΩ 1/10 W 1% 0603 SMD
Resistor 1.00 kΩ 1/10 W 1% 0603 SMD
Resistor 220 kΩ 1/10 W 1% 0603 SMD
Resistor 5.1 kΩ 1/10 W 5% 0603 SMD
Resistor 100 kΩ 1/8 W 5% 0805 SMD
Resistor 8.20 kΩ 1/10 W 1% 0603 SMD
Resistor 220 Ω 1/10 W 5% 0603 SMD
Resistor 1 Ω 5% 1/8 W 0805
Resistor 20 Ω 1/8 W 5% 0805 SMD
Resistor 14.0 kΩ 1/10 W 1% 0603 SMD
Resistor 1.00 MΩ 1/8 W 1% 0805 SMD
Resistor 680 Ω 1/8 W 5% 0805 SMD
Resistor 5.10 kΩ 1/10 W 1% 0603 SMD
Resistor 54.9 kΩ 1/10 W 1% 0603 SMD
Resistor 36.0 kΩ 1/10 W 1% 0603 SMD
Resistor 20 kΩ 1/4 W 5% 1206 SMD
CRCW080510K0JNEA
EG1218
541-10KATR-ND
EG1903-ND
R0805
SPDT-SLSW
Resistor 10 kΩ 1/8 W 5% 0805 SMD
Switch slide SPDT 30 V 2 A PC MNT
Rev. 0 | Page 42 of 44
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
Qty
43
3
1
1
Reference Designator
TP1, TP3, TP4, TP5, TP6,
TP7, TP8, TP9, TP10,
TP11, TP12, TP13,
TP14, TP15, TP16,
TP17, TP18, TP19,
TP20, TP21, TP22,
TP23, TP24, TP25,
TP26, TP27, TP28,
TP29, TP30, TP33,
TP34, TP35, TP36,
TP37, TP38, TP40,
TP41, TP42, TP47,
TP48, TP49, TP50, TP51
TP39, TP44, TP45
T1
T2
1
T3
1
2
3
1
1
1
T4
U1, U4
U2, U5, U7
U3
U14
Manufacturer
5010
Part Number 1
Digi-Key
5010K-ND
GTP002
PA1005.100NL
#750341378
BDC-25-69
#750341379
N/A
553-1529-2-ND
N/A
N/A
N/A
BSER9-77
N/A
PA1005.100NL
HIP2101EIBZT
ADUM3210BRZ-RL7
ADP3654ARDZ-R7
NCP1031DR2G
553-1529-2-ND
HIP2101EIBZTTR-ND
ADUM3210BRZ-RL7TR-ND
ADP3654ARDZ-R7-ND
NCP1031DR2GOSTR-ND
UG-664
Footprint
TP-70
Description
Test point PC
TP-70 dual
P820X
BDC_2512
P820X
8-SOIC-EP
8-SOIC
8-SOIC_N_EP
8-SOIC
Ground test point
Transformer current sense 2.0 MH 1:100 SMD
Transformer ER25 5:2:2
Transformer ER25 5:2:2
36 V to 75 V input, 12 V 0.25 A pri output,
12 V, 0.25 A sec output, ER9.5 22:8:8
36 V to 75 V input, 12 V pri output, 12 V sec
output, ER9.5 22:8:8
Transformer current sense 2.0 MH 1:100 SMD
IC driver half bridge 100 V 8EPSOIC
iCoupler 2-CH 8-lead SOIC
IC MOSFET DVR 4 A dual HS SOIC_N_EP
IC CTRLR PWM OTP OVD HV 8SOIC
Footprint
C0603
C0603
C0603
C0603
C0603
C0603
SOT323
Header-dr-22
HEADER-L-SR-4
R0603
R0603
R0603
R0805
R0603
R0603
R0603
R0603
R0603
R0603
SO8
CP-20-10
Description
Capacitor ceramic 0.1 µF 25 V 10% X7R 0603
Capacitor ceramic 1 nF 50 V 5% COG 0603
Capacitor ceramic 1 nF 50 V 5% COG 0603
Capacitor ceramic 1 µF 16 V 10% X7R 0603
Capacitor ceramic 100 pF 50 V 5% NP0 0603
Capacitor ceramic 330 nF 50 V 10% X7R 0603
Diode switch dual CC 70 V SOT323
Connector header FMAL 22 POS 0.1" DL gold
Connector header 4 POS SGL PCB 30 gold
Resistor 200 Ω 1/10 W 1% 0603 SMD
Resistor 11 kΩ 1/10 W 0.1% 0603 SMD
Resistor 1.00 kΩ 1/10 W 0.1% 0603 SMD
Resistor 19.1 kΩ 1/8 W 1% 0805 SMD
Resistor 10 kΩ 1/10 W 1% 0603 SMD
Resistor 10 kΩ 1/10 W 0.1% 0603 SMD
Resistor 2 Ω 1/10 W 1% 0603 SMD
Resistor 2.2 kΩ 1/10 W 1% 0603 SMD
Resistor 10 Ω 1/10 W 1% 0603 SMD
Resistor 0 Ω 1/10 W 5% 0603 SMD
IC regulator LDO 200 mA 3.3 V 8-lead SOIC
Digital controller
PBSER9-77
N/A = not applicable.
Table 8. ADP1050DC1-EVALZ Daughter Card
Qty
3
1
2
3
2
1
1
1
1
1
2
3
1
1
1
1
3
1
2
1
1
1
2
Reference
Designator
C1, C6, C9
C4
C5, C10
C7, C8, C13
C11, C12
C14
D2
J1
J2
R3
R4, R8
R5, R7, R9
R6
R10
R11
R12
R13, R14, R15
R16
R17, R18
U1
U2
Part Number 1, 2
Manufacturer
Digi-Key
C1608X7R1H104K
445-1316-2-ND
N/C
N/C
C1608COG1H102J
445-1293-2-ND
C1608X7R1C105K
445-1604-2-ND
C1608COG1H101J
445-1281-2-ND
C1608X7R1H334K
445-5950-2-ND
BAV70WT1G
BAV70WT1GOSTR-ND
PPPC112LFBN-RC
S7114-ND
69167-104HLF
609-2411-ND
N/C
N/C
TNPW060311K0BEEA
TNP11.0KAATR-ND
TNPW06031K00BEEA
TNP1.00KAATR-ND
CRCW080519K1FKEA
541-19.1KCTR-ND
CRCW060310K0FKEA
541-10.0KHTR-ND
TNPW060310K0BEEA
TNP10.0KAATR-ND
CRCW06032R00FKEA
541-2.00HHTR-ND
CRCW06032K20FKEA
541-2.20KHTR-ND
CRCW060310R0FKEA
541-10.0HTR-ND
RC0603JR-070RL
311-0.0GRTR-ND
ADP3303ARZ-3.3
ADP3303ARZ-3.3-ND
ADP1050ACPZ
N/A
N/A = not applicable.
N/C = no connection.
Rev. 0 | Page 43 of 44
UG-664
ADP1051-240-EVALZ/ADP1050DC1-EVALZ User Guide
NOTES
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
“Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including
ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may
not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to
promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any
occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board.
Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice
to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO
WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED
TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL
PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF
THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE
AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable
United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of
Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby
submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
UG12085-0-1/14(0)
Rev. 0 | Page 44 of 44
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