ADP1074ARWZ

Isolated, Synchronous Forward Controller with Active Clamp and iCoupler ADP1074 Data Sheet FEATURES Remote (secondary side) shutdown/reset function Safety and regulatory approvals (pending) UL recognition 5000 V rms for 1 minute per UL 1577 (for wide body SOIC package) 3000 V rms for 1 minute per UL 1577 (for LGA package) CSA component acceptance notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 849 V peak (for wide body SOIC package) VIORM = 560 V peak (for LGA package) CQC certification per GB4943.1-2011 Available in 24-lead SOIC_W package and 24-terminal LGA package AEC-Q100 Qualified for Automotive Applications Current mode controller for active clamp forward topology Integrated 5 kV (wide body SOIC package) or 3.0 kV (LGA package) rated dielectric isolation voltage with Analog Devices, Inc., patented iCoupler technology Wide voltage supply range Primary VIN: up to 60 V Secondary VDD2: up to 36 V Integrated 1 A primary side MOSFET driver for power switch and active clamp reset switch Integrated 1 A secondary side MOSFET drivers for synchronous rectification Integrated error amplifier and VIN UVLO, NGATE and PGATE unloaded At 100 kHz At 300 kHz At 600 kHz VIN > VIN UVLO, NGATE and PGATE loaded with 2.2 nF and 410 pF, respectively At 100 kHz At 300 kHz At 600 kHz EN pin voltage (VEN) < 1.2 V, VREG1 = 0 V, VIN = 60 V VEN < 1.2 V, VREG1 = 12 V, VIN = 12 V VIN rising VIN falling 4.7 24 60 V IVIN VIN Shutdown Current (VIN + VREG1) Start-Up Current VIN UVLO UVLO Hysteresis Time from EN High to PGATE Output Switching Time from EN Low to SR1/SR2 Output Stops Switching SUPPLY (SECONDARY) Supply Voltage Quiescent Supply Current IVIN_STARTUP UVLO Hysteresis Secondary UVLO Hiccup Time OSCILLATOR Switching Frequency (fS) VREG1 PIN VREG1 Voltage Clamp VREG1 Clamp Series Resistance mA mA mA 7.5 12 19.5 mA mA mA μA 55 160 4.7 VEN > 1.2 V, 1 μF capacitor on VREG1 1 μA V V V ms VEN < 1.0 V, 1 μF capacitor on VREG1 1 μs 36 V 4.0 0.19 VDD2 IDD2 IDD2 VDD2 UVLO Threshold 5.3 5.8 6.8 4.7 μF capacitor from VDD2 to PGND2, 1 μF capacitor from VREG2 to PGND2 SR1 and SR2 unloaded At 100 kHz At 300 kHz At 600 kHz SR1 and SR2 loaded with 2.2 nF At 100 kHz At 300 kHz At 600 kHz VDD2 rising VDD2 falling 4.5 12 6.5 6.7 7 mA mA mA 8.3 12 18 3.55 mA mA mA V V V ms 3.0 0.145 200 RT resistance (RRT) = 480 kΩ (±1%) RRT = 240 kΩ (±1%) RRT = 120 kΩ (±1%) RRT = 80 kΩ (±1%) RRT = 60 kΩ (±1%) RRT = 40 kΩ (±1%) 50 − 10% 100 − 10% 200 − 10% 300 − 10% 400 − 10% 600 − 10% 50 100 200 300 400 600 50 + 10% 100 + 10% 200 + 10% 300 + 10% 400 + 10% 600 + 10% kHz kHz kHz kHz kHz kHz VREG1 current (IVREG1) = 3 mA, VEN < 1.2 V VREG1 forced current of 5 mA and 15 mA 13.5 14.3 16 15.2 V Ω Rev. D | Page 4 of 32 Data Sheet Parameter GATE DRIVERS (PRIMARY) NGATE and PGATE High Voltage Gate Short-Circuit Peak Current1 Rise Time NGATE PGATE Fall Time NGATE PGATE Source Resistance NGATE PGATE Sink Resistance NGATE PGATE NGATE Maximum Duty Cycle ADP1074 Symbol SR1 and SR2 Dead Time CURRENT-LIMIT SENSE (PRIMARY) CS Limit Threshold CS Leading Edge Blanking Time Current Source di/dt for Slope Compensation Min Typ Max Unit IVREG1 = 20 mA, VIN > 9 V 7.8 8 8.2 V 8 V on VREG1 RON_SOURCE RON_SINK DMAX NGATE Minimum On Time SRx DRIVERS (SECONDARY) SR1 and SR2 High Voltage Gate Short-Circuit Peak Current1 SRx Time Rise Fall Minimum On SRx Resistance Source Sink DELAYS Gate Delay (SR1 Rising to NGATE Rising) Delay Between NGATE Falling Edge and SR1 Falling Edge SR DEAD TIME (PGATE RISING TO SR2 FALLING) Test Conditions/Comments RON_SR_SOURCE RON_SR_SINK 10% to 90% CNGATE = 2.2 nF CPGATE = 410 pF 90% to 10% CNGATE = 2.2 nF CPGATE = 410 pF Source 100 mA 1.0 A 18 8 ns ns 16 7 ns ns 4 6.5 Ω Ω 3 3.5 50 75 Ω Ω % % Sink 100 mA Divider bottom resistor (RBOT) = 0 Ω Divider top resistor (RTOP) = RBOT, 1% resistors Includes propagation delay and CS comparator blanking time 45 IVREG2 = 15 mA, VDD2 > 5.5 V 5 V on VREG2 4.9 55 170 5 1.0 ns 5.1 V A CSRx = 2.2 nF 10% to 90% 90% to 10% Includes blanking time 14 11 230 ns ns ns Source 100 mA Sink 100 mA 3.5 2 35 Ω Ω   ns 21 ns Dead time resistor (RDT) = 10 kΩ RDT = 22 kΩ RDT = 47 kΩ RDT is open Dead time between SR1 and SR2 154 109 72 42 25 ns ns ns ns ns Over current sense limit threshold 120 150 20 mV ns μA per tS iCoupler delay Resistor (±5%) at NGATE VCS_LIM Switching period (tS) = 1/fS Rev. D | Page 5 of 32 ADP1074 Parameter Overcurrent Protection (OCP) Comparator Delay Time in OCP Before Entering Hiccup Mode OCP Hiccup Time FB PIN AND ERROR AMPLIFIER Feedback Accuracy Voltage Temperature Coefficient FB Input Bias Current Transconductance Output Current Clamp Minimum Maximum COMP Clamp Voltage Minimum Maximum Open-Loop Gain Output Shunt Resistance Gain Bandwidth Product PRECISION ENABLE THRESHOLD EN Threshold EN Hysteresis EN Hysteresis Current MODE PIN Light Load Mode Current Source Hysteresis TEMPERATURE Thermal Shutdown Hysteresis SOFT START SS1 AND SS2 PINS Primary Side SS1 Current Source Secondary Side SS2 Current Source SS2 Discharging Current SYNC PIN Synchronization Range Input Pulse Width Number of Cycles Before Synchronization Input Voltage Low High Leakage Current iCOUPLER DELAY COMP Signal Delay Through iCoupler Data Sheet Symbol Test Conditions/Comments Min See Input/Output Current-Limit Protection section VFB TJ = −40°C to +85°C TJ = −40°C to +125°C gm Max Unit ns 1.5 ms 40 ms 1.2 − 0.85% 1.2 − 1.25% +1.2 +1.2 −100 230 +1 250 20 μA sinking current from COMP pin 20 μA sourcing current to COMP pin VEN Typ 40 1.2 + 0.85% 1.2 + 1.25% 76 +100 270 −57 43 V V ppm/°C nA μA/V   μA  μA  0.7 2.52 80 5 1 V V dB GΩ MHz EN rising VEN < 1.2 V VEN > 1.2 V 1.14 1.2 4 1 3 1.26 V μA μA μA Connect a resistor from MODE to AGND2 6 6.5 7 μA 24 40 60 mV 155 −15 °C °C During soft start only 9.1 μA During soft start only, post handover 20 μA During a fault condition or soft stop 30 μA 100 100 600 kHz ns Cycles 0.4 V V μA 7 3 1 600 Rev. D | Page 6 of 32 ns Data Sheet Parameter FB, OVP, AND PGOOD THRESHOLDS FB Pin OV Hysteresis OVP Pin Hysteresis FB Pin UV Threshold ADP1074 Symbol Undervoltage (UV) threshold for PGOOD to toggle FB Pin UV Hysteresis OVP Comparator Delay (Includes iCoupler Delay) Time from Fault Condition to PGOOD Toggling OVP Pin Leakage Current PGOOD Pin Leakage Current OVP Hiccup 1 Test Conditions/Comments Overvoltage (OV) threshold for PGOOD to toggle for FB and OVP pin Min 1.3 Typ 1.36 1.04 36 36 1.11 Max 1.42 Unit V 1.16 mV mV V 36 320 mV ns OVP pin fault to PGOOD toggling 90 ns FB pin OV/UV to PGOOD toggling 5 200 μs μA μA  μs 200 ms  1 1 Time in OVP before entering OVP hiccup mode Hiccup time triggered by OVP event Short-circuit duration less than 1 μs. Average power must conform to the limit shown in the Absolute Maximum Ratings section. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 3. Parameter WIDE BODY SOIC iCoupler Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Air Gap (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group LAND GRID ARRAY (LGA) iCoupler Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Air Gap (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol Test Conditions/Comments Min 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation Typ 5 Max Unit kV 7.6 mm 7.6 mm CTI 0.030 mm >400 V 2.5 kV Material Group II (DIN VDE 0110, 1/89, Table 1) 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation CTI Material Group I (DIN VDE 0110, 1/89, Table 1) Rev. D | Page 7 of 32 4 mm 4 mm 0.030 mm >400 V ADP1074 Data Sheet REGULATORY INFORMATION See Table 4, Table 5, and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross isolation waveforms and insulation levels. Table 4. Regulatory Information for Wide Body SOIC Package UL (Pending) Recognized Under UL 1577 Component Recognition Program1 Single Protection, 5000 V rms Isolation Voltage File (pending) 1 2 CSA (Pending) Approved under CSA Component Acceptance Notice 5A CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1+A2 and IEC62368: Basic insulation at 780 V rms (1103 V peak) Reinforced insulation at 390 V rms (552 V peak) IEC 60601-1 Edition 3.1: Basic insulation (1 means of patient protection (1 MOPP)), 490 V rms (686 V peak) Reinforced insulation (2 MOPP), 238 V rms (325 V peak) CSA 61010-1-12 and IEC 61010-1 third edition: Basic insulation at 300 V rms mains, 780 V secondary (1103 V peak) File (pending) VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation, maximum working insulation voltage (VIORM) = 849 V peak, highest allowable overvoltage (VIOTM) = 8000 V peak CQC (Pending) Certified by CQC11-471543-2012, GB4943.1-2011: Basic insulation at 780 V rms (1103 V peak) Reinforced insulation at 389 V rms (552 V peak), tropical climate, altitude ≤5000 meters File (pending) File (pending) In accordance with UL 1577, each product is proof tested by applying an insulation test voltage ≥6000 V rms for 1 sec. In accordance with DIN V VDE V 0884-10, each product is proof tested by applying an insulation test voltage ≥1592 V peak for 1 sec (partial discharge detection limit = 5 pC). Note that the asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. Table 5. Regulatory Information for LGA Package UL (Pending) Recognized Under UL 1577 Component Recognition Program1 Single Protection, 3000V rms Isolation Voltage File (pending) 1 2 CSA (Pending) Approved under CSA Component Acceptance Notice 5A CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1+A2 and IEC62368: Basic insulation at 400 V rms (565 V peak) Reinforced insulation at 200 V rms (283 V peak) IEC 60601-1 Edition 3.1: Basic insulation (1 means of patient protection (1 MOPP)), 250 V rms (354 V peak) CSA 61010-1-12 and IEC 61010-1 third edition: Basic insulation at 300 V rms mains, 400 V secondary (565 V peak) File (pending) VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation, VIORM = 565 V peak, VIOTM = 4242 V peak impulse voltage = 4242 V peak CQC (Pending) Certified by CQC11-471543-2012, GB4943.1-2011: Basic insulation at 400 V rms (565 V peak) Reinforced insulation at 200 V rms (283 V peak), tropical climate, altitude ≤5000 meters File (pending) File (pending) In accordance with UL 1577, each product is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec. In accordance with DIN V VDE V 0884-10, each product is proof tested by applying an insulation test voltage ≥1059 V peak for 1 sec (partial discharge detection limit = 5 pC). Note that the asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. Rev. D | Page 8 of 32 Data Sheet ADP1074 DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS This isolator is suitable for reinforced isolation within the safety limit data only. Maintenance of the safety data is ensured by protective circuits. Note that the asterisk (*) marked on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 6. DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics for Wide Body SOIC Package Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Conditions VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Reinforced Safety-Limiting Values Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 565 1060 VPEAK VPEAK 905 679 VPEAK VPEAK VIOTM VIOSM 7071 6000 VPEAK VPEAK TS IS1 IS2 RS 150 160 170 >109 °C mA mA Ω VPR VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds VPEAK = 10 kV, 1.2 μs rise time, 50 μs, 50% fall time Maximum value allowed in the event of a failure; see Figure 2 Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS VIO = 500 V 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 15627-026 SAFE OPERATING PVDDA , PVREG POWER (W) 1.2 Figure 2. Thermal Derative Curve, Dependence of Safety Limiting Values with Ambient Temperature per DINV VDE V 0884-10 Rev. D | Page 9 of 32 ADP1074 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS This isolator is suitable for reinforced isolation within the safety limit data only. Maintenance of the safety data is ensured by protective circuits. Note that the asterisk (*) marked on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 7. DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics for LGA Package Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Conditions VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Reinforced Safety-Limiting Values Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 565 1060 VPEAK VPEAK 905 679 VPEAK VPEAK VTR VIOSM 4242 6000 VPEAK VPEAK TS IS1 IS2 RS 150 160 170 >109 °C mA mA Ω VPR VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds VPEAK = 10 kV, 1.2 μs rise time, 50 μs, 50% fall time Maximum value allowed in the event of a failure; see Figure 3 Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS VIO = 500 V 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 15627-025 SAFE OPERATING PVDDA , PVREG POWER (W) 1.2 Figure 3. Thermal Derative Curve, Dependence of Safety Limiting Values with Ambient Temperature per DINV VDE V 0884-10 Rev. D | Page 10 of 32 Data Sheet ADP1074 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter VIN, EN VDD2 VREG1 VREG2 NGATE, PGATE RT, CS, SYNC, SS1, SS2, PGOOD, FB, COMP, OVP, MODE, DMAX, SR1, SR2 AGND1, PGND1, AGND2, PGND2 Common-Mode Transients1 Operating Temperature Range Storage Temperature Range Junction Temperature Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) RoHS Compliant Assemblies (20 sec to 40 sec) Electrostatic Discharge (ESD) Charged Device Model (CDM) Human Body Model (HBM) 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating −0.3 V to +66 V −0.3 V to +42 V −0.3 V to +16 V −0.3 V to +6 V −0.3 V to +16 V −0.3 V to +6 V Table 9. Thermal Resistance1 Package Type RW-24 (Wide Body SOIC) CC-24-6 (LGA) ±0.3 V ±25 kV/μs −40°C to +125°C −65°C to +150°C 150°C 1 ±1250 V ±2 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Unit °C/W °C/W Table 10. Maximum Continuous Working Voltage, Wide Body SOIC1 1 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum rating can cause latch-up or permanent damage. θJC 43.8 43 Thermal impedance simulated values are based on JEDEC 2S2P thermal test board. See JEDEC JESD-51. Waveform AC Voltage Bipolar Unipolar DC Voltage 240°C 260°C θJA 65.4 62.1 Maximum Voltage (VPEAK) Constraint 565 1131 1131 50-year minimum lifetime 50-year minimum lifetime 50-year minimum lifetime Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 11. Maximum Continuous Working Voltage, LGA1 Waveform AC Voltage Bipolar Unipolar DC Voltage 1 Maximum Voltage (VPEAK) Constraint 565 909 565 50-year minimum lifetime Limited by creepage Limited by creepage Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. ESD CAUTION Rev. D | Page 11 of 32 ADP1074 Data Sheet NGATE 1 24 SR1 PGATE 2 23 SR2 PGND1 PGATE NGATE SR1 SR2 PGND2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PGND1 3 22 PGND2 3 2 1 24 23 22 AGND1 4 21 AGND2 19 VDD2 18 OVP 17 FB 16 COMP VIN 6 EN 7 CS 8 RT 9 17 FB 16 COMP 15 SS2 14 PGOOD 13 MODE TOP VIEW (TERMINAL SIDE DOWN) Not to Scale AGND1 AGND2 10 11 12 13 14 15 15627-027 VREG2 ADP1074 SS2 DMAX 12 AGND2 20 PGOOD SS1 11 21 5 MODE RT 9 SYNC 10 4 VREG1 DMAX CS 8 AGND1 SS1 20 VREG2 TOP VIEW VIN 6 (Not to Scale) 19 VDD2 18 OVP EN 7 SYNC ADP1074 15627-002 VREG1 5 Figure 5. 24-Terminal LGA Pin Configuration Figure 4. 24-Lead SOIC_W Pin Configuration Table 12. Pin Function Descriptions Pin No. 1 Mnemonic NGATE 2 3 4 PGATE PGND1 AGND1 5 VREG1 6 VIN 7 EN 8 CS 9 RT 10 SYNC 11 12 SS1 DMAX 13 MODE 14 15 PGOOD SS2 Description Driver Output for the Main Power MOSFET on the Primary Side. Multiple function pin. Connect a resistor from NGATE to PGND1 to set up the predetermined dead time between PGATE and SR2. Driver for the Active Clamp MOSFET of the Forward Topology. This pin is referenced to PGND1. Power Ground on the Primary Side. Star connect this pin to AGND1. Analog Ground on the Primary Side. Star connect this pin to PGND1. Use this pin to differentially sense the primary current sensed with the sense resistor between the CS and AGND1 pins. 8 V Output for the MOSFET Drivers. Connect 1 μF or greater at this pin. Do not put an external load on this pin. Reference this pin to PGND1. Input Voltage. Connect a 4.7 μF capacitor to this pin. The size of this capacitor can be reduced if the input voltage to this pin is guaranteed stable. Reference this pin to PGND1. Precision Enable Input. The controller is enabled when the voltage at the EN pin is above the EN threshold voltage. Soft stop is enabled when EN drops below the EN threshold voltage. This pin also has a programmable EN hysteresis. Reference this pin to AGND1. Input Current Sensing. This pin senses the input pulse width modulated current. Place a current sense resistor between the source terminal of the power MOSFET and PGND1. This current sense resistor sets up the input current limit. This pin is also used for an external slope compensator. Connect a resistor from CS to the current sense resistor to generate a voltage ramp for the slope compensation. Reference this pin to AGND1. Connect a 33 pF to 100 pF capacitor to this pin to act as a resistor capacitor (RC) filter along with the slope compensation resistor in noisy environments. Switching Period Resistor. Connect two resistors in series that sum up to the appropriate resistor from RT to AGND1 to set the switching frequency. See the DMAX pin for more information. Also see the Frequency Setting (RT Pin) section and the Maximum Duty Cycle section for the relevant equations. Frequency Synchronization. Connect an external clock to the SYNC pin to synchronize the internal oscillator to this external clock frequency. Connect SYNC to AGND1 if this feature is not used. It is recommended that the SYNC frequency be within 10% of the frequency set by the RT pin. Soft Start 1. Connect a capacitor at this pin to set up the open-loop soft start time. Reference this pin to AGND1. Maximum Duty Cycle Control. Connect DMAX to the center tap of the resistive divider at the RT pin to set up the maximum duty cycle. See the Frequency Setting (RT Pin) section and the Maximum Duty Cycle section for the relevant equations. Light Load Mode Setting. Connect MODE to AGND2 to disable discontinuous conduction mode (DCM) operation, or to a high logic (2.5 V or higher, such as the VREG2 pin) to force LLM operation, or to a resistor to set up a fixed LLM threshold voltage. Power Good Pin. Open-drain output. Connect a pull-up resistor from PGOOD to VREG2. Soft Start on the Secondary Side. Connect a capacitor from SS2 to AGND2 to set up the soft start time on the secondary side. Rev. D | Page 12 of 32 Data Sheet Pin No. 16 Mnemonic COMP 17 FB 18 OVP 19 VDD2 20 VREG2 21 AGND2 22 23 24 PGND2 SR2 SR1 ADP1074 Description Compensation Node on the Secondary Side. This pin is the output of the transconductance (gm) amplifier. This pin is referenced to AGND2. Feedback Node on the Secondary Side. Set up the resistive divider from the output voltage such that the nominal voltage, when the power supply is in regulation, is 1.2 V. Reference this pin to AGND2. Output Overvoltage Protection (OVP). The OVP threshold is set at 1.36 V. Connect a resistive divider from OVP to the output and AGND2. Input Supply on the Secondary Side. Connect VDD2 to the output voltage of the power supply for a self driven configuration. Connect a 4.7 μF capacitor from VDD2 to AGND2. The size of this capacitor can be reduced if the input voltage to VDD2 is guaranteed stable. 5 V Regulated Low Dropout (LDO) Output for Internal Bias and Powering of the Drivers of the Synchronous Rectifiers. Do not use VREG2 as a reference or load. Connect a 1 μF capacitor from VREG2 to AGND2. Analog Ground on the Secondary Side. Star connect AGND2 to PGND2. Use AGND2 for differential sensing of the output voltage between the FB pin and AGND2. Power Ground on the Secondary Side. Star connect PGND2 to AGND2. MOSFET Driver Output 2 for the Synchronous Rectifier MOSFET. This PWM controls the freewheeling switch. MOSFET Driver Output 1 for the Synchronous Rectifier MOSFET. This PWM is in phase with NGATE. Rev. D | Page 13 of 32 ADP1074 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.24 1.210 FB PIN REFERENCE THRESHOLD (V) EN PIN RISING THRESHOLD (V) 1.23 1.22 1.21 1.20 1.19 MAXIMUM MEAN MINIMUM 1.18 1.17 1.16 1.205 1.200 1.195 MAXIMUM MEAN MINIMUM 1.190 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 1.185 –40 –10 5 20 35 50 65 80 95 110 125 125 TEMPERATURE (°C) Figure 6. EN Pin Rising Threshold vs. Temperature Figure 8. FB Pin Reference Threshold vs. Temperature 1.24 6.8 1.23 6.7 MODE PIN CURRENT (µA) 1.22 1.21 1.20 1.19 MAXIMUM MEAN MINIMUM 1.18 1.17 6.6 6.5 6.4 6.3 6.2 1.16 1.14 –40 MAXIMUM MEAN MINIMUM 6.1 1.15 –25 –10 5 20 35 50 65 80 95 110 TEMPERATURE (°C) 125 15627-004 EN PIN FALLING THRESHOLD (V) –25 15627-005 –25 15627-003 1.14 –40 15627-006 1.15 Figure 7. EN Pin Falling Threshold vs. Temperature 6.0 –40 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) Figure 9. MODE Pin Current vs. Temperature Rev. D | Page 14 of 32 110 Data Sheet ADP1074 43 24 NGATE DELAY (ns) SR1 RISING TO NGATE RISING SR DEADTIME (ns) SR1 FALLING TO SR2 RISING 41 MAXIMUM MEAN MINIMUM 23 22 21 20 19 39 37 35 33 MAXIMUM MEAN MINIMUM 31 29 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 25 –40 15627-007 18 –40 Figure 10. SR Dead Time (SR1 Falling to SR2 Rising) vs. Temperature MAXIMUM MEAN MINIMUM SR DEADTIME (ns) SR2 FALLING TO SR1 RISING 26 25 24 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 15627-008 23 –25 5 20 35 50 65 80 95 110 125 Figure 12. NGATE Delay (SR1 Rising to NGATE Rising) vs. Temperature 27 22 –40 –10 TEMPERATURE (°C) 29 28 –25 15627-009 27 Figure 11. SR Dead Time (SR2 Falling to SR1 Rising) vs. Temperature Rev. D | Page 15 of 32 ADP1074 Data Sheet THEORY OF OPERATION The ADP1074 is a current mode, fixed frequency, active clamp, synchronous forward controller designed for isolated dc to dc power supplies. Analog Devices proprietary iCouplers are integrated in the ADP1074 to eliminate the bulky signal transformers and optocouplers that transmit signals over the isolation boundary. Integrating the iCouplers reduces system design complexity, cost, and component count and improves overall system reliability. With the integrated isolators and MOSFET drivers on both the primary and the secondary side, the ADP1074 offers a compact system level design and yields a higher efficiency than a nonsynchronous forward converter at heavy loads. Traditionally in a forward or flyback converter, a discrete optocoupler is used in the feedback path to transmit the signal from the secondary to the primary side, and an external transformer is used for transmitting the PWM signal from the primary to the secondary side for synchronous rectification. However, the current transfer ratio (CTR) of the optocouplers degrades over time and over temperature and so the optocoupler must be replaced every five to ten years, depending on the manufacturing quality and optocoupler grade that determines the initial CTR. The ADP1074 eliminates the use of optocouplers and signal transformers, thus reducing system cost, PCB area, and complexity while improving system reliability, without the issue of CTR degradation of the optocouplers. The ADP1074 controller offers a complete solution for an isolated dc to dc power supply by integrating the 5 kV isolators and the primary and secondary control circuitries in one package. The PWM controls are performed on the primary side by sensing the input peak current cycle by cycle with a sense resistor at the source of the main switching MOSFET. The output of the converter is sensed by the secondary circuitry, which sends the feedback and PWM signals to the primary side via the 5 kV integrated isolators for a complete control loop solution. The primary circuitry in the ADP1074 includes an 8 V LDO, input current sensing, bias circuit, and MOSFET drivers including an active clamp reset driver, slope compensation, external frequency synchronization, PWM generator, and a programmable maximum duty cycle setting. The primary side also has pins for differential sensing of the current sense signal. The secondary circuitry includes the feedback compensation, a 5 V LDO regulator, an internal reference, two MOSFET drivers for synchronous rectification, and a dedicated pin for overvoltage protection. Additionally, the secondary side features differential output voltage sensing and power good pins, and a programmable light load mode setting. The integrated iCouplers carry out the communications between the primary and secondary sides by transmitting the feedback signal and the PWMs over the isolation barrier. The feedback signal and timing of synchronous rectifier PWMs are transmitted between the primary and the secondary sides, or between the secondary and primary sides, through the iCouplers using a proprietary transmission scheme. The ADP1074 also offers features such as input current protection, UVLO, precision enable with adjustable hysteresis, OTP, LLM, and tracking. Rev. D | Page 16 of 32 Data Sheet ADP1074 DETAILED BLOCK DIAGRAM Figure 13 shows a detailed block diagram of the ADP1074. VDD2 VIN 5V LDO 8V LDO VREG2 VREG1 BIAS VREF VREF2 1.2V 14V OVP 1.36V OV 1.2V EN LOGIC CLAMP MAXIMUM 1µA 4µA THERMAL LIMIT COMP CLAMP MINIMUM VREG2 RT fOSC DC SS2 OSCILLATOR OCP RECOVERY gm AMPLIFIER 1.2VREF SYNC COMP SLOPE RAMP 1.10V VREG NGATE DRV VREG PGATE DRV LOGIC AND DEAD TIME CTRL FB Tx Rx Q S R DETECT SECONDARY SIDE UVLO AND HANDOVER CONTROL FROM PRIMARY HANDOVER TO SECONDARY Tx PGOOD LOGIC 1.36V VREG2 Rx SR1 DRV CS PWM LOGIC CONTROL OV DETECT VREG2 SR2 DRV DMAX VREG2 6µA COMP SS1 MODE OV LLM THRESHOLD AGND1 AGND2 PGND2 15627-010 PGND1 OC THRESHOLD Figure 13. Detailed Block Diagram Rev. D | Page 17 of 32 ADP1074 Data Sheet PRIMARY SIDE SUPPLY, INPUT VOLTAGE, AND LDO Two pins on the primary side are supply pins: VIN and VREG1. A high voltage LDO regulator connected to VIN has a regulated output of 8 V at the VREG1 pin. This LDO regulator provides power to the internal bias circuitry, primary side iCouplers and housekeeping circuits, and the primary MOSFET drivers at the NGATE and PGATE pins. To reduce power consumption in the LDO for input voltages higher than approximately 30 V, an auxiliary winding on the transformer of the active clamp forward topology can be used to power VREG1. This auxiliary supply voltage must be higher than the regulated output at VREG1 so that the LDO shuts off during normal operation. The recommended auxiliary voltage is ≥8.5 V and ≤13 V because an internal 14 V Zener diode is connected at VREG1. For a high input voltage application to avoid losses in the LDO, connect the VIN and VREG1 pins together and apply an auxiliary voltage of 8 V to 10 V, which exceeds the VIN pin UVLO of typically 4.5 V. Take care that this voltage does not exceed the internal Zener clamp voltage of 14 V (typical). The typical value is 10 V. hysteresis, use the superposition theorem or nodal analysis to obtain the EN pin voltage, as follows: VEN  VIN  R2  I EN  (R1 || R2  RH ) R1  R2 where: VEN is the EN pin voltage. IEN is the current source at the EN pin (1 μA for turn on and 4 μA for turn off). The user can adjust the R1, R2, and RH resistors such that VEN ≥ 1.2 V and obtain the desired hysteresis. An internal 1 μA pull-down current is always on, and the 3 μA current is active only when the VEN is below the EN threshold and becomes inactive when VEN is above the EN threshold. In general, a higher input voltage requires a larger hysteresis. It is recommended to keep a capacitor on the EN pin to AGND1 to provide a low impedance path that prevents any noise, which toggles the EN pin when the input voltage hovers at the threshold. VIN R1 SECONDARY SIDE SUPPLY AND LDO 8V LDO VREF 1.2V ADP1074 LOGIC RH EN Two pins on the secondary side are supply pins: VDD2 and VREG2. R2 The secondary side is typically powered by the output rail of the converter by connecting it to the VDD2 pin. The UVLO for the secondary side is typically 3.5 V, at which the secondary side starts up. For output voltages less than the secondary UVLO voltage, a third winding is required to generate an auxiliary voltage to power the secondary circuitry. The internal 5 V LDO regulator at the VREG2 pin powers the MOSFET drivers, secondary side iCouplers, and housekeeping circuits. When VDD2 is less than 5 V, the LDO regulator operates in dropout mode. For output voltages higher than 24 V, connecting the output voltage directly to VDD2 can result in significant power dissipation in the LDO. For instance, at 24 V and with the total driver current at 10 mA, the power dissipated in the LDO is 0.19 W (10 mA × 19 V). It is recommended to power VDD2 with an auxiliary voltage in the 8 V to 12 V range. PRECISION ENABLE The enable threshold at the EN pin is precision voltage referenced at 1.2 V. Assuming VIN is above the UVLO voltage (typically 4.5 V), the ADP1074 is enabled when the voltage at EN rises above 1.2 V. The crossing of the voltage, such that VEN > 1.2 V, enables the internal 8 V LDO regulator on the VREG1 pin, and, after the internal biasing is finished, a soft start procedure is initiated. Connect a resistive divider between EN and VIN to set up the input start-up voltage (see Figure 14.) An internal current source at EN allows the user to program the UVLO start-up voltage with a desirable hysteresis. To calculate the start-up voltage with 3µA HYSTERESIS GENERATOR 15627-011 1µA Figure 14. Precision EN with Adjustable Hysteresis When the EN pin is less than the EN threshold, the system enables the soft stop procedure. SR1 and SR2 take up to a maximum of two switching periods to terminate. See the Soft Start Procedure section for more details. SOFT START PROCEDURE The following procedure assumes that the VDD2 pin is powered directly from the output voltage of the power supply. To ensure a smooth output voltage ramp during startup, the soft start sequence is controlled by two soft start control circuits, one in the primary (for open-loop soft start, using the SS1 pin) and the other in the secondary (for closed-loop soft start, using the SS2 pin). Proper handshaking between the primary side and the secondary side is needed prior to the secondary side taking control. The open-loop soft start time is determined by the capacitor on the SS1 pin. This pin sources a 9.1 μA constant current that builds up a voltage on the SS1 pin. The voltage on the SS1 pin is proportional to the peak primary current limit where 0 V and 1.5 V correspond to a peak current of 0 A and 120 mV/RSENSE, respectively. This rate is the open-loop soft start. During this time, the ADP1074 starts firing the PWM pulses, and the output voltage continues to build up slowly if the average inductor current limit exceeds the load current. Because the ADP1074 is a current mode controller, the output capacitor Rev. D | Page 18 of 32 Data Sheet ADP1074 starts charging only when the primary current limit exceeds the load current requirement. The rate at which the SS1 pin voltage rises to the maximum current limit is given by dt = CSS1 × 1.5/(9.1 μA) The handshaking process is as follows. When VDD2 reaches the UVLO of approximately 3.5 V, the internal circuitry on the secondary side is activated and the ADP1074 initiates the following process: 1. 2. The ADP1074 makes the voltage on the SS2 pin equal to the value on the FB pin, with an SS2 pin current, at ten times the nominal current source of 20 μA on the SS2 pin. Simultaneously, the current limit on the primary (which is the voltage on SS1) is transferred over to the secondary side, and the voltage on the COMP pin is made equal to the instantaneous SS1 voltage ± 100 mV. There is a timeout for this process, which is 1.5 ms after the VDD2 UVLO threshold is crossed. When this process is satisfied, the transmission of the COMP signal occurs from the secondary to the primary side. The ADP1074 transmits the COMP signal by continuously sampling the analog signal at the COMP pin. The sampled value is then transmitted using a proprietary scheme to the primary side where the instantaneous value of the CS pin is compared to the COMP level to determine the falling edge of the NGATE pulse. The COMP signal is, therefore, a representation of the primary current limit. After COMP transmission begins, the primary side receives the signal and control is completely handed over to the secondary side when either the received level of COMP on the primary side is within ±100 mV, or up to 128 switching periods (typically 8) have passed, starting from the first pulse being transmitted to the primary side. Then, the control is handed over to the secondary side and the closed-loop soft start begins, where the SS2 capacitor is charged at a nominal rate of 20 μA. The output voltage then rises to the regulation voltage based on the SS2 pin voltage. The voltage on the SS2 pin continues to rise to 1.2 V, that is, the steady state voltage on the FB pin. At this stage, the power supply is in regulation, and the output voltage is at its target value. At the end of the soft start process, the voltage on the SS2 pin continues to rise to approximately 1.4 V. The instant that the handover takes place, SS1 is discharged to 0 V. In steady state, the FB pin (that is, the reference voltage) is 1.2 V. The SR1 and SR2 synchronous drivers begin to pulse after VDD2 crosses the UVLO threshold. If the voltage at the VDD2 pin is greater than the UVLO voltage, such as a soft start from the precharged output, or if the VDD2 pin is powered by an external supply, the secondary side assumes control from the moment the EN pin is enabled, and only SS2 is used for the soft start procedure. When initiating a soft start from the precharged output, the SS2 pin tracks the FB pin and then initiates a soft start. This process eliminates any glitches in the output voltage. When soft starting into a precharged output, the SRx gates are prevented from turning on until the SS2 voltage has reached the precharged voltage at the FB pin. This soft start scheme prevents the output from being discharged, and it prevents reverse current. Under abnormal situations, such as a shorted load or a transient condition on the load during the soft start process, FB may not be able to track SS2 accurately. If this occurs before the VDD2 UVLO threshold is crossed, SS1 is in control. If it occurs after the VDD2 UVLO threshold is crossed, SS2 tracks the FB pin and then continues with the soft start process until the regulation voltage is reached. In all conditions, control is handed over to the secondary if FB ≥ 1.2 V. When the secondary VDD2 is directly powered by the output of the converter, the minimum output voltage required is higher than the secondary UVLO voltage. For output voltages less than the secondary UVLO voltage, a third winding is needed to generate an auxiliary voltage to power the secondary side circuitry. Alternately, in most cases, a diode resistor capacitor combination from the switch node can provide the voltage to VDD2. OUTPUT VOLTAGE SENSING AND FEEDBACK The output voltage of the converter is set by a resistive divider to the FB pin. The resistive divider must be set in a manner such that the voltage at the FB pin is 1.2 V in steady state. The output voltage must be differentially sensed using the FB pin and the AGND2 pin. LOOP COMPENSATION AND STEADY STATE OPERATION The FB pin feeds into the negative terminal of a transconductance amplifier (or gm amplifier) with a gain of approximately 250 μA/V. The positive input terminal of the gm amplifier is connected to SS2, which provides the reference setpoint voltage. The output of the gm amplifier is connected to the COMP pin. The voltage on the COMP pin is representative of the current peak limit required to sustain regulation. This pin is continuously sampled, and the signal is transmitted to the primary side, where it is compared to the sensed primary current using a comparator. When the comparator trips, it causes NGATE to terminate. Typically, an RC network in series is connected between the COMP pin and AGND2 for compensation. A high frequency pole in the form of a capacitor can also be added in parallel to the RC network. The output of the gm amplifier is clamped to a minimum and maximum current of approximately −57 μA and +43 μA, respectively. Rev. D | Page 19 of 32 ADP1074 Data Sheet The COMP node is clamped to a lower and higher level of approximately 0.7 V and 2.52 V, respectively. This is representative of the CS range from 0 mV to 120 mV. SLOPE COMPENSATION For a peak current mode controller with duty cycle higher than 50%, slope compensation is necessary for a stable operation. To set up an external compensation in the ADP1074, connect the external RRAMP resistor (see Figure 25) between CS and the current sense resistor, RSENSE, to set up the slope voltage ramp for the control signal. It is important to sense the signal differentially. See the Layout Guidelines section for more details. An internal ramp current starts from 0 μA at the minimum duty cycle (that is, the beginning of the switching period) and increases linearly toward a maximum of 20 μA at the end of the switching period. The slope of the voltage ramp is the ramp current times RRAMP. RRAMP is sized using the following equation: RRAMP  k VOUT N2 RSENSE    tS L N1 20 μA where: k = 0.5 for nominal cases and k = 1 for deadbeat control. VOUT is the desired output voltage. L is the output inductor. N1 and N2 are the primary and secondary turns of the transformer. tS is the switching period. INPUT/OUTPUT CURRENT-LIMIT PROTECTION There is no direct current-limit sensing circuit on the secondary; the output current limit is indirectly limited by the cycle-by-cycle primary side current limit of 120 mV on the CS pin. The input peak current limit is set by connecting a sense resistor, RSENSE, from the source of the main MOSFET to PGND1 (see Figure 25), and the sensed voltage appears at the CS pin. To generate the slope-comp ramp, insert the slope compensation resistor, RRAMP, between CS and RSENSE. the inaccuracy of the peak current limit. For instance, if the added slope ramp voltage is 20% of the current-limit threshold, the actual input peak current limit can be off by as much as 20% depending on where the peak current-limit threshold is tripped during the on cycle. In the event of an output short circuit, the controller treats this condition as an overcurrent event and enters the 40 ms hiccup mode. Under certain conditions, the ADP1074 exits OCP hiccup mode. In these conditions, the COMP pin is at the maximum clamp level, but the device does not enter hiccup mode. However, it is guaranteed that the PWMs are terminated whenever the CS maximum threshold is reached. The condition under which the ADP1074 skips entering hiccup mode is when VDD2 is powered through an auxiliary winding and an output short circuit occurs that results in the FB pin having a voltage that is 85°C), and can be exacerbated at higher temperatures. The root cause of the device exiting hiccup mode is due to the effect that the OCP hiccup mode feature has on the SS2 pin. During OCP recovery, the SS2 pin tracks the FB pin and attempts a soft start from the precharge sequence. During the time when SS2 tracks the FB pin, the SS2 pin voltage can be less than the FB pin for a short interval, which causes the COMP pin (output of the gm amplifier) to momentarily dip below the maximum COMP pin clamp level. This event means that the current limit required for the next few switching periods is less than the maximum threshold and puts the device out of hiccup mode because the ADP1074 fails to register 1.25 ms worth of consecutive overcurrent cycles. The following scenarios guarantee OCP hiccup mode based on the configuration of the VDD2 power supply: 1. The CS current limit, VCSLIM, is internally set to 120 mV. Calculate the RSENSE value by RSENSE  2. VCSLIM  RRAMP  20 μA I PKPRI where: VCSLIM is the CS current limit. IPKPRI is the primary peak current. When the sensed input peak current is above the CS limit threshold, the controller operates in the cycle-by-cycle constant current-limit mode for 1.5 ms. Then the controller immediately shuts down the primary and secondary drivers. The controller then goes into hiccup mode for the next 40 ms and restarts the soft start sequence after this timeout period. The slope ramp can affect the accuracy of the current-limit threshold because the voltage drop across RRAMP contributes to Rev. D | Page 20 of 32 When VDD2 is powered directly from the output voltage, if a short circuit occurs on the output terminals of the load after steady state regulation is achieved, the voltage of the VDD2 pin is less than the UVLO, and the device enters hiccup mode for 200 ms, similar to the hiccup time described in the Remote System Reset section. When VDD2 is powered through auxiliary winding or another configuration, when a short circuit occurs on the output terminals, the auxiliary winding is not shorted and maintains a positive voltage above the UVLO threshold of the VDD2 pin. To enter hiccup mode, it is recommended to use the circuit shown in Figure 15. The circuit operates as follows: when the output voltage goes low due to a short circuit, the D1 diode turns on, which pulls the base of the bipolar junction transistor low, shutting off VDD2. The system then enters hiccup mode, as described in the Remote System Reset section. Data Sheet ADP1074 MAXIMUM DUTY CYCLE To prevent the transformer core from saturating in the event of high current or extreme load transient and reduce voltage stress on the MOSFETs, a maximum duty cycle clamp can be set by connecting the DMAX pin to the center tap of the resistive divider that is connected from RT to AGND1, as shown in Figure 16. DMAX RT RTOP RBOT VOUT VDD2 D1 R4 100Ω VOUT ~6.3V ZENER AGND2 15627-028 R3 500Ω Figure 15. Recommended Circuit to Guarantee Hiccup Mode Showing Typical Values TEMPERATURE SENSING The ADP1074 has an internal temperature sensor that shuts down the controller when the internal temperature exceeds the OTP limit. At this time, the primary and secondary MOSFET drivers (PGATE, NGATE, SR1, and SR2) are held low. When the temperature drops below the OTP hysteresis level, the ADP1074 restarts with a soft start sequence. FREQUENCY SETTING (RT PIN) The switching frequency can be programmed in a range of 50 kHz to 600 kHz by connecting a resistor from RT to AGND1. A small current flows out of the RT pin and the voltage across it sets up the internal oscillator frequency. The value of this pin is approximately 1.224 V in steady state. Use the following equation to determine the resistor (in Ω) for a particular switching frequency (in kHz): f S (kHz)  41.67 10 12 1 1   (RTOP  RBOT ) 1000 where: fS is the switching frequency. RTOP is the top resistor of the divider. RBOT is the bottom resistor of the divider. AGND1 The maximum duty cycle is calculated by the following: DMAX  50  50  RBOT % (RTOP  RBOT ) where: DMAX is 50% when RBOT is 0 Ω or when the DMAX pin is connected to AGND1. For example, when RTOP is equal to RBOT, DMAX is 75%. DMAX can reach 100% if RTOP is 0 or when RBOT becomes open circuit. RBOT is the bottom resistor of the divider. RTOP is the top resistor of the divider. D1 FROM AUMILIARY WINDING ~10V ADP1074 Figure 16. Setting the Maximum Duty Cycle, DMAX ALTERNATE OPTION R4 100Ω PGND1 15627-012 R3 is sized to bias the Zener diode and R4 is sized such that (VZENER – 1)/R4 > IZENER, where VZENER is the voltage of the diode and IZENER is the biasing current of the diode. This sizing ensures that the impedance of the resistor is less than the impedance of the diode, which causes the voltage of the diode to drop, and allows VDD2 to enter UVLO. If the output voltage is (VFB + 100 mV), the COMP pin voltage increases to the clamp level, and the system again enters OCP/feedback recovery mode. OUTPUT VOLTAGE TRACKING The ADP1074 offers a tracking feature. During steady state, the FB pin is at 1.2 V. At this time, the SS2 pin voltage is at 1.4 V. Using an external DAC, the voltage on the SS2 pin can modulate the output voltage. It is recommended that the SS2 pin voltage be changed only after the VDD2 UVLO point is crossed, and control is handed over to the secondary side, or else the handover process does not occur smoothly, resulting in glitches in the output voltage. Ideally, the PGOOD pin can be used as a signal that indicates that regulation is achieved, to initiate the tracking. The SS2 voltage must be brought down from 1.4 V to 1.2 V, and it must be brought down even further to effect any change in the output voltage. The rate at which the output tracks the SS2 pin is dependent upon the overall system bandwidth. Note that while modulating the output voltage, if the FB pin voltage drops below (1.2 V − 100 mV = 1.1 V), the PGOOD pin toggles. REMOTE SYSTEM RESET For a remote (secondary side) system shutdown, an open-drain general-purpose input/output (GPIO) of an external microcontroller can be used to force the SS2 pin to 0 V. This pull-down causes the ADP1074 to regulate to 0 V, and the ADP1074 enters pulse skip mode or outputs a minimum duty cycle because the SS2 pin offsets because of the finite resistance of the GPIO. When VDD2 is charged from the output bus, this setup is equivalent to a system shutdown, because when VDD2 < VDD2 UVLO, the ADP1074 enters a special hiccup mode of 200 ms (instead of the standard 40 ms hiccup). When VDD2 is powered using auxiliary winding, the system regulates to the voltage proportional to the voltage on the SS2 pin and eventually enters the special hiccup mode previously mentioned, after the auxiliary rail decays below the VDD2 UVLO threshold. Therefore, the SS2 pin can achieve output tracking as well as a secondary side shutdown, also known as remote system reset, as shown in Figure 20. Rev. D | Page 24 of 32 Data Sheet ADP1074 VDD2 DEPENDS ON VDD2 CAPACITOR AND I DD2 CONSUMPTION VDD2 UVLO (3.5V) SS2 (1.4V) VFB (1.2V) DEPENDS ON SYSTEM BANDWIDTH SS2 CAPACITOR SS1 CAPACITOR TIME HANDOVER TIME FROM PRIMARY TO SECONDARY PWM SWITCHING Figure 20. Remote Software Reset with 200 ms Hiccup Rev. D | Page 25 of 32 15627-016 200ms HICCUP COUNTER ADP1074 Data Sheet The values shown in Table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition. In many cases, the approved working voltage is higher than the 50 year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. VDD2 VDD2_UVLO 3.5V SS2 = 1.4V The ADP1074 insulation lifetime depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 22, Figure 23, and Figure 24 show these different isolation voltage waveforms. Figure 21. Tracking with SS2 Pin OCP COUNTER During overload conditions, when the peak sensed currents exceed the OCP threshold voltage of 120 mV on the CS pin, the ADP1074 immediately terminates the remainder of the PWM pulse. If the peak sense current continues to exceed the threshold every switching period for 1.5 ms, the system enters hiccup mode, by which it shuts down for approximately 40 ms and then soft starts. During an exceeded overcurrent situation, such as a dead short, it is likely that the programmed slope compensation is not enough, and therefore, the system enters subharmonic oscillation. If this is the case, the system cannot enter hiccup mode because the OCP threshold is crossed every alternate switching period, and the 1.5 ms hiccup counter resets. A bipolar ac voltage environment is the worst case for the iCoupler products, yet meets the 50 year operating lifetime recommended by Analog Devices for maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. The low stress allows operation at higher working voltages while still achieving a 50 year service life. Treat any cross insulation voltage waveform that does not conform to Figure 23 or Figure 24 as a bipolar ac waveform, and limit its peak voltage to the 50 year lifetime voltage value listed in Table 10. Note that the voltage presented in Figure 23 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. To prevent this scenario, the ADP1074 latches the last known state, whereby if an OCP condition registered as a 1 in one switching period and as a 0 in the next switching period, it is still counted as a 1. In this manner, the system can enter hiccup mode even in subharmonic oscillation. Missing two OCP thresholds consecutively resets the hiccup counter. INSULATION LIFETIME RATED PEAK VOLTAGE 15627-018 TIME 15627-017 DEPENDS ON LOOP BANDWIDTH 0V Figure 22. Bipolar AC Waveform RATED PEAK VOLTAGE 15627-019 DEPENDS ON LOOP BANDWIDTH 0V Figure 23. Unipolar AC Waveform All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent upon the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADP1074. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. Rev. D | Page 26 of 32 RATED PEAK VOLTAGE 15627-020 VFB 1.2V 0V Figure 24. DC Waveform Data Sheet ADP1074 LAYOUT GUIDELINES The layout guidelines for the secondary side are as follows: The layout guidelines for the primary side are as follows: 1. 1. 2. 3. 4. 5. 6. Ground all the capacitors to their respective grounds. For example, ground the SS1 capacitor to AGND1. Use the CS pin and the AGND1 pin to differentially sense the primary current measurement through the sense resistor. Do not cross the CS and AGND1 traces for current sensing across any switch nodes. Place a capacitor (33 pF to 470 pF typical) close to the CS pin, connected to AGND1. Connect the ground plane on the primary side to PGND1. Connect AGND1 to PGND1 using a 0 Ω resistor. Place resistors (1 Ω to 5 Ω typical) in series with NGATE and the main power MOSFET. These resistors aid in eliminating any ringing on the drive voltages. 2. 3. 4. 5. Rev. D | Page 27 of 32 Ground all the capacitors to their respective grounds. For example, ground the SS2 capacitor to AGND2. Place resistors (1 Ω to 5 Ω) in series with SRx and the synchronous MOSFET. These resistors aid in eliminating any ringing on the drive voltages. Connect the ground plane on the secondary side to PGND2. Connect the negative terminal of the output voltage to the PGND2 plane. Use the FB pin and the AGND2 pin to remotely differentially sense the output voltage by connecting AGND2 to the negative terminal of the output voltage using a 0 Ω resistor. Use a 100 nF capacitor on the MODE pin if light load mode is used in noisy environments. ADP1074 Data Sheet TYPICAL APPLICATION CIRCUITS VIN VOUT SR2 ACTIVE CLAMP NMOS PMOS SR1 RRAMP RSENSE VIN CS EN SR1 ADP1074 VREG1 VREG2 COMP PGATE FB SYNC OVP SS1 SS2 PGOOD RT RTOP MODE PGND1 PGND2 AGND1 AGND2 RBOT 15627-021 RDT VDD2 NGATE DMAX CSS1 SR2 Figure 25. Typical Application Circuit for Active Clamp Forward Topology Rev. D | Page 28 of 32 Data Sheet ADP1074 TO VREG1 VIN VBIAS = 8V TO 13V VOUT SR2 ACTIVE CLAMP NMOS PMOS SR1 RRAMP RSENSE VIN CS R1 14kΩ 114mW AT 48V EN ZENER C1 10µF SR1 ADP1074 CSS1 RDT VREG2 NGATE COMP PGATE FB SYNC OVP SS1 SS2 RT RTOP VDD2 VREG1 DMAX EXTERNAL START-UP CIRCUIT SR2 PGOOD MODE PGND1 PGND2 AGND1 AGND2 15627-022 RBOT Figure 26. Typical Application Circuit for Active Clamp Forward Topology with Simple Start-Up Circuit and Bias Winding Rev. D | Page 29 of 32 ADP1074 Data Sheet OPTIONAL POST FILTER VIN VOUT ACTIVE CLAMP NMOS PMOS SR2 RRAMP RSENSE VIN CS EN SR1 ADP1074 VREG2 NGATE COMP PGATE FB SYNC OVP SS1 SS2 PGOOD RT RTOP MODE PGND1 PGND2 AGND1 AGND2 RBOT 15627-023 RDT VDD2 VREG1 DMAX CSS1 SR2 Figure 27. Typical Application Circuit for Active Clamp Flyback Topology Rev. D | Page 30 of 32 Data Sheet ADP1074 OUTLINE DIMENSIONS 15.60 (0.6142) 15.20 (0.5984) 13 24 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 12 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) BSC SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) 12-09-2010-A COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 28. 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) PIN 1 INDICATOR 8.10 8.00 7.90 6.50 BSC 2.25 BSC 0.50 BSC PIN 1 CORNER INDICATOR 22 4.10 4.00 3.90 1.775 BSC 0.25 0.20 0.15 1 24 4 2.50 BSC 0.25 BSC 0.75 REF SIDE VIEW SEATING PLANE 10 BOTTOM VIEW 1.15 2.825 BSC 3.78 BSC 0.28 REF PKG-005313 COPLANARITY 0.08 0.35 0.30 0.25 04-20-2017-B 1.20 MAX 2.80 9 16 15 TOP VIEW 3 21 Figure 29. 24-Terminal Land Grid Array [LGA] (CC-24-6) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP1074WARWZ ADP1074WARWZ-RL ADP1074WARWZ-R7 ADP1074ARWZ ADP1074ARWZ-RL ADP1074ARWZ-R7 ADP1074-EVALZ ADP1074ACCZ ADP1074ACCZ-RL ADP1074ACCZ-R7 ADP1074LGA-EVALZ 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 24-Lead Standard Small Outline Package [SOIC_W] 24-Lead Standard Small Outline Package [SOIC_W] 24-Lead Standard Small Outline Package [SOIC_W] 24-Lead Standard Small Outline Package [SOIC_W] 24-Lead Standard Small Outline Package [SOIC_W] 24-Lead Standard Small Outline Package [SOIC_W] ADP1074 Evaluation Board with Wide Body IC 24-Terminal Land Grid Array [LGA] 24-Terminal Land Grid Array [LGA] 24-Terminal Land Grid Array [LGA] ADP1074 Evaluation Board with LGA IC Z = RoHS-Compliant Part. Rev. D | Page 31 of 32 Package Option RW-24 RW-24 RW-24 RW-24 RW-24 RW-24 CC-24-6 CC-24-6 CC-24-6 ADP1074 Data Sheet NOTES ©2017–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15627-6/20(D) Rev. D | Page 32 of 32