ADP125

5.5 V Input, 500 mA, Low Quiescent Current, CMOS Linear Regulators ADP124/ADP125 FEATURES Input voltage supply range: 2.3 V to 5.5 V 500 mA maximum output current Fixed and adjustable output voltage versions 1% initial accuracy Up to 31 fixed-output voltage options available from 1.75 V to 3.3 V Adjustable-output voltage range from 0.8 V to 5.0 V Very low dropout voltage: 130 mV Low quiescent current: 45 μA Low shutdown current: 2.3 V IOUT = 10 mA, TJ = −40°C to +125°C IOUT = 250 mA, VOUT > 2.3 V IOUT = 250 mA, TJ = −40°C to +125°C IOUT = 500 mA, VOUT > 2.3V IOUT = 500 mA, TJ = −40°C to +125°C VOUT = 3.0 V 550 TJ rising −1 −2 Min 2.3 Typ 45 105 60 120 160 210 210 280 0.1 1 +1 +1.5 Max 5.5 Unit V μA μA μA μA μA μA μA μA μA μA % % SHUTDOWN CURRENT OUTPUT VOLTAGE ACCURACY 2 Fixed Output ISD VOUT Adjustable Output 0.495 0.485 −0.05 0.0005 0.001 15 3 5 65 120 130 230 350 750 150 15 1.2 0.4 0.1 1 2.1 1.5 125 1000 0.500 0.500 0.505 0.515 +0.05 V V %/V %/mA %/mA nA mV mV mV mV mV mV μs mA °C °C V V μA μA V V mV LINE REGULATION LOAD REGULATION 3 ADJ INPUT BIAS CURRENT DROPOUT VOLTAGE 4 ∆VOUT/∆VIN ∆VOUT/∆IOUT ADJI-BIAS VDROPOUT START-UP TIME 5 CURRENT LIMIT THRESHOLD 6 THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis EN INPUT EN Input Logic High EN Input Logic Low EN Input Leakage Current UNDERVOLTAGE LOCKOUT Input Voltage Rising Input Voltage Falling Hysteresis tSTART-UP ILIMIT TSSD TSSD-HYS VIH VIL VI-LEAKAGE UVLO UVLORISE UVLOFALL UVLOHYS 2.3 V ≤ VIN ≤ 5.5 V 2.3 V ≤ VIN ≤ 5.5 V EN = VIN or GND EN = VIN or GND, TJ = −40°C to +125°C TJ = −40°C to +125°C TJ = −40°C to +125°C TA = 25°C Rev. 0 | Page 3 of 20 ADP124/ADP125 Parameter OUTPUT NOISE Symbol OUTNOISE Test Conditions 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.2 V 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 2.5 V 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 3.3 V 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 4.2V 10 kHz to 100 kHz, VOUT = 1.8 V, 2.5 V, 3.3 V Min Typ 25 35 45 55 65 60 Max Unit μV rms μV rms μV rms μV rms μV rms dB POWER SUPPLY REJECTION RATIO (VIN = VOUT +1V) 1 2 PSRR The current from the external resistor divider network in the case of adjustable voltage output (as with the ADP125) should be subtracted from the ground current measured. Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of the resistors used. 3 Based on an endpoint calculation using 1 mA and 500 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages greater than 2.3V. 5 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value. 6 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.3 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.3V, or 2.97 V. RECOMMENDED CAPACITOR SPECIFICATIONS Table 2. Parameter Minimum Input and Output Capacitance 1 Capacitor ESR 1 Symbol CAPMIN RESR Test Conditions TA = −40°C to +125°C TA = −40°C to +125°C Min 0.70 0.001 Typ Max Unit μF Ω 1 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with this LDO. Rev. 0 | Page 4 of 20 ADP124/ADP125 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN to GND ADJ to GND EN to GND VOUT to GND Storage Temperature Range Operating Ambient Temperature Range Operating Junction Temperature Range Soldering Conditions Rating −0.3 V to +6.5V −0.3 V to +4 V −0.3 V to +6.5V −0.3 V to VIN −65°C to +150°C −40°C to +85°C −40°C to +125°C JEDEC J-STD-020 application and board layout. In applications in which high maximum power dissipation exists, close attention to thermal board design is required. The value of θJA may vary, depending on PCB material, layout, and environmental conditions. The specified values of θJA are based on a 4-layer, 4 inch × 3 inch circuit board. Refer to JESD 51-7 for detailed information on the board construction ΨJB is the junction-to-board thermal characterization parameter and is measured in °C/W. The ΨJB of the package is based on modeling and calculation using a 4-layer board. The Guidelines for Reporting and Using Package Thermal Information: JESD51-12 states that thermal characterization parameters are not the same as thermal resistances. ΨJB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, θJB. Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package—factors that make ΨJB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD × ΨJB) Refer to JESD51-8 and JESD51-12 for more detailed information about ΨJB. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP124/ADP125 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ will remain within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be limited. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (θJA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula TJ = TA + (PD × θJA) The junction-to-ambient thermal resistance (θJA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the THERMAL RESISTANCE θJA and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 8-Lead MSOP θJA 102.8 ΨJB 31.8 Unit °C/W ESD CAUTION Rev. 0 | Page 5 of 20 ADP124/ADP125 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUT 1 VOUT 2 VOUT SENSE 3 GND 4 8 ADP124 TOP VIEW (Not to Scale) VIN VIN NC 08476-003 VOUT 1 VOUT 2 ADJ 3 GND 4 8 7 6 5 ADP125 TOP VIEW (Not to Scale) VIN VIN NC 08476-004 7 6 5 EN EN NC = NO CONNECT NC = NO CONNECT Figure 3. ADP124 Fixed Output Pin Configuration Figure 4. ADP125 Adjustable Output Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 Mnemonic ADP124 ADP125 VOUT VOUT VOUT VOUT VOUT SENSE N/A N/A ADJ GND EN NC VIN VIN EP GND EN NC VIN VIN EP Description Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor. Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor. Feedback Node for the Error Amplifier. Connect to VOUT. Feedback Node for the Error Amplifier. Connect the midpoint of an external divider from VOUT to GND to this pin to set the output voltage. Ground. Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. No Connect. This pin is not connected internally. Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor. Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor. The exposed pad must be connected to ground. 4 5 6 7 8 Rev. 0 | Page 6 of 20 ADP124/ADP125 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.8 V, VOUT = 3.3V, IOUT = 10 mA, CIN = 1.0 μF, COUT = 1.0 μF, TA = 25°C, unless otherwise noted. 3.310 3.305 250 3.300 3.295 IOUT = 500mA 200 IOUT = 300mA 150 IOUT = 100mA 100 IOUT = 10mA 50 IOUT = 1mA IOUT = 100µA 300 3.290 3.285 3.280 3.275 3.270 IOUT = 100µA IOUT = 1mA IOUT = 10mA IOUT = 100mA IOUT = 300mA IOUT = 500mA GROUND CURRENT (µA) VOUT (V) 08476-005 –40 –5 +25 +85 JUNCTION TEMPERATURE (°C) +125 –40 –5 +25 +85 JUNCTION TEMPERATURE (°C) +125 Figure 5. Output Voltage vs. Junction Temperature Figure 8. Ground Current vs. Junction Temperature 3.309 250 3.308 GROUND CURRENT (µA) 200 3.307 VOUT (V) 150 3.306 100 3.305 3.304 50 08476-006 1 10 IOUT (mA) 100 1000 1 10 ILOAD (mA) 100 1000 Figure 6. Output Voltage vs. Load Current Figure 9. Ground Current vs. Load Current 3.310 3.308 3.306 GROUND CURRENT (µA) 250 230 210 190 170 150 130 110 90 70 08476-007 IOUT = 500mA 3.304 VOUT (V) IOUT = 300mA 3.302 3.300 3.298 3.296 3.294 3.292 3.50 IOUT = 100µA IOUT = 1mA IOUT = 10mA IOUT = 100mA IOUT = 300mA IOUT = 500mA IOUT = 100mA IOUT = 10mA IOUT = 1mA IOUT = 100µA VIN (V) VIN (V) Figure 7. Output Voltage vs. Input Voltage Figure 10. Ground Current vs. Input Voltage Rev. 0 | Page 7 of 20 08476-010 4.00 4.50 5.00 5.50 50 3.50 4.00 4.50 5.00 5.50 08476-009 3.303 0.1 0 0.1 08476-008 ADP124/ADP125 0.7 0.6 SHUTDOWN CURRENT (µA) 3.35 3.30 3.25 3.20 VOUT (V) 0.5 0.4 0.3 0.2 VIN = 5.50 VIN = 5.40 VIN = 5.20 VIN = 5.00 VIN = 4.40 VIN = 4.20 VIN = 3.80 IOUT = 10mA IOUT = 100mA IOUT = 300mA IOUT = 500mA 3.15 3.10 3.05 0.1 0 –50 3.00 2.95 3.00 VIN (V) Figure 11. Shutdown Current vs. Temperature at Various Input Voltages Figure 14. Output Voltage vs. Input Voltage (in Dropout) 120 –10 –20 –30 IOUT = 100µA IOUT = 1mA IOUT = 10mA IOUT = 100mA IOUT = 300mA IOUT = 500mA 100 DROPOUT (mV) 80 –40 PSRR (dB) 60 –50 –60 –70 –80 –90 40 20 0 1 10 IOUT (mA) 100 1000 08476-012 VIN = VOUT +1V VRIPPLE = 50mV CIN = COUT = 1µF 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 08476-015 08476-016 –100 10 Figure 12. Dropout Voltage vs. Load Current Figure 15. Power Supply Rejection Ratio vs. Frequency, VOUT = 2.8 V, VIN = 3.8 V 450 400 350 300 250 200 150 100 50 0 3.00 PSRR (dB) –10 –20 –30 –40 IOUT = 100µA IOUT = 1mA IOUT = 10mA IOUT = 100mA IOUT = 300mA IOUT = 500mA IOUT IOUT IOUT IOUT = 10mA = 100mA = 300mA = 500mA IGND (µA) –50 –60 –70 –80 –90 –100 10 VIN = VOUT +1V VRIPPLE = 50mV CIN = COUT = 1µF 100 1k 10k 100k FREQUENCY (Hz) 1M 10M VIN (V) Figure 13. Ground Current vs. Input Voltage (in Dropout) 08476-013 3.10 3.20 3.30 3.40 3.50 3.60 3.70 Figure 16. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 4.3 V Rev. 0 | Page 8 of 20 08476-014 –25 0 25 50 75 TEMPERATURE (°C) 100 125 08476-011 3.10 3.20 3.30 3.40 3.50 3.60 ADP124/ADP125 –10 –20 –30 –40 PSRR (dB) 5 NOISE (µv/ √Hz) –50 –60 –70 –80 IOUT = 100µA IOUT = 1mA IOUT = 10mA IOUT = 100mA IOUT = 300mA IOUT = 500mA VOUT = 4.2V 4 VOUT = 3.3V 3 2 08476-017 –90 –100 10 0 10 100 1k FREQUENCY (Hz) 10k 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100k Figure 17. Power Supply Rejection Ratio vs. Frequency, VOUT = 4.2 V, VIN = 5.2 V Figure 20. Output Noise Spectrum, VIN = 5 V –10 –20 –30 –40 PSRR (dB) 70 RMS NOISE (µV) VOUT = 2.8V, VOUT = 3.3V, VOUT = 4.2V, VOUT = 2.8V, VOUT = 3.3V, VOUT = 4.2V, IOUT = 10mA IOUT = 10mA IOUT = 10mA IOUT = 500mA IOUT = 500mA IOUT = 500mA 65 60 55 50 45 40 35 VOUT = 4.2V VOUT = 3.3V –50 –60 –70 –80 08476-018 VOUT = 2.8V 25 20 0.001 0.01 0.1 1 ILOAD (mA) 10 100 1k –100 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 18. Power Supply Rejection Ratio vs. Frequency, Various Output Voltages and Load Currents Figure 21. Output Noise vs. Load Current and Output Voltage, VIN = 5 V –10 –20 –30 –40 PSRR (dB) VIN = 3.1V, VIN = 3.3V, VIN = 3.8V, VIN = 4.8V, IOUT = 10mA IOUT = 10mA IOUT = 10mA IOUT = 10mA IOUT 1mA TO 500mA LOAD STEP 1 –50 –60 2 VOUT –70 –80 –90 –100 10 100 1k 10k 100k 1M FREQUENCY (Hz) VIN = 3.1V, VIN = 3.3V, VIN = 3.8V, VIN = 4.8V, IOUT = 500mA IOUT = 500mA IOUT = 500mA IOUT = 500mA 08476-019 10M CH1 500mA Ω BW CH2 50.0mV B W M40.0µs A CH1 T 9.800% 200mA Figure 19. Power Supply Rejection Ratio vs. Headroom Voltage (VIN − VOUT), VOUT = 2.8 V Figure 22. Load Transient Response, COUT = 1 μF Rev. 0 | Page 9 of 20 08476-022 VIN = 4V VOUT = 3.3V 08476-021 –90 VIN = VOUT + 1V VRIPPLE = 50mV CIN = COUT = 1µF 30 08476-020 VIN = VOUT + 1V VRIPPLE = 50mV CIN = COUT = 1µF 1 VOUT = 2.8V ADP124/ADP125 IOUT 1mA TO 500mA LOAD STEP 1 VIN 4V TO 4.5V VOLTAGE STEP 2 2 VOUT VOUT VIN = 4V VOUT = 3.3V CH1 500mA Ω BW CH2 50.0mV B W 1 08476-023 M40.0µs A CH1 T 9.800% 200mA CH1 1.00V BW CH2 2.00mV B W M10.0µs A CH3 T 9.800% 200mA Figure 23. Load Transient Response, COUT = 4.7 μF Figure 25. Line Transient Response, Load Current = 500 mA VIN 4V TO 4.5V VOLTAGE STEP 2 VOUT 1 CH1 1.00V BW CH2 2.00mV B W M10.0µs A CH3 T 9.600% 2.36V Figure 24. Line Transient Response, Load Current = 1 mA 08476-024 Rev. 0 | Page 10 of 20 08476-025 ADP124/ADP125 THEORY OF OPERATION The ADP124/ADP125 are low quiescent current, low dropout linear regulators that operate from 2.3 V to 5.5 V and can provide up to 500 mA of output current. Drawing a low 210 μA of quiescent current (typical) at full load makes the ADP124/ADP125 ideal for battery-operated portable equipment. Shutdown current consumption is typically 100 nA. Optimized for use with small 1 μF ceramic capacitors, the ADP124/ADP125 provide excellent transient performance. Internally, the ADP124/ADP125 consist of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. The adjustable ADP125 has an output voltage range of 0.8 V to 5.0 V. The output voltage is set by the ratio of two external resistors, as shown in Figure 2. The device servos the output to maintain the voltage at the ADJ pin at 0.5 V referenced to ground. The current in R1 is then equal to 0.5 V/R2 and the current in R1 is the current in R2 plus the ADJ pin bias current. The ADJ pin bias current, 15 nA at 25°C, flows through R1 into the ADJ pin. The output voltage can be calculated using the equation: VOUT = 0.5 V(1 + R1/R2) + (ADJI-BIAS)(R1) The value of R1 should be less than 200 kΩ to minimize errors in the output voltage caused by the ADJ pin bias current. For example, when R1 and R2 each equal 200 kΩ, the output voltage is 1.0 V. The output voltage error introduced by the ADJ pin bias current is 3 mV or 0.3%, assuming a typical ADJ pin bias current of 15 nA at 25°C. Note that in shutdown, the output is turned off and the divider current is 0. EN SHUTDOWN 0.5V REFERENCE 08476-122 The ADP124/ADP125 use the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on; when EN is low, VOUT turns off. For automatic startup, EN can be tied to VIN. ADP124 VIN VOUT VOUT SENSE SHORT CIRCUIT, UVLO, AND THERMAL PROTECT R1 GND EN SHUTDOWN 0.5V REFERENCE R2 NOTES 1. R1 AND R2 ARE INTERNAL RESISTORS, AVAILABLE ON THE ADP124 ONLY. Figure 26. ADP124 Internal Block Diagram (Fixed Output) ADP125 VIN VOUT GND SHORT CIRCUIT, UVLO, AND THERMAL PROTECT ADJ Figure 27. ADP125 Internal Block Diagram (Adjustable Output) Rev. 0 | Page 11 of 20 08476-121 ADP124/ADP125 APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor The ADP124/ADP125 are designed for operation with small, space-saving ceramic capacitors, but these devices can function with most commonly used capacitors as long as care is taken to ensure an appropriate effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 0.70 μF capacitance with an ESR of 1 Ω or less is recommended to ensure stability of the ADP124/ADP125. The transient response to changes in load current is also affected by the output capacitance. Using a larger value of output capacitance improves the transient response of the ADP124/ADP125 to dynamic changes in load current. Figure 28 and Figure 29 show the transient responses for output capacitance values of 1 μF and 4.7μF, respectively. IOUT 1mA TO 500mA LOAD STEP 1 Input Bypass Capacitor Connecting a 1 μF capacitor from VIN to GND reduces the circuit sensitivity to the printed circuit board (PCB) layout, especially when a long input trace or high source impedance is encountered. If greater than 1 μF of output capacitance is required, the input capacitor should be increased to match it. Input and Output Capacitor Properties Any good quality ceramic capacitors can be used with the ADP124/ADP125, as long as the capacitor meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. Using an X5R or X7R dielectric with a voltage rating of 6.3 V or 10 V is recommended. However, using Y5V and Z5U dielectrics are not recommended for any LDO, due to their poor temperature and dc bias characteristics. Figure 30 depicts the capacitance vs. capacitor voltage bias characteristics of an 0402, 1 μF, 10 V X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and the voltage rating. In general, a capacitor in a larger package or of a higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating. 1.10 1.05 1.00 2 VOUT VIN = 4V VOUT = 3.3V CH1 500mA Ω BW CH2 50.0mV B W M400ns A CH1 T 13.20% 200mA Figure 28. Output Transient Response, COUT = 1 μF CAPACITANCE (µF) 0.95 0.90 0.85 0.80 08476-030 IOUT 1mA TO 500mA LOAD STEP 1 08476-028 0.75 2 VOUT VIN = 4V VOUT = 3.3V CH1 500mA Ω BW CH2 50.0mV B W 0.70 0 1 2 3 4 BIAS VOLTAGE (V) 5 6 7 08476-029 Figure 30. Capacitance vs. Capacitor Voltage Bias Characteristics M400ns A CH1 T 13.60% 200mA Figure 29. Output Transient Response, COUT = 4.7 μF Equation 1 can be used to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = C × (1 − TEMPCO) × (1 − TOL) where: CEFF is the effective capacitance at the operating voltage. C is the rated capacitance value. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. Rev. 0 | Page 12 of 20 (1) ADP124/ADP125 In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and C is 0.94 μF at 4.2 V from the graph in Figure 30. Substituting these values in Equation 1 yields CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF ENABLE (EN) TRESHOLDS (V) The active and inactive thresholds of the EN pin are derived from the VIN voltage. Therefore, these thresholds vary as the input voltage changes. Figure 32 shows typical EN active and inactive thresholds when the VIN voltage varies from 2.3 V to 5.5 V. 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 08476-032 Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP124/ADP125, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application. RISING FALLING UNDERVOLTAGE LOCKOUT The ADP124/ADP125 have an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately 2 V. This ensures that the ADP124/ADP125 inputs and the output behave in a predictable manner during power-up. 0.65 0.60 2.2 2.7 3.2 3.7 VIN (V) 4.2 4.7 5.2 Figure 32. Typical EN Pin Thresholds vs. Input Voltage ENABLE FEATURE The ADP124/ADP125 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 31, when a rising voltage on EN crosses the active threshold, VOUT turns on. Conversely, when a falling voltage on EN crosses the inactive threshold, VOUT turns off. 3.5 The ADP124/ADP125 use an internal soft start to limit the inrush current when the output is enabled. The start-up time for the 2.8 V option is approximately 350 μs from the time the EN active threshold is crossed to when the output reaches 90% of its final value. As shown in Figure 33, the start-up time is dependent on the output voltage setting and increases slightly as the output voltage increases. VIN = 5V 3.0 2.5 2.0 1.5 1.0 0.5 0 VOUT = 4.2V VOUT = 3.3V VOUT VOUT = 2.8V 1 2 08476-230 0 0.2 0.4 0.6 0.8 VEN 1.0 1.2 1.4 1.6 CH1 1.00V CH2 1.00V B W M100µs A CH1 T 296.800µs 2.00V Figure 31. Typical EN Pin Operation Figure 33. Typical Start-Up Time As shown in Figure 31, the EN pin has built-in hysteresis. This prevents on/off oscillations that may occur due to noise on the EN pin as it passes through the threshold points. Rev. 0 | Page 13 of 20 08476-033 ADP124/ADP125 CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION The ADP124/ADP125 are protected from damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP124/ADP125 are designed to limit the current when the output load reaches 750 mA (typical). When the output load exceeds 750 mA, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is included, which limits the junction temperature to a maximum of 150°C typical. Under extreme conditions (that is, high ambient temperature and power dissipation), when the junction temperature starts to rise above 150°C, the output is turned off, reducing output current to zero. When the junction temperature cools to less than 135°C, the output is turned on again and the output current is restored to its nominal value. Consider the case where a hard short from VOUT to GND occurs. At first, the ADP124/ADP125 limit the current so that only 750 mA is conducted into the short. If self-heating causes the junction temperature to rise above 150°C, thermal shutdown activates, turning off the output and reducing the output current to zero. When the junction temperature cools to less than 135°C, the output turns on and conducts 750 mA into the short, again causing the junction temperature to rise above 150°C. This thermal oscillation between 135°C and 150°C results in a current oscillation between 750 mA and 0 mA that continues as long as the short remains at the output. Current and thermal limit protections are intended to protect the device from damage due to accidental overload conditions. For reliable operation, the device power dissipation must be externally limited so that the junction temperature does not exceed 125°C. The junction temperature of the ADP124/ADP125 can be calculated from the following equation: TJ = TA + (PD × θJA) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND) where: ILOAD is the load current. IGND is the ground current. VIN and VOUT are input and output voltages, respectively. The power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation can be simplified as follows: TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA} (4) As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 125°C. Figure 34 through Figure 40 show junction temperature calculations for different ambient temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper. In cases where the board temperature is known, the thermal characterization parameter, ΨJB, can be used to estimate the junction temperature rise. The maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD × ΨJB) (5) (3) (2) THERMAL CONSIDERATIONS To guarantee reliable operation, the junction temperature of the ADP124/ADP125 must not exceed 125°C. To ensure that the junction temperature is less than this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (θJA). The value of θJA is dependent on the package assembly compounds used and the amount of copper to which the GND pins of the package are soldered on the PCB. Table 6 shows typical θJA values of the 8-lead MSOP package for various PCB copper sizes. Table 6. Typical θJA Values for Specified PCB Copper Sizes Copper Size (mm2) 40 100 500 1000 6400 θJA (°C/W) 102.8 75.5 42.5 34.7 26.1 The typical ΨJB value is 31.7°C/W. Rev. 0 | Page 14 of 20 ADP124/ADP125 JUNCTION TEMPERATURE CALCULATIONS 140 TJ MAX 120 JUNCTION TEMPERATURE (°C) JUCTION TEMPERATURE (°C) 140 TJ MAX 120 ILOAD = 500mA ILOAD = 400mA 100 80 60 40 20 0 0.5 ILOAD = 50mA ILOAD = 100mA ILOAD = 75mA ILOAD = 150mA 100 80 60 40 20 ILOAD = 10mA 0 0.5 1.0 1.5 2.0 ILOAD = 100mA 2.5 3.0 ILOAD = 300mA ILOAD = 200mA ILOAD = 10mA ILOAD = 25mA ILOAD = 1mA 08476-037 ILOAD = 1mA 3.5 4.0 4.5 08476-034 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN – VOUT (V) VIN – VOUT (V) Figure 34. Junction Temperature vs. Power Dissipation, 1000 mm2 of PCB Copper, TA = 25°C 140 TJ MAX 120 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 37. Junction Temperature vs. Power Dissipation, 1000 mm2 of PCB Copper, TA = 50°C 140 TJ MAX 120 100 80 60 40 20 0 0.5 ILOAD = 200mA ILOAD = 500mA ILOAD = 400mA ILOAD = 300mA ILOAD = 500mA ILOAD = 400mA ILOAD = 300mA 100 80 ILOAD = 200mA 60 40 ILOAD = 10mA ILOAD = 100mA ILOAD = 1mA 08476-038 ILOAD = 10mA ILOAD = 100mA 1.0 1.5 2.0 2.5 3.0 ILOAD = 1mA 3.5 4.0 08476-035 20 0 0.5 4.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN – VOUT (V) VIN – VOUT (V) Figure 35. Junction Temperature vs. Power Dissipation, 500 mm2 of PCB Copper, TA = 25°C 140 TJ MAX 120 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 38. Junction Temperature vs. Power Dissipation, 500 mm2 of PCB Copper, TA = 50°C 140 TJ MAX 120 100 80 60 40 20 0 0.5 ILOAD = 500mA ILOAD = 200mA ILOAD = 300mA ILOAD = 500mA ILOAD = 400mA ILOAD = 300mA 100 80 60 40 20 ILOAD = 200mA ILOAD = 100mA ILOAD = 10mA ILOAD = 1mA ILOAD = 400mA 08476-039 ILOAD = 100mA ILOAD = 10mA 08476-036 ILOAD = 1mA 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN – VOUT (V) VIN – VOUT (V) Figure 36. Junction Temperature vs. Power Dissipation, 40 mm2 of PCB Copper, TA = 25°C Figure 39. Junction Temperature vs. Power Dissipation, 40 mm2 of PCB Copper, TA = 50°C Rev. 0 | Page 15 of 20 ADP124/ADP125 140 TJ MAX 120 JUNCTION TEMPERATURE (°C) ILOAD = 500mA ILOAD = 400mA ILOAD = 300mA 100 80 ILOAD = 200mA 60 40 20 0 0.5 ILOAD = 100mA ILOAD = 1mA ILOAD = 10mA 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN – VOUT (V) Figure 40. Junction Temperature vs. Power Dissipation, 40 mm2 of PCB Copper at Board Temperature = 85°C Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP124/ADP125. However, as shown in Table 6, a point of diminishing returns eventually is reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. The input capacitor should be placed as close as possible to the VIN and GND pins, and the output capacitor should be placed as close as possible to the VOUT and GND pins. Use of 0402 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where the area is limited. Figure 41. Example ADP124 PCB Layout Figure 42. Example ADP125 PCB Layout Rev. 0 | Page 16 of 20 08476-042 08476-041 PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS 08476-040 ADP124/ADP125 OUTLINE DIMENSIONS 3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 INDICATOR 0.65 BSC 0.94 0.86 0.78 0.15 0.10 0.05 COPLANARITY 0.10 0.40 0.33 0.25 8 5 2.26 2.16 2.06 5.05 4.90 4.75 1.83 1.73 1.63 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. TOP VIEW 1 4 EXPOSED PAD 0.525 BSC 1.10 MAX BOTTOM VIEW 0.23 0.18 0.13 8° 0° SEATING PLANE 0.70 0.55 0.40 071008-A COMPLIANT TO JEDEC STANDARDS MO-187-AA-T Figure 43. 8-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] (RH-8-1) Dimensions shown in millimeters ORDERING GUIDE Model ADP124ARHZ-1.8-R7 2 ADP124ARHZ-2.5-R72 ADP124ARHZ-2.7-R72 ADP124ARHZ-2.8-R72 ADP124ARHZ-2.85-R72 ADP124ARHZ-2.9-R72 ADP124ARHZ-3.0-R72 ADP124ARHZ-3.3-R72 ADP125ARHZ-R72 ADP124-3.3-EVALZ2 ADP125-EVALZ2 1 Temperature Range (TJ) –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Output Voltage (V) 1 1.8 2.5 2.7 2.8 2.85 2.9 3.0 3.3 0.8 to 5.0 (Adjustable) 3.3 Adjustable Package Description 8-Lead MINI_SO_EP 8-Lead MINI_SO_EP 8-Lead MINI_SO_EP 8-Lead MINI_SO_EP 8-Lead MINI_SO_EP 8-Lead MINI_SO_EP 8-Lead MINI_SO_EP 8-Lead MINI_SO_EP 8-Lead MINI_SO_EP Evaluation Board Evaluation Board Package Option RH-8-1 RH-8-1 RH-8-1 RH-8-1 RH-8-1 RH-8-1 RH-8-1 RH-8-1 RH-8-1 Branding 37 3T 3U 3Z 40 41 49 4F 38 2 Up to 31 fixed-output voltage options from 1.75 V to 3.3 V are available. For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative. Z = RoHS Compliant Part. Rev. 0 | Page 17 of 20 ADP124/ADP125 NOTES Rev. 0 | Page 18 of 20 ADP124/ADP125 NOTES Rev. 0 | Page 19 of 20 ADP124/ADP125 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08476-0-12/09(0) Rev. 0 | Page 20 of 20