FEATURES
TYPICAL APPLICATION CIRCUITS
APPLICATIONS
1
VOUT = 3.3V
VOUT
VIN
8
VIN = 5.5V
C1
ADP124
C2
2
VOUT
VIN
7
3
VOUT
SENSE
NC
6
4
GND
EN
5
ON
08476-001
Input voltage supply range: 2.3 V to 5.5 V
500 mA maximum output current
Fixed and adjustable output voltage versions
1% initial accuracy
Up to 31 fixed-output voltage options available
from 1.75 V to 3.3 V
Adjustable-output voltage range from 0.8 V to 5.0 V
Very low dropout voltage: 130 mV
Low quiescent current: 45 µA
Low shutdown current: 2.3 V
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 250 mA, VOUT > 2.3 V
IOUT = 250 mA, TJ = −40°C to +125°C
IOUT = 500 mA, VOUT > 2.3V
IOUT = 500 mA, TJ = −40°C to +125°C
VOUT = 3.0 V
START-UP TIME5
CURRENT LIMIT THRESHOLD6
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TSSD
TSSD-HYS
TJ rising
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Leakage Current
VIH
VIL
VI-LEAKAGE
2.3 V ≤ VIN ≤ 5.5 V
2.3 V ≤ VIN ≤ 5.5 V
EN = VIN or GND
EN = VIN or GND, TJ = −40°C to +125°C
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
UVLO
UVLORISE
UVLOFALL
UVLOHYS
0.500
0.500
3
5
65
120
130
230
550
350
750
1000
°C
°C
150
15
TJ = −40°C to +125°C
TJ = −40°C to +125°C
TA = 25°C
Rev. D | Page 3 of 20
1.2
0.4
0.1
1
2.1
1.5
125
mV
mV
mV
mV
mV
mV
µs
mA
V
V
µA
µA
V
V
mV
ADP124/ADP125
Data Sheet
Parameter
OUTPUT NOISE
Symbol
OUTNOISE
POWER SUPPLY REJECTION RATIO
(VIN = VOUT +1V)
PSRR
Test Conditions
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.2 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 2.5 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 3.3 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 4.2V
10 kHz to 100 kHz, VOUT = 1.8 V, 2.5 V, 3.3 V
Min
Typ
25
35
45
55
65
60
Max
Unit
µV rms
µV rms
µV rms
µV rms
µV rms
dB
The current from the external resistor divider network in the case of adjustable voltage output (as with the ADP125) should be subtracted from the ground current measured.
Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of
the resistors used.
3
Based on an endpoint calculation using 1 mA and 500 mA loads.
4
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages
greater than 2.3 V.
5
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
6
Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.3 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.3 V, or 2.97 V.
1
2
RECOMMENDED CAPACITOR SPECIFICATIONS
Table 2.
Parameter
Minimum Input and Output
Capacitance1
Capacitor ESR
1
Symbol
CAPMIN
Test Conditions
TA = −40°C to +125°C
Min
0.70
RESR
TA = −40°C to +125°C
0.001
Typ
Max
Unit
µF
1
Ω
The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with this LDO.
Rev. D | Page 4 of 20
Data Sheet
ADP124/ADP125
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
ADJ to GND
EN to GND
VOUT to GND
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to VIN
−65°C to +150°C
−40°C to +85°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP124/ADP125 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ will remain within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be limited.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (TJ) of
the device is dependent on the ambient temperature (TA), the
power dissipation of the device (PD), and the junction-to-ambient
thermal resistance of the package (θJA).
application and board layout. In applications in which high maximum power dissipation exists, close attention to thermal board
design is required. The value of θJA may vary, depending on PCB
material, layout, and environmental conditions. The specified
values of θJA are based on a 4-layer, 4 inch × 3 inch circuit board.
Refer to JESD 51-7 for detailed information on the board
construction.
ΨJB is the junction-to-board thermal characterization parameter
and is measured in °C/W. The ΨJB of the package is based on
modeling and calculation using a 4-layer board. The Guidelines for
Reporting and Using Package Thermal Information: JESD51-12
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package—factors that make ΨJB more useful in real-world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD)
using the formula
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
8-Lead MSOP
8-Lead LFCSP
ESD CAUTION
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on the
Rev. D | Page 5 of 20
θJA
102.8
68.9
ΨJB
31.8
44.1
Unit
°C/W
°C/W
ADP124/ADP125
Data Sheet
VOUT 2
VOUT SENSE 3
ADP124
TOP VIEW
(Not to Scale)
GND 4
8
VIN
VOUT 1
7
VIN
VOUT 2
6
NC
ADJ 3
5
EN
08476-003
VOUT 1
ADP125
TOP VIEW
(Not to Scale)
GND 4
8
VIN
7
VIN
6
NC
5
EN
08476-004
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
Figure 3. ADP124 Fixed Output MSOP Pin Configuration
Figure 5. ADP125 Adjustable Output MSOP Pin Configuration
VOUT SENSE 3
ADP124
TOP VIEW
(Not to Scale)
8 VIN
VOUT 1
7 VIN
VOUT 2
6 NC
5 EN
GND 4
ADJ 3
GND 4
8 VIN
ADP125
7 VIN
TOP VIEW
(Not to Scale)
6 NC
5 EN
08476-106
VOUT 2
08476-105
VOUT 1
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
Figure 4. ADP124 Fixed Output LFCSP Pin Configuration
Figure 6. ADP125 Adjustable Output LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
ADP124
ADP125
VOUT
VOUT
VOUT
VOUT
VOUT SENSE N/A
N/A
ADJ
4
5
GND
EN
GND
EN
6
7
8
NC
VIN
VIN
EPAD
NC
VIN
VIN
EPAD
Description
Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor.
Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor.
Feedback Node for the Error Amplifier. Connect to VOUT.
Feedback Node for the Error Amplifier. Connect the midpoint of an external divider from VOUT to GND
to this pin to set the output voltage.
Ground.
Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For
automatic startup, connect EN to VIN.
No Connect. This pin is not connected internally.
Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor.
Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor.
The exposed pad must be connected to ground.
Rev. D | Page 6 of 20
Data Sheet
ADP124/ADP125
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.8 V, VOUT = 3.3V, IOUT = 10 mA, CIN = 1.0 µF, COUT = 1.0 µF, TA = 25°C, unless otherwise noted.
3.310
300
3.305
250
GROUND CURRENT (µA)
3.300
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 300mA
IOUT = 500mA
3.290
3.285
3.280
200
IOUT = 300mA
150
IOUT = 100mA
IOUT = 1mA
100
+85
–5
+25
JUNCTION TEMPERATURE (°C)
–40
50
08476-005
3.270
+125
–40
Figure 7. Output Voltage vs. Junction Temperature
+125
Figure 10. Ground Current vs. Junction Temperature
3.309
250
3.308
GROUND CURRENT (µA)
200
3.307
3.306
3.305
150
100
10
IOUT (mA)
100
1000
0
0.1
08476-006
1
1
10
ILOAD (mA)
100
1000
08476-009
50
3.304
3.303
0.1
–5
+25
+85
JUNCTION TEMPERATURE (°C)
08476-008
IOUT = 10mA
3.275
VOUT (V)
IOUT = 100µA
5.50
08476-010
VOUT (V)
3.295
IOUT = 500mA
Figure 11. Ground Current vs. Load Current
Figure 8. Output Voltage vs. Load Current
3.310
250
3.308
230
3.306
210
GROUND CURRENT (µA)
IOUT = 500mA
3.302
3.300
3.298
3.296
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 300mA
IOUT = 500mA
3.294
3.292
3.50
190
IOUT = 300mA
170
150
130
IOUT = 100mA
110
90
IOUT = 10mA
IOUT = 1mA
IOUT = 100µA
70
4.00
4.50
5.00
VIN (V)
5.50
08476-007
VOUT (V)
3.304
Figure 9. Output Voltage vs. Input Voltage
50
3.50
4.00
4.50
5.00
VIN (V)
Figure 12. Ground Current vs. Input Voltage
Rev. D | Page 7 of 20
Data Sheet
0.7
3.35
0.6
3.30
0.5
3.25
VIN = 5.50
VIN = 5.40
VIN = 5.20
VIN = 5.00
VIN = 4.40
VIN = 4.20
VIN = 3.80
0.4
0.3
IOUT = 10mA
IOUT = 100mA
IOUT = 300mA
IOUT = 500mA
3.20
VOUT (V)
3.15
3.10
0.2
3.05
0.1
3.00
–25
0
50
25
75
TEMPERATURE (°C)
100
2.95
3.00
08476-011
0
–50
125
3.10
3.20
3.30
3.40
3.50
3.60
VIN (V)
Figure 13. Shutdown Current vs. Temperature at Various Input Voltages
08476-014
SHUTDOWN CURRENT (µA)
ADP124/ADP125
Figure 16. Output Voltage vs. Input Voltage (in Dropout)
120
–10
–20
100
80
–40
PSRR (dB)
60
40
–50
–60
–70
–80
–90
0
10
100
1000
IOUT (mA)
–100
10
08476-012
1
Figure 14. Dropout Voltage vs. Load Current
–10
400
–20
350
–30
300
–40
IOUT = 10mA
IOUT = 100mA
IOUT = 300mA
IOUT = 500mA
PSRR (dB)
200
–50
–70
100
–80
50
–90
3.20
3.30
3.40
3.50
3.60
3.70
VIN (V)
Figure 15. Ground Current vs. Input Voltage (in Dropout)
–100
10
08476-013
3.10
1k
10k
100k
FREQUENCY (Hz)
1M
10M
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 300mA
IOUT = 500mA
–60
150
0
3.00
100
Figure 17. Power Supply Rejection Ratio vs. Frequency, VOUT = 2.8 V, VIN = 3.8 V
450
250
VIN = VOUT +1V
VRIPPLE = 50mV
CIN = COUT = 1µF
08476-015
20
IGND (µA)
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 300mA
IOUT = 500mA
VIN = VOUT +1V
VRIPPLE = 50mV
CIN = COUT = 1µF
100
1k
100k
10k
FREQUENCY (Hz)
1M
10M
08476-016
DROPOUT (mV)
–30
Figure 18. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 4.3 V
Rev. D | Page 8 of 20
Data Sheet
ADP124/ADP125
–10
5
–20
IOUT = 100µA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 300mA
IOUT = 500mA
PSRR (dB)
–40
–50
VOUT = 4.2V
4
NOISE (µv/√Hz)
–30
–60
VOUT = 3.3V
3
2
–70
–80
1
100
1k
10k
100k
FREQUENCY (Hz)
1M
VOUT = 2.8V
08476-020
–100
10
08476-017
VIN = VOUT + 1V
VRIPPLE = 50mV
CIN = COUT = 1µF
–90
0
10
10M
Figure 19. Power Supply Rejection Ratio vs. Frequency, VOUT = 4.2 V, VIN = 5.2 V
1k
FREQUENCY (Hz)
10k
100k
Figure 22. Output Noise Spectrum, VIN = 5 V
70
–10
–30
–40
IOUT = 10mA
IOUT = 10mA
IOUT = 10mA
IOUT = 500mA
IOUT = 500mA
IOUT = 500mA
VOUT = 4.2V
65
60
VOUT = 3.3V
55
RMS NOISE (µV)
VOUT = 2.8V,
VOUT = 3.3V,
VOUT = 4.2V,
VOUT = 2.8V,
VOUT = 3.3V,
VOUT = 4.2V,
–20
–50
–60
–70
50
VOUT = 2.8V
45
40
35
–80
30
–100
10
100
08476-018
VIN = VOUT + 1V
VRIPPLE = 50mV
CIN = COUT = 1µF
–90
1k
10k
100k
FREQUENCY (Hz)
1M
08476-021
PSRR (dB)
100
25
20
0.001
10M
Figure 20. Power Supply Rejection Ratio vs. Frequency,
Various Output Voltages and Load Currents
0.01
0.1
1
ILOAD (mA)
10
100
1k
Figure 23. Output Noise vs. Load Current and Output Voltage, VIN = 5 V
–10
VIN = 3.1V,
VIN = 3.3V,
VIN = 3.8V,
VIN = 4.8V,
–20
–30
IOUT
IOUT = 10mA
IOUT = 10mA
IOUT = 10mA
IOUT = 10mA
1mA TO 500mA LOAD STEP
1
PSRR (dB)
–40
–50
–60
VOUT
2
–70
IOUT = 500mA
IOUT = 500mA
IOUT = 500mA
IOUT = 500mA
–100
10
100
1k
VIN = 4V
VOUT = 3.3V
10k
100k
1M
CH1 500mA Ω BW CH2 50.0mV
10M
FREQUENCY (Hz)
Figure 21. Power Supply Rejection Ratio vs. Headroom Voltage (VIN − VOUT),
VOUT = 2.8 V
Rev. D | Page 9 of 20
08476-022
VIN = 3.1V,
VIN = 3.3V,
VIN = 3.8V,
VIN = 4.8V,
–90
08476-019
–80
B
W
M40.0µs A CH1
T 9.800%
200mA
Figure 24. Load Transient Response, COUT = 1 μF
ADP124/ADP125
Data Sheet
IOUT
VIN
1mA TO 500mA LOAD STEP
4V TO 4.5V VOLTAGE STEP
1
VOUT
2
2
VOUT
08476-023
VIN = 4V
VOUT = 3.3V
CH1 500mA Ω BW CH2 50.0mV
B
W
M40.0µs A CH1
T 9.800%
08476-025
1
CH1 1.00V BW
200mA
Figure 25. Load Transient Response, COUT = 4.7 μF
4V TO 4.5V VOLTAGE STEP
VOUT
08476-024
1
CH1 1.00V BW
CH2 2.00mV
B
W
M10.0µs A CH3
T 9.600%
B
W
M10.0µs A CH3
T 9.800%
200mA
Figure 27. Line Transient Response, Load Current = 500 mA
VIN
2
CH2 2.00mV
2.36V
Figure 26. Line Transient Response, Load Current = 1 mA
Rev. D | Page 10 of 20
Data Sheet
ADP124/ADP125
THEORY OF OPERATION
The ADP124/ADP125 are low quiescent current, low dropout
linear regulators that operate from 2.3 V to 5.5 V and can provide
up to 500 mA of output current. Drawing a low 210 µA of quiescent current (typical) at full load makes the ADP124/ADP125
ideal for battery-operated portable equipment. Shutdown current
consumption is typically 100 nA.
The ADP124/ADP125 use the EN pin to enable and disable the
VOUT pin under normal operating conditions. When EN is high,
VOUT turns on; when EN is low, VOUT turns off. For automatic
startup, EN can be tied to VIN.
ADP124
VIN
VOUT
Optimized for use with small 1 µF ceramic capacitors, the
ADP124/ADP125 provide excellent transient performance.
VOUT SENSE
GND
EN
SHUTDOWN
0.5V REFERENCE
R1
R2
08476-121
Internally, the ADP124/ADP125 consist of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass transistor.
Output current is delivered via the PMOS pass device, which is
controlled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower than
the reference voltage, the gate of the PMOS device is pulled lower,
allowing more current to pass and increasing the output voltage.
If the feedback voltage is higher than the reference voltage, the
gate of the PMOS device is pulled higher, allowing less current
to pass and decreasing the output voltage.
SHORT CIRCUIT,
UVLO, AND
THERMAL
PROTECT
NOTES
1. R1 AND R2 ARE INTERNAL RESISTORS, AVAILABLE ON
THE ADP124 ONLY.
The adjustable ADP125 has an output voltage range of 0.8 V to
5.0 V. The output voltage is set by the ratio of two external resistors,
as shown in Figure 2. The device servos the output to maintain
the voltage at the ADJ pin at 0.5 V referenced to ground. The
current in R1 is then equal to 0.5 V/R2 and the current in R1 is
the current in R2 plus the ADJ pin bias current. The ADJ pin
bias current, 15 nA at 25°C, flows through R1 into the ADJ pin.
Figure 28. ADP124 Internal Block Diagram (Fixed Output)
ADP125
VIN
GND
VOUT
SHORT CIRCUIT,
UVLO, AND
THERMAL
PROTECT
The output voltage can be calculated using the equation:
ADJ
VOUT = 0.5 V(1 + R1/R2) + (ADJI-BIAS)(R1)
The value of R1 should be less than 200 kΩ to minimize errors
in the output voltage caused by the ADJ pin bias current. For
example, when R1 and R2 each equal 200 kΩ, the output voltage
is 1.0 V. The output voltage error introduced by the ADJ pin
bias current is 3 mV or 0.3%, assuming a typical ADJ pin bias
current of 15 nA at 25°C.
Note that in shutdown, the output is turned off and the divider
current is 0.
Rev. D | Page 11 of 20
SHUTDOWN
0.5V REFERENCE
08476-122
EN
Figure 29. ADP125 Internal Block Diagram (Adjustable Output)
ADP124/ADP125
Data Sheet
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Input Bypass Capacitor
Output Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces the circuit
sensitivity to the printed circuit board (PCB) layout, especially
when a long input trace or high source impedance is encountered.
If greater than 1 µF of output capacitance is required, the input
capacitor should be increased to match it.
The ADP124/ADP125 are designed for operation with small,
space-saving ceramic capacitors, but these devices can function
with most commonly used capacitors as long as care is taken to
ensure an appropriate effective series resistance (ESR) value. The
ESR of the output capacitor affects the stability of the LDO control
loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or
less is recommended to ensure stability of the ADP124/ADP125.
The transient response to changes in load current is also affected by
the output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP124/ADP125 to
dynamic changes in load current. Figure 30 and Figure 31 show
the transient responses for output capacitance values of 1 µF and
4.7 µF, respectively.
IOUT
1mA TO 500mA LOAD STEP
1
2
VOUT
08476-028
VIN = 4V
VOUT = 3.3V
CH1 500mA Ω BW CH2 50.0mV
B
W
M400ns A CH1
T 13.20%
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP124/ADP125, as long as the capacitor meets the minimum
capacitance and maximum ESR requirements. Ceramic capacitors
are manufactured with a variety of dielectrics, each with different
behavior over temperature and applied voltage. Capacitors must
have an adequate dielectric to ensure the minimum capacitance
over the necessary temperature range and dc bias conditions.
Using an X5R or X7R dielectric with a voltage rating of 6.3 V or
10 V is recommended. However, using Y5V and Z5U dielectrics
are not recommended for any LDO, due to their poor temperature
and dc bias characteristics.
Figure 32 depicts the capacitance vs. capacitor voltage bias characteristics of an 0402, 1 µF, 10 V X5R capacitor. The voltage stability
of a capacitor is strongly influenced by the capacitor size and the
voltage rating. In general, a capacitor in a larger package or of a
higher voltage rating exhibits better stability. The temperature
variation of the X5R dielectric is about ±15% over the −40°C to
+85°C temperature range and is not a function of package or
voltage rating.
1.10
200mA
1.05
Figure 30. Output Transient Response, COUT = 1 µF
CAPACITANCE (µF)
1.00
IOUT
1mA TO 500mA LOAD STEP
1
0.95
0.90
0.85
0.80
2
08476-030
0.75
0.70
0
VOUT
2
4
3
BIAS VOLTAGE (V)
5
6
7
Figure 32. Capacitance vs. Capacitor Voltage Bias Characteristics
08476-029
VIN = 4V
VOUT = 3.3V
CH1 500mA Ω BW CH2 50.0mV
1
B
W
M400ns A CH1
T 13.60%
200mA
Equation 1 can be used to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
Figure 31. Output Transient Response, COUT = 4.7 µF
CEFF = C × (1 − TEMPCO) × (1 − TOL)
where:
CEFF is the effective capacitance at the operating voltage.
C is the rated capacitance value.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
Rev. D | Page 12 of 20
(1)
Data Sheet
ADP124/ADP125
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
C is 0.94 μF at 4.2 V from the graph in Figure 32.
The active and inactive thresholds of the EN pin are derived from
the VIN voltage. Therefore, these thresholds vary as the input
voltage changes. Figure 34 shows typical EN active and inactive
thresholds when the VIN voltage varies from 2.3 V to 5.5 V.
Substituting these values in Equation 1 yields
1.05
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
ENABLE (EN) TRESHOLDS (V)
1.00
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP124/ADP125, it is
imperative that the effects of dc bias, temperature, and tolerances
on the behavior of the capacitors are evaluated for each application.
UNDERVOLTAGE LOCKOUT
ENABLE FEATURE
The ADP124/ADP125 uses the EN pin to enable and disable the
VOUT pin under normal operating conditions. As shown in
Figure 33, when a rising voltage on EN crosses the active threshold,
VOUT turns on. Conversely, when a falling voltage on EN crosses
the inactive threshold, VOUT turns off.
RISING
0.90
0.85
0.80
FALLING
0.75
0.70
0.65
0.60
2.2
08476-032
The ADP124/ADP125 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage is less than approximately 2 V. This ensures that the
ADP124/ADP125 inputs and the output behave in a predictable
manner during power-up.
0.95
2.7
3.7
3.2
4.2
4.7
5.2
VIN (V)
Figure 34. Typical EN Pin Thresholds vs. Input Voltage
The ADP124/ADP125 use an internal soft start to limit the
inrush current when the output is enabled. The start-up time
for the 2.8 V option is approximately 350 µs from the time the
EN active threshold is crossed to when the output reaches 90%
of its final value. As shown in Figure 35, the start-up time is
dependent on the output voltage setting and increases slightly
as the output voltage increases.
3.5
VIN = 5V
3.0
VOUT = 4.2V
2.5
VOUT
VOUT = 3.3V
2.0
VOUT = 2.8V
1.5
1.0
1
2
0
0
0.2
0.4
0.6
0.8
VEN
1.0
1.2
1.4
08476-033
08476-230
0.5
1.6
CH1 1.00V
Figure 33. Typical EN Pin Operation
CH2 1.00V
B
W
M100µs
A CH1
T
296.800µs
Figure 35. Typical Start-Up Time
As shown in Figure 33, the EN pin has built-in hysteresis. This
prevents on/off oscillations that may occur due to noise on the
EN pin as it passes through the threshold points.
Rev. D | Page 13 of 20
2.00V
ADP124/ADP125
Data Sheet
Table 6. Typical θJA Values for Specified PCB Copper Sizes
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
θJA (°C/W)
The ADP124/ADP125 are protected from damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP124/ADP125 are designed to limit the current
when the output load reaches 750 mA (typical). When the output
load exceeds 750 mA, the output voltage is reduced to maintain
a constant current limit.
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C typical. Under extreme conditions (that is, high ambient temperature and power dissipation),
when the junction temperature starts to rise above 150°C, the
output is turned off, reducing output current to zero. When the
junction temperature cools to less than 135°C, the output is turned
on again and the output current is restored to its nominal value.
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP124/ADP125 limit the current so that only
750 mA is conducted into the short. If self-heating causes the
junction temperature to rise above 150°C, thermal shutdown
activates, turning off the output and reducing the output
current to zero. When the junction temperature cools to less
than 135°C, the output turns on and conducts 750 mA into the
short, again causing the junction temperature to rise above
150°C. This thermal oscillation between 135°C and 150°C results
in a current oscillation between 750 mA and 0 mA that
continues as long as the short remains at the output.
Copper
Size (mm2)
25
100
500
1000
6400
MSOP
108.6
75.5
42.5
34.7
26.1
LFCSP
177.8
138.2
79.8
67.8
53.5
Table 7. Typical ΨJB Values
MSOP
31.7
ΨJB (°C/W)
LFCSP
44.1
The junction temperature of the ADP124/ADP125 can be
calculated from the following equation:
TJ = TA + (PD × θJA)
(2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND)
(3)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
Current and thermal limit protections are intended to protect the
device from damage due to accidental overload conditions. For
reliable operation, the device power dissipation must be externally
limited so that the junction temperature does not exceed 125°C.
The power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
can be simplified as follows:
THERMAL CONSIDERATIONS
As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current, there
exists a minimum copper size requirement for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 36
through Figure 41 show junction temperature calculations for
different ambient temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
To guarantee reliable operation, the junction temperature of the
ADP124/ADP125 must not exceed 125°C. To ensure that the
junction temperature is less than this maximum value, the user
needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal
resistances between the junction and ambient air (θJA). The value
of θJA is dependent on the package assembly compounds used
and the amount of copper to which the GND pins of the package
are soldered on the PCB. Table 6 shows typical θJA values of the
8-lead MSOP package for various PCB copper sizes. Table 7
shows typical ΨJB values of the 8-lead MSOP and 8-lead 3 mm ×
3 mm LFCSP package.
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(4)
In cases where the board temperature is known, the thermal
characterization parameter, ΨJB, can be used to estimate the junction temperature rise. The maximum junction temperature (TJ) is
calculated from the board temperature (TB) and power dissipation
(PD) using the formula
Rev. D | Page 14 of 20
TJ = TB + (PD × ΨJB)
(5)
Data Sheet
ADP124/ADP125
JUNCTION TEMPERATURE CALCULATIONS
140
145
130
115
105
95
85
75
65
55
6400 mm 2
500 mm 2
25 mm2
TJ MAX
45
35
110
100
90
80
6400 mm 2
500 mm 2
25 mm2
TJ MAX
70
60
50
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
25
120
08476-037
JUNCTION TEMPERATURE (°C)
125
08476-034
JUNCTION TEMPERATURE (°C)
135
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
TOTAL POWER DISSIPATION (W)
TOTAL POWER DISSIPATION (W)
Figure 36. Junction Temperature vs. Power Dissipation and copper area,
MSOP, TA = 25°C
Figure 39. Junction Temperature vs. Power Dissipation and copper area,
LFCSP, TA = 50°C
140
145
120
115
105
95
85
75
65
55
6400 mm 2
500 mm 2
45
25 mm2
TJ MAX
35
25
0
0.2
0.4
0.8
1.6
1.0
0.6
1.2
1.4
TOTAL POWER DISSIPATION (W)
1.8
80
60
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
40
20
0
2.0
Figure 37. Junction Temperature vs. Power Dissipation and copper area,
LFCSP, TA = 25°C
0
0.25
0.50
0.75 1.00 1.25 1.50 1.75 2.00
TOTAL POWER DISSIPATION (W)
2.25
2.50
Figure 40. Junction Temperature vs. Power Dissipation, MSOP package
at various Board Temperatures
140
140
130
110
100
90
80
70
6400 mm 2
500 mm 2
60
25 mm2
TJ MAX
50
0
100
80
60
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
40
20
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
TOTAL POWER DISSIPATION (W)
Figure 38. Junction Temperature vs. Power Dissipation and copper area,
MSOP, TA = 50°C
08476-039
JUNCTION TEMPERATURE (°C)
120
120
08476-036
JUNCTION TEMPERATURE (°C)
100
08476-038
JUNCTION TEMPERATURE (°C)
125
08476-035
JUNCTION TEMPERATURE (°C)
135
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TOTAL POWER DISSIPATION (W)
4.0
4.5
Figure 41. Junction Temperature vs. Power Dissipation, LFCSP package
at various Board Temperatures
Rev. D | Page 15 of 20
ADP124/ADP125
Data Sheet
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP124/
ADP125. However, as shown in Table 6, a point of diminishing
returns eventually is reached, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
08476-042
The input capacitor should be placed as close as possible to the
VIN and GND pins, and the output capacitor should be placed
as close as possible to the VOUT and GND pins. Use of 0402 or
0603 size capacitors and resistors achieves the smallest possible
footprint solution on boards where the area is limited.
08476-041
Figure 43. Example ADP125 MSOP PCB Layout
08476-045
Figure 42. Example ADP124 MSOP PCB Layout
Figure 44. Example ADP124/ADP125 LFCSP PCB Layout
Rev. D | Page 16 of 20
Data Sheet
ADP124/ADP125
OUTLINE DIMENSIONS
3.10
3.00
2.90
8
3.10
3.00
2.90
1.825
1.725
1.625
5
5.05
4.90
4.75
1.760
1.660
1.560
EXPOSED
PAD
1
4
TOP VIEW
BOTTOM VIEW
1.95 BSC
1.10
MAX
SIDE VIEW
0.13
MAX
COPLANARITY
0.10
0.25 GAGE
PLANE
END VIEW
6°
0°
0.40
0.33
0.25
PKG-3371
0.23
0.08
0.70
0.55
0.40
0.95
REF
06-04-2013-A
0.65
BSC
0.94
0.86
0.78
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-187-AA-T
Figure 45. 8-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP]
(RH-8-1)
Dimensions shown in millimeters
1.70
1.60
1.50
2.10
2.00 SQ
1.90
0.50 BSC
8
5
1.10
1.00
0.90
EXPOSED
PAD
0.425
0.350
0.275
4
TOP VIEW
0.60
0.55
0.50
SEATING
PLANE
0.05 MAX
0.02 NOM
0.30
0.25
0.20
1
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
Figure 46. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD]
2 mm × 2 mm Body, Ultra Thin, Dual Lead
(CP-8-10)
Dimensions shown in millimeters
Rev. D | Page 17 of 20
PIN 1
INDICATOR
(R 0.15)
01-14-2013-C
PIN 1 INDEX
AREA
0.15 REF
ADP124/ADP125
Data Sheet
ORDERING GUIDE
Model1
ADP124ARHZ-1.8-R7
ADP124ARHZ-2.5-R7
ADP124ARHZ-2.7-R7
ADP124ARHZ-2.8-R7
ADP124ARHZ-2.85-R7
ADP124ARHZ-2.9-R7
ADP124ARHZ-3.0-R7
ADP124ARHZ-3.3-R7
ADP124ACPZ-1.8-R7
ADP124ACPZ-2.8-R7
ADP124ACPZ-2.9-R7
ADP124ACPZ-3.0-R7
ADP124ACPZ-3.3-R7
ADP125ACPZ-R7
ADP125ARHZ-R7
ADP125ARHZ
ADP125-EVALZ
ADP125CP-EVALZ
ADP124RHZ-REDYKIT
ADP124CPZ-REDYKIT
1
2
Temperature Range (TJ)
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Output Voltage (V)2
1.8
2.5
2.7
2.8
2.85
2.9
3.0
3.3
1.8
2.8
2.9
3.0
3.3
0.8 to 5.0 (Adjustable)
0.8 to 5.0 (Adjustable)
0.8 to 5.0 (Adjustable)
Adjustable
Adjustable
Package Description
8-Lead MINI_SO_EP
8-Lead MINI_SO_EP
8-Lead MINI_SO_EP
8-Lead MINI_SO_EP
8-Lead MINI_SO_EP
8-Lead MINI_SO_EP
8-Lead MINI_SO_EP
8-Lead MINI_SO_EP
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead MINI_SO_EP
8-Lead MINI_SO_EP
MSOP Evaluation Board
LFCSP Evaluation Board
REDYKIT
REDYKIT
Package Option
RH-8-1
RH-8-1
RH-8-1
RH-8-1
RH-8-1
RH-8-1
RH-8-1
RH-8-1
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
RH-8-1
RH-8-1
Branding
37
3T
3U
3Z
40
41
49
4F
LHH
LHJ
LM2
LHK
LHL
LHM
38
38
Z = RoHS Compliant Part.
Up to 31 fixed-output voltage options from 1.75 V to 3.3 V are available. For additional voltage options, contact a local Analog Devices, Inc., sales or distribution
representative.
Rev. D | Page 18 of 20
Data Sheet
ADP124/ADP125
NOTES
Rev. D | Page 19 of 20
ADP124/ADP125
Data Sheet
NOTES
©2009–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08476-0-12/14(D)
Rev. D | Page 20 of 20
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