ADP1707ACPZ-0.8-R7

Data Sheet ADP1706/ADP1707/ADP1708 1 A, Low Dropout, CMOS Linear Regulator FEATURES ► ► ► ► ► ► ► TYPICAL APPLICATION CIRCUITS Maximum output current: 1 A Input voltage range: 2.5 V to 5.5 V Low shutdown current: 1.8 V, TJ = −40°C to +125°C −60 +60 mV 1.8 EN INPUT EN Input Logic High VIH 2.5 V ≤ VIN ≤ 5.5 V EN Input Logic Low VIL 2.5 V ≤ VIN ≤ 5.5 V analog.com V 0.4 V Rev. B | 3 of 19 Data Sheet ADP1706/ADP1707/ADP1708 SPECIFICATIONS Table 1. Parameter EN Input Leakage Current Symbol Test Conditions/Comments VI-LEAKAGE EN = IN or GND Min Typ Max Unit 0.1 1 µA 100 nA ADJ INPUT BIAS CURRENT (ADP1708) ADJI-BIAS 30 SENSE INPUT BIAS CURRENT SNSI-BIAS 4 µA OUTPUT NOISE OUTNOISE POWER SUPPLY REJECTION RATIO PSRR 10 Hz to 100 kHz, VOUT = 0.75 V 125 µV rms 10 Hz to 100 kHz, VOUT = 3.3 V 450 µV rms 1 kHz, VOUT = 0.75 V 70 dB 1 kHz, VOUT = 3.3 V 56 dB 1 Accuracy when OUT is connected directly to ADJ. When OUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of resistors used. 2 Based on an end-point calculation using 10 mA and 1 A loads. See Figure 11 for typical load regulation performance for loads less than 10 mA. 3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.5 V. 4 Start-up time is defined as the time between the rising edge of EN to OUT being at 95% of its nominal value. 5 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V. analog.com Rev. B | 4 of 19 Data Sheet ADP1706/ADP1707/ADP1708 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Rating IN to GND −0.3 V to +6 V OUT to GND –0.3 V to IN EN to GND –0.3 V to +6 V SS/ADJ/TRK to GND –0.3 V to +6 V SENSE to GND –0.3 V to +6 V Storage Temperature Range –65°C to +150°C Operating Junction Temperature Range –40°C to +125°C Soldering Conditions JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. analog.com θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type θJA Unit 8-Lead SOIC (Exposed Paddle) 58 °C/W 8-Lead 3 mm × 3 mm LFCSP (Exposed Paddle) 66 °C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Rev. B | 5 of 19 Data Sheet ADP1706/ADP1707/ADP1708 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. 8-Lead SOIC, ADP1706 Figure 5. 8-Lead LFCSP, ADP1706 Table 4. ADP1706 Pin Function Descriptions Pin No. SOIC LFCSP Mnemonic Description 1 1 EN Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For automatic startup, connect EN to IN. 2 2 GND Ground. 3, 4 3, 4 IN Regulator Input Supply. Bypass IN to GND with a 4.7 µF or greater capacitor. 5, 6 5, 6 OUT Regulated Output Voltage. Bypass OUT to GND with a 4.7 µF or greater capacitor. 7 7 SENSE Sense. Measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. 8 8 SS Soft Start. A capacitor connected to this pin determines the soft start time. 0 0 EP Exposed Pad. The exposed pad enhances thermal performance and is electrically connected to GND inside the package. It is recommended to connect the exposed pad to the ground plane on the board. analog.com Rev. B | 6 of 19 Data Sheet ADP1706/ADP1707/ADP1708 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. 8-Lead SOIC, ADP1707 Figure 7. 8-Lead LFCSP, ADP1707 Table 5. ADP1707 Pin Function Descriptions Pin No. SOIC LFCSP Mnemonic Description 1 1 EN Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For automatic startup, connect EN to IN. 2 2 GND Ground. 3, 4 3, 4 IN Regulator Input Supply. Bypass IN to GND with a 4.7 µF or greater capacitor. 5, 6 5, 6 OUT Regulated Output Voltage. Bypass OUT to GND with a 4.7 µF or greater capacitor. 7 7 SENSE Sense. Measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. 8 8 TRK Track. The output follows the voltage applied at the TRK pin. See the Theory of Operation section for a more detailed description. 0 0 EP Exposed Pad. The exposed pad enhances thermal performance and is electrically connected to GND inside the package. It is recommended to connect the exposed pad to the ground plane on the board. analog.com Rev. B | 7 of 19 Data Sheet ADP1706/ADP1707/ADP1708 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 8. 8-Lead SOIC, ADP1708 Figure 9. 8-Lead LFCSP, ADP1708 Table 6. ADP1708 Pin Function Descriptions Pin No. SOIC LFCSP Mnemonic Description 1 1 EN Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For automatic startup, connect EN to IN. 2 2 GND Ground. 3, 4 3, 4 IN Regulator Input Supply. Bypass IN to GND with a 4.7 µF or greater capacitor. 5, 6 5, 6 OUT Regulated Output Voltage. Bypass OUT to GND with a 4.7 µF or greater capacitor. 7 7 SENSE Sense. Measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. 8 8 ADJ Adjust. A resistor divider from OUT to ADJ sets the output voltage. 0 0 EP Exposed Pad. The exposed pad enhances thermal performance and is electrically connected to GND inside the package. It is recommended to connect the exposed pad to the ground plane on the board. analog.com Rev. B | 8 of 19 Data Sheet ADP1706/ADP1707/ADP1708 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.8 V, IOUT = 100 mA, CIN = 4.7 µF, COUT = 4.7 µF, TA = 25°C, unless otherwise noted. Figure 10. Output Voltage (VOUT) vs. Junction Temperature (TJ) Figure 13. Ground Current (IGND) vs. Junction Temperature (TJ) Figure 11. Output Voltage (VOUT) vs. Load Current (ILOAD) Figure 14. Ground Current (IGND) vs. Load Current (ILOAD) Figure 12. Output Voltage (VOUT) vs. Input Voltage (VIN) Figure 15. Ground Current (IGND) vs. Input Voltage (VIN) analog.com Rev. B | 9 of 19 Data Sheet ADP1706/ADP1707/ADP1708 TYPICAL PERFORMANCE CHARACTERISTICS Figure 16. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD) Figure 19. Load Transient Response, CIN = 4.7 µF, COUT = 4.7 µF Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN) (in Dropout) Figure 20. Load Transient Response, CIN = 22 µF, COUT = 22 µF Figure 18. Ground Current (IGND) vs. Input Voltage (VIN) (in Dropout) Figure 21. Line Transient Response analog.com Rev. B | 10 of 19 Data Sheet ADP1706/ADP1707/ADP1708 TYPICAL PERFORMANCE CHARACTERISTICS Figure 22. Output Voltage Ramp-Up Time vs. Soft Start Capacitor Value Figure 25. ADP1708 Power Supply Rejection Ratio (PSRR) vs. Input Voltage (VIN) Figure 23. ADP1706 Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 26. ADP1708 Power Supply Rejection Ratio (PSRR) vs. Output Voltage (VOUT) Figure 24. ADP1708 Power Supply Rejection Ratio (PSRR) vs. Frequency analog.com Rev. B | 11 of 19 Data Sheet ADP1706/ADP1707/ADP1708 THEORY OF OPERATION The ADP1706/ADP1707/ADP1708 are low dropout linear regulators that use an advanced, proprietary architecture to provide high power supply rejection ratio (PSRR) and excellent line and load transient response with a small 4.7 µF ceramic output capacitor. All devices operate from a 2.5 V to 5.5 V input rail and provide up to 1 A of output current. Supply current in shutdown mode is typically 100 nA. Figure 27. Internal Block Diagram where: TSS is the soft start period. VREF is the 0.8 V reference voltage. CSS is the soft start capacitance from SS to GND. ISS is the current sourced from SS (1.2 µA). When the ADP1706 is disabled (using EN), the soft start capacitor is discharged to GND through an internal 100 Ω resistor. Figure 28. OUT Ramp-Up with External Soft Start Capacitor Internally, the ADP1706/ADP1707/ADP1708 consist of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. The ADP1707 and ADP1708 have no pins for soft start; therefore, the function is switched to an internal soft start capacitor, which sets the soft start ramp-up period to approximately 48 µs. Note that the ramp-up period is the time it takes OUT to go from 0% to 90% of the nominal value and is different from the start-up time in Table 1, which is the time between the rising edge of EN to OUT being at 90% of the nominal value. For the worst-case output voltage of 5 V, using the suggested 4.7 µF output capacitor, the resulting input inrush current is approximately 490 mA, which is less than the maximum 1 A load current. The ADP1706/ADP1707 are available in 16 fixed output voltage options between 0.75 V and 3.3 V. The ADP1706 allows for connection of an external soft start capacitor, which controls the output voltage ramp during startup. The ADP1707 features a TRK pin that allows the output voltage to follow the voltage at this pin. The ADP1708 is available in an adjustable version with an output voltage that can be set to between 0.8 V and 5.0 V by an external voltage divider. All devices are controlled by an enable pin (EN). SOFT START FUNCTION (ADP1706) For applications that require a controlled startup, the ADP1706 provides a programmable soft start function. The programmable soft start is useful for reducing inrush current upon startup and for providing voltage sequencing. To implement a soft start, connect a small ceramic capacitor from SS to GND. Upon startup, a 1.2 µA current source charges this capacitor. The ADP1706 start-up output voltage is limited by the voltage at SS, providing a smooth ramp-up to the nominal output voltage. The soft start time is calculated by The ADP1708 can have its output voltage set over a 0.8 V to 5.0 V range. The output voltage is set by connecting a resistive voltage divider from OUT to ADJ. The output voltage is calculated by TSS = VREF × (CSS/ISS) VOUT = 0.8 V (1 + R1/R2) analog.com (1) Figure 29. OUT Ramp-Up with Internal Soft Start ADJUSTABLE OUTPUT VOLTAGE (ADP1708) (2) Rev. B | 12 of 19 Data Sheet ADP1706/ADP1707/ADP1708 THEORY OF OPERATION where: R1 is the resistor from OUT to ADJ. R2 is the resistor from ADJ to GND. The maximum bias current into ADJ is 100 nA, so for less than 0.5% error due to the bias current, use values less than 60 kΩ for R2. TRACK MODE (ADP1707) The ADP1707 includes a tracking mode feature. As shown in Figure 30, if the voltage applied at the TRK pin is less than the nominal output voltage, OUT is equal to the voltage at TRK. Otherwise, OUT regulates to its nominal output value. Figure 31. ADP1706 Typical EN Pin Operation As shown in Figure 31, the EN pin has hysteresis built in. This prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. The EN pin active/inactive thresholds are derived from the IN voltage. Therefore, these thresholds vary when changing the input voltage. Figure 32 shows typical EN active/inactive thresholds when the input voltage varies from 2.5 V to 5.5 V. Figure 30. ADP1707 Output Voltage vs. Tracking Voltage For example, consider an ADP1707 with a nominal output voltage of 3.3 V. If the voltage applied to its TRK pin is greater than 3.3 V, OUT maintains a nominal output voltage of 3.3 V. If the voltage applied to TRK is reduced below 3.3 V, OUT tracks this voltage. OUT can track the TRK pin voltage from the nominal value all the way down to 0 V. A voltage divider is present from TRK to the error amplifier input with a divider ratio equal to the divider from OUT to the error amplifier, which sets the output voltage equal to the tracking voltage. Both divider ratios are set by postpackage trim, depending on the desired output voltage. Figure 32. Typical EN Pin Thresholds vs. Input Voltage ENABLE FEATURE The ADP1706/ADP1707/ADP1708 use the EN pin to enable and disable the OUT pin under normal operating conditions. As shown in Figure 31, when a rising voltage on EN crosses the active threshold, OUT turns on. When a falling voltage on EN crosses the inactive threshold, OUT turns off. analog.com Rev. B | 13 of 19 Data Sheet ADP1706/ADP1707/ADP1708 APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor The ADP1706/ADP1707/ADP1708 are designed for operation with small, space-saving ceramic capacitors, but they function with most commonly used capacitors as long as care is taken with the effective series resistance (ESR) value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 4.7 µF capacitance with an ESR of 500 mΩ or less is recommended to ensure stability of the ADP1706/ADP1707/ADP1708. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP1706/ADP1707/ADP1708 to large changes in load current. Figure 33 and Figure 34 show the transient responses for output capacitance values of 4.7 µF and 22 µF, respectively. Input and Output Capacitor Properties Any good quality ceramic capacitors can be used with the ADP1706/ADP1707/ADP1708, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. VOLTAGE TRACKING APPLICATIONS Figure 35. Voltage Tracking Feature Using the ADP1707 Figure 33. Output Transient Response, COUT = 4.7 µF Figure 35 shows an application where the ADP1707 tracking feature is used. An ADP1706 powers the input/output of a microprocessor and an ADP1707 powers the core. At startup, the output of the ADP1706 ramps to 2.5 V, which is divided down via a voltage divider (R1 and R2) to a lower voltage at the TRK pin of the ADP1707. The output of the ADP1707 thus follows the TRK pin and ramps up steadily to 1.2 V. This implementation ensures that the core of the processor powers up after the input/output. CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION Figure 34. Output Transient Response, COUT = 22 µF Input Bypass Capacitor Connecting a 4.7 µF capacitor from the IN pin to GND reduces the circuit sensitivity to the printed circuit board (PCB) layout, especially when long input traces, or high source impedance, is encountered. If greater than 4.7 µF of output capacitance is required, it is recommended that the input capacitor be increased to match it. analog.com The ADP1706/ADP1707/ADP1708 are protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP1706/ADP1707/ADP1708 are designed to reach current limit when the output load reaches 1.5 A (typical). When the output load exceeds 1.5 A, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is included, which limits the junction temperature to a maximum of 150°C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150°C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 135°C (typical), the output is turned on again and output current is restored to its nominal value. Rev. B | 14 of 19 Data Sheet ADP1706/ADP1707/ADP1708 APPLICATIONS INFORMATION Consider the case where a hard short from OUT to ground occurs. At first, the ADP1706/ADP1707/ADP1708 reach current limit so that only 1.5 A is conducted into the short. If self-heating of the junction becomes great enough to cause its temperature to rise above 150°C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 135°C, the output turns on and conducts 1.5 A into the short, again causing the junction temperature to rise above 150°C. This thermal oscillation between 135°C and 150°C causes a current oscillation between 1.5 A and 0 A that continues as long as the short remains at the output. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation should be externally limited so junction temperatures do not exceed 125°C. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to the following: TJ = TA + (((VIN – VOUT) × ILOAD) × θJA) (5) As shown in Equation 5, for a given ambient temperature, input-tooutput voltage differential, and continuous load current, a minimum copper size requirement exists for the PCB to ensure the junction temperature does not rise above 125°C. Figure 36 to Figure 41 show junction temperature calculations for different ambient temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper. THERMAL CONSIDERATIONS To guarantee reliable operation, the junction temperature of the ADP1706/ADP1707/ADP1708 must not exceed 125°C. To ensure that the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistance between the junction and ambient air (θJA). The θJA value is dependent on the package assembly compounds used and the amount of copper to which the GND pins of the package are soldered on the PCB. Table 7 shows typical θJA values of the 8-lead SOIC and 8-lead LFCSP for various PCB copper sizes. Figure 36. 500 mm2 of PCB Copper, TA = 25°C, SOIC Table 7. Typical θJA Values Copper Size (mm2) θJA (°C/W), SOIC θJA (°C/W), LFCSP 01 57.6 65.9 50 53.1 62.3 100 52.3 61.2 300 51.3 59.7 500 51.3 59.4 1 Device soldered to minimum size pin traces. The junction temperature of the ADP1706/ADP1707/ADP1708 can be calculated by TJ = TA + (PD × θJA) Figure 37. 100 mm2 of PCB Copper, TA = 25°C, SOIC (3) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = ((VIN – VOUT) × ILOAD) + (VIN × IGND) (4) where: ILOAD is the load current. IGND is the ground current. VIN and VOUT are the input and output voltages, respectively. analog.com Rev. B | 15 of 19 Data Sheet ADP1706/ADP1707/ADP1708 APPLICATIONS INFORMATION Figure 38. 0 mm2 of PCB Copper, TA = 25°C, SOIC Figure 41. 0 mm2 of PCB Copper, TA = 25°C, LFCSP PCB LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP1706/ ADP1707/ADP1708. However, as can be seen from Table 7, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Figure 39. 500 mm2 of PCB Copper, TA = 25°C, LFCSP The ADP1706/ADP1707/ADP1708 feature an exposed pad on the bottom of both the SOIC and LFCSP packages to improve thermal performance. Because the exposed pad is electrically connected to GND inside the package, it is recommended that it also be connected to the ground plane on the PCB with a sufficient amount of copper. Here are a few general tips when designing PCBs: Place the input capacitor as close as possible to the IN and GND pins. ► Place the output capacitor as close as possible to the OUT and GND pins. ► For the ADP1706, place the soft start capacitor as close as possible to the SS pin. ► Connect the load as close as possible to the OUT and SENSE pins. ► Use of 0402 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. Figure 40. 100 mm2 of PCB Copper, TA = 25°C, LFCSP analog.com Rev. B | 16 of 19 Data Sheet ADP1706/ADP1707/ADP1708 APPLICATIONS INFORMATION Figure 42. Example PCB Layout analog.com Rev. B | 17 of 19 Data Sheet ADP1706/ADP1707/ADP1708 OUTLINE DIMENSIONS Figure 43. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters Figure 44. 8-Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters Updated: June 23, 2022 ORDERING GUIDE Table 8. Model1 Temperature Range Package Description Packing Quantity Package Option ADP1706ACPZ-1.05R7 ADP1706ACPZ-1.2-R7 ADP1706ACPZ-1.3-R7 ADP1706ACPZ-1.5-R7 ADP1706ACPZ-2.5-R7 ADP1706ACPZ-3.3-R7 ADP1706ARDZ-1.15R7 -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C 8-Lead LFCSP (3mm x 3mm w/ EP) 8-Lead LFCSP (3mm x 3mm w/ EP) 8-Lead LFCSP (3mm x 3mm w/ EP) 8-Lead LFCSP (3mm x 3mm w/ EP) 8-Lead LFCSP (3mm x 3mm w/ EP) 8-Lead LFCSP (3mm x 3mm w/ EP) 8-Lead SOIC w/ EP Reel, 1500 Reel, 1500 Reel, 1500 Reel, 1500 Reel, 1500 Reel, 1500 Reel, 1000 CP-8-13 CP-8-13 CP-8-13 CP-8-13 CP-8-13 CP-8-13 RD-8-1 analog.com Marking Code L67 L6A L6C L6D L6E L6G Rev. B | 18 of 19 Data Sheet ADP1706/ADP1707/ADP1708 OUTLINE DIMENSIONS Table 8. Model1 Temperature Range Package Description Packing Quantity Package Option ADP1706ARDZ-1.2-R7 ADP1706ARDZ-1.3-R7 ADP1706ARDZ-1.5-R7 ADP1706ARDZ-1.8-R7 ADP1706ARDZ-2.5-R7 ADP1706ARDZ-3.0-R7 ADP1706ARDZ-3.3-R7 ADP1707ACPZ-1.8-R7 ADP1707ACPZ-3.3-R7 ADP1707ARDZ-1.2-R7 ADP1707ARDZ-1.5-R7 ADP1707ARDZ-1.8-R7 ADP1707ARDZ-2.5-R7 ADP1707ARDZ-3.3-R7 ADP1708ACPZ-R7 ADP1708ARDZ-R7 -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead LFCSP (3mm x 3mm w/ EP) 8-Lead LFCSP (3mm x 3mm w/ EP) 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead SOIC w/ EP 8-Lead LFCSP (3mm x 3mm w/ EP) 8-Lead SOIC w/ EP Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1500 Reel, 1500 Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1000 Reel, 1500 Reel, 1000 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 CP-8-13 CP-8-13 RD-8-1 RD-8-1 RD-8-1 RD-8-1 RD-8-1 CP-8-13 RD-8-1 1 Marking Code L71 L74 L7P Z = RoHS Compliant Part. OUTPUT VOLTAGE OPTIONS Table 9. Output Voltage Options Model1 Output Voltage (V) ADP1706ACPZ-1.05R7 ADP1706ARDZ-1.15R7 ADP1706ARDZ-1.2-R7, ADP1706ACPZ-1.2-R7, ADP1707ARDZ-1.2-R7 ADP1706ARDZ-1.3-R7, ADP1706ACPZ-1.3-R7 ADP1706ARDZ-1.5-R7, ADP1706ACPZ-1.5-R7, ADP1707ARDZ-1.5-R7 ADP1706ARDZ-1.8-R7, ADP1707ARDZ-1.8-R7, ADP1707ACPZ-1.8-R7 ADP1706ARDZ-2.5-R7, ADP1706ACPZ-2.5-R7, ADP1707ARDZ-2.5-R7 ADP1706ARDZ-3.0-R7 ADP1706ARDZ-3.3-R7, ADP1706ACPZ-3.3-R7, ADP1707ARDZ-3.3-R7, ADP1707ACPZ-3.3-R7 ADP1708ARDZ-R7, ADP1708ACPZ-R7 ADP1706-3.3-EVALZ ADP1707-3.3-EVALZ ADP1708-EVALZ 1.05 1.15 1.2 1.3 1.5 1.8 2.5 3.0 3.3 0.8 to 5.0 3.3 3.3 Adjustable, but set to 1.6 V 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Description ADP1706-3.3-EVALZ Evaluation Board ADP1707-3.3-EVALZ Evaluation Board ADP1708-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2007-2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. B | 19 of 19