ADP1715ARMZ-R7

500 mA, Low Dropout, CMOS Linear Regulator ADP1715/ADP1716 FEATURES TYPICAL APPLICATION CIRCUITS ADP1715 VIN = 5V 2.2µF VOUT = 3.3V 2.2µF EN GND 8 2 IN GND 7 3 OUT GND 6 4 SS GND 5 10nF Figure 1. ADP1715 with Fixed Output Voltage, 3.3 V ADP1715 ADJUSTABLE 2.2µF R1 VOUT = 0.8(1 + R1/R2) 1 EN GND 8 2 IN GND 7 3 OUT GND 6 4 ADJ GND 5 06110-002 VIN = 5V R2 2.2µF Figure 2. ADP1715 with Adjustable Output Voltage, 0.8 V to 5.0 V ADP1716 VIN = 5V 2.2µF VOUT 2.2µF VOUT (V) 1 EN GND 8 2 IN GND 7 3 OUT GND 6 2 4 TRK GND 5 1 3 0 VTRK = 0V TO 5V 1 2 3 4 5 VTRK (V) 06110-003 APPLICATIONS Notebook computers Memory components Telecommunications equipment Network equipment DSP/FPGA/μP supplies Instrumentation equipment/data acquisition systems 1 06110-001 Maximum output current: 500 mA Input voltage range: 2.5 V to 5.5 V Low shutdown current: 1.8 V, TJ = –40°C to +125°C 2.5 V ≤ VIN ≤ 5.5 V 2.5 V ≤ VIN ≤ 5.5 V EN = IN or GND –50 –100 1.8 POWER SUPPLY REJECTION RATIO Typ TSTART-UP CSS = 10 nF VIH VIL VI-LEAKAGE ADJI-BIAS OUTNOISE PSRR 550 TJ rising 100 7.3 750 150 °C 15 10 Hz to 100 kHz, VOUT = 0.75 V 10 Hz to 100 kHz, VOUT = 3.3 V 1 kHz, VOUT = 0.75 V 1 kHz, VOUT = 3.3 V 1 1.2 1.7 +50 +100 0.1 30 125 450 67 53 0.4 1 100 °C μA mV mV V V μA nA μVrms μVrms dB dB Accuracy when OUT is connected directly to ADJ. When OUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of resistors used. 2 Based on an end-point calculation using 10 mA and 500 mA loads. See Figure 8 for typical load regulation performance for loads less than 10 mA. 3 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.5 V. 4 Start-up time is defined as the time between the rising edge of EN to OUT being at 95% of its nominal value. 5 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V. Rev. 0 | Page 3 of 20 ADP1715/ADP1716 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter IN to GND OUT to GND EN to GND SS/ADJ/TRK to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating –0.3 V to +6 V –0.3 V to IN –0.3 V to +6 V –0.3 V to +6 V –65°C to +150°C –40°C to +125°C JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 8-Lead MSOP ESD CAUTION Rev. 0 | Page 4 of 20 θJA 118 Unit °C/W ADP1715/ADP1716 OUT 3 SS 4 ADP1715 FIXED TOP VIEW (Not to Scale) 8 GND EN 1 7 GND IN 2 6 GND OUT 3 5 GND ADJ 4 Figure 4. 8-Lead MSOP (RM-Suffix) ADP1715 ADJUSTABLE TOP VIEW (Not to Scale) 8 GND EN 1 7 GND IN 2 6 GND OUT 3 5 GND 06110-005 IN 2 06110-004 EN 1 Figure 5. 8-Lead MSOP (RM-Suffix) TRK 4 8 GND ADP1716 7 GND TOP VIEW (Not to Scale) 6 GND 5 GND 06110-006 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. 8-Lead MSOP (RM-Suffix) Table 4. Pin Function Descriptions ADP1715 Fixed Pin No. 1 ADP1715 Adjustable Pin No. 1 ADP1716 Pin No. 1 Mnemonic EN 2 3 2 3 2 3 IN OUT 4 SS ADJ TRK 5, 6, 7, 8 GND 4 4 5, 6, 7, 8 5, 6, 7, 8 Description Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For automatic startup, connect EN to IN. Regulator Input Supply. Bypass IN to GND with a 2.2 μF or greater capacitor. Regulated Output Voltage. Bypass OUT to GND with a 2.2 μF or greater capacitor. Soft Start. A capacitor connected to this pin determines the soft-start time. Adjust. A resistor divider from OUT to ADJ sets the output voltage. Track. The output will follow the voltage placed on the TRK pin. (See the Theory of Operation section for a more detailed description.) Ground. Rev. 0 | Page 5 of 20 ADP1715/ADP1716 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.8 V, IOUT = 10 mA, CIN = 2.2 μF, COUT = 2.2 μF, TA = 25°C, unless otherwise noted. 500 3.364 3.354 450 3.344 ILOAD = 100mA ILOAD = 10mA 3.314 350 IGND (µA) ILOAD = 100µA 3.304 3.294 3.284 3.274 ILOAD = 360mA 3.254 200 ILOAD = 100mA 06110-007 3.234 –5 25 ILOAD = 10mA 100 ILOAD = 250mA 3.244 –40 ILOAD = 250mA 250 150 ILOAD = 500mA 3.264 ILOAD = 360mA 300 85 ILOAD = 100µA 50 0 125 –40 –5 TJ (°C) 25 85 06110-010 3.324 VOUT (V) ILOAD = 500mA 400 3.334 125 TJ (°C) Figure 7. Output Voltage vs. Junction Temperature Figure 10. Ground Current vs. Junction Temperature 500 3.325 450 3.315 400 350 IGND (µA) 3.295 3.285 250 200 150 100 06110-008 3.275 3.265 0.1 300 1 10 50 0 0.1 1000 100 06110-011 VOUT (V) 3.305 1 ILOAD (mA) 10 100 1000 ILOAD (mA) Figure 8. Output Voltage vs. Load Current Figure 11. Ground Current vs. Load Current 3.325 600 3.315 500 ILOAD = 100µA ILOAD = 500mA 400 3.295 IGND (µA) ILOAD = 10mA ILOAD = 100mA ILOAD = 360mA 300 ILOAD = 250mA ILOAD = 250mA 200 3.265 3.3 ILOAD = 360mA ILOAD = 500mA 3.275 3.8 4.3 4.8 ILOAD = 100mA ILOAD = 10mA 100 5.3 VIN (V) ILOAD = 100µA 0 3.3 3.8 4.3 4.8 VIN (V) Figure 9. Output Voltage vs. Input Voltage Figure 12. Ground Current vs. Input Voltage Rev. 0 | Page 6 of 20 5.3 06110-012 3.285 06110-009 VOUT (V) 3.305 ADP1715/ADP1716 350 5V/DIV 1 2 SWITCH SIGNAL TO CHANGE OUTPUT LOAD FROM 25mA TO 475mA 200 150 100 VIN = 5V VOUT = 3.3V CIN = 2.2µF COUT = 2.2µF 06110-013 50 VOUT 0 0.1 1 10 1000 100 ILOAD (mA) 06110-034 VDROPOUT (mV) 250 50mV/DIV 300 TIME (10µs/DIV) Figure 13. Dropout Voltage vs. Load Current Figure 16. Load Transient Response 3.35 1 2 SWITCH SIGNAL TO CHANGE OUTPUT LOAD FROM 25mA TO 475mA 3.15 ILOAD = 100µA ILOAD = 10mA ILOAD = 100mA ILOAD = 250mA ILOAD = 360mA ILOAD = 500mA 3.05 3.00 2.95 3.2 3.3 3.4 VOUT VIN = 5V VOUT = 3.3V CIN = 22µF COUT = 22µF 3.6 3.5 VIN (V) 06110-035 3.10 06110-014 VOUT (V) 3.20 5V/DIV 3.25 50mV/DIV 3.30 TIME (10µs/DIV) Figure 17. Load Transient Response Figure 14. Output Voltage vs. Input Voltage (in Dropout) 700 ILOAD = 500mA 600 ILOAD = 360mA 2V/DIV ILOAD = 250mA 300 ILOAD = 100mA 0 3.20 ILOAD = 100µA 3.25 ILOAD = 10mA 3.30 3.35 3.40 3.45 3.50 3.55 3.60 VIN (V) 2 VIN = 5V VOUT = 3.3V CIN = 2.2µF COUT = 2.2µF ILOAD = 500mA 06110-036 100 1 VOUT 200 20mV/DIV 400 VIN STEP FROM 4V TO 5V 06110-015 IGND (µA) 500 TIME (100µs/DIV) Figure 18. Line Transient Response Figure 15. Ground Current vs. Input Voltage (in Dropout) Rev. 0 | Page 7 of 20 18 0 16 –10 14 –20 VRIPPLE = 50mV p-p VIN = 5V VOUT = 0.75V COUT = 2.2µF ILOAD = 10mA –30 12 PSRR (dB) 10 8 –40 –50 –60 6 –70 4 06110-018 –80 2 0 0 5 10 15 20 06110-020 RAMP-UP TIME (ms) ADP1715/ADP1716 –90 –100 10 25 100 1k CSS (nF) –10 –20 –40 –40 PSRR (dB) –30 –50 –60 –60 –70 –80 –80 –90 100 1k 10k 100k 1M 10M FREQUENCY (Hz) VRIPPLE = 50mV p-p VIN = 5V VOUT = 0.75V COUT = 2.2µF ILOAD = 100mA –50 –70 06110-037 PSRR (dB) 10M 0 VRIPPLE = 50mV p-p VIN = 5V VOUT = 0.75V COUT = 2.2µF ILOAD = 100µA –30 –100 10 1M 06110-038 0 –20 100k Figure 21. Power Supply Rejection Ratio vs. Frequency Figure 19. Output Voltage Ramp-Up Time vs. Soft-Start Capacitor Value –10 10k FREQUENCY (Hz) –90 –100 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 20. Power Supply Rejection Ratio vs. Frequency Figure 22. Power Supply Rejection Ratio vs. Frequency Rev. 0 | Page 8 of 20 10M ADP1715/ADP1716 0 –20 –10 –20 PSRR (dB) –30 –40 –50 –50 –60 –70 –70 –80 –90 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) –20 VRIPPLE = 50mV p-p VIN = 5V VOUT = 3.3V COUT = 2.2µF ILOAD = 10mA –30 –40 –50 –60 06110-019 –70 –80 –90 10 100 1k 10k 100k –90 10 100 1k 10k 100k 1M Figure 25. Power Supply Rejection Ratio vs. Frequency 0 –10 –80 FREQUENCY (Hz) Figure 23. Power Supply Rejection Ratio vs. Frequency PSRR (dB) –40 –60 06110-039 PSRR (dB) –30 VRIPPLE = 50mV p-p VIN = 5V VOUT = 3.3V COUT = 2.2µF ILOAD = 100mA 06110-040 –10 0 VRIPPLE = 50mV p-p VIN = 5V VOUT = 3.3V COUT = 2.2µF ILOAD = 100µA 1M 10M FREQUENCY (Hz) Figure 24. Power Supply Rejection Ratio vs. Frequency Rev. 0 | Page 9 of 20 10M ADP1715/ADP1716 THEORY OF OPERATION The ADP1715/ADP1716 are low dropout, CMOS linear regulators that use an advanced, proprietary architecture to provide high power supply rejection ratio (PSRR) and excellent line and load transient response with just a small 2.2 μF ceramic output capacitor. Both devices operate from a 2.5 V to 5.5 V input rail and provide up to 500 mA of output current. Supply current in shutdown mode is typically 100 nA. IN TSS = VREF × (CSS/ISS) (1) where: TSS is the soft-start period. VREF is the 0.8 V reference voltage. CSS is the soft-start capacitance from SS to GND. ISS is the current sourced from SS (1.2 μA). OUT CURRENT LIMIT THERMAL PROTECT When the ADP1715 is disabled (using EN), the soft-start capacitor is discharged to GND through an internal 100 Ω resistor. SHUTDOWN The ADP1715 is available in two versions, one with fixed output voltage options and one with an adjustable output voltage. The fixed output voltage options are set internally to one of sixteen values between 0.75 V and 3.3 V, using an internal feedback network. The adjustable output voltage can be set to between 0.8 V and 5.0 V by an external voltage divider connected from OUT to ADJ. The fixed output version of ADP1715 allows for connection of an external soft-start capacitor, which controls the output voltage ramp during startup. The ADP1716 features a track pin and is available with fixed output voltage options. All devices are controlled by an enable pin (EN). 1 VIN = 5V VOUT = 3.3V COUT = 2.2µF CSS = 22nF ILOAD = 500mA 2 06110-041 OUT 1V/DIV Internally, the ADP1715/ADP1716 consist of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. 2V/DIV Figure 26. Internal Block Diagram TIME (4ms/DIV) Figure 27. OUT Ramp-Up with External Soft-Start Capacitor The ADP1715 adjustable version and the ADP1716 have no pins for soft start, so the function is switched to an internal softstart capacitor. This sets the soft-start ramp-up period to approximately 24 μs. For the worst-case output voltage of 5 V, using the suggested 2.2 μF output capacitor, the resulting input inrush current is approximately 460 mA, which is less than the maximum 500 mA load current. EN 2V/DIV GND EN 1 1V/DIV SOFT START REFERENCE SS/ ADJ/ TRK 06110-021 EN connect a small ceramic capacitor from SS to GND. Upon startup, a 1.2 μA current source charges this capacitor. The ADP1715 start-up output voltage is limited by the voltage at SS, providing a smooth ramp up to the nominal output voltage. The soft-start time is calculated by 2 For applications that require a controlled startup, the ADP1715 provides a programmable soft-start function. Programmable soft start is useful for reducing inrush current upon startup and for providing voltage sequencing. To implement soft start, Rev. 0 | Page 10 of 20 VIN = 5V VOUT = 1.6V COUT = 2.2µF ILOAD = 10mA OUT TIME (20µs/DIV) Figure 28. OUT Ramp-Up with Internal Soft-Start 06110-042 SOFT-START FUNCTION (ADP1715) ADP1715/ADP1716 ADJUSTABLE OUTPUT VOLTAGE (ADP1715 ADJUSTABLE) ENABLE FEATURE The ADP1715 adjustable version can have its output voltage set over a 0.8 V to 5.0 V range. The output voltage is set by connecting a resistive voltage divider from OUT to ADJ. The output voltage is calculated using the equation VOUT = 0.8 V (1 + R1/R2) The ADP1715/ADP1716 use the EN pin to enable and disable the OUT pin under normal operating conditions. As shown in Figure 30, when a rising voltage on EN crosses the active threshold, OUT turns on. When a falling voltage on EN crosses the inactive threshold, OUT turns off. (2) where: The maximum bias current into ADJ is 100 nA, so for less than 0.5% error due to the bias current, use values less than 60 kΩ for R2. TRACK MODE (ADP1716) The ADP1716 includes a tracking mode feature. As shown in Figure 29, if the voltage applied at the TRK pin is less than the nominal output voltage, OUT is equal to the voltage at TRK. Otherwise, OUT regulates to its nominal output value. 4 1 OUT VIN = 5V VOUT = 1.6V COUT = 2.2µF ILOAD = 10mA TIME (1ms/DIV) Figure 30. ADP1715 Adjustable Typical EN Pin Operation As can be seen, the EN pin has hysteresis built in. This prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. 3 VOUT (V) EN 06110-043 CH1, CH2 (500mV/DIV) R1 is the resistor from OUT to ADJ. R2 is the resistor from ADJ to GND. The EN pin active/inactive thresholds are derived from the IN voltage. Therefore, these thresholds vary with changing input voltage. Figure 31 shows typical EN active/inactive thresholds when the input voltage varies from 2.5 V to 5.5 V. 2 1.4 1 0 1 2 3 4 5 VTRK (V) Figure 29. ADP1716 Output Voltage vs. Tracking Voltage with Nominal Output Voltage Set to 3 V For example, consider an ADP1716 with a nominal output voltage of 3 V. If the voltage applied to its TRK pin is greater than 3 V, OUT maintains a nominal output voltage of 3 V. If the voltage applied to TRK is reduced below 3 V, OUT tracks this voltage. OUT can track the TRK pin voltage from the nominal value all the way down to 0 V. A voltage divider is present from TRK to the error amplifier input with a divider ratio equal to the divider from OUT to the error amplifier. This sets the output voltage equal to the tracking voltage. Both divider ratios are set by post-package trim, depending on the desired output voltage. Rev. 0 | Page 11 of 20 1.2 EN ACTIVE 1.1 HYSTERESIS 1.0 0.9 0.8 0.7 EN INACTIVE 06110-044 0 TYPICAL EN THRESHOLDS (V) 06110-047 1.3 0.6 0.5 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 VIN (V) Figure 31. Typical EN Pin Thresholds vs. Input Voltage ADP1715/ADP1716 APPLICATION INFORMATION CAPACITOR SELECTION Input and Output Capacitor Properties Output Capacitor The ADP1715/ADP1716 are designed for operation with small, space-saving ceramic capacitors, but they will function with most commonly used capacitors as long as care is taken about the effective series resistance (ESR) value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 2.2 μF capacitance with an ESR of 500 mΩ or less is recommended to ensure stability of the ADP1715/ADP1716. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP1715/ADP1716 to large changes in load current. Figure 32 and Figure 33 show the transient responses for output capacitance values of 2.2 μF and 22 μF. Thermal overload protection is included, which limits the junction temperature to a maximum of 150°C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150°C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 135°C, the output is turned on again and output current is restored to its nominal value. 2 VOUT 06110-045 2V/DIV 20mV/DIV 1 TIME (2µs/DIV) Figure 32. Output Transient Response Consider the case where a hard short from OUT to ground occurs. At first the ADP1715/ADP1716 will current limit, so that only 750 mA is conducted into the short. If self heating of the junction is great enough to cause its temperature to rise above 150°C, thermal shutdown will activate, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 135°C, the output turns on and conducts 750 mA into the short, again causing the junction temperature to rise above 150°C. This thermal oscillation between 135°C and 150°C causes a current oscillation between 750 mA and 0 mA that continues as long as the short remains at the output. 1 2 VOUT 06110-046 20mV/DIV 2V/DIV SWITCH SIGNAL TO CHANGE OUTPUT LOAD FROM 25mA TO 475mA VIN = 5V VOUT = 3.3V CIN = 22µF COUT = 22µF CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION The ADP1715/ADP1716 are protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP1715/ADP1716 are designed to current limit when the output load reaches 750 mA (typical). When the output load exceeds 750 mA, the output voltage is reduced to maintain a constant current limit. SWITCH SIGNAL TO CHANGE OUTPUT LOAD FROM 25mA TO 475mA VIN = 5V VOUT = 3.3V CIN = 2.2µF COUT = 2.2µF Any good quality ceramic capacitors can be used with the ADP1715/ADP1716, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. TIME (2µs/DIV) Figure 33. Output Transient Response Input Bypass Capacitor Connecting a 2.2 μF capacitor from the IN pin to GND reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces, or high source impedance, is encountered. If greater than 2.2 μF of output capacitance is required, the input capacitor should be increased to match it. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation should be externally limited so junction temperatures do not exceed 125°C. THERMAL CONSIDERATIONS To guarantee reliable operation, the junction temperature of the ADP1715/ADP1716 should not exceed 125°C. To ensure the junction temperature stays below this maximum value, the user Rev. 0 | Page 12 of 20 ADP1715/ADP1716 140 DO NOT OPERATE ABOVE THIS POINT 120 MAX TJ 100 TJ (°C) should be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (θJA). The θJA number is dependent on the package assembly compounds used and the amount of copper to which the GND pins of the package are soldered to on the PCB. Table 5 shows typical θJA values of the 8-lead thermally enhanced MSOP package for various PCB copper sizes. 60 40 2 Copper Size (mm ) 01 100 300 500 700 1mA 10mA θJA (°C/W) 118 99 77 75 74 250mA 360mA 500mA (LOAD CURRENT) 0 0 1 2 3 4 5 VIN – VOUT (V) Figure 34. 700 mm2 of PCB Copper, TA = 25°C 140 DO NOT OPERATE ABOVE THIS POINT 120 Device soldered to minimum size pin traces. MAX TJ (3) TJ (°C) 100 The junction temperature of the ADP1715/ADP1716 can be calculated from the following equation: TJ = TA + (PD × θJA) 50mA 100mA 06110-022 20 Table 5. 1 80 80 60 where: 40 TA is the ambient temperature. PD is the power dissipation in the die, given by 1mA 10mA (4) 50mA 100mA 250mA 360mA 06110-023 PD = [(VIN – VOUT) × ILOAD] + (VIN × IGND) 20 500mA (LOAD CURRENT) 0 0 1 2 3 4 5 VIN – VOUT (V) where: Figure 35. 300 mm2 of PCB Copper, TA = 25°C ILOAD is the load current. IGND is ground current. VIN and VOUT are input and output voltages, respectively. 140 DO NOT OPERATE ABOVE THIS POINT 120 MAX TJ (5) As shown in Equation 5, for a given ambient temperature, input to output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure the junction temperature does not rise above 125°C. The following figures show junction temperature calculations for different ambient temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper. Rev. 0 | Page 13 of 20 80 60 40 20 1mA 10mA 50mA 100mA 250mA 360mA 06110-024 TJ = TA + {[(VIN – VOUT) × ILOAD] × θJA} 100 TJ (°C) Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to the following: 500mA (LOAD CURRENT) 0 0 1 2 3 4 VIN – VOUT (V) Figure 36. 100 mm2 of PCB Copper, TA = 25°C 5 ADP1715/ADP1716 140 140 DO NOT OPERATE ABOVE THIS POINT DO NOT OPERATE ABOVE THIS POINT 120 120 MAX TJ 100 80 80 TJ (°C) 60 40 60 40 50mA 100mA 250mA 360mA 500mA (LOAD CURRENT) 0 0 1 2 3 4 20 1mA 10mA 5 0 500mA (LOAD CURRENT) 1 2 3 4 5 VIN – VOUT (V) Figure 37. 0 mm2 of PCB Copper, TA = 25°C Figure 40. 100 mm2 of PCB Copper, TA = 50°C 140 140 DO NOT OPERATE ABOVE THIS POINT DO NOT OPERATE ABOVE THIS POINT 120 120 MAX TJ MAX TJ 100 100 80 80 TJ (°C) 60 40 60 40 1mA 10mA 50mA 100mA 250mA 360mA 500mA (LOAD CURRENT) 0 0 1 2 3 4 20 06110-026 20 1mA 10mA 50mA 100mA 250mA 360mA 06110-029 TJ (°C) 250mA 360mA 0 VIN – VOUT (V) 500mA (LOAD CURRENT) 0 5 0 1 VIN – VOUT (V) 2 3 4 5 VIN – VOUT (V) Figure 38. 700 mm2 of PCB Copper, TA = 50°C Figure 41. 0 mm2 of PCB Copper, TA = 50°C 140 140 DO NOT OPERATE ABOVE THIS POINT DO NOT OPERATE ABOVE THIS POINT 120 120 MAX TJ MAX TJ 100 80 80 TJ (°C) 100 60 40 60 40 20 1mA 10mA 50mA 100mA 250mA 360mA 06110-027 TJ (°C) 50mA 100mA 06110-028 1mA 10mA 06110-025 20 500mA (LOAD CURRENT) 0 0 1 2 3 4 5 20 1mA 10mA 250mA 360mA 500mA (LOAD CURRENT) 0 0 VIN – VOUT (V) 50mA 100mA 1 2 3 4 VIN – VOUT (V) Figure 39. 300 mm2 of PCB Copper, TA = 50°C Figure 42. 700 mm2 of PCB Copper, TA = 85°C Rev. 0 | Page 14 of 20 06110-030 TJ (°C) MAX TJ 100 5 ADP1715/ADP1716 140 PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS DO NOT OPERATE ABOVE THIS POINT 120 MAX TJ The 8-lead MSOP package has the four GND pins fused together internally, which enhances its thermal characteristics. Heat dissipation from the package is increased by connecting as much copper as possible to the four GND pins of the ADP1715/ ADP1716. From Table 5 it can be seen that a point of diminishing returns eventually is reached, beyond which an increase in the copper size does not yield additional heat dissipation benefits. TJ (°C) 100 80 60 40 1mA 10mA 50mA 100mA 250mA 360mA 06110-031 20 500mA (LOAD CURRENT) 0 0 1 2 3 4 5 VIN – VOUT (V) 2 Figure 43. 300 mm of PCB Copper, TA = 85°C 140 DO NOT OPERATE ABOVE THIS POINT 120 MAX TJ TJ (°C) 100 Figure 46 shows a typical layout for the ADP1715/ADP1716. The four GND pins are connected to a large copper pad. If a second layer is available, multiple vias can be used to connect them, increasing the overall copper area. The input capacitor should be placed as close as possible to the IN and GND pins. The output capacitor should be placed as close as possible to the OUT and GND pins. 0603 or 0402 size capacitors and resistors should be used to achieve the smallest possible footprint solution on boards where area is limited. 80 GND (TOP) 60 40 1mA 10mA 50mA 100mA 250mA 360mA 06110-032 20 500mA (LOAD CURRENT) 0 0 1 2 3 4 ADP1715/ ADP1716 C1 5 C2 VIN – VOUT (V) Figure 44. 100 mm2 of PCB Copper, TA = 85°C IN 140 OUT DO NOT OPERATE ABOVE THIS POINT 120 MAX TJ R1 80 C3 60 R2 06110-048 EN GND (BOTTOM) 40 Figure 46. Example PCB Layout 20 1mA 10mA 50mA 100mA 250mA 360mA 06110-033 TJ (°C) 100 500mA (LOAD CURRENT) 0 0 1 2 3 4 5 VIN – VOUT (V) Figure 45. 0 mm2 of PCB Copper, TA = 85°C Rev. 0 | Page 15 of 20 ADP1715/ADP1716 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5 5.15 4.90 4.65 4 PIN 1 0.65 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 47. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions show in millimeters Rev. 0 | Page 16 of 20 0.80 0.60 0.40 ADP1715/ADP1716 ORDERING GUIDE Model ADP1715ARMZ-0.75R71 ADP1715ARMZ-0.8-R71 ADP1715ARMZ-0.85R71 ADP1715ARMZ-0.9-R71 ADP1715ARMZ-0.95R71 ADP1715ARMZ-1.0-R71 ADP1715ARMZ-1.05R71 ADP1715ARMZ-1.1-R71 ADP1715ARMZ-1.15R71 ADP1715ARMZ-1.2-R71 ADP1715ARMZ-1.3-R71 ADP1715ARMZ-1.5-R71 ADP1715ARMZ-1.8-R71 ADP1715ARMZ-2.5-R71 ADP1715ARMZ-3.0-R71 ADP1715ARMZ-3.3-R71 ADP1715ARMZ-R71 ADP1716ARMZ-0.75R7 1 ADP1716ARMZ-0.8-R71 ADP1716ARMZ-0.85R71 ADP1716ARMZ-0.9-R71 ADP1716ARMZ-0.95R71 ADP1716ARMZ-1.0-R71 ADP1716ARMZ-1.05R71 ADP1716ARMZ-1.1-R71 ADP1716ARMZ-1.15R71 ADP1716ARMZ-1.2-R71 ADP1716ARMZ-1.3-R71 ADP1716ARMZ-1.5-R71 ADP1716ARMZ-1.8-R71 ADP1716ARMZ-2.5-R71 ADP1716ARMZ-3.0-R71 ADP1716ARMZ-3.3-R71 1 Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Output Voltage (V) 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.30 1.50 1.80 2.50 3.00 3.30 0.8 to 5.0 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.30 1.50 1.80 2.50 3.00 3.30 Z = Pb-free part. Rev. 0 | Page 17 of 20 Package Description 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Package Option RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding L29 L2A L2C L2D L2E L2F L2G L2H L2J L2K L32 L2L L3R L33 L34 L35 L3K L2N L2P L2Q L2R L2S L2T L3D L2U L2 V L2W L2X L2Y L31 L37 L38 L39 ADP1715/ADP1716 NOTES Rev. 0 | Page 18 of 20 ADP1715/ADP1716 NOTES Rev. 0 | Page 19 of 20 ADP1715/ADP1716 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06110-0-9/06(0) Rev. 0 | Page 20 of 20