2 A, Low VIN, Low Dropout
Linear Regulator
ADP1740/ADP1741
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUITS
VIN = 1.8V
VOUT = 1.5V
4.7µF
4.7µF
16
VIN
1 VIN
100kΩ
VOUT 12
ADP1740
2 VIN
VOUT 11
TOP VIEW
(Not to Scale)
3 VIN
VOUT 10
PG
4 EN
SENSE 9
GND
6
SS
7
NC
8
07081-001
PG
5
10nF
Figure 1. ADP1740 with Fixed Output Voltage, 1.5 V
VIN = 1.8V
VOUT = 0.5V(1 + R1/R2)
4.7µF
4.7µF
16
VIN
13
14
15
VIN VOUT VOUT
1 VIN
100kΩ
APPLICATIONS
VOUT 12
ADP1741
2 VIN
TOP VIEW
(Not to Scale)
3 VIN
Server computers
Memory components
Telecommunications equipment
Network equipment
DSP/FPGA/microprocessor supplies
Instrumentation equipment/data acquisition systems
13
14
15
VIN VOUT VOUT
VOUT 11
VOUT 10
R1
PG
4 EN
ADJ 9
PG
5
GND
6
SS
7
NC
8
R2
10nF
07081-002
Maximum output current: 2 A
Input voltage range: 1.6 V to 3.6 V
Low shutdown current: 2 µA
Low dropout voltage: 160 mV at 2 A load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2%
7 fixed output voltage options with soft start:
0.75 V to 2.5 V (ADP1740)
Adjustable output voltage options with soft start:
0.75 V to 3.3 V (ADP1741)
High PSRR
65 dB at 1 kHz
65 dB at 10 kHz
54 dB at 100 kHz
23 μV rms at 0.75 V output
Stable with small 4.7 µF ceramic output capacitor
Excellent load and line transient response
Current-limit and thermal overload protection
Power-good indicator
Logic-controlled enable
Reverse current protection
Figure 2. ADP1741 with Adjustable Output Voltage, 0.75 V to 3.3 V
GENERAL DESCRIPTION
The ADP1740/ADP1741 are low dropout (LDO) CMOS linear
regulators that operate from 1.6 V to 3.6 V and provide up to 2 A
of output current. These low VIN/VOUT LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5 V down
to 1.8 V I/O rails, and for powering core voltages down to 0.75 V.
Using an advanced, proprietary architecture, the ADP1740/
ADP1741 provide high power supply rejection ratio (PSRR) and
low noise, and achieve excellent line and load transient response
with only a small 4.7 µF ceramic output capacitor.
The ADP1740 is available in seven fixed output voltage options.
The ADP1741 is an adjustable version that allows output
Rev. H
voltages ranging from 0.75 V to 3.3 V via an external divider.
The ADP1740/ADP1741 allow an external soft start capacitor
to be connected to program the startup. A digital power-good
output allows power system monitors to check the health of the
output voltage.
The ADP1740/ADP1741 are available in a 16-lead, 4 mm ×
4 mm LFCSP, making them not only very compact solutions,
but also providing excellent thermal performance for applications that require up to 2 A of output current in a small, low
profile footprint.
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ADP1740/ADP1741
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Soft Start Function ..................................................................... 11
Applications ....................................................................................... 1
Adjustable Output Voltage (ADP1741) ................................... 12
Typical Application Circuits............................................................ 1
Enable Feature ............................................................................ 12
General Description ......................................................................... 1
Power-Good Feature .................................................................. 12
Revision History ............................................................................... 2
Reverse Current Protection Feature ........................................ 13
Specifications..................................................................................... 3
Applications Information .............................................................. 14
Input and Output Capacitor, Recommended Specifications .. 4
Capacitor Selection .................................................................... 14
Absolute Maximum Ratings ............................................................ 5
Undervoltage Lockout ............................................................... 15
Thermal Data ................................................................................ 5
Current-Limit and Thermal Overload Protection ................. 15
Thermal Resistance ...................................................................... 5
Thermal Considerations............................................................ 15
ESD Caution .................................................................................. 5
PCB Layout Considerations ...................................................... 17
Pin Configurations and Function Descriptions ........................... 6
Outline Dimensions ....................................................................... 19
Typical Performance Characteristics ............................................. 7
Ordering Guide .......................................................................... 19
Theory of Operation ...................................................................... 11
REVISION HISTORY
1/15—Rev. G to Rev. H
Changes to Ordering Guide .......................................................... 19
4/14—Rev. F to Rev. G
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Figure 3 and Figure 4 ................................................... 6
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
8/13—Rev. E to Rev. F
Changes to Ordering Guide .......................................................... 19
6/13—Rev. D to Rev. E
Changed Adjustable Output Voltage Option with Soft Start
(ADP1755) from 0.75 V to 3.0 V to 0.75 V to 3.3 V
(Throughout) .................................................................................... 1
Updated Outline Dimensions ....................................................... 19
12/12—Rev. C to Rev. D
Added Junction Temperature of 150°C, Table 3 ........................... 5
Changes to Ordering Guide .......................................................... 19
9/12—Rev. B to Rev. C
Changes to Table 3 ............................................................................ 5
Changes to Ordering Guide .......................................................... 19
2/10—Rev. A to Rev. B
Changes to Table 4 ............................................................................ 5
Changes to Ordering Guide .......................................................... 19
4/09—Rev. 0 to Rev. A
Changes to Table 3 ............................................................................ 5
10/08—Revision 0: Initial Version
Rev. H | Page 2 of 20
Data Sheet
ADP1740/ADP1741
SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 1.6 V (whichever is greater), IOUT = 100 mA, CIN = COUT = 4.7 µF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT1
Symbol
VIN
IGND
SHUTDOWN CURRENT
IGND-SD
OUTPUT VOLTAGE ACCURACY
Fixed Output Voltage Accuracy
(ADP1740)
VOUT
Adjustable Output Voltage
Accuracy (ADP1741)2
LINE REGULATION
LOAD REGULATION3
DROPOUT VOLTAGE4
VADJ
∆VOUT/∆VIN
∆VOUT/∆IOUT
VDROPOUT
START-UP TIME5
tSTART-UP
CURRENT-LIMIT THRESHOLD6
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
ILIMIT
PG OUTPUT LOGIC LEVEL
PG Output Logic High
PG Output Logic Low
PG Output Delay from EN
Transition, Low to High
PG OUTPUT THRESHOLD
Output Voltage Falling
Output Voltage Rising
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Leakage Current
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
SOFT START CURRENT
ADJ INPUT BIAS CURRENT
(ADP1741)
Test Conditions/Comments
TJ = −40°C to +125°C
IOUT = 500 µA
IOUT = 100 mA
IOUT = 100 mA, TJ = −40°C to +125°C
IOUT = 2 A
IOUT = 2 A, TJ = −40°C to +125°C
EN = GND, VIN = 3.6 V
EN = GND, VIN = 1.6 V, TJ = −40°C to +85°C
EN = GND, VIN = 3.6 V, TJ = −40°C to +85°C
Min
1.6
IOUT = 100 mA
IOUT = 10 mA to 2 A
10 mA < IOUT < 2 A, TJ = −40°C to +125°C
IOUT = 100 mA
IOUT = 10 mA to 2 A
10 mA < IOUT < 2 A, TJ = −40°C to +125°C
VIN = (VOUT + 0.4 V) to 3.6 V, TJ = −40°C to +125°C
IOUT = 10 mA to 2 A, TJ = −40°C to +125°C
IOUT = 100 mA, VOUT ≥ 1.8 V
IOUT = 100 mA, VOUT ≥ 1.8 V, TJ = −40°C to +125°C
IOUT = 2 A, VOUT ≥ 1.8 V
IOUT = 2 A, VOUT ≥ 1.8 V, TJ = −40°C to +125°C
CSS = 0 nF, IOUT = 10 mA
CSS = 10 nF, IOUT = 10 mA
−1
−1.5
−2
0.495
0.492
0.490
−0.3
TJ rising
PGHIGH
PGLOW
1.6 V ≤ VIN ≤ 3.6 V, IOH < 1 µA
1.6 V ≤ VIN ≤ 3.6 V, IOL < 2 mA
1.6 V ≤ VIN ≤ 3.6 V, CSS = 10 nF
Max
3.6
90
400
800
1.5
2
0.5
1.8
6
30
100
+1
+1.5
+2
0.505
0.508
0.510
+0.3
0.5
10
18
160
280
2.4
TSSD
TSSD-HYS
Typ
200
5.2
3
5
1.6 V ≤ VIN ≤ 3.6 V
1.6 V ≤ VIN ≤ 3.6 V
VIH
VIL
VI-LEAKAGE
UVLO
UVLORISE
UVLOFALL
UVLOHYS
ISS
ADJI-BIAS
1.6 V ≤ VIN ≤ 3.6 V
1.6 V ≤ VIN ≤ 3.6 V
EN = VIN or GND
1.0
5.5
V
V
ms
−10
−6.5
%
%
0.4
1.2
0.1
0.4
1
1.58
1.25
1.6 V ≤ VIN ≤ 3.6 V
1.6 V ≤ VIN ≤ 3.6 V, TJ = −40°C to +125°C
Rev. H | Page 3 of 20
0.6
%
%
%
V
V
V
%/V
%/A
mV
mV
mV
mV
µs
ms
A
°C
°C
150
15
PGFALL
PGRISE
Unit
V
µA
µA
µA
mA
mA
µA
µA
µA
100
0.9
10
1.2
150
V
V
µA
V
V
mV
µA
nA
ADP1740/ADP1741
Data Sheet
Parameter
SENSE INPUT BIAS CURRENT
(ADP1740)
OUTPUT NOISE
Symbol
SNSI-BIAS
Test Conditions/Comments
1.6 V ≤ VIN ≤ 3.6 V
OUTNOISE
POWER SUPPLY REJECTION RATIO
PSRR
10 Hz to 100 kHz, VOUT = 0.75 V
10 Hz to 100 kHz, VOUT = 2.5 V
VIN = VOUT + 1 V, IOUT = 10 mA
1 kHz, VOUT = 0.75 V
1 kHz, VOUT = 2.5 V
10 kHz, VOUT = 0.75 V
10 kHz, VOUT = 2.5 V
100 kHz, VOUT = 0.75 V
100 kHz, VOUT = 2.5 V
Min
Typ
10
Max
Unit
µA
23
65
µV rms
µV rms
65
56
65
56
54
51
dB
dB
dB
dB
dB
dB
Minimum output load current is 500 μA.
Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances
of the resistors used.
3
Based on an endpoint calculation using 10 mA and 2 A loads. See Figure 6 for typical load regulation performance.
4
Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages
above 1.6 V.
5
Start-up time is defined as the time between the rising edge of EN to VOUT being at 95% of its nominal value.
6
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
1
2
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
MINIMUM INPUT AND OUTPUT CAPACITANCE1
CAPACITOR ESR
1
Symbol
CMIN
RESR
Test Conditions/Comments
TA = –40°C to +125°C
TA = –40°C to +125°C
Min
3.3
0.001
Typ
Max
0.1
Unit
µF
Ω
The minimum input and output capacitance should be greater than 3.3 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during capacitor selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with this LDO.
Rev. H | Page 4 of 20
Data Sheet
ADP1740/ADP1741
ABSOLUTE MAXIMUM RATINGS
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in × 3 in circuit
board. Refer to JEDEC JESD51-7 for detailed information about
board construction. For more information, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
SS to GND
PG to GND
SENSE/ADJ to GND
Storage Temperature Range
Junction Temperature Range
Junction Temperature
Soldering Conditions
Rating
−0.3 V to +4.0 V
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to +4.0 V
−0.3 V to VIN
−65°C to +150°C
−40°C to +125°C
150°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply only individually, not in
combination. The ADP1740/ADP1741 may be damaged when
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that the junction temperature is
within the specified temperature limits. In applications with
high power dissipation and poor PCB thermal resistance, the
maximum ambient temperature may need to be derated. In
applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits.
The junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA). TJ is calculated using the following formula:
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JEDEC JESD51-12
document, Guidelines for Reporting and Using Electronic Package
Thermal Information, states that thermal characterization
parameters are not the same as thermal resistances. ΨJB measures
the component power flowing through multiple thermal paths
rather than through a single path, as in thermal resistance (θJB).
Therefore, ΨJB thermal paths include convection from the top of
the package, as well as radiation from the package, factors that
make ΨJB more useful in real-world applications. Maximum
junction temperature (TJ) is calculated from the board temperature (TB) and the power dissipation (PD) using the following
formula:
TJ = TB + (PD × ΨJB)
Refer to the JEDEC JESD51-8 and JESD51-12 documents for
more detailed information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
16-Lead LFCSP with Exposed Pad
ESD CAUTION
TJ = TA + (PD × θJA)
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
Rev. H | Page 5 of 20
θJA
42
ΨJB
25.5
Unit
°C/W
ADP1740/ADP1741
Data Sheet
13 VOUT
14 VOUT
16 VIN
15 VIN
VIN 1
12 VOUT
VIN 1
VIN 2
ADP1740
11 VOUT
VIN 2
ADP1741
11 VOUT
VIN 3
TOP VIEW
10 VOUT
VIN 3
TOP VIEW
10 VOUT
9
EN 4
SS 7
ADJ
NC 8
GND 6
9
PG 5
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
07081-003
SS 7
SENSE
NC 8
PG 5
GND 6
EN 4
12 VOUT
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
Figure 3. ADP1740 Pin Configuration
07081-004
13 VOUT
14 VOUT
16 VIN
15 VIN
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADP1741 Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
ADP1740
ADP1741
1, 2, 3, 15, 16 1, 2, 3, 15, 16
Mnemonic
VIN
4
4
EN
5
5
PG
6
7
8
9
6
7
8
GND
SS
NC
SENSE
9
10, 11, 12,
13, 14
EP
ADJ
VOUT
10, 11, 12,
13, 14
EP
Exposed
pad
Description
Regulator Input Supply. Bypass VIN to GND with a 4.7 μF or greater capacitor. Note that all
five VIN pins must be connected to the source supply.
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For
automatic startup, connect EN to VIN.
Power-Good Output. This open-drain output requires an external pull-up resistor to VIN. If
the part is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below
90% of the nominal output voltage, the PG pin immediately transitions low.
Ground.
Soft Start Pin. A capacitor connected to this pin determines the soft start time.
Not Connected. No internal connection.
Sense Input. This pin measures the actual output voltage at the load and feeds it to the error
amplifier. Connect the SENSE pin as close to the load as possible to minimize the effect of IR
drop between the regulator output and the load.
Adjust Pin. A resistor divider from VOUT to ADJ sets the output voltage.
Regulated Output Voltage. Bypass VOUT to GND with a 4.7 μF or greater capacitor. Note that
all five VOUT pins must be connected to the load.
The exposed pad on the bottom of the LFCSP enhances thermal performance and is
electrically connected to GND inside the package. It is recommended that the exposed pad
be connected to the ground plane on the board.
Rev. H | Page 6 of 20
Data Sheet
ADP1740/ADP1741
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 1.9 V, VOUT = 1.5 V, IOUT = 100 mA, CIN = COUT = 4.7 µF, TA = 25°C, unless otherwise noted.
1.520
1600
1.505
1.500
1.495
1.490
1.485
1200
1000
LOAD = 800mA
800
LOAD = 400mA
600
LOAD = 100mA
400
LOAD = 10mA
200
–40
–5
25
85
0
07081-005
1.480
125
JUNCTION TEMPERATURE (°C)
–40
25
85
125
Figure 8. Ground Current vs. Junction Temperature
1600
1.515
1400
1.510
1200
GROUND CURRENT (µA)
1.520
1.505
1.500
1.495
1.490
1.485
1000
800
600
400
1k
10k
LOAD CURRENT (mA)
0
10
07081-006
100
100
1k
10k
LOAD CURRENT (mA)
Figure 6. Output Voltage vs. Load Current
07081-009
200
1.480
10
Figure 9. Ground Current vs. Load Current
1600
1.520
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
LOAD = 2A
1.510
1400
LOAD = 2A
GROUND CURRENT (µA)
1.515
1.505
1.500
1.495
1.490
1200
LOAD = 1.2A
1000
800
LOAD = 800mA
600
LOAD = 400mA
400
LOAD = 100mA
1.485
200
2.0
2.2
2.4
2.6
2.8
3.0
3.2
INPUT VOLTAGE (V)
3.4
3.6
Figure 7. Output Voltage vs. Input Voltage
0
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
INPUT VOLTAGE (V)
Figure 10. Ground Current vs. Input Voltage
Rev. H | Page 7 of 20
3.4
3.6
07081-010
LOAD = 10mA
1.480
1.8
07081-007
OUTPUT VOLTAGE (V)
–5
JUNCTION TEMPERATURE (°C)
Figure 5. Output Voltage vs. Junction Temperature
OUTPUT VOLTAGE (V)
LOAD = 1.2A
07081-008
1.510
1400
GROUND CURRENT (µA)
1.515
OUTPUT VOLTAGE (V)
LOAD = 2A
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
LOAD = 2A
ADP1740/ADP1741
Data Sheet
100
4500
1.9V
2.0V
2.4V
2.6V
3.0V
3.6V
70
3500
60
50
40
30
3000
2500
2000
1500
1000
20
500
10
–15
10
35
60
85
TEMPERATURE (°C)
0
2.3
07081-011
0
–40
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
2.4
2.6
2.5
2.8
2.7
INPUT VOLTAGE (V)
Figure 14. Ground Current vs. Input Voltage (in Dropout), VOUT = 2.5 V
0.25
T
ILOAD
DROPOUT VOLTAGE (V)
0.20
1
0.15
1mA TO 2A LOAD STEP, 2.5A/µs, 1A/DIV
1.6V
VOUT
0.10
2
2.5V
50mV/DIV
0.05
10
100
1k
10k
LOAD CURRENT (mA)
CH1 1.0 A Ω BW CH2 50mV
B
W M10µs
A CH1
380mA
T 10.40%
07081-015
1
07081-012
VIN = 3.6V
VOUT = 1.5V
0
Figure 15. Load Transient Response, CIN = 4.7 µF, COUT = 4.7 µF
Figure 12. Dropout Voltage vs. Load Current, VOUT = 1.6 V, 2.5 V
2.50
T
ILOAD
2.40
2.35
1
1mA TO 2A LOAD STEP, 2.5A/µs, 1A/DIV
2.30
VOUT
2.25
2
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
LOAD = 2A
2.10
2.3
2.4
2.5
2.6
INPUT VOLTAGE (V)
2.7
50mV/DIV
VIN = 3.6V
VOUT = 1.5V
2.8
Figure 13. Output Voltage vs. Input Voltage (in Dropout), VOUT = 2.5 V
Rev. H | Page 8 of 20
CH1 1.0 A Ω BW CH2 50mV
B
W
M10µs
A CH1
T 10.20%
880mA
Figure 16. Load Transient Response, CIN = 22 µF, COUT = 22 µF
07081-016
2.15
07081-013
OUTPUT VOLTAGE (V)
2.45
2.20
07081-014
SHUTDOWN CURRENT (µA)
80
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 1.2A
LOAD = 2A
4000
GROUND CURRENT (µA)
90
Data Sheet
ADP1740/ADP1741
0
T
VIN
LOAD = 2A
LOAD = 1.2A
LOAD = 800mA
LOAD = 400mA
LOAD = 100mA
LOAD = 10mA
–10
–20
–30
PSRR (dB)
3V TO 3.5V INPUT VOLTAGE STEP, 2V/µs
VOUT
–40
–50
–60
2
5mV/DIV
–70
–80
B
CH1 500mV BW CH2 5mV
W
M10µs
A CH4
T 9.40%
800mV
–100
10
07081-017
1
10k
1k
100k
1M
10M
FREQUENCY (Hz)
Figure 17. Line Transient Response, Load Current = 2 A
Figure 20. Power Supply Rejection Ratio vs. Frequency,
VOUT = 0.75 V, VIN = 1.75 V
70
0
LOAD = 2A
LOAD = 1.2A
LOAD = 800mA
LOAD = 400mA
LOAD = 100mA
LOAD = 10mA
–10
2.5V
60
–20
50
–30
40
PSRR (dB)
NOISE (µV rms)
100
07081-020
–90
VOUT = 1.5V
CIN = COUT = 4.7µF
1.5V
30
–50
–60
–70
0.75V
20
–40
–80
10
0.001
0.01
1
0.1
10
LOAD CURRENT (A)
–100
10
07081-018
0
0.0001
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 18. Noise vs. Load Current and Output Voltage
Figure 21. Power Supply Rejection Ratio vs. Frequency,
VOUT = 1.5 V, VIN = 2.5 V
10
0
LOAD = 2A
LOAD = 1.2A
LOAD = 800mA
LOAD = 400mA
LOAD = 100mA
LOAD = 10mA
–10
–20
–30
PSRR (dB)
1
1.5V
2.5V
0.1
–40
–50
–60
–70
–80
0.75V
100
1k
10k
100k
FREQUENCY (Hz)
Figure 19. Noise Spectral Density vs. Output Voltage, ILOAD = 10 mA
–100
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 22. Power Supply Rejection Ratio vs. Frequency,
VOUT = 2.5 V, VIN = 3.5 V
Rev. H | Page 9 of 20
10M
07081-022
–90
0.01
10
07081-019
NOISE SPECTRAL DENSITY (µV/ Hz)
100
07081-021
–90
ADP1740/ADP1741
Data Sheet
0
–10
PSRR (dB)
–20
1.5V/2A
2.5V/10mA
0.75V/2A
2.5V/2A
0.75V/10mA
1.5V/10mA
–30
–40
–50
–60
–80
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
07081-048
–70
Figure 23. Power Supply Rejection Ratio vs. Frequency and Output Voltage
Rev. H | Page 10 of 20
Data Sheet
ADP1740/ADP1741
THEORY OF OPERATION
The ADP1740/ADP1741 are low dropout linear regulators
that use an advanced, proprietary architecture to provide high
power supply rejection ratio (PSRR) and excellent line and load
transient response with only a small 4.7 µF ceramic output capacitor. Both devices operate from a 1.6 V to 3.6 V input rail and
provide up to 2 A of output current. Supply current in shutdown
mode is typically 2 µA.
ADP1740
REVERSE POLARITY
PROTECTION
VIN
VOUT
SHORT-CIRCUIT
AND THERMAL
PROTECTION
SENSE
R1
0.5V
REF
PG
R2
tSS = VREF × (CSS/ISS)
PG
DETECT
SS
SHUTDOWN
07081-023
0.9µA
EN
Figure 24. ADP1740 Internal Block Diagram
ADP1741
SOFT START FUNCTION
For applications that require a controlled startup, the ADP1740/
ADP1741 provide a programmable soft start function. The
programmable soft start is useful for reducing inrush current
upon startup and for providing voltage sequencing. To implement
soft start, connect a small ceramic capacitor from SS to GND.
Upon startup, a 0.9 µA current source charges this capacitor.
The ADP1740/ADP1741 start-up output voltage is limited by
the voltage at SS, providing a smooth ramp-up to the nominal
output voltage. The soft start time is calculated as follows:
UVLO
GND
The ADP1740 is available in seven fixed output voltage options
from 0.75 V to 2.5 V. The ADP1740 allows for connection of an
external soft start capacitor, which controls the output voltage
ramp during startup. The ADP1741 is an adjustable version with
an output voltage that can be set to a value from 0.75 V to 3.3 V
by an external voltage divider. Both devices are controlled by an
enable pin (EN).
where:
tSS is the soft start period.
VREF is the 0.5 V reference voltage.
CSS is the soft start capacitance from SS to GND.
ISS is the current sourced from SS (0.9 µA).
When the ADP1740/ADP1741 are disabled (using the EN pin),
the soft start capacitor is discharged to GND through an
internal 100 Ω resistor.
REVERSE POLARITY
PROTECTION
VIN
(1)
VOUT
2.50
UVLO
2.25
EN
2.00
SHORT-CIRCUIT
AND THERMAL
PROTECTION
1.75
ADJ
0.5V
REF
PG
DETECT
1.25
4.7nF
1.00
10nF
0.75
0.9µA
SHUTDOWN
SS
0.50
07081-024
EN
1nF
1.50
Figure 25. ADP1741 Internal Block Diagram
0.25
0
0
Internally, the ADP1740/ADP1741 consist of a reference,
an error amplifier, a feedback voltage divider, and a PMOS
pass transistor. Output current is delivered via the PMOS pass
transistor, which is controlled by the error amplifier. The error
amplifier compares the reference voltage with the feedback
voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the
PMOS device is pulled lower, allowing more current to pass
and increasing the output voltage. If the feedback voltage is
higher than the reference voltage, the gate of the PMOS device
is pulled higher, allowing less current to pass and decreasing the
output voltage.
Rev. H | Page 11 of 20
2
4
6
8
10
TIME (ms)
Figure 26. VOUT Ramp-Up with External Soft Start Capacitor
07081-025
PG
VOLTAGE (V)
GND
ADP1740/ADP1741
T
Data Sheet
The EN pin active/inactive thresholds are derived from the VIN
voltage. Therefore, these thresholds vary with changing input
voltage. Figure 29 shows typical EN active/inactive thresholds
when the input voltage varies from 1.6 V to 3.6 V.
EN
1
1.1
1.0
CH1 2.0V BW
VOUT = 1.5V
CIN = COUT = 4.7µF
CH2 500mV BW M40µs
T 9.8%
A CH1
920mV
Figure 27. VOUT Ramp-Up with Internal Soft Start
0.9
EN ACTIVE
0.8
EN INACTIVE
0.7
0.6
ADJUSTABLE OUTPUT VOLTAGE (ADP1741)
The output voltage of the ADP1741 can be set over a 0.75 V to
3.3 V range. The output voltage is set by connecting a resistive
voltage divider from VOUT to ADJ. The output voltage is calculated using the following equation:
VOUT = 0.5 V × (1 + R1/R2)
(2)
where:
R1 is the resistor from VOUT to ADJ.
R2 is the resistor from ADJ to GND.
The maximum bias current into ADJ is 150 nA, so to achieve less
than 0.5% error due to the bias current, use values less than
60 kΩ for R2.
ENABLE FEATURE
The ADP1740/ADP1741 use the EN pin to enable and disable
the VOUT pins under normal operating conditions. As shown
in Figure 28, when a rising voltage on EN crosses the active
threshold, VOUT turns on. When a falling voltage on EN
crosses the inactive threshold, VOUT turns off.
T
EN
0.5
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
INPUT VOLTAGE (V)
Figure 29. Typical EN Pin Thresholds vs. Input Voltage
POWER-GOOD FEATURE
The ADP1740/ADP1741 provide a power-good pin, PG, to
indicate the status of the output. This open-drain output
requires an external pull-up resistor to VIN. If the part is in
shutdown mode, current-limit mode, or thermal shutdown, or
if it falls below 90% of the nominal output voltage, the powergood pin (PG) immediately transitions low. During soft start,
the rising threshold of the power-good signal is 93.5% of the
nominal output voltage.
The open-drain output is held low when the ADP1740/ADP1741
have sufficient input voltage to turn on the internal PG transistor.
An optional soft start delay can be detected. The PG transistor
is terminated via a pull-up resistor to VOUT or VIN.
Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90% trip point when
this voltage is falling. Regulator input voltage brownouts or
glitches trigger power no-good if VOUT falls below 90%.
A normal power-down triggers power no-good when VOUT
drops below 90%.
VOUT
1
2
VOUT = 1.5V
CIN = COUT = 4.7µF
CH1 500mV BW CH2 500mV BW M2.0ms
T 29.6%
A CH1
1.05V
07081-027
500mV/DIV
07081-028
500mV/DIV
07081-026
2
EN THRESHOLD (V)
VOUT
Figure 28. Typical EN Pin Operation
As shown in Figure 28, the EN pin has hysteresis built in. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.
Rev. H | Page 12 of 20
Data Sheet
ADP1740/ADP1741
REVERSE CURRENT PROTECTION FEATURE
T
VIN
1V/DIV
1
VOUT
500mV/DIV
PG
1V/DIV
2
CH1 1.0V BW
CH3 1.0V BW
CH2 500mV BW M40.0µs A CH3
T 50.40%
900mV
07081-029
VOUT = 1.5V
CIN = COUT = 4.7µF
Figure 30. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.5 V)
The ADP1740/ADP1741 have additional circuitry to protect
against reverse current flow from VOUT to VIN. For a typical
LDO with a PMOS pass device, there is an intrinsic body diode
between VIN and VOUT. When VIN is greater than VOUT, this
diode is reverse-biased. If VOUT is greater than VIN, the intrinsic
diode becomes forward-biased and conducts current from
VOUT to VIN, potentially causing destructive power dissipation.
The reverse current protection circuitry detects when VOUT is
greater than VIN and reverses the direction of the intrinsic diode
connection, reverse-biasing the diode. The gate of the PMOS
pass device is also connected to VOUT, keeping the device off.
Figure 32 shows a plot of the reverse current vs. the VOUT to VIN
differential.
4000
3500
REVERSE CURRENT (µA)
T
VIN
1V/DIV
1
VOUT
500mV/DIV
3000
2500
2000
1500
1000
0
0
VOUT = 1.5V
CIN = COUT = 4.7µF
CH1 1.0V BW
CH3 1.0V BW
CH2 500mV BW M40.0µs A CH3
T 50.40%
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VOUT – VIN (V)
900mV
Figure 32. Reverse Current vs. VOUT − VIN
07081-030
2
Figure 31. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.5 V)
Rev. H | Page 13 of 20
3.3
3.6
07081-132
500
PG
1V/DIV
ADP1740/ADP1741
Data Sheet
APPLICATIONS INFORMATION
Input Bypass Capacitor
CAPACITOR SELECTION
Output Capacitor
The ADP1740/ADP1741 are designed for operation with small,
space-saving ceramic capacitors, but they function with most
commonly used capacitors as long as care is taken with regard
to the effective series resistance (ESR) value. The ESR of the
output capacitor affects the stability of the LDO control loop. A
minimum of 3.3 µF capacitance with an ESR of 100 mΩ or less is
recommended to ensure the stability of the ADP1740/ADP1741.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP1740/ADP1741 to
large changes in load current. Figure 33 and Figure 34 show the
transient responses for output capacitance values of 4.7 µF and
22 µF, respectively.
ILOAD
1A/DIV
T
1mA TO 2A LOAD STEP, 2.5A/µs
1
VOUT
50mV/DIV
2
CH1 1.0A Ω BW CH2 50.0mV
B
W M1.0µs
A CH1
380mA
T 10.80%
07081-032
VIN = 3.6V, VOUT = 1.5V
CIN = COUT = 4.7µF
Connecting a 4.7 µF capacitor from the VIN pin to GND
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source
impedance are encountered. If output capacitance greater than
4.7 µF is required, it is recommended that the input capacitor be
increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP1740/ADP1741, as long as they meet the minimum
capacitance and maximum ESR requirements. Ceramic
capacitors are manufactured with a variety of dielectrics, each
with different behavior over temperature and applied voltage.
Capacitors must have a dielectric adequate to ensure the
minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended. Y5V and Z5U
dielectrics are not recommended, due to their poor temperature
and dc bias characteristics.
Figure 35 shows the capacitance vs. voltage bias characteristics
of an 0805 case, 4.7 μF, 10 V, X5R capacitor. The voltage stability
of a capacitor is strongly influenced by the capacitor size and
voltage rating. In general, a capacitor in a larger package or with
a higher voltage rating exhibits better stability. The temperature
variation of the X5R dielectric is approximately ±15% over the
−40°C to +85°C temperature range and is not a function of
package size or voltage rating.
5
MURATA P/N GRM219R61A475KE34
Figure 33. Output Transient Response, COUT = 4.7 µF
CAPACITANCE (µF)
4
ILOAD
1A/DIV
T
1mA TO 2A LOAD STEP, 2.5A/µs
3
2
1
VOUT
50mV/DIV
2
0
0
2
4
6
8
10
VOLTAGE BIAS (V)
07081-133
1
Figure 35. Capacitance vs. Voltage Bias Characteristics
CH1 1.0A Ω W CH2 50.0mV
B
B
W
M1.0µs
A CH1
T 11.80%
880mA
07081-033
VIN = 3.6V, VOUT = 1.5V
CIN = COUT = 22µF
Use Equation 3 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component tolerance, and voltage.
Figure 34. Output Transient Response, COUT = 22 µF
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
Rev. H | Page 14 of 20
(3)
Data Sheet
ADP1740/ADP1741
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and COUT = 4.46 μF at 1.8 V, as shown in Figure 35.
Substituting these values in Equation 3 yields
CEFF = 4.46 μF × (1 − 0.15) × (1 − 0.1) = 3.41 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP1740/ADP1741,
it is imperative that the effects of dc bias, temperature, and
tolerances on the behavior of the capacitors be evaluated for
each application.
THERMAL CONSIDERATIONS
To guarantee reliable operation, the junction temperature of the
ADP1740/ADP1741 must not exceed 125°C. To ensure that the
junction temperature stays below this maximum value, the user
needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal
resistance between the junction and ambient air (θJA). The θJA
value is dependent on the package assembly compounds used
and the amount of copper to which the GND pin and the exposed
pad (EP) of the package are soldered on the PCB. Table 6 shows
typical θJA values for the 16-lead LFCSP for various PCB copper
sizes. Table 7 shows typical ΨJB values for the 16-lead LFCSP.
Table 6. Typical θJA Values
UNDERVOLTAGE LOCKOUT
The ADP1740/ADP1741 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage is less than approximately 1.58 V. This ensures that the
ADP1740/ADP1741 inputs and the output behave in a predictable manner during power-up.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
Copper Size (mm2)
01
100
500
1000
6400
1
The ADP1740/ADP1741 are protected against damage due to
excessive power dissipation by current-limit and thermal
overload protection circuits. The ADP1740/ADP1741 are
designed to reach current limit when the output load reaches
3 A (typical). When the output load exceeds 3 A, the output
voltage is reduced to maintain a constant current limit.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and power
dissipation) when the junction temperature begins to rise above
150°C, the output is turned off, reducing the output current to
zero. When the junction temperature drops below 135°C
(typical), the output is turned on again and output current is
restored to its nominal value.
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP1740/ADP1741 reach current limit so
that only 3 A is conducted into the short. If self-heating of the
junction becomes great enough to cause its temperature to rise
above 150°C, thermal shutdown activates, turning off the output
and reducing the output current to zero. As the junction temperature cools and drops below 135°C, the output turns on and
conducts 3 A into the short, again causing the junction temperature to rise above 150°C. This thermal oscillation between
135°C and 150°C causes a current oscillation between 3 A and
0 A that continues as long as the short remains at the output.
Current-limit and thermal overload protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation should be externally
limited so that junction temperatures do not exceed 125°C.
θJA (°C/W), LFCSP
130
80
69
54
42
Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Values
Copper Size (mm2)
100
500
1000
ΨJB (°C/W) at 1 W
32.7
31.5
25.5
The junction temperature of the ADP1740/ADP1741 can be
calculated from the following equation:
TJ = TA + (PD × θJA)
(4)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND)
(5)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation can
be simplified as follows:
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(6)
As shown in Equation 6, for a given ambient temperature, inputto-output voltage differential, and continuous load current, a
minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 36
through Figure 41 show junction temperature calculations for
different ambient temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
Rev. H | Page 15 of 20
ADP1740/ADP1741
140
JUNCTION TEMPERATURE, TJ (°C)
120
LOAD = 2A
100
LOAD = 1A
80
LOAD = 500mA
60
LOAD = 250mA
LOAD = 100mA
LOAD = 10mA
0
0.5
1.0
1.5
2.0
2.5
3.0
VIN – VOUT (V)
LOAD = 1A
60
20
JUNCTION TEMPERATURE, TJ (°C)
LOAD = 250mA
60
LOAD = 100mA
40
LOAD = 10mA
1.5
2.0
2.5
3.0
VIN – VOUT (V)
JUNCTION TEMPERATURE, TJ (°C)
60
LOAD = 100mA
40
LOAD = 10mA
2.0
2.5
VIN – VOUT (V)
3.0
07081-036
JUNCTION TEMPERATURE, TJ (°C)
LOAD = 250mA
80
1.5
LOAD = 250mA
80
LOAD = 100mA
60
LOAD = 10mA
40
20
1.0
LOAD = 1A
100
1.0
LOAD = 500mA
LOAD = 1A
140
LOAD = 1A
0
0.5
MAX JUNCTION
TEMPERATURE
1.5
2.0
2.5
3.0
3.0
Figure 40. 500 mm2 of PCB Copper, TA = 50°C, LFCSP
120
20
3.0
VIN – VOUT (V)
MAX JUNCTION
TEMPERATURE
LOAD = 500mA
2.5
100
Figure 37. 500 mm2 of PCB Copper, TA = 25°C, LFCSP
140
2.0
120
0
0.5
07081-035
JUNCTION TEMPERATURE, TJ (°C)
LOAD = 1A
1.0
1.5
VIN – VOUT (V)
LOAD = 2A
100
0
0.5
1.0
140
LOAD = 2A
20
LOAD = 100mA
Figure 39. 6400 mm2 of PCB Copper, TA = 50°C, LFCSP
120
LOAD = 500mA
LOAD = 10mA
40
0
0.5
MAX JUNCTION
TEMPERATURE
80
LOAD = 250mA
80
Figure 36. 6400 mm2 of PCB Copper, TA = 25°C, LFCSP
140
LOAD = 500mA
07081-038
20
LOAD = 2A
100
07081-039
40
MAX JUNCTION
TEMPERATURE
120
07081-037
MAX JUNCTION
TEMPERATURE
07081-034
JUNCTION TEMPERATURE, TJ (°C)
140
Data Sheet
Figure 38. 0 mm2 of PCB Copper, TA = 25°C, LFCSP
MAX JUNCTION
TEMPERATURE
120
LOAD = 500mA
100
LOAD = 250mA
80
LOAD = 100mA
60
LOAD = 10mA
40
20
0
0.5
1.0
1.5
2.0
2.5
VIN – VOUT (V)
Figure 41. 0 mm2 of PCB Copper, TA = 50°C, LFCSP
Rev. H | Page 16 of 20
Data Sheet
ADP1740/ADP1741
140
TJ = TB + (PD × ΨJB)
JUNCTION TEMPERATURE, TJ (°C)
In cases where the board temperature is known, the thermal
characterization parameter, ΨJB, can be used to estimate the
junction temperature rise. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and the power
dissipation (PD) using the following formula:
(7)
Figure 42 through Figure 45 show junction temperature
calculations for different board temperatures, load currents,
VIN to VOUT differentials, and areas of PCB copper.
100
LOAD = 2A
LOAD = 1A
80
LOAD = 500mA
60
LOAD = 250mA
40
20
LOAD = 10mA
0
0.25
120
0.75
LOAD = 2A
80
140
2.75
MAX JUNCTION
TEMPERATURE
LOAD = 500mA
60
LOAD = 250mA
40
20
LOAD = 10mA
1.75
2.25
2.75
07081-040
1.25
VIN – VOUT (V)
Figure 42. 500 mm2 of PCB Copper, TB = 25°C, LFCSP
140
2.25
Figure 44. 1000 mm2 of PCB Copper, TB = 25°C, LFCSP
LOAD = 1A
0.75
1.75
VIN – VOUT (V)
100
0
0.25
1.25
07081-042
LOAD = 100mA
LOAD = 100mA
120
LOAD = 1A
LOAD = 2A
100
LOAD = 500mA
80
LOAD = 250mA
60
40
LOAD = 100mA
LOAD = 10mA
20
0
0.25
120
LOAD = 2A
LOAD = 10mA
20
1.25
2.25
1.75
2.75
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP1740/
ADP1741. However, as shown in Table 6, a point of diminishing
returns is eventually reached, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
LOAD = 100mA
0.75
1.75
PCB LAYOUT CONSIDERATIONS
LOAD = 250mA
60
0
0.25
1.25
Figure 45. 1000 mm2 of PCB Copper, TB = 50°C, LFCSP
LOAD = 500mA
80
40
0.75
VIN – VOUT (V)
LOAD = 1A
100
07081-043
MAX JUNCTION
TEMPERATURE
2.25
VIN – VOUT (V)
2.75
07081-041
JUNCTION TEMPERATURE, TJ (°C)
120
MAX JUNCTION
TEMPERATURE
JUNCTION TEMPERATURE, TJ (°C)
JUNCTION TEMPERATURE, TJ (°C)
140
MAX JUNCTION
TEMPERATURE
Here are a few general tips when designing PCBs:
Figure 43. 500 mm2 of PCB Copper, TB = 50°C, LFCSP
Place the input capacitor as close as possible to the VIN
and GND pins.
Place the output capacitor as close as possible to the VOUT
and GND pins.
Place the soft start capacitor close to the SS pin.
Connect the load as close as possible to the VOUT and
SENSE pins (ADP1740) or to the VOUT and ADJ pins
(ADP1741).
Use of 0603 or 0805 size capacitors and resistors achieves the
smallest possible footprint solution on boards where area is
limited.
Rev. H | Page 17 of 20
Data Sheet
Figure 46. Evaluation Board
07081-046
07081-044
ADP1740/ADP1741
07081-045
Figure 48. Typical Board Layout, Bottom Side
Figure 47. Typical Board Layout, Top Side
Rev. H | Page 18 of 20
Data Sheet
ADP1740/ADP1741
OUTLINE DIMENSIONS
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.35
0.30
0.25
0.65
BSC
PIN 1
INDICATOR
16
13
1
12
EXPOSED
PAD
2.25
2.10 SQ
1.95
9
0.80
0.75
0.70
4
8
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
111908-A
TOP VIEW
0.70
0.60
0.50
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-23)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADP1740ACPZ-0.75R7
ADP1740ACPZ-1.0-R7
ADP1740ACPZ-1.1-R7
ADP1740ACPZ-1.2-R7
ADP1740ACPZ-1.3-R7
ADP1740ACPZ-1.5-R7
ADP1740ACPZ-1.8-R7
ADP1740ACPZ-2.5-R7
ADP1741ACPZ-R7
ADP1740-1.5-EVALZ
ADP1741-EVALZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage (V)
0.75
1.0
1.1
1.2
1.3
1.5
1.8
2.5
Adjustable, 0.75 to 3.3
1.5
Adjustable
Z = RoHS Compliant Part.
Rev. H | Page 19 of 20
Package Description
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
Evaluation Board
Evaluation Board
Package Option
CP-16-23
CP-16-23
CP-16-23
CP-16-23
CP-16-23
CP-16-23
CP-16-23
CP-16-23
CP-16-23
ADP1740/ADP1741
Data Sheet
NOTES
©2008–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07081-0-1/15(H)
Rev. H | Page 20 of 20
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