Data Sheet
ADP1763
3 A, Low VIN, Low Noise, CMOS Linear Regulator
FEATURES
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TYPICAL APPLICATION CIRCUITS
3 A maximum output current
Low input voltage supply range
► VIN = 1.10 V to 1.98 V, no external bias supply required
Fixed output voltage range: VOUT_FIXED = 0.9 V to 1.5 V
Adjustable output voltage range: VOUT_ADJ = 0.5 V to 1.5 V
Ultralow noise: 2 µV rms, 100 Hz to 100 kHz
Noise spectral density
► 4 nV/√Hz at 10 kHz
► 3 nV/√Hz at 100 kHz
Low dropout voltage: 95 mV typical at 3 A load
Operating supply current: 4.5 mA typical at no load
±1.5% fixed output voltage accuracy over line, load, and temperature
Excellent power supply rejection ratio (PSRR) performance
► 59 dB typical at 10 kHz at 3 A load
► 43 dB typical at 100 kHz at 3 A load
Excellent load/line transient response
Soft start to reduce inrush current
Optimized for small 10 µF ceramic capacitors
Current-limit and thermal overload protection
Power-good indicator
Precision enable
16-lead, 3 mm × 3 mm LFCSP package
AEC-Q100 qualified for automotive applications
APPLICATIONS
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Regulation to noise sensitive applications such as RF transceivers, analog-to-digital converter (ADC) and digital-to-analog
converter (DAC) circuits, phase-locked loops (PLLs), voltage
controlled oscillators (VCOs) and clocking integrated circuits
Field-programmable gate array (FPGA) and digital signal processor (DSP) supplies
Medical and healthcare
Industrial and instrumentation
Automotive
Figure 1. Fixed Output Operation
Figure 2. Adjustable Output Operation
GENERAL DESCRIPTION
The ADP1763 is a low noise, low dropout (LDO) linear regulator.
It is designed to operate from a single input supply with an input
voltage as low as 1.10 V without the requirement of an external
bias supply to increase efficiency and provide up to 3 A of output
current.
The low 95 mV typical dropout voltage at a 3 A load allows the
ADP1763 to operate with a small headroom while maintaining
regulation and providing better efficiency.
The ADP1763 is optimized for stable operation with small 10 µF
ceramic output capacitors. The ADP1763 delivers optimal transient
performance with minimal board area.
The ADP1763 is available in fixed output voltages ranging from 0.9
V to 1.5 V. The output of the adjustable output model can be set
from 0.5 V to 1.5 V through an external resistor connected between
VADJ and ground.
The ADP1763 has an externally programmable soft start time by
connecting a capacitor to the SS pin. Short-circuit and thermal
overload protection circuits prevent damage in adverse conditions.
The ADP1763 is available in a small 16-lead LFCSP package for
the smallest footprint solution to meet a variety of applications.
Rev. E
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
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Data Sheet
ADP1763
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Typical Application Circuits....................................1
General Description...............................................1
Specifications........................................................ 3
Input and Output Capacitor: Recommended
Specifications................................................... 5
Absolute Maximum Ratings...................................6
Thermal Data......................................................6
Thermal Resistance/Parameter..........................6
ESD Caution.......................................................6
Pin Configuration and Function Descriptions........ 7
Typical Performance Characteristics..................... 8
Theory of Operation.............................................12
Soft Start Function ...........................................12
Adjustable Output Voltage ...............................13
Enable Feature.................................................13
Power-Good (PG) Feature............................... 13
Applications Information...................................... 15
Capacitor Selection.......................................... 15
Undervoltage Lockout...................................... 16
Current-Limit and Thermal Overload
Protection....................................................... 16
Paralleling ADP1763 for High Current
Applications.................................................... 16
Thermal Considerations................................... 17
PCB Layout Considerations............................. 19
Outline Dimensions............................................. 21
Ordering Guide.................................................21
Output Voltage Options.................................... 22
Evaluation Boards............................................ 22
Automotive Products........................................ 22
REVISION HISTORY
3/2022—Rev. D to Rev. E
Changes to Features Section.......................................................................................................................... 1
Changes to Applications Section..................................................................................................................... 1
Changes to Figure 4 Caption to Figure 9 Caption........................................................................................... 8
Changes to Figure 10 Caption to Figure 13 Caption....................................................................................... 9
Moved Table 8, Renumbered Sequentially.................................................................................................... 20
Changes to Ordering Guide........................................................................................................................... 21
Added Output Voltage Options Section......................................................................................................... 22
Added Automotive Products Section............................................................................................................. 22
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Rev. E | 2 of 22
Data Sheet
ADP1763
SPECIFICATIONS
VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, ILOAD = 10 mA, CIN = 10 µF, COUT = 10 µF, CREF = 1 µF, CREG = 1 µF, TA = 25°C,
Minimum and maximum limits at TJ = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
INPUT VOLTAGE SUPPLY RANGE
CURRENT
Operating Supply Current
VIN
TJ = −40°C to +125°C
1.10
IGND
ILOAD = 0 µA
ILOAD = 10 mA
ILOAD = 100 mA
ILOAD = 3 A
EN = GND
TJ = −40°C to +85°C,
VIN = (VOUT + 0.2 V) to 1.98 V
TJ = 85°C to 125°C,
VIN = (VOUT + 0.2 V) to 1.98 V
10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V
100 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V
10 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V
100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V
10 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V
100 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V
VOUT = 0.9 V to 1.5 V, ILOAD = 100 mA
At 10 kHz
At 100 kHz
ILOAD = 3 A, modulated VIN
10 kHz, VOUT = 1.3 V, VIN = 1.7 V
100 kHz, VOUT = 1.3 V, VIN = 1.7 V
1 MHz, VOUT = 1.3 V, VIN = 1.7 V
10 kHz, VOUT = 0.9 V, VIN = 1.3 V
100 kHz, VOUT = 0.9 V, VIN = 1.3 V
1 MHz, VOUT = 0.9 V, VIN = 1.3 V
Shutdown Current
OUTPUT NOISE1
Noise Spectral Density
POWER SUPPLY REJECTION RATIO1
IGND-SD
OUTNOISE
OUTNSD
PSRR
OUTPUT VOLTAGE
Output Voltage Range
Fixed Output Voltage Accuracy
VOUT_FIXED
VOUT_ADJ
VOUT
IADJ
ADJUSTABLE OUTPUT VOLTAGE GAIN FACTOR
AD
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4.5
4.9
5.5
12
2
Max
Unit
1.98
V
8
8
8.5
16
180
mA
mA
mA
mA
µA
µA
800
µA
12
2
15
2
21
2
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
4
3
nV/√Hz
nV/√Hz
59
43
37
62
45
33
dB
dB
dB
dB
dB
dB
TA = 25°C
ADJUSTABLE PIN CURRENT
REGULATION
Line Regulation
Load Regulation2
DROPOUT VOLTAGE3
Typ
∆VOUT/∆VIN
∆VOUT/∆IOUT
VDROPOUT
ILOAD = 100 mA, TA = 25°C
10 mA < ILOAD < 3 A, VIN = (VOUT + 0.2 V) to
1.98 V, TJ = 0°C to 85°C
10 mA < ILOAD < 3 A, VIN = (VOUT + 0.2 V) to
1.98 V
TA = 25°C
VIN = (VOUT + 0.2 V) to 1.98 V
TA = 25°C
VIN = (VOUT + 0.2 V) to 1.98 V
VIN = (VOUT + 0.2 V) to 1.98 V
ILOAD = 10 mA to 3 A
ILOAD = 100 mA, VOUT ≥ 1.2 V
ILOAD = 3 A, VOUT ≥ 1.2 V
0.9
0.5
−0.5
−1
1.5
1.5
+0.5
+1.5
V
V
%
%
−1.5
+1.5
%
50.5
51.0
µA
µA
49.5
48.8
50.0
50.0
3.0
2.95
3.055
−0.15
+0.15
0.45
23
145
0.12
12
95
%/V
%/A
mV
mV
Rev. E | 3 of 22
Data Sheet
ADP1763
SPECIFICATIONS
Table 1.
Parameter
Symbol
Test Conditions/Comments
START-UP TIME1, 4
SOFT START CURRENT
CURRENT-LIMIT THRESHOLD5
THERMAL SHUTDOWN
Threshold
Hysteresis
POWER-GOOD (PG) OUTPUT THRESHOLD
Output Voltage
Falling
Rising
PG OUTPUT
Output Voltage Low
Leakage Current
Delay1
PRECISION EN INPUT
Logic Input
High
Low
Input Logic Hysteresis
Input Leakage Current
Input Delay Time
UNDERVOLTAGE LOCKOUT
Input Voltage
Rising
Falling
Hysteresis
tSTART-UP
ISS
ILIMIT
CSS = 10 nF, VOUT = 1.3 V
1.1 V ≤ VIN ≤ 1.98 V
TSSD
TSSD-HYS
TJ rising
150
15
°C
°C
PGFALL
PGRISE
1.1 V ≤ VIN ≤ 1.98 V
1.1 V ≤ VIN ≤ 1.98 V
−7.5
−5
%
%
PGLOW
IPG-LKG
PGDELAY
1.1 V ≤ VIN ≤ 1.98 V, IPG ≤ 1 mA
1.1 V ≤ VIN ≤ 1.98 V
ENRISING to PGRISING
1.1 V ≤ VIN ≤ 1.98 V
ENHIGH
ENLOW
ENHYS
IEN-LKG
tIEN-DLY
UVLO
UVLORISE
UVLOFALL
UVLOHYS
Min
Typ
8
3.3
0.6
10
4
EN = VIN or GND
From EN rising from 0 V to VIN to 0.1 × VOUT
TJ = −40°C to +125°C
TJ = −40°C to +125°C
0.87
Unit
12
5
ms
µA
A
0.35
1
V
µA
ms
625
580
45
0.01
100
690
630
mV
mV
mV
µA
µs
1.01
0.93
80
1.06
0.01
0.75
595
550
Max
1
V
V
mV
1
Guaranteed by design and characterization; not production tested.
2
Based on an endpoint calculation using 10 mA and 3 A loads.
3
Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage, which applies only for output voltages above
1.1 V.
4
Start-up time is defined as the time from the rising edge of EN to VOUT being at 90% of its nominal value.
5
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output
voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
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Rev. E | 4 of 22
Data Sheet
ADP1763
SPECIFICATIONS
INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
Symbol
CAPACITANCE1
Input
Output
Regulator
Reference
CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR)
CIN, COUT
CREG, CREF
1
Test Conditions/Comments
Min
Typ
7.0
7.0
0.7
0.7
10
10
1
1
Max
Unit
TA = −40°C to +125°C
CIN
COUT
CREG
CREF
RESR
µF
µF
µF
µF
TA = −40°C to +125°C
0.001
0.001
0.5
0.2
Ω
Ω
The minimum input and output capacitance must be >7.0 µF over the full range of the operating conditions. Consider the full range of the operating conditions in the
application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U capacitors
are not recommended for use with any LDO.
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Rev. E | 5 of 22
Data Sheet
ADP1763
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE/PARAMETER
Table 3.
Parameter
Rating
VIN to GND
EN to GND
VOUT to GND
SENSE to GND
VREG to GND
REFCAP to GND
VADJ to GND
SS to GND
PG to GND
Storage Temperature Range
Operating Temperature Range
Operating Junction Temperature
Lead Temperature (Soldering, 10 sec)
−0.3 V to +2.16 V
−0.3 V to +3.96 V
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to +3.96 V
−65°C to +150°C
−40°C to +125°C
125°C
300°C
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in combination. The ADP1763 can be damaged when the junction temperature
limits are exceeded. The use of appropriate thermal management
techniques is recommended to ensure that the maximum junction
temperature does not exceed the limits shown in Table 3.
Values shown in Table 4 are calculated in compliance with JEDEC
standards for thermal reporting. θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot
sealed enclosure. θJC is the junction to case thermal resistance. θJB
is the junction to board thermal resistance. ΨJB is the junction to
board thermal characterization parameter. ΨJT is the junction to top
thermal characterization parameter.
In applications where high maximum power dissipation exists,
close attention to thermal board design is required. Thermal resistance/parameter values may vary, depending on the PCB material,
layout, and environmental conditions.
Table 4. Thermal Resistance/Parameter
Package
Type
θJA
θJB
θJC-T
θJC-B
ΨJB
ΨJT
Unit
CP-16-221
50.95
29.31
49.53
8.53
29.31
0.3
°C/W
1
Thermal resistance/parameter simulated values are based on a JEDEC 2S2P
thermal test board for ΨJT, ΨJB, θJA and θJB and a JEDEC 1S0P thermal test
board for θJC with four thermal vias. See JEDEC JESD51-12.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Use the following equation to calculate the junction temperature
(TJ) from the board temperature (TBOARD) or package top temperature (TTOP)
TJ = TBOARD + (PD × ΨJB)
TJ = TTOP + (PD × ΨJT)
ΨJB is the junction to board thermal characterization parameter and
ΨJT is the junction to top thermal characterization parameter with
units of °C/W.
ΨJB of the package is based on modeling and calculation using
a 4-layer board. JESD51-12, Guidelines for Reporting and Using
Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances.
ΨJB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, θJB.
Therefore, ΨJB thermal paths include convection from the top of the
package as well as radiation from the package, factors that make
ΨJB more useful in real-world applications.
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Rev. E | 6 of 22
Data Sheet
ADP1763
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 4
VIN
5
6
7
8
REFCAP
VREG
GND
VADJ
9 to 12
VOUT
13
SENSE
14
15
SS
PG
16
EN
Regulator Input Supply. Bypass VIN to GND with a 10 µF or greater capacitor. Note that all four VIN pins must be connected to the source
supply.
Reference Filter Capacitor. Connect a 1 µF capacitor from the REFCAP pin to ground. Do not connect a load to ground.
Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 1 µF or greater capacitor. Do not connect a load to ground.
Ground.
Adjustable Voltage Pin for the Adjustable Output Option. Connect a 10 kΩ external resistor between the VADJ pin and ground to set the
output voltage to 1.5 V. For the fixed output option, leave this pin floating.
Regulated Output Voltage. Bypass VOUT to GND with a 10 µF or greater capacitor. Note that all four VOUT pins must be connected to the
load.
Sense Input. The SENSE pin measures the actual output voltage at the load and feeds it to the error amplifier. Connect VSENSE as close
to the load as possible to minimize the effect of IR voltage drop between VOUT and the load.
Soft Start Pin. A 10 nF capacitor connected to the SS pin and ground sets the start-up time to 0.6 ms.
Power-Good Output. This open-drain output requires an external pull-up resistor. If the device is in shutdown mode, current-limit mode, or
thermal shutdown mode, or if VOUT falls below 90% of the nominal output voltage, the PG pin immediately transitions low.
Enable Input. Drive the EN pin high to turn on the regulator. Drive the EN pin low to turn off the regulator. For automatic startup, connect the
EN pin to the VIN pin.
Exposed Pad. The exposed pad is electrically connected to GND. It is recommended that this pad be connected to a ground plane on the
PCB. The exposed pad is on the bottom of the package.
EP
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Rev. E | 7 of 22
Data Sheet
ADP1763
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 1.5 V, VOUT = 1.3 V, TA = 25°C, unless otherwise noted.
Figure 4. Output Voltage (VOUT) vs. Junction Temperature (TJ)
Figure 7. Ground Current (IGND) vs. Junction Temperature (TJ)
Figure 5. Output Voltage (VOUT) vs. Load Current (ILOAD)
Figure 8. Ground Current (IGND) vs. Load Current (ILOAD)
Figure 6. Output Voltage (VOUT) vs. Input Voltage (VIN)
Figure 9. Ground Current (IGND) vs. Input Voltage (VIN)
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Rev. E | 8 of 22
Data Sheet
ADP1763
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 10. Shutdown Current (IGND-SD) vs. Junction Temperature (TJ) at
Various Input Voltages (VIN)
Figure 13. Ground Current (IGND) vs. Input Voltage (VIN) (in Dropout),
VOUT = 1.3 V
Figure 11. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD), VOUT = 1.3 V
Figure 14. Load Transient Response, COUT = 10 µF, VIN = 1.8 V, VOUT = 1.3 V
Figure 12. Output Voltage (VOUT) vs. Input Voltage (VIN) (in Dropout),
VOUT = 1.3 V
Figure 15. Load Transient Response, COUT = 47 µF, VIN = 1.8 V, VOUT = 1.3 V
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Rev. E | 9 of 22
Data Sheet
ADP1763
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 16. Line Transient Response, Load Current = 3 A, VIN = 1.5 V to 1.98 V
Step, VOUT = 1.3 V
Figure 19. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various
Input Voltages, VOUT = 0.9 V, Load Current = 3 A
Figure 17. Noise vs. Load Current for Various Output Voltages
Figure 20. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various
Input Voltages, VOUT = 1.3 V, Load Current = 3 A
Figure 18. Noise Spectral Density vs. Frequency for Various Output Voltages,
ILOAD = 100 mA
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Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various
Input Voltages, VOUT = 1.5 V, Load Current = 3 A
Rev. E | 10 of 22
Data Sheet
ADP1763
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various
Loads, VOUT = 1.3 V, VIN = 1.7 V
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Rev. E | 11 of 22
Data Sheet
ADP1763
THEORY OF OPERATION
The ADP1763 is an LDO, low noise linear regulator that uses
an advanced proprietary architecture to achieve high efficiency
regulation. It also provides high PSRR and excellent line and load
transient response using a small 10 μF ceramic output capacitor.
The device operates from a 1.10 V to 1.98 V input rail to provide
up to 3 A of output current. Supply current in shutdown mode is
typically 2 µA.
SOFT START FUNCTION
For applications that require a controlled startup, the ADP1763
provides a programmable soft start function. The programmable
soft start is useful for reducing inrush current upon startup and
for providing voltage sequencing. To implement soft start, connect
a small ceramic capacitor from SS to GND. At startup, a 10 µA
current source charges this capacitor. The voltage at SS limits the
ADP1763 start-up output voltage, providing a smooth ramp-up to
the nominal output voltage. To calculate the start-up time for the
fixed output and adjustable output, use the following equations:
tSTART − UP_FIXED = tDELAY + VREF × CSS /ISS
tSTART − UP_ADJ = tDELAY + VADJ × CSS /ISS
Figure 23. Functional Block Diagram, Fixed Output
(1)
(2)
where:
tDELAY is a fixed delay of 100 µs.
VREF is a 0.5 V internal reference for the fixed output model option.
CSS is the soft start capacitance from SS to GND.
ISS is the current sourced from SS (10 µA).
VADJ is the voltage at the VADJ pin equal to RADJ × IADJ.
Figure 24. Functional Block Diagram, Adjustable Output
Internally, the ADP1763 consists of a reference, an error amplifier,
and a pass device. The output current is delivered via the pass
device, which is controlled by the error amplifier, forming a negative feedback system that ideally drives the feedback voltage to
equal the reference voltage. If the feedback voltage is lower than
the reference voltage, the negative feedback drives more current,
increasing the output voltage. If the feedback voltage is higher than
the reference voltage, the negative feedback drives less current,
decreasing the output voltage.
Figure 25. Fixed VOUT Ramp-Up with External Soft Start Capacitor (VOUT, EN)
vs. Time
The ADP1763 is available in output voltages ranging from 0.9 V to
1.5 V for a fixed output. Contact a local Analog Devices, Inc., sales
representative for other fixed voltage options. The adjustable output
option can be set from 0.5 V to 1.5 V.
The ADP1763 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. When EN is high, VOUT turns
on. When EN is low, VOUT turns off. For automatic startup, tie EN
to VIN.
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Rev. E | 12 of 22
Data Sheet
ADP1763
THEORY OF OPERATION
As shown in Figure 28, the EN pin has hysteresis built in. This
hysteresis prevents on/off oscillations that can occur due to noise
on the EN pin as it passes through the threshold points.
Figure 26. Adjustable VOUT Ramp-Up with External Soft Start Capacitor
(VOUT, EN) vs. Time
ADJUSTABLE OUTPUT VOLTAGE
The output voltage of the ADP1763 can be set over a 0.5 V to 1.5 V
range. Connect a resistor (RADJ) from the VADJ pin to ground to set
the output voltage. To calculate the output voltage, use the following
equation:
VOUT = AD × RADJ × IADJ
(3)
where:
AD is the gain factor with a typical value of 3.0 between the VADJ
pin and the VOUT pin.
IADJ is the 50.0 µA constant current out of the VADJ pin.
ENABLE FEATURE
The ADP1763 uses the EN pin to enable and disable the VOUT
pins under normal operating conditions. As shown in Figure 27,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive threshold, VOUT turns off.
Figure 28. Output Voltage vs. Typical EN Pin Voltage, VOUT = 1.3 V
POWER-GOOD (PG) FEATURE
The ADP1763 provides a power-good pin (PG) to indicate the
status of the output. This open-drain output requires an external
pull-up resistor that can be connected to VIN or VOUT. If the device
is in shutdown mode, current-limit mode, or thermal shutdown, or
if it falls below 90% of the nominal output voltage, PG immediately
transitions low. During soft start, the rising threshold of the powergood signal is 95% of the nominal output voltage.
The open-drain output is held low when the ADP1763 has sufficient
input voltage to turn on the internal PG transistor. An optional soft
start delay can be detected. The PG transistor is terminated via a
pull-up resistor to VOUT or VIN.
Power-good accuracy is 92.5% of the nominal regulator output
voltage when this voltage is rising, with a 95% trip point when this
voltage is falling.
Regulator input voltage brownouts or glitches trigger a power no
good if VOUT falls below 92.5%.
A normal power-down triggers a power good when VOUT is at 95%.
Figure 27. Typical EN Pin Operation
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Rev. E | 13 of 22
Data Sheet
ADP1763
THEORY OF OPERATION
Figure 29. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.3 V)
Figure 30. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.3 V)
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Rev. E | 14 of 22
Data Sheet
ADP1763
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP1763 is designed for operation with small, space-saving
ceramic capacitors, but it can function with most commonly used
capacitors as long as care is taken with the effective series resistance (ESR) value. The ESR of the output capacitor affects the
stability of the LDO control loop. A minimum of 10 µF capacitance
with an ESR of 500 mΩ or less is recommended to ensure the
stability of the ADP1763. Transient response to changes in load
current is also affected by output capacitance. Using a larger
value of output capacitance improves the transient response of the
ADP1763 to large changes in load current. Figure 31 and Figure 32
show the transient responses for output capacitance values of 10
µF and 47 µF, respectively.
tered. If output capacitance greater than 10 µF is required, it is
recommended that the input capacitor be increased to match it.
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP1763, as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics
are not recommended, due to their poor temperature and dc bias
characteristics.
Figure 33 shows the capacitance vs. bias voltage characteristics of
an 0805 case, 10 µF, 10 V, X5R capacitor. The voltage stability of
a capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or with a higher
voltage rating exhibits better stability. The temperature variation
of the X5R dielectric is about ±15% over the −40°C to +85°C
temperature range and is not a function of package size or voltage
rating.
Figure 31. Output Transient Response, COUT = 10 µF
Figure 33. Capacitance vs. DC Bias Voltage
Use Equation 4 to determine the worst case capacitance, accounting for capacitor variation over temperature, component tolerance,
and voltage.
CEFF = COUT × 1 − tempco × 1 − TOL
Figure 32. Output Transient Response, COUT = 47 µF
Input Bypass Capacitor
Connecting a 10 µF capacitor from the VIN pin to the GND pin
to ground reduces the circuit sensitivity to the PCB layout, especially when long input traces or a high source impedance is encounanalog.com
(4)
where:
CEFF is the effective capacitance at the operating voltage.
COUT is the output capacitor.
Tempco is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
In this example, the worst case temperature coefficient (tempco)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
Rev. E | 15 of 22
Data Sheet
ADP1763
APPLICATIONS INFORMATION
The tolerance of the capacitor (TOL) is assumed to be 10%, and
COUT = 10 µF at 1.0 V, as shown in Figure 33.
Substituting these values in Equation 4 yields
CEFF = 10 μF × (1 − 0.15) × (1 − 0.1) = 7.65 μF
Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and
tolerance at the chosen output voltage.
To guarantee the performance of the ADP1763, it is imperative that
the effects of dc bias, temperature, and tolerances on the behavior
of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT
The ADP1763 has an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than
approximately 1.06 V. The UVLO ensures that the ADP1763 inputs
and the output behave in a predictable manner during power-up.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP1763 is protected against damage due to excessive power
dissipation by current-limit and thermal overload protection circuits.
The ADP1763 is designed to reach the current limit when the output
load reaches 4 A (typical). When the output load exceeds 4 A, the
output voltage is reduced to maintain a constant current limit.
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and power dissipation)
when the junction temperature begins to rise above 150°C, the
output is turned off, reducing the output current to zero. When
the junction temperature drops below 135°C (typical), the output is
turned on again, and the output current is restored to its nominal
value.
Consider the case where a hard short from VOUT to ground occurs.
At first, the ADP1763 reaches the current limit so that only 4 A
is conducted into the short circuit. If self heating of the junction becomes great enough to cause its temperature to rise above 150°C,
thermal shutdown activates, turning off the output and reducing the
output current to zero. As the junction temperature cools and drops
below 135°C, the output turns on and conducts 4 A into the short
circuit, again causing the junction temperature to rise above 150°C.
This thermal oscillation between 135°C and 150°C causes a current
oscillation between 4 A and 0 A that continues as long as the short
circuit remains at the output.
Current-limit and thermal overload protections are intended to protect the device against accidental overload conditions. For reliable
operation, limit device power dissipation externally so that junction
temperatures do not exceed 125°C.
PARALLELING ADP1763 FOR HIGH CURRENT
APPLICATIONS
In applications where high output current is required while maintaining low noise and high PSRR performance, connect two ADP1763
devices in parallel to handle loads up to 5 A.
When paralleling the ADP1763, the two outputs must be of the
same voltage setting to maintain stable current sharing between
the two LDO regulators. To improve current sharing accuracy, add
identical ballast resistors (RBALLAST) at the output of each regulator,
as shown in Figure 34. Note that large ballast resistors improve
current sharing accuracy but degrade the load regulation performance and increase the losses along the power line; therefore, it
is recommended to keep the ballast resistors at a minimum. In
addition, tie the VADJ, SS, and REFCAP pins of the LDO regulators
together to minimize error between the two outputs.
Figure 34. Two ADP1763 Devices Connected in Parallel to Achieve Higher Current Output
analog.com
Rev. E | 16 of 22
Data Sheet
ADP1763
APPLICATIONS INFORMATION
Use Equation 5 to calculate the output of the two paralleled
ADP1763 LDOs.
VOUT = 2 × AD × RADJ × IADJ
exists for the PCB to ensure that the junction temperature does not
rise above 125°C.
(5)
where:
AD is the gain factor with a typical value of 3.0 between the VADJ
pin and the VOUT pin.
IADJ is the 50.0 µA constant current out of the VADJ pin.
Figure 35 through Figure 40 show junction temperature calculations
for different ambient temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper.
THERMAL CONSIDERATIONS
To guarantee reliable operation, the junction temperature of the
ADP1763 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user needs to
be aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistance between the
junction and ambient air (θJA). The θJA value is dependent on the
package assembly compounds used and the amount of copper to
which the GND pin and the exposed pad (EPAD) of the package
are soldered on the PCB. Table 6 shows typical θJA values for the
16-lead LFCSP for various PCB copper sizes. Table 7 shows typical
ΨJB values for the 16-lead LFCSP.
Figure 35. 6400 mm2 of PCB Copper, TA = 25°C
Table 6. Typical θJA Values
Copper Size (mm2)
θJA (°C/W), LFCSP
25
100
500
1000
6400
138.1
102.9
76.9
67.3
56
Table 7. Typical ΨJB Values
Copper Size (mm2)
ΨJB (°C/W) at 1 W
100
500
1000
33.3
28.9
28.5
Figure 36. 500 mm2 of PCB Copper, TA = 25°C
To calculate the junction temperature of the ADP1763, use the
following equation:
T J = TA + PD × θ JA
(6)
PD =
(7)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
VIN − VOUT × ILOAD + VIN × IGND
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
As shown in Equation 6, for a given ambient temperature, and
computed power dissipation, a minimum copper size requirement
analog.com
Figure 37. 25 mm2 of PCB Copper, TA = 25°C
Rev. E | 17 of 22
Data Sheet
ADP1763
APPLICATIONS INFORMATION
In cases where the board temperature is known, the thermal characterization parameter (ΨJB) can be used to estimate the junction
temperature rise. The maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD)
using the following formula:
T J = TB + PD × Ψ JB
(8)
Figure 41 through Figure 44 show junction temperature calculations
for different board temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper.
Figure 38. 6400 mm2 of PCB Copper, TA = 50°C
Figure 41. 500 mm2 of PCB Copper, TB = 25°C
Figure 39. 500 mm2 of PCB Copper, TA = 50°C
Figure 42. 500 mm2 of PCB Copper, TB = 50°C
Figure 40. 25 mm2 of PCB Copper, TA = 50°C
analog.com
Rev. E | 18 of 22
Data Sheet
ADP1763
APPLICATIONS INFORMATION
as shown in Table 7, a point of diminishing returns is eventually
reached, beyond which an increase in the copper size does not
yield significant heat dissipation benefits.
Use the following recommendations when designing PCBs:
►
►
►
►
Figure 43. 1000 mm2 of PCB Copper, TB = 25°C
►
Place the input capacitor as close as possible to the VIN and
GND pins.
Place the output capacitor as close as possible to the VOUT and
GND pins.
Place the soft start capacitor (CSS) as close as possible to the
SS pin.
Place the reference capacitor (CREF) and regulator capacitor
(CREG) as close as possible to the REFCAP pin and VREG pin,
respectively.
Connect the load as close as possible to the VOUT and SENSE
pins.
Use of 0603 or 0805 size capacitors and resistors achieves the
smallest possible footprint solution on boards where area is limited.
Figure 44. 1000 mm2 of PCB Copper, TB = 50°C, LFCSP
Figure 46. Evaluation Board
Figure 45. Thermal Image of the ADP1763 Evaluation Board at ILOAD = 3 A,
VIN = 1.5 V, VOUT = 1.3 V, TB = 92°C
Figure 45 shows a thermal image of the ADP1763 evaluation
board operating at a 3 A current load. The total power dissipation
on the ADP1763 is 600 mW, which makes the temperature on
the surface of the device higher by 20°C than the temperature of
the evaluation board.
Figure 47. Typical Board Layout, Top Side
PCB LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of ADP1763. However,
analog.com
Rev. E | 19 of 22
Data Sheet
ADP1763
APPLICATIONS INFORMATION
Figure 48. Typical Board Layout, Bottom Side
Table 8. Related Devices
Device
ADP1761
ADP1762
ADP1740/
ADP1741
ADP1752/
ADP1753
ADP1754/
ADP1755
Input
Voltage
Maximum
Current
Fixed/Adjustable
Package
1.10 V to
1.98 V
1.10 V to
1.98 V
1.6 V to
3.6 V
1.6 V to
3.6 V
1.6 V to
3.6 V
1A
Fixed/adjustable
2A
Fixed/adjustable
2A
Fixed/adjustable
0.8 A
Fixed/adjustable
1.2 A
Fixed/adjustable
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
analog.com
Rev. E | 20 of 22
Data Sheet
ADP1763
OUTLINE DIMENSIONS
Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
Updated: February 03, 2022
ORDERING GUIDE
Table 9. Ordering Guide
Model1, 2
Temperature Range
Package Description
Packing Quantity
Package
Option
Marking Code
ADP1763ACPZ0.95-R7
ADP1763ACPZ-0.9-R7
ADP1763ACPZ-1.0-R7
ADP1763ACPZ-1.1-R7
ADP1763ACPZ1.25-R7
ADP1763ACPZ-1.2-R7
ADP1763ACPZ-1.3-R7
ADP1763ACPZ-1.5-R7
ADP1763ACPZ-R7
ADP1763WACPZ0.95-R7
ADP1763WACPZ-0.9-R7
ADP1763WACPZ-1.0-R7
ADP1763WACPZ-1.1-R7
ADP1763WACPZ1.25-R7
ADP1763WACPZ-1.2-R7
ADP1763WACPZ-1.3-R7
ADP1763WACPZ-1.5-R7
ADP1763WACPZ-R7
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
16-Lead LFCSP (3mm x 3mm w/ EP)
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
Reel, 1500
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
CP-16-22
LUQ
LS1
LS2
LS3
LS5
LS4
LS6
LS7
LS0
LWA
LW4
LW5
LWD
LWB
LW6
LW7
LW8
LW9
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
analog.com
Rev. E | 21 of 22
Data Sheet
ADP1763
OUTLINE DIMENSIONS
OUTPUT VOLTAGE OPTIONS
Table 10. Output Voltage Options
Model1, 2
Output Voltage (V)3
ADP1763ACPZ0.95-R7
ADP1763ACPZ-0.9-R7
ADP1763ACPZ-1.0-R7
ADP1763ACPZ-1.1-R7
ADP1763ACPZ1.25-R7
ADP1763ACPZ-1.2-R7
ADP1763ACPZ-1.3-R7
ADP1763ACPZ-1.5-R7
ADP1763ACPZ-R7
ADP1763WACPZ0.95-R7
ADP1763WACPZ-0.9-R7
ADP1763WACPZ-1.0-R7
ADP1763WACPZ-1.1-R7
ADP1763WACPZ1.25-R7
ADP1763WACPZ-1.2-R7
ADP1763WACPZ-1.3-R7
ADP1763WACPZ-1.5-R7
ADP1763WACPZ-R7
0.95
0.9
1.0
1.1
1.25
1.2
1.3
1.5
Adjustable
0.95
0.9
1.0
1.1
1.25
1.2
1.3
1.5
Adjustable
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
3
For additional options, contact a local Analog Devices sales or distribution representative. Additional voltage output options available include the following: 0.5 V, 0.55 V, 0.6
V, 0.65 V, 0.7 V, 0.75 V, 0.8 V, 0.85 V, 1.05 V, 1.15 V, 1.35 V, 1.4 V, or 1.45 V.
EVALUATION BOARDS
Table 11. Evaluation Boards
Model1
Output Voltage (V)
Package Description
ADP1763-1.3-EVALZ
ADP1763-ADJ-EVALZ
1.3
1.1
Evaluation Board
Evaluation Board
1
Z = RoHS compliant.
AUTOMOTIVE PRODUCTS
The ADP1763W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should
review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive
applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific
Automotive Reliability reports for these models.
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registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. E | 22 of 22
