Synchronous Buck PWM,
Step-Down, DC-to-DC Controller
ADP1828
Data Sheet
FEATURES
to regulate an output voltage as low as 0.6 V to 85% of the input
voltage and is sized to handle large MOSFETs for point-of-load
regulators. The ADP1828 is ideal for a wide range of high power
applications, such as DSP and processor core I/O power, and
general-purpose power in telecommunications, medical imaging,
PC, gaming, and industrial applications. It operates from input
bias voltages of 3 V to 20 V with an internal LDO that generates
a 5 V output for input bias voltages greater than 5.5 V.
Wide bias voltage range 3.0 V to 20 V
Wide power stage input range 1 V to 24 V
Wide output voltage range: 0.6 V to 85% of input voltage
±0.85% accuracy at 0oC to 70oC
All N-channel MOSFET design for low cost
Fixed-frequency operation at 300 kHz, 600 kHz, or resistor
adjustable 300 kHz to 600 kHz
Clock output for synchronizing other controllers
No current sense resistor required
Internal linear regulator
Voltage tracking for sequencing
Soft start and thermal overload protection
Overvoltage and undervoltage power-good indicator
15 μA shutdown supply current
Available in a 20-lead QSOP and 20-lead, 4 mm × 4 mm LFCSP
The ADP1828 operates at a pin-selectable, fixed switching
frequency of either 300 kHz or 600 kHz, or at any frequency
between 300 kHz and 600 kHz with a resistor. The switching
frequency can also be synchronized to an external clock up to
2× the nominal oscillator frequency of the device The clock
output can e used for synchronizing additional ADP1828s (or
the ADP1829 controllers), thus eliminating the need for an
external clock source. The ADP1828 includes soft start protection
to limit any inrush current from the input supply during startup,
reverse current protection during soft start for a precharged
output, as well as a unique adjustable lossless current-limit
scheme utilizing external MOSFET RDSON sensing.
APPLICATIONS
Telecom and networking systems
Base station power
Set-top boxes, game consoles
Printers and copiers
Medical imaging systems
DSP and microprocessor core power supplies
DDR termination
For applications requiring power-supply sequencing, the ADP1828
provides a tracking input that allows the output voltage to track
during startup, shutdown, and faults. The additional supervisory
and control features include thermal overload, undervoltage
lockout, and power good.
GENERAL DESCRIPTION
The ADP1828 operates over the −40°C to +125°C junction temperature range and is available in a 20-lead QSOP and 20-lead, 4 mm ×
4 mm LFCSP.
The ADP1828 is a versatile and synchronous PWM voltage
mode buck controller. It drives an all N-channel power stage
VIN = 10V TO 18V
D1
VREG
IN
R6
100kΩ
C6
1µF
CIN
180µF
×2
20V
C7
1µF
C5
1µF
TRK BST
PV
ADP1828
DH
SW
EN
CSL
FREQ
DL
SYNC
C4
0.47µF
M1
L1 = 0.82µH
OUTPUT
1.8V, 20A
RCL
1.8kΩ
M2
×2
COUT2
1000µF
×2
PGND
PGOOD
FB
CLKOUT
CLKSET
COMP
C2
33pF
R8
20kΩ
C3
5.6nF
SS
CSS
200nF
COUT1
R3
47µF
7.5kΩ
X5R
C1
6.3V
R1
20kΩ 680pF
R2
10kΩ
AGND PGND
GND
fSW = 300kHz
CIN: SANYO, OSCON 20SP180M
COUT2: SANYO, POSCAP 2R5TPD1000M5
L1: WURTH ELEKTRONIC, 0.82µH, 744355182
D1: BAT54
M1: INFINEON, BSC080N03LS
M2: INFINEON, 2 × BSC030N03LS
06865-001
AGND
Figure 1. Typical Application Circuit with 20 A Output
Rev. E
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Tel: 781.329.4700 ©2007–2018 Analog Devices, Inc. All rights reserved.
Technical Support
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ADP1828
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Shutdown Control ...................................................................... 18
Applications ....................................................................................... 1
Tracking ....................................................................................... 18
General Description ......................................................................... 1
Application Information ................................................................ 19
Revision History ............................................................................... 2
Selecting the Input Capacitor ................................................... 19
Specifications..................................................................................... 3
Output LC Filter ......................................................................... 19
Absolute Maximum Ratings............................................................ 6
Selecting the MOSFETs ............................................................. 20
ESD Caution .................................................................................. 6
Setting the Current Limit .......................................................... 21
Simplified Block Diagram ............................................................... 7
Accurate Current-Limit Sensing .............................................. 21
Pin Configurations and Function Descriptions ........................... 8
Feedback Voltage Divider ......................................................... 21
Typical Performance Characteristics ........................................... 10
Compensating the Voltage Mode Buck Regulator ................. 21
Theory of Operation ...................................................................... 15
Soft Start ...................................................................................... 25
Input Power ................................................................................. 15
Switching Noise and Overshoot Reduction ............................ 25
Internal Linear Regulator .......................................................... 15
Voltage Tracking ......................................................................... 25
Soft Start ...................................................................................... 15
Coincident Tracking .................................................................. 26
Error Amplifier ........................................................................... 16
Ratiometric Tracking ................................................................. 26
Current-Limit Scheme ............................................................... 16
Thermal Considerations............................................................ 28
MOSFET Drivers ........................................................................ 16
PCB Layout Guideline ................................................................... 29
Setting the Output Voltage ........................................................ 17
Recommended Component Manufacturers ........................... 30
Switching Frequency Control and Synchronization .............. 17
Application Circuits ....................................................................... 31
Compensation ............................................................................. 18
Outline Dimensions ....................................................................... 33
Power-Good Indicator ............................................................... 18
Ordering Guide .......................................................................... 33
Thermal Shutdown..................................................................... 18
REVISION HISTORY
8/2018—Rev. D to Rev. E
Updated Outline Dimensions ....................................................... 33
Changes to Ordering Guide .......................................................... 33
2/2017—Rev. C to Rev. D
Updated Outline Dimensions ....................................................... 33
Changes to Ordering Guide .......................................................... 34
11/2010—Rev. B to Rev. C
Added 20-Lead LFCSP_WQ ............................................. Universal
Changes to Features and General Description Sections.............. 1
Changes to Table 2 ............................................................................ 6
Added Figure 4; Renumbered Sequentially .................................. 8
Changes to Table 3 ............................................................................ 8
Updated Outline Dimensions ....................................................... 33
Added Figure 59; Renumbered Sequentially .............................. 33
Changes to Ordering Guide .......................................................... 34
6/2009—Rev. A to Rev. B
Changes to Figure 40...................................................................... 24
4/2009—Rev. 0 to Rev. A
Changes to Features Section and General Description Section .....1
Changes to IN Input Voltage Parameter and EN Input Impedance
to 5 V Zener Parameter, Table 1 ......................................................3
Changes to Table 2.............................................................................6
Changes to Table 3.............................................................................8
Changes to Theory of Operation Section and Input Power
Section.............................................................................................. 14
Changes to MOSFET Drivers Section ......................................... 15
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
9/2007—Revision 0: Initial Version
Rev. E | Page 2 of 33
Data Sheet
ADP1828
SPECIFICATIONS
IN = 12 V, PV = VEN = VTRK = 5 V, SYNC = GND, unless otherwise specified. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C.
Table 1.
Parameter
POWER SUPPLY
IN Input Voltage
IN Input Voltage
IN Quiescent Current
IN Shutdown Current
VREG-to-GND Shutdown Impedance
VREG Undervoltage Lockout Threshold
VREG Undervoltage Lockout Hysteresis
ERROR AMPLIFER
FB Regulation Voltage
FB Input Bias Current
Open-Loop Voltage Gain
Gain-Bandwidth Product
COMP Sink Current
COMP Source Current
COMP Clamp High Voltage
COMP Clamp Low Voltage
LINEAR REGULATOR
VREG Output Voltage
VREG Load Regulation
VREG Line Regulation
VREG Current Limit
VREG Short-Circuit Current
IN to VREG Dropout Voltage 1
VREG Minimum Output Capacitance
PWM CONTROLLER
VRAMP Peak-to-Peak Voltage 2
DH Maximum Duty Cycle
DH Minimum On Time
DL Minimum On Time
SOFT START
SS Pull-Up Resistance
SS Pull-Down Resistance
SS to FB Offset Voltage
SS Pull-Up Voltage
TRACKING
TRK Common-Mode Input Voltage Range
TRK to FB Offset Voltage
TRK Input Bias Current
Test Conditions/Comments
Min
PV is tied to VREG, IN is not tied to VREG (using internal regulator)
IN = PV = VREG, IN is tied to VREG (not using internal regulator)
Not switching, IVREG = 0 mA
EN = GND
EN = GND, IN is not tied to VREG
VREG rising
VREG falling
5.5
3.0
TA = 25°C, TRK > 700 mV
TA = 0°C to +70°C, TRK > 700 mV
TJ = −40°C to +125°C, TRK > 700 mV
597
595
591
2.4
Typ
1.5
5
1.6
2.7
0.125
600
5
70
20
600
120
2.4
3.6
0.75
IN = VREG = 3 V
IN = 12 V
IN = 5 V+ dropout voltage to18 V, IVREG = 100 mA
TJ = −40°C to +125°C
IVREG = 0 mA to 100 mA, IN = 5.25 V to 18 V
IN = 5 V+ dropout voltage to 18 V, no load
VREG drops to 4 V
VREG drops to 0.4 V
IVREG = 100 mA, IN < 5 V
4.75
60
5.0
−10
1
220
140
0.6
Max
Unit
20
5.5
3.0
15
V
V
mA
μA
MΩ
V
V
3.0
603
605
609
100
mV
mV
mV
nA
dB
MHz
µA
µA
V
V
V
5.25
V
200
1.0
1
FREQ = GND (300 kHz)
Any frequency
Any frequency
0.7
91
SS = GND
SS = 0.6 V
SS = 0 mV to 500 mV
TRK = 0 mV to 500 mV
Rev. E | Page 3 of 33
1.0
93
100
200
1.45
90
6
−45
0.8
0
−5.5
mV
mV
mA
mA
V
μF
V
%
ns
ns
kΩ
kΩ
mV
V
600
+5
100
mV
mV
nA
ADP1828
Parameter
OSCILLATOR
Oscillator Frequency
SYNC Synchronization Range
SYNC Input Pulse Width
SYNC Pin Capacitance
CURRENT SENSE
CSL Threshold Voltage
CSL Output Current
Current Sense Blanking Period
GATE DRIVERS
DH Rise Time
DH Fall Time
DL Rise Time
DL Fall Time
DH or DL Driver RON, Sourcing Current 3, 4
DH or DL Driver RON, Sinking Current3, 4
DH or DL Driver RON, Sourcing Current
DH or DL Driver RON, Sinking Current
DH to DL, DL to DH Dead Time
CLOCK OUT
CLOCKOUT Pulse Width
CLKOUT Rise or Fall Time
SYNC to CLKOUT Propagation Delay, tPD
SYNC to CLKOUT Propagation Delay, tPD
LOGIC THRESHOLDS
SYNC, CLKSET, FREQ Logic High
SYNC, CLKSET Logic Low
FREQ Logic Low
CLKSET, SYNC, FREQ Input Leakage
Current
EN Input Threshold
EN Input Threshold Hysteresis
EN Current Source
EN Input Impedance to 5 V Zener
THERMAL SHUTDOWN
Thermal Shutdown Threshold 4
Thermal Shutdown Hysteresis4
Data Sheet
Test Conditions/Comments
Min
Typ
Max
Unit
SYNC = FREQ = GND
SYNC = GND, FREQ = VREG
RFREQ = 57.6 kΩ
RFREQ = 35.7 kΩ
RFREQ = 24.9 kΩ
FREQ = GND
FREQ = VREG
240
480
240
370
480
300
600
200
300
600
300
450
600
360
720
360
530
720
600
1200
kHz
kHz
kHz
kHz
kHz
kHz
kHz
ns
pF
−58
56
mV
μA
ns
5
Relative to PGND
CSL = PGND
−17
42
CDH = 3 nF, VBST − VSW = 5 V
CDH = 3 nF, VBST − VSW = 5 V
CDL = 3 nF
CDL = 3 nF
Sourcing 1.5 A with a 0.1 µs pulse
Sinking 1.5 A with a 0.1 µs pulse
IN = VREG = 3 V; sourcing 1 A with a 0.1 µs pulse
IN = VREG = 3 V; sinking 1 A with a 0.1 µs pulse
CCLKOUT = 47 pF
CCLKOUT = 47 pF, CSYNC = 5 pF
CCLKOUT = 47 pF, CSYNC = 5 pF, IN < 5 V
−38
50
100
15
10
15
10
2
1.5
2.3
2
40
ns
ns
ns
ns
Ω
Ω
Ω
Ω
ns
360
10
40
52
ns
ns
ns
ns
1.8
0.4
0.25
1
CLKSET, SYNC, FREQ = 0 V or VREG
1.1
EN = 0 V to 3.0 V
EN = 5.5 V to 20 V
−0.1
1.5
0.2
−0.6
100
145
15
Rev. E | Page 4 of 33
1.8
−1.5
V
V
V
μA
V
V
μA
kΩ
°C
°C
Data Sheet
Parameter
POWER GOOD
FB Overvoltage Threshold
FB Overvoltage Hysteresis
FB Undervoltage Threshold
FB Undervoltage Hysteresis
PGOOD Propagation Delay
PGOOD Off Leakage Current
PGOOD Output Low Voltage
ADP1828
Test Conditions/Comments
Min
Typ
Max
Unit
VFB rising
700
810
VFB falling
500
750
50
550
50
8
mV
mV
mV
mV
μs
μA
mV
VPGOOD = 5.5 V
IPGOOD = 10 mA
150
585
1
500
Connect IN to VREG when IN < 5.5 V. For applications with IN < 5.5V and IN not connected to VREG, keep in mind that VREG = VIN – dropout. VREG must be ≥ 3 V for
proper operation.
VRAMP = 1.0 V × fOSC/fSW, where fOSC is the natural oscillator frequency and fSW is the actual switching frequency. If SYNC is not used, then fOSC = fSW. If SYNC is used,
then fSW = fSYNC.
3
With a 5 V drive, the peak source or sink current can be up to 2.5 A and 3.3 A, respectively, when driving external power MOSFETs. The duration of the peak current
pulse is generally in the order of 10 ns.
4
Guaranteed by design and characterization. Not subject to production test.
1
2
Rev. E | Page 5 of 33
ADP1828
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
IN
EN
PV, SYNC, FREQ, COMP, SS, FB, PGOOD,
CLKSET, CLKOUT, VREG, TRK
BST-to-GND, SW-to-GND
BST-to-SW
BST-to-GND, SW-to-GND, 50 ns transients
SW-to-GND, 30 ns negative transients
CSL-to-GND
DH-to-GND
DL-to-PGND
PGND-to-GND
θJA, 20-Lead QSOP on a Multilayer PCB
(Natural Convection)1
θJA, 20-Lead LFCSP on a Multilayer PCB
(Natural Convection)1
Operating Junction Temperature2
Storage Temperature
Maximum Soldering Lead Temperature
Rating
−0.3 V to +20.5 V
−0.3 V < IN + 0.3 V
−0.3 V to +6 V
−0.3 V to +30 V
−0.3 V to +6 V
+38 V
−7 V
−1 V to +30 V
(SW − 0.3 V) to
(BST + 0.3 V)
−0.3 V to
(PV + 0.3 V)
±2 V
83°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified all other voltages
are referenced to GND.
ESD CAUTION
35.6°C/W
−40°C to +125°C
−65°C to +150°C
260°C
Junction-to-ambient thermal resistance (θJA) of the package was calculated
or simulated on a multilayer PCB.
2
The junction temperature, TJ, of the device is dependent on the ambient
temperature, TA, the power dissipation of the device, PD, and the junction-toambient thermal resistance of the package, θJA. Maximum junction
temperature is calculated from the ambient temperature and power
dissipation using the formula TJ = TA + PD × θJA.
1
Rev. E | Page 6 of 33
Data Sheet
ADP1828
SIMPLIFIED BLOCK DIAGRAM
IN
ADP1828
LINEAR
REG
VREG
0.6V
0.75V
REF
0.8V
0.55V
THERMAL
SHUTDOWN
UVLO
IN
EN
100kΩ
LOGIC
BST
CLKOUT
CLKSET
CLKOUT
DRIVER
FAULT
DH
S
Q
SW
PWM
FREQ
CLK
OSCILLATOR
R
SYNC
PWM
COMPARATOR
RAMP
Q
PV
DL
VREG
ILIM
PGND
50µA
COMP
FB
TRK
CSL
0.75V
ERROR
AMPLIFIER
0.6V
SS
90kΩ
PGOOD
0.8V
0.55V
6kΩ
FAULT
06865-003
GND
Figure 2. Simplified Block Diagram
Rev. E | Page 7 of 33
ADP1828
Data Sheet
CLKSET
EN 3
18
BST
17
DH
16
SW
GND 6
15
CSL
COMP 7
14
PGND
FB 8
13
DL
TRK 9
12
PV
SS 10
11
PGOOD
IN 4
VREG
5
ADP1828
TOP VIEW
(Not to Scale)
EN
IN
VREG
GND
COMP
1
2
3
4
5
(Not to Scale)
ADP1828
TOP
VIEW
15
14
13
12
11
DH
SW
CSL
PGND
DL
NOTES
1. CONNECT THE BOTTOM EXPOSED PAD OF THE
LFCSP PACKAGE TO SYSTEM AGND PLANE.
Figure 3. 20-Lead QSOP Pin Configuration
06865-059
CLKOUT
19
20
19
18
17
16
20
FB 6
TRK 7
SS 8
PGOOD 9
PV 10
1
2
06865-004
FREQ
SYNC
SYNC
FREQ
CLKOUT
CLKSET
BST
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. 20-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
QSOP
Pin No.
1
LSCSP
Pin No.
19
Mnemonic
FREQ
2
20
SYNC
3
1
EN
4
2
IN
5
3
VREG
6
7
8
4
5
6
GND
COMP
FB
9
7
TRK
10
11
8
9
SS
PGOOD
12
10
PV
13
14
15
11
12
13
DL
PGND
CSL
16
17
18
14
15
16
SW
DH
BST
Description
Frequency Control Input. Low for 300 kHz, high for 600 kHz, or connect a resistor from FREQ to GND to
set the free-running frequency between 300 kHz and 600 kHz.
Frequency Synchronization Input. Accepts external signals between 300 kHz and 600 kHz if FREQ is set
to low, or between 600 kHz and 1.2 MHz if FREQ is set to high. If fOSC is set by RFREQ, then the
synchronization frequency range is from fOSC up to 600 kHz. If SYNC is not used, connect SYNC to GND
or VREG. VSYNC can be driven up to 6 V even when VIN is less than 6 V.
Enable Input. Drive EN high or tristate EN to turn on the ADP1828 controller, and drive it low to turn off.
Connect EN to IN for automatic startup.
Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 20 V to power the ADP1828 from
LDO, VREG; tie PV to VREG. For input voltages between 3 V and 5.5 V, tie IN, PV, and VREG together.
Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from
VREG. Bypass VREG to AGND plane with 1 μF ceramic capacitor for stable operation, for example, a 10 V
X5R 1 μF ceramic capacitor is sufficient. The VREG output is 5 V when IN = 5 V + dropout. Connect IN to
VREG and PV when IN = 3 V to 5.5 V. For applications with IN < 5.5 V and IN not connected to VREG, keep
in mind that VREG = VIN – dropout. VREG needs to be ≥3 V for proper operation.
Ground for Internal Circuits. Tie the bottom of the feedback dividers to this GND.
Error Amplifier Output. Connect an RC network from COMP to FB for loop compensation.
Voltage Feedback. Connect a resistor divider from the buck regulator output to GND and tie the tap to
FB to set the output voltage.
Tracking Input. To track a master voltage, drive TRK from a voltage divider from the master voltage. If
the tracking function is not used, connect TRK to VREG.
Soft Start Control Input. Connect a capacitor from SS to GND to set the soft start period.
Open-Drain Power-Good Output. Sinks current when FB is out of regulation. Connect a pull-up resistor
from PGOOD to VREG.
Positive Input Voltage for Gate Driver DL. When IN is 3 V to 5.5 V, connect IN to VREG and PV. Connect a
1 μF bypass capacitor from PV to PGND. When IN = 5.5 V to 20 V, connect PV to VREG.
Low-Side (Synchronous Rectifier) Gate Driver Output.
Power GND. Ground for gate driver.
Current Sense Comparator Inverting Input. Connect a resistor between CSL and SW to set the currentlimit offset.
Switch Node Connection.
High-Side (Switch) Gate Driver Output.
Boost Capacitor Input. Powers the high-side gate driver DH. Connect a 0.22 μF to 0.47 μF ceramic
capacitor from BST to SW and a Schottky diode from PV to BST.
Rev. E | Page 8 of 33
Data Sheet
ADP1828
QSOP
Pin No.
19
LSCSP
Pin No.
17
Mnemonic
CLKSET
20
18
CLKOUT
N/A 1
EPAD
EPAD
1
Description
Clock Set Input. Setting CLKSET to logic high (connect CLKSET to VREG) sets the CLKOUT to 2× the
internal oscillator frequency and is in phase with the oscillator. Setting CLKSET to logic low sets the
CLKOUT to 1× the oscillator frequency and 180° out of phase.
Clock Output. The CLKOUT frequency, fCLKOUT, is either 1× or 2× the oscillator frequency. CLKOUT can
0be used to synchronize another ADP1828 or ADP1829 controllers. Set fCLKOUT to 1× when synchronizing
another ADP1828, or to 2× when synchronizing the ADP1829. If SYNC is used, fSYNC = fCLKOUT
independent of the CLKSET voltage. CLKOUT is able to drive a 100 pF load.
Exposed Pad. Connect the bottom exposed pad of the LFCSP package to system AGND plane.
N/A means not applicable.
Rev. E | Page 9 of 33
ADP1828
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
95
90
300kHz
90
600kHz
85
VIN = 12V
VOUT = 1.8V
TA = 25°C
70
EFFICIENCY (%)
EFFICIENCY (%)
80
60
50
fSW = 600kHz
VIN = 12V
VOUT = 3.3V
TA = 25°C
80
75
70
65
60
40
4
6
8
10
12
LOAD (A)
14
16
18
20
50
0
1
2
3
4
5
06865-007
2
30
06865-008
0
06865-002
55
30
LOAD (A)
Figure 8. Efficiency vs. Load Current of Figure 55
Figure 5. Efficiency vs. Load Current of Figure 1
95
95
90
90
85
VIN = 12V
VIN = 3.3V
80
VIN = 5.5V
EFFICIENCY (%)
EFFICIENCY (%)
85
80
fSW = 300kHz
VIN = 15V
75
VOUT = 1.8V
TA = 25°C
70
fSW = 300kHz
VIN = 12V
VOUT = 1.8V
TA = 25°C
75
70
65
60
65
55
60
0
5
10
15
20
25
LOAD (A)
06865-005
50
55
45
0
10
15
LOAD (A)
20
25
Figure 9. Efficiency vs. Load Current of Figure 57
Figure 6. Efficiency vs. Load Current of Figure 1
95
5.5
TA = 25°C
90
5.0
85
75
VREG OUTPUT (V)
fSW = 600kHz
VIN = 3.3V
VOUT = 1.2V
TA = 25°C
80
70
4.5
4.0
65
3.5
55
0
1
2
3
4
LOAD (A)
5
3.0
3.0
3.5
4.0
4.5
5.0
VIN (V)
Figure 7. Efficiency vs. Load Current of Figure 54
Figure 10. VREG in Dropout, No Load
Rev. E | Page 10 of 33
5.5
06865-009
60
06865-006
EFFICIENCY (%)
5
Data Sheet
ADP1828
3.0
5.000
VIN = 5.5V
TA = 25°C
4.995
TA = 25°C
600kHz
2.5
4.990
300kHz
VREG OUTPUT (V)
4.985
2.0
∆fOSC (%)
4.980
4.975
4.970
1.5
1.0
4.965
4.960
0.5
0
20
40
60
VREG LOAD CURRENT (mA)
80
0
06865-010
4.950
100
3
5
7
9
5.000
T
VIN = 7V
15
17
VIN = 5.5V
LOAD = 5A
SW
4.990
NO LOAD
4.985
VREG (V)
13
Figure 14. Δ fOSC vs. VIN, Referenced at VIN = 3 V
Figure 11. VREG vs. Load Current
4.995
11
VIN (V)
06865-013
4.955
1
4.980
4.975
10mA LOAD
4.970
2
4.965
VREG (AC-COUPLED)
100mA LOAD
4.960
–25
0
25
50
75
TEMPERATURE (°C)
100
125
CH1 5.00V
BW
CH2 100mV
BW
M 400ns
A CH1
3.60V
06865-014
4.950
–50
06865-011
4.955
Figure 15. VREG Output of Figure 55
Figure 12. VREG Voltage vs. Temperature
0.6025
VIN = 5.5V
TA = 25°C
5
0.6020
FEEDBACK VOLTAGE (V)
3
2
0.6015
0.6010
0.6005
0.6000
1
0
0
50
100
150
VREG LOAD CURRENT (mA)
200
250
0.5990
–40
–15
10
35
60
TEMPERATURE (°C)
85
110
Figure 16. Feedback Voltage vs. Temperature, VIN = 12 V
Figure 13. VREG Current-Limit Foldback
Rev. E | Page 11 of 33
135
06865-015
0.5995
06865-012
VREG OUTPUT (V)
4
ADP1828
Data Sheet
2.0
T
VIN = 3V TO 18V
fOSC = 300kHz OR 600kHz
REFERENCE POINT IS AT 25°C
1.5
VOUT (AC-COUPLED)
1
∆fOSC (kHz)
1.0
0.5
STEP LOAD (5A TO 20A)
0
–0.5
–1.0
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
4
06865-016
–2.0
–50
CH1 100mV
BW
M 200µs
8.20A
Figure 20. Load Transient Response of Figure 1, 5 A to 20 A, VIN = 12 V
Figure 17. Δ fOSC vs. Temperature
6
T
TA = 25°C
SW
5
1
4
2
3
INPUT RIPPLE
2
1
3
2
5
8
11
VIN (V)
14
17
20
CH2 50.0mV
CH1 10.0V
CH3 10.0mV BW
Figure 18. Supply Current vs. Input Voltage
BW
M 1.00µs
A CH1
5.80V
06865-020
0
06865-017
OUTPUT RIPPLE
Figure 21. Input and Output Ripple of Figure 55, 4 A Load
T
T
SW
INPUT VOLTAGE (AC-COUPLED)
1
2
INPUT RIPPLE
2
OUTPUT (AC-COUPLED)
3
OUTPUT RIPPLE
3
4
CH1 10.0V
CH3 50.0mV
BW
CH2 5.00V
BW
M 1.00µs
A CH1
6.40V
BW
Figure 19. Input and Output Ripple of Figure 1, 22 A Load
CH3 100mV
BW
CH2 200mV
CH4 5.00A Ω
BW
M 200µs
A CH4
4.20A
06865-021
STEP LOAD (1A TO 5A)
06865-018
QUIESCENT CURRENT (mA)
A CH4
CH4 5.00A Ω
06865-019
–1.5
Figure 22. Load Transient Response of Figure 55, 1 A to 5 A, VIN = 12 V
Rev. E | Page 12 of 33
Data Sheet
ADP1828
T
T
VIN = 5V TO 9V TO 5V
VIN
1
SS
2
VOUT
3
SW
VOUT (AC-COUPLED)
1
3
M 4.00ms
A CH1
6.08V
CH1 5.00V
CH3 1.00V
Figure 23. Line Transient Response of Figure 1, No Load
BW
CH2 500mV
CH4 5.00V
BW
M 2.00ms
A CH1
4.10V
06865-025
BW
CH1 2.00V
CH3 50.0mV
06865-022
4
Figure 26. Power-On Response, EN Tied to VIN
T
SHORT CIRCUIT APPLIED
SHORT CIRCUIT REMOVED
1
TRK
SS
2
VOUT
FB
VIN = 5.5V
3
INPUT CURRENT
4
CH2 500mV
CH4 5.00A Ω
BW
M 20.0ms
A CH3
1.34V
CH1 200mV
Figure 24. Output Short-Circuit Response
BW
CH2 200mV
BW
M 20.0ms
A CH1
680mV
06865-026
BW
352mV
06865-027
CH1 5.00V
CH3 1.00V
06865-023
1
Figure 27. Tracking, TRK from 0 V to 1 V
T
T
EN
TRK AND FB SUPERIMPOSED
1
VOUT
2
SS
3
CH1 5.00V
CH3 1.00V
CH2 1.00V
BW
M 4.00ms
A CH1
3.000V
BW
06865-024
1
CH1 100mV
Figure 25. Soft Start and Inrush Current of Figure 1
BW
CH2 100mV
BW
M 20.0ms
A CH1
Figure 28. Tracking, TRK from 0 V to 0.5 V
Rev. E | Page 13 of 33
ADP1828
Data Sheet
T
T
DH
1
DH
2
FB
DL
3
SS
VIN = 0V TO 3V
2
CLKOUT
VREG
4
4.80V
4
CH1 5.00V
CH3 200mV
Figure 29. CLKOUT, CLKSET = 0 V
BW
BW
CH2 200mV
CH4 2.00V
BW
M 4.00ms
A CH4
1.12V
06865-032
A CH2
8.20V
06865-033
M 1.00µs
06865-029
CH3 5.00V
CH2 10.0V
CH4 5.00V
BW
Figure 32. Start into Precharged Output
T
T
EN
1
DH
2
DH
DL
3
2
DL
4
3
CH3 5.00V
CH2 10.0V
CH4 5.00V
M 1.00µs
A CH2
4.80V
06865-030
CLKOUT
CH1 5.00V
CH3 5.00V
Figure 30. CLKOUT, CLKSET = 5 V
SYNC
1
DH
2
DL
3
CLKOUT
M 1.00µs
A CH1
3.50V
06865-031
4
CH2 10.0V
CH4 5.00V
CH2 10.0V
BW
M 4.00µs
BW
Figure 33. EN, Shutdown
T
CH1 5.00V
CH3 5.00V
BW
Figure 31. SYNC
Rev. E | Page 14 of 33
A CH2
Data Sheet
ADP1828
THEORY OF OPERATION
The ADP1828 is a versatile, synchronous-rectified, fixed-frequency,
pulse-width modulation (PWM), voltage mode, step-down
controller capable of generating an output voltage as low as 0.6 V
to 85% of the input voltage. It is ideal for a wide range of applications, such as DSP and processor core input/output supplies,
general-purpose power in telecom, medical imaging, gaming,
PCs, set-top boxes, and industrial controls. The ADP1828
controller operates directly from 3 V to 20 V, and includes fully
integrated MOSFET gate drivers and a linear regulator for
internal and gate drive bias.
The ADP1828 operates at a pin-selectable, fixed switching
frequency of either 300 kHz or 600 kHz, or operates at any
frequency between 300 kHz and 600 kHz by connecting a
resistor between FREQ and GND. The switching frequency can
also be synchronized to an external clock up to 2× the nominal
oscillator frequency of the device. The built-in clock output can
be used for synchronizing the ADP1829 and other ADP1828
controllers, thus eliminating the need for an external clock
source. The ADP1828 also includes clockout, voltage tracking,
thermal overload protection, undervoltage lockout, power
good, soft start to limit inrush current from the input supply
during startup, reverse current protection during soft start for
precharged outputs, and an adjustable lossless current-limit
scheme utilizing external MOSFET RDSON sensing. The ADP1828
operates over the −40°C to +125°C junction temperature range
and is available in a 20-lead QSOP.
INPUT POWER
The ADP1828 is powered from the IN pin from 3.0 V up to 20 V.
The internal low dropout linear regulator, regulates the IN voltage
down to 5 V when IN is between 5.5 V and 20 V. The output of
the LDO is denoted as VREG. The control circuits, gate drivers,
and the external boost capacitor operate from the LDO output
for IN between 5.5 V and 20 V. PV powers the low-side MOSFET
gate drive (DL), and IN powers the internal control circuitry.
Bypass PV to PGND with a 1 μF or greater capacitor, and bypass
IN to GND with a 0.1 μF or greater capacitor. Bypass the power
input to PGND with a suitably large capacitor.
The VREG output is sensed by the undervoltage lockout (UVLO)
circuit to be certain that enough voltage headroom is available
to run the controllers and gate drivers. As VREG rises above
about 2.7 V, the controllers are enabled. The IN voltage is not
directly monitored by the UVLO circuit. If the IN voltage is
insufficient to allow VREG to be above the UVLO threshold,
the controllers are disabled, but the LDO continues to operate.
The LDO is enabled and cannot be turned off whenever EN is
high, even if VREG is below the UVLO threshold.
For a supply voltage between 5.5 V and 20 V, connect IN to the
supply voltage, and tie VREG to PV. For a supply voltage between
3 V and 5.5 V, connect IN, PV, and VREG to the supply voltage.
In this case, the input supply voltage directly powers the lowside gate driver.
While IN is limited to 20 V, the switching stage can run from up
to 24 V and the BST pin can go to 30 V to support the gate
drive. This can provide an advantage, for example, in the case of
high frequency operation from high input voltage. Power
dissipation in the ADP1828 can be limited by running IN from
a low voltage rail while operating the switches from the high
voltage rail.
INTERNAL LINEAR REGULATOR
The internal linear regulator has low dropout, meaning it can
regulate its output voltage (VREG) close to the input voltage.
It powers up the internal control circuitry and provides bias for
the gate drivers when VREG is tied to PV. It is guaranteed to
have more than 100 mA of output current capability, which is
sufficient to handle the gate drive requirements of typical logic
threshold MOSFETs driven at up to 1.2 MHz. Bypass VREG to
AGND with a 1 µF or greater capacitor.
Because the LDO supplies the gate drive current, the output
of VREG is subjected to sharp transient currents as the drivers
switch and the boost capacitors recharge during each switching
cycle. The LDO has been optimized to handle these transients
without overload faults. Due to the gate drive loading, using
the VREG output for other auxiliary system loads is not
recommended.
The LDO includes a current limit well above the expected
maximum gate drive load. This current limit also includes a
short-circuit fold back to further limit the VREG current in
the event of a short-circuit fault.
SOFT START
The ADP1828 employs a programmable soft start that reduces
input current transients and prevents output overshoot. SS drives
an auxiliary positive input to the error amplifier; thus, the voltage
at this pin regulates the voltage at the feedback control pin.
Program the soft start by connecting a capacitor from SS to
GND. On startup, the capacitor charges from an internal
90 kΩ resistor to 0.8 V. The dc-to-dc converter output voltage
rises with the voltage at the soft start pin, allowing the output
voltage to rise slowly and reducing the inrush current.
Rev. E | Page 15 of 33
ADP1828
Data Sheet
If the output voltage is precharged prior to turn-on, the ADP1828
prevents reverse inductor current, which would discharge the
output capacitor. When the voltage at SS exceeds the regulation
voltage (typically 0.6 V), the reverse current is re-enabled to
allow the output voltage regulation to be independent of load
current.
similarly forced below PGND and an overcurrent fault is
flagged.
When a controller is disabled or experiences any form of fault
condition, the soft start capacitor is discharged through an
internal 6 kΩ resistor, so that at restart or recovery from fault
the output voltage soft starts again.
When the ADP1828 senses an overcurrent condition, the next
switching cycle is suppressed, the soft start capacitor is discharged
through an internal 6 kΩ resistor, and the error amplifier output
voltage is pulled down. The ADP1828 remains in this mode for
as long as the overcurrent condition persists.
ERROR AMPLIFIER
The ADP1828 error amplifier is an operational amplifier. The
ADP1828 senses the output voltage through an external resistor
divider at the FB pin. The FB pin is the inverting input to the
error amplifier. The error amplifier compares this feedback
voltage to the internal 0.6 V reference, and the output of the
error amplifier appears at the COMP pin. The COMP pin
voltage then directly controls the duty cycle of the switching
converter.
A series/parallel RC network is tied between the FB pin and the
COMP pin to provide the compensation for the buck converter
control loop. A detailed design procedure for compensating the
system is provided in the Compensating the Voltage Mode Buck
Regulator section.
The error amplifier output is clamped between a lower limit of
about 0.75 V and a higher limit of up to about 3.6 V, depending
on the VREG voltage. When the COMP pin is low, the switching
duty cycle goes to 0%, and when the COMP pin is high, the
switching duty cycle goes to the maximum.
The SS and TRK pins are auxiliary positive inputs to the error
amplifier. Whichever voltage is lowest (SS, TRK, or the internal
0.6 V reference) controls the FB pin voltage and the output.
Consequently, if two of these inputs are close to each other, a
small offset is imposed on the error amplifier.
CURRENT-LIMIT SCHEME
The ADP1828 employs a programmable, cycle-by-cycle lossless
current-limit circuit that uses an inexpensive resistor to set the
threshold. Every switching cycle, the synchronous rectifier turns on
for a minimum time and the voltage drop across the MOSFET
RDSON is measured to determine if the current is too high.
This measurement is done by an internal current-limit comparator and an external current-limit setting resistor. The resistor
is connected between the switch node (that is the drain of the
rectifier MOSFET) and the CSL pin. The CSL pin, which is the
inverting input of the comparator, forces 50 μA through the
resistor to create an offset voltage drop across it.
The normal transient ringing on the switch node is ignored
for 100 ns after the synchronous rectifier turns on, so the overcurrent condition must also persist for 100 ns for a fault to be
flagged.
Note that the current-limit scheme in the ADP1828 is not the
same as a short-circuit protection. The ADP1828 does not go
into current foldback in the event of a short circuit. The shortcircuit output current is the current limit set by the RCL resistor
and is monitored cycle by cycle. When the overcurrent condition
is removed, operation resumes in soft start mode.
MOSFET DRIVERS
The DH pin drives the high-side switch MOSFET. This is a
boosted 5 V gate driver that is powered by a bootstrap capacitor
circuit. This configuration allows the high-side, N-channel
MOSFET gate to be driven above the input voltage, allowing full
enhancement and a low voltage drop across the MOSFET. The
bootstrap capacitor is connected from the SW pin to the BST
pin. A bootstrap Schottky diode connected from the PV pin to
the BST pin recharges the boost capacitor every time the SW
node goes low. Use a bootstrap capacitor value greater than
100× the high-side MOSFET input capacitance.
In practice, the switch node can run up to 24 V of input voltage,
and the boost nodes can operate more than 5 V above this to
allow full gate drive. The IN pin can be run from 3 V to 20 V.
The switching cycle is initiated by the internal clock signal. The
high-side MOSFET is turned on by the DH driver, and the SW
node goes high, pulling up on the inductor. When the internally
generated ramp signal crosses the COMP pin voltage, the switch
MOSFET is turned off and the low-side synchronous rectifier
MOSFET is turned on by the DL driver. Active break-beforemake circuitry as well as a supplemental fixed dead time are
used to prevent cross-conduction in the switches.
The DL pin provides the gate drive for the low-side MOSFET
synchronous rectifier. Internal circuitry monitors the external
MOSFETs to ensure break-before-make switching to prevent
cross-conduction. An active dead-time reduction circuit
reduces the break-before-make time of the switch to limit the
losses due to current flowing through the synchronous rectifier
body diode.
When the inductor current is flowing in the MOSFET rectifier,
its drain is forced below PGND by the voltage drop across its
RDSON. If the RDSON voltage drop exceeds the preset drop on
the current-limit resistor, the inverting comparator input is
Rev. E | Page 16 of 33
Data Sheet
ADP1828
The PV pin provides power to the low-side drivers. It is limited
to 5.5 V maximum input and must have a local decoupling
capacitor to PGND.
The synchronous rectifier is turned on for a minimum time of
about 200 ns on every switching cycle in order to sense the
current. This minimum off time plus the nonoverlap dead time
puts a limit on the maximum high-side switch duty cycle based
on the selected switching frequency. Typically, this maximum
duty cycle is about 90% at 300 kHz switching. At 1.2 MHz
switching, it reduces to about 70% maximum duty cycle.
The 1× output is suitable for synchronizing other ADP1828s.
Setting CLKSET high (connect to VREG) sets the frequency to
2× fOSC and is in phase with fOSC. The 2× output is suitable for
synchronizing the dual channel ADP1829 controller (see
Table 4).
Table 4. CLKOUT Truth Table1
EN
H
H
H
CLKSET
L
H
X
SYNC
H/L
H/L
Clock in
CLKOUT
1× fOSC
2× fOSC
Clock
L
X
X
L
SETTING THE OUTPUT VOLTAGE
The output voltage is set using a resistive voltage divider from
the output to FB. The voltage divider splits the output voltage to
the 0.6 V FB regulation voltage to set the regulation output
voltage. The output voltage can be set to as low as 0.6 V and as
high as 85% of the power input voltage.
SWITCHING FREQUENCY CONTROL AND
SYNCHRONIZATION
The ADP1828 has a logic controlled frequency select input, FREQ,
which sets the switching frequency to 300 kHz or 600 kHz. Drive
FREQ low at 300 kHz and high at 600 kHz. The frequency can also
be set to between 300 kHz and 600 kHz by connecting a resistor
between FREQ and GND. A 24.9 kΩ sets the frequency to
600 kHz, 35.7 kΩ to 450 kHz, and 57.6 kΩ to 300 kHz. Figure 34
shows fOSC as a function of RFREQ.
600
TA = 25°C
500
450
VIN = 3V
400
350
X: don’t care, H: Logic high, L: Logic low.
To synchronize the ADP1828 switching frequency to an external
signal, drive the SYNC input with an external clock or with the
CLKOUT signal from another ADP1828. The ADP1828 can be
synchronized to between 1× and 2× the internal oscillator frequency. If fOSC is set by RFREQ, then the synchronization frequency
range is from fOSC up to 600 kHz. Driving SYNC faster than
recommended for the FREQ setting results in a small ramp
signal, which can affect the signal-to-noise ratio and the
modulator gain and stability.
When an external clock is detected at the first SYNC edge, the
internal oscillator is reset and the clock control shifts to SYNC.
The SYNC edges then trigger subsequent clocking of the PWM
outputs. The high-side MOSFET turn-on follows the rising edge
of the sync input by approximately 320 ns (see Figure 35 for an
illustration). If the external SYNC signal disappears during
operation, the ADP1828 reverts to its internal oscillator and
experiences a delay of no more than a single cycle of the
internal oscillator.
VIN = 5V
SYNC
300
200
24000
06865-034
250
29000
34000
39000
44000
49000
54000
320ns
DH
59000
RFREQ (Ω)
DT
Figure 34. fOSC vs. RFREQ
DT (DEAD TIME) = 40ns
06865-035
OSCILLATOR FREQUENCY (kHz)
550
1
Comment
180° out of phase with fOSC
In phase with fOSC
CLKOUT in-sync with
clock in
CLKOUT is low
DL
The SYNC input is used to synchronize the converter switching
frequency to an external signal. This allows multiple ADP1828
converters to be operated at the same frequency to prevent
frequency beating or other interactions. The ADP1828 has a
clock output (CLKOUT), which can be used for synchronizing
the ADP1829 and other ADP1828 controllers, thus eliminating
the need for an external clock source. Pulling CLKSET low sets
the frequency at CLKOUT to 1× the internal oscillator frequency,
fOSC, and is 180° out of phase with fOSC.
Rev. E | Page 17 of 33
Figure 35. Synchronization
ADP1828
Data Sheet
COMPENSATION
THERMAL SHUTDOWN
The control loop is compensated by an external series RC network
from COMP to FB and sometimes requires a series RC in parallel
with the top voltage divider resistor. COMP is the output of the
internal error amplifier.
In most applications, the ADP1828 controller itself does not
generate a significant amount of heat under normal conditions,
even when driving relatively large MOSFETs. However, the
surrounding power components or other circuits on the same
PCB can heat up the PCB to an unsafe operating temperature. A
thermal shutdown protection circuit on the ADP1828 shuts off
the LDO and the controllers if the die temperature exceeds
approximately 145°C, but this is a gross fault protection only
and must not be depended on for system reliability.
The internal error amplifier compares the voltage at FB to the
internal 0.6 V reference voltage. The difference between the FB
voltage and the 0.6 V reference voltage is amplified by the openloop voltage 1000 volt-to-volt gain of the error amplifier. To
optimize the ADP1828 for stability and transient response for a
given set of external components and input/output voltage
conditions, choose the compensation components carefully. For
more information on choosing the compensation components,
see the Compensating the Voltage Mode Buck Regulator
section.
POWER-GOOD INDICATOR
The ADP1828 features an open-drain power-good output
(PGOOD) that sinks current when the output voltage drops
8.3% below or rises 25% above the nominal regulation voltage.
Two comparators measure the voltage at FB to set these thresholds. The PGOOD comparator directly monitors FB, and the
threshold is fixed at 0.55 V for undervoltage and 0.75 V for
overvoltage. The PGOOD output also sinks current if an
overtemperature or input undervoltage condition is detected
and is operational with power-input voltage as low as 1.0 V.
Use this output as a logical power-good signal by connecting a
pull-up resistor from PGOOD to an appropriate supply voltage.
SHUTDOWN CONTROL
The ADP1828 dc-to-dc converter features a low power shutdown
mode that reduces the quiescent supply current to 20 μA, or
40 μA when IN is tied to VREG. To shut down the ADP1828,
drive EN low. To turn it on, drive EN high or tristate EN. For
automatic startup, connect EN to IN.
TRACKING
The ADP1828 features a tracking input, TRK that makes the
output voltage track another voltage, that is, the master voltage.
This feature is especially useful in core and input/output voltage
sequencing applications where the output of the ADP1828 can
be set to track and not exceed another voltage.
The internal error amplifier includes three positive inputs: the
internal 0.6 V reference voltage, and the SS and TRK pins. The
error amplifier regulates the FB pin to the lowest of the three
inputs. To track a supply voltage, tie the TRK pin to a resistor
divider from the voltage to be tracked. If the TRK function is
not used, tie the TRK pin to VREG.
Rev. E | Page 18 of 33
Data Sheet
ADP1828
APPLICATION INFORMATION
SELECTING THE INPUT CAPACITOR
The input current to a buck converter is a pulse waveform. It is
zero when the high-side switch is off and approximately equal
to the load current when it is on. The input capacitor carries the
input ripple current, allowing the input power source to supply
only the dc current. The input capacitor needs sufficient ripple
current rating to handle the input ripple as well as an ESR that
is low enough to mitigate input voltage ripple. For the usual
current ranges for these converters, it is good practice to use
two parallel capacitors placed close to the drains of the highside switch MOSFETs (one bulk capacitor of sufficiently high
current rating as calculated in Equation 2 along with a 10 μF
ceramic capacitor).
Select an input bulk capacitor based on its ripple current rating.
First, determine the duty cycle of the output with the larger load
current:
D=
VOUT
V IN
(1)
The input capacitor ripple current is approximately
I RIPPLE ≈ I L D(1 − D)
(2)
where:
IL is the maximum inductor or load current.
D is the duty cycle.
The output LC filter smoothes the switched voltage at SW, making
the dc output voltage. Choose the output LC filter to achieve the
desired output ripple voltage. Because the output LC filter is
part of the regulator negative-feedback control loop, the choice
of the output LC filter components affects the regulation control
loop stability.
Choose an inductor value such that the inductor ripple current
is approximately 1/3 of the maximum dc output load current.
Using a larger value inductor results in a physical size larger
than required and using a smaller value results in increased
losses in the inductor and/or MOSFET switches.
Choose the inductor value by the following equation:
f SW
V
1
VOUT 1 − OUT
× ∆I L
V IN
1
∆VOUT = ∆I L ESR 2 +
8
f
SW C OUT
2
+ (4 f SW ESL) 2
(4)
where:
∆VOUT is the output ripple voltage.
∆IL is the inductor ripple current.
ESR is the equivalent series resistance of the output capacitor
(or the parallel combination of ESR of all output capacitors).
ESL is the equivalent series inductance of the output capacitor
(or the parallel combination of ESL of all capacitors).
Note that the factors of 8 and 4 in Equation 4 would normally
be 2π for sinusoidal waveforms, but the ripple current waveform in this application is triangular. Parallel combinations of
different types of capacitors, for example, a large aluminum
electrolytic in parallel with MLCCs, can give different results.
Usually the impedance is dominated by ESR at the switching
frequency, as stated in the maximum ESR rating on the capacitor data sheet, so this equation reduces to
OUTPUT LC FILTER
L=
Choose the output bulk capacitor to set the desired output
voltage ripple. The impedance of the output capacitor at the
switching frequency multiplied by the ripple current gives the
output voltage ripple. The impedance is made up of the
capacitive impedance plus the nonideal parasitic characteristics,
including the equivalent series resistance (ESR) and the equivalent series inductance (ESL). The output voltage ripple can be
approximated with:
∆VOUT ≅ ∆IL ESR
Electrolytic capacitors have significant ESL also, on the order of
5 nH to 20 nH, depending on type, size, and geometry, and PCB
traces contribute some ESR and ESL as well. However, using the
maximum ESR rating from the capacitor data sheet usually
provides some margin such that measuring the ESL is not
usually required.
In the case of output capacitors, the impedance of the ESR and
ESL at the switching frequency are small, for instance, where
the effective output capacitor is a bank of parallel MLCC capacitors, the capacitive impedance dominates and the ripple
equation reduces to
∆VOUT ≅
(3)
where:
L is the inductor value.
fSW is the switching frequency.
VOUT is the output voltage.
VIN is the input voltage.
∆IL is the inductor ripple current, typically 1/3 of the maximum
dc load current.
(5)
∆I L
8C OUT f SW
(6)
Make sure that the ripple current rating of the output capacitors
is greater than the maximum inductor ripple current.
Rev. E | Page 19 of 33
ADP1828
Data Sheet
During a load step transient on the output, the output capacitor
supplies the load until the control loop has a chance to ramp the
inductor current. This initial output voltage deviation, due to a
change in load, is dependent on the output capacitor characteristics. Again, usually the capacitor ESR dominates this
response, and the ΔVOUT in Equation 6 can be used with the
load step current value for ΔIL.
SELECTING THE MOSFETS
The choice of MOSFET directly affects the dc-to-dc converter
performance. The MOSFET must have low on resistance to
reduce I2R losses and low gate charge to reduce transition losses.
In addition, the MOSFET must have low thermal resistance to
ensure that the power dissipated in the MOSFET does not result
in excessive MOSFET die temperature.
The high-side MOSFET carries the load current during on-time
and usually carries most of the transition losses of the converter.
Typically, the lower the MOSFET’s on resistance, the higher the
gate charge and vice versa. Therefore, it is important to choose a
high-side MOSFET that balances the two losses. The conduction
loss of the high-side MOSFET is determined by the equation
V
PC ≅ (I LOAD ) 2 R DSON OUT
V IN
(7)
where:
PC is the conduction power loss.
RDSON is the MOSFET on resistance.
The gate charging loss is approximated by the equation
PG ≅ V PV Q G f SW
(8)
where:
PG is the gate charging loss power.
VPV is the gate driver supply voltage.
QG is the MOSFET total gate charge.
fSW is the converter switching frequency.
V IN I LOAD (t R + t F ) f SW
2
TJ = TA + θJAPD
(9)
where:
PT is the high-side MOSFET switching loss power.
tR is the MOSFET rise time.
tF is the MOSFET fall time.
RDSON at TJ = RDSON at 25°C (1 + TC(TJ − 25°C))
(12)
where TC is the temperature coefficient of the MOSFET’s RDSON,
and its typical value is 0.004/°C.
Then the conduction losses can be recalculated and the procedure iterated until the junction temperature calculations are
relatively consistent.
The synchronous rectifier, or low-side MOSFET, carries the
inductor current when the high-side MOSFET is off. The lowside MOSFET transition loss is small and can be neglected in
the calculation. For high input voltage and low output voltage,
the low-side MOSFET carries the current most of the time.
Therefore, to achieve high efficiency, it is critical to optimize the
low-side MOSFET for low on resistance. In cases where the
power loss exceeds the MOSFET rating or lower resistance is
required than is available in a single MOSFET, connect multiple
low-side MOSFETs in parallel. The equation for low-side MOSFET
power loss is
(13)
where:
PLS is the total low-side MOSFET power loss.
RDSON is the total on resistance of the low-side MOSFET(s).
Check the gate charge losses of the synchronous rectifier using
Equation 8 to be sure it is reasonable. If multiple low-side
MOSFETs are used in parallel, then use the parallel combination of the on resistances for determining RDSON to solve this
equation.
The total power dissipation of the high-side MOSFET is the
sum of all the previous losses, or
PHS ≅ PC + PG + PT
(11)
Then, calculate the new RDSON from the temperature coefficient
curve and the RDSON specification at 25°C. An alternate method
to calculate the MOSFET RDSON at a second temperature, TJ, is
V
PLS ≅ (I LOAD ) 2 R DSON 1 − OUT
V IN
The high-side MOSFET transition loss is approximated by the
equation
PT =
The conduction losses can need an adjustment to account for the
MOSFET RDSON variation with temperature. Note that MOSFET
RDSON increases with increasing temperature. The MOSFET data
sheet must list the thermal resistance of the package, θJA, along with
a normalized curve of the temperature coefficient of the RDSON. For
the power dissipation estimated in Equation 10, calculate the
MOSFET junction temperature rise over the ambient temperature
of interest:
(10)
where PHS is the total high-side MOSFET power loss.
Rev. E | Page 20 of 33
Data Sheet
ADP1828
SETTING THE CURRENT LIMIT
The current-limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
The current limit is set through the current-limit resistor, RCL.
The current sense pin, CSL, sources 50 μA through the external
current-limit setting resistor, RCL. This creates an offset voltage
of RCL multiplied by the 50 μA CSL current. When the drop
across the low-side MOSFET RDSON is equal to or greater than
this offset voltage, the ADP1828 flags a current-limit event.
Because the CSL current and the MOSFET RDSON vary over
process and temperature, the minimum current limit must be
set to ensure that the system can handle the maximum desired
load current. To do this, use the peak current in the inductor,
which is the desired current-limit level plus the ripple current,
the maximum RDSON of the MOSFET at its highest expected
temperature, and the minimum CSL current:
RCL =
I LPK RDSON ( MAX ) − 38 mV
(14)
42 μA
where:
ILPK is the peak inductor current.
−38 mV is the CSL threshold voltage.
Because the buck converters are usually running a fairly high
current, PCB layout and component placement can affect the
current-limit setting. An iteration of the RCL value can be required
for a particular board layout and MOSFET selection. If alternate
MOSFETs are substituted at some point in production, these
resistor values can need an iteration.
ACCURATE CURRENT-LIMIT SENSING
The RDSON of the external low-side MOSFET can vary by more
than 50% over the temperature range. Accurate current-limit
sensing can be achieved by adding a current sense resistor from
the source of the low-side MOSFET to PGND. Make sure that
the power rating of the current sense resistor is adequate for the
application. Apply Equation 14 to calculate RCL and replace
RDSON(MAX) with RSENSE.
VIN
with 100 nA bias current, the low-side resistor, RBOT, needs to be
less than 9 kΩ, which results in 67 µA of divider current. For
RBOT, use a 1 kΩ to 10 kΩ resistor. A larger value resistor can be
used, but results in a reduction in output voltage accuracy due
to the input bias current at the FB pin, while lower values cause
increased quiescent current consumption. Choose RTOP to set
the output voltage by using the following equation:
V
− VFB
RTOP = R BOT OUT
V
FB
COMPENSATING THE VOLTAGE MODE BUCK
REGULATOR
Assuming the LC filter design is complete, the feedback control
system can then be compensated. Good compensation is critical
to proper operation of the regulator. Calculate the quantities in
Equation 16 through Equation 44 to derive the compensation
values. The goal is to guarantee that the voltage gain of the buck
converter crosses unity at a slope that provides adequate phase
margin for stable operation. Additionally, at frequencies above
the crossover frequency (fCO), guaranteeing sufficient gain margin
and attenuation of switching noise are important secondary
goals. For initial practical designs, a good choice for the
crossover frequency is one tenth of the switching frequency,
calculate first
f CO =
f LC =
COUT
DL
RCL
RSENSE
06865-037
CSL
Figure 36. Accurate Current-Limit Sensing
FEEDBACK VOLTAGE DIVIDER
The output regulation voltage is set through the feedback voltage divider. The output voltage is divided down through the
voltage divider and drives the FB feedback input. The regulation
threshold at FB is 0.6 V. The maximum input bias current into
FB is 100 nA. For a 0.15% degradation in regulation voltage and
(16)
The output LC filter is a resonant network that inflicts two poles
upon the response at a frequency (fLC). Next, calculate
VOUT
M2
f SW
10
This gives sufficient frequency range to design a compensation
scheme that attenuates switching artifacts, while also giving
sufficient control loop bandwidth to provide a good transient
response.
M1
L
(15)
where:
RTOP is the high-side voltage divider resistance.
RBOT is the low-side voltage divider resistance.
VOUT is the regulated output voltage.
VFB is the feedback regulation threshold, 0.6 V.
ADP1828
DH
1
2π LC
(17)
Generally speaking, the LC corner frequency is about two
orders of magnitude below the switching frequency, and
therefore about one order of magnitude below crossover. To
achieve sufficient phase margin at crossover to guarantee
stability, the design must compensate for the two poles at the
LC corner frequency with two zeros to boost the system phase
prior to crossover. The two zeros require an additional pole or
two above the crossover frequency to guarantee adequate gain
margin and attenuation of switching noise at high frequencies.
Rev. E | Page 21 of 33
ADP1828
Data Sheet
Depending on component selection, one zero might already be
generated by the ESR of the output capacitor. Calculate this zero
corner frequency, fESR, as
f ESR
1
2π RESRCOUT
AFILTER ALC A ESR
f
A FILTER 40 dB log ESR
f LC
f
20 dB log CO
f
ESR
(19)
If fESR ≈ fCO, then add another 3 dB to account for the local
difference between the exact solution and the linear approximation in Equation 19.
fLC
fESR
fCO
fSW
–40dB/dec
AFILTER
PHASE
0°
–90°
06865-038
ΦFILTER
–180°
Figure 37. LC Filter Bode Plot
To compensate the control loop, the gain of the system must
be brought back up so that it is 0 dB at the desired crossover
frequency. Some gain is provided by the PWM modulation itself.
V
A MOD 20 log IN
V
RAMP
(20)
For systems using the internal oscillator, this becomes
V
A MOD 20 log IN
1.0 V
AT = AMOD + AFILTER + ACOMP
(23)
where:
AMOD is the gain of the PWM modulator.
AFILTER is the gain of the LC filter including the effects of
the ESR zero.
ACOMP is the gain of the compensated error amplifier.
Additionally, the phase of the system must be brought back up
to guarantee stability. Note from the Bode plot of the filter that
the LC contributes −180° of phase shift (see Figure 37). Because
the error amplifier is an integrator at low frequency, it contributes
an initial −90°. Therefore, before adding compensation or
accounting for the ESR zero, the system is already down −270°.
To avoid loop inversion at crossover, or −180° phase shift, a good
initial practical design is to require a phase margin of 60°, which
is therefore an overall phase loss of −120° from the initial low
frequency dc phase. The goal of the compensation is to boost
the phase back up from −270° to −120° at crossover.
FREQUENCY
–20dB/dec
(22)
For example, if FREQ is grounded or connected to VREG, then
fFREQ is 300 kHz or 600 kHz, respectively. If the frequency is set
by a resistor, then fFREQ is 300 kHz and fSYNC is the frequency set
by the resistor. VRAMP is greater than 1.0 V if fSYNC is less than
fFREQ. The rest of the system gain needs to reach 0 dB at crossover. The total gain of the system, therefore, is given by
The gain of the LC filter at crossover can be linearly
approximated from Figure 37 as
0dB
f
VRAMP 1.0 V FREQ
f SYNC
(18)
Figure 37 shows a typical Bode plot of the LC filter by itself.
GAIN
Note that if the converter is being synchronized, the ramp
voltage, VRAMP, is lower than 1.0 V by the percentage of
frequency increase over the nominal setting of the FREQ pin:
(21)
Two common compensation schemes are used, which are
sometimes referred to as Type II or Type III compensation,
depending on whether the compensation design includes two
or three poles (see the Type II Compensator and Type III
Compensator sections). Dominant-pole compensation, or
single-pole compensation, is referred to as Type I compensation,
but it is not very useful for dealing successfully with switching
regulators.
If the zero produced by the ESR of the output capacitor provides
sufficient phase boost at crossover, Type II compensation is
adequate. If the phase boost produced by the ESR of the output
capacitor is not sufficient, another zero is added to the compensation network, and thus Type III is used.
In Figure 38, the location of the ESR zero corner frequency
gives a significantly different net phase at the crossover
frequency.
Rev. E | Page 22 of 33
Data Sheet
ADP1828
Use the following guidelines for selecting between Type II and
Type III compensators:
G
(dB)
f
CO , use Type II compensation.
2
–1
S
LO
PE
–1
S
PHASE
If f ESRZ fCO , use Type III compensation.
LO
PE
fP
fZ
–180°
2
–270°
CHF
PHASE CONTRIBUTION AT CROSSOVER
OF VARIOUS ESR ZERO CORNERS
RZ
GAIN
fLC fESR1 fESR2 fESR3 fCO
0dB
fSW
FREQUENCY
–40dB/dec
CI
RTOP
VOUT
FB
RBOT
EA
COMP
INTERNAL
VREF
–20dB/dec
06865-040
If f ESRZ
Type II Compensator
Figure 39. Type II Compensation
If the output capacitor ESR zero frequency is sufficiently low (≤½ of
the crossover frequency), use the ESR to stabilize the regulator. In
this case, use the circuit shown in Figure 39. Calculate the
compensation resistor, RZ, with the following equation:
PHASE
0°
RZ
Φ1
Φ2
Next, choose the compensation capacitor to set the compensation zero, fZ1, to the lesser of ¼ of the crossover frequency or ½
of the LC resonant frequency
06865-039
Φ3
Figure 38. LC Filter Bode Plot
The following equations are used for the calculation of the
compensation components as shown in Figure 39 and Figure 40:
f Z1
f Z2
f P1
1
2R Z C I
(24)
1
2C FF (RTOP R FF )
1
C I C HF
2R Z
C I C HF
f P2
1
2R FF C FF
(28)
where:
fCO is chosen to be 1/10 of fSW.
VRAMP is 1.0 V.
–90°
–180°
RTOP VRAMP f ESR f CO
V IN f LC 2
f Z1
f CO
f Z1
f LC
4
f SW
1
2R Z C I
40
1
2R Z C I
(29)
or
(25)
2
(30)
Solving for CI in Equation 29 yields
(26)
CI
20
R Z f SW
(31)
Solving for CI in Equation 30 yields
(27)
where:
fZ1 is the zero produced in the Type II compensation.
fZ2 is the zero produced in the Type III compensation.
fP1 is the pole produced in the Type II compensation.
fP2 in the pole produced in the Type III compensation.
Rev. E | Page 23 of 33
CI
1
R Z f LC
(32)
ADP1828
Data Sheet
Use the larger value of CI from Equation 31 or Equation 32.
Because of the finite output current drive of the error amplifier,
CI needs to be less than 10 nF. If it is larger than 10 nF, choose a
larger RTOP and recalculate RZ and CI until CI is less than 10 nF.
Next, calculate CI,
Next, choose the high frequency pole, fP1, to be ½ of fSW.
Because of the finite output current drive of the error amplifier,
CI needs to be less than 10 nF. If it is larger than 10 nF, choose a
larger RTOP and recalculate RZ and CI until CI is less than 10 nF.
f P1
1
f SW
2
(33)
1
2R Z C HF
(34)
Combine Equation 33 and Equation 34, and solve for CHF,
C HF
1
(35)
f SW R Z
C HF
f Z2
–1
SL
O
PE
O
SL
+1
–1
SL
O
PE
C FF
fP
PHASE
CHF
RFF
CFF
RZ
EA
R FF
COMP
INTERNAL
VREF
06865-041
FB
RBOT
Figure 40. Type III Compensation
If the output capacitor ESR zero frequency is greater than ½ of
the crossover frequency, use the Type III compensator as shown
in Figure 40. Set the poles and zeros as follows:
f P1 f P2
1
f SW
2
f Z1 f Z2
f CO
f Z1 f Z2
f LC
1
2
2R Z C I
(36)
f SW
40
1
2R Z C I
(37)
or
(38)
Use the lower zero frequency from Equation 37 or Equation 38.
Calculate the compensator resistor, RZ
RZ
1
2C FF RTOP
(42)
1
2RTOP f Z2
(43)
The feedforward resistor, RFF, can be calculated by combining
Equation 27 and Equation 36
CI
RTOP
4
(41)
where fZ2 is obtained from Equation 37 or Equation 38.
–270°
VOUT
1
f SW R Z
Solving CFF in Equation 42 yields
PE
fZ
–90°
(40)
Next, calculate the feedforward capacitor CFF. Assuming RFF
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