Dual, Interleaved, Step-Down
DC-to-DC Controller with Tracking
ADP1829
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
Fixed frequency operation: 300 kHz, 600 kHz, or
synchronized operation up to 1 MHz
Supply input range: 3.0 V to 20 V
Wide power stage input range: 1 V to 24 V
Interleaved operation results in smaller, low cost
input capacitor
All-N-channel MOSFET design for low cost
±0.85% accuracy at 0°C to 70°C
Soft start, thermal overload, current-limit protection
10 µA shutdown supply current
Internal linear regulator
Lossless RDSON current-limit sensing
Reverse current protection during soft start for handling
precharged outputs
Independent Power OK outputs
Voltage tracking for sequencing or DDR termination
Available in 5 mm × 5 mm, 32-lead LFCSP
APPLICATIONS
VIN = 12V
180µF
180µF
1µF
PV IN
TRK1
EN1
EN2
TRK2
VREG
0.47µF
IRLR7807Z
BST2
BST1
0.47µF
IRLR7807Z
DH2
DH1
ADP1829
1.2V,
6A
2.2µH
2.2µH
2kΩ
560µF
2kΩ
SW1
SW2
CSL1
DL1
CSL2
PGND2
PGND1
FB1
2kΩ
560µF
DL2
IRFR3709Z
1.8V,
8A
IRFR3709Z
2kΩ
FB2
390pF
1kΩ
COMP2
390pF
2kΩ
COMP1
3900pF 4.53kΩ
FREQ
4.53kΩ 3900pF
LDOSD
GND
SYNC
06784-001
Telecommunications and networking systems
Medical imaging systems
Base station power
Set-top boxes
Printers
DDR termination
Figure 1.
GENERAL DESCRIPTION
The ADP1829 is a versatile, dual, interleaved, synchronous
PWM buck controller that generates two independent output
rails from an input of 3.0 V to 20 V, with power input voltage
ranging from 1.0 V to 24 V. Each controller can be configured
to provide output voltages from 0.6 V to 85% of the input
voltage and is sized to handle large MOSFETs for point-of-load
regulators. The two channels operate 180° out of phase,
reducing stress on the input capacitor and allowing smaller, low
cost components. The ADP1829 is ideal for a wide range of
high power applications, such as DSP and processor core I/O
power, and general-purpose power in telecommunications,
medical imaging, PC, gaming, and industrial applications.
The ADP1829 operates at a pin-selectable, fixed switching
frequency of either 300 kHz or 600 kHz, minimizing external
component size and cost. For noise-sensitive applications, it can
Rev. D
also be synchronized to an external clock to achieve switching
frequencies between 300 kHz and 1 MHz. The ADP1829
includes soft start protection to prevent inrush current from the
input supply during startup, reverse current protection during
soft start for precharged outputs, as well as a unique adjustable
lossless current-limit scheme utilizing external MOSFET sensing.
For applications requiring power supply sequencing, the
ADP1829 also provides tracking inputs that allow the output
voltages to track during startup, shutdown, and faults. This
feature can also be used to implement DDR memory bus
termination.
The ADP1829 is specified over the −40°C to +125°C junction
temperature range and is available in a 32-lead LFCSP package.
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ADP1829
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Tracking ....................................................................................... 14
Applications ....................................................................................... 1
MOSFET Drivers ........................................................................ 15
Typical Application Circuit ............................................................. 1
Current Limit .............................................................................. 15
General Description ......................................................................... 1
Applications Information .............................................................. 16
Revision History ............................................................................... 2
Selecting the Input Capacitor ................................................... 16
Specifications..................................................................................... 3
Selecting the MOSFETs ............................................................. 17
Absolute Maximum Ratings ............................................................ 5
Setting the Current Limit .......................................................... 18
ESD Caution .................................................................................. 5
Feedback Voltage Divider ......................................................... 18
Functional Block Diagram .............................................................. 6
Compensating the Voltage Mode Buck Regulator ................. 19
Pin Configuration and Function Descriptions ............................. 7
Soft Start ...................................................................................... 22
Typical Performance Characteristics ............................................. 9
Voltage Tracking ......................................................................... 22
Theory of Operation ...................................................................... 13
Coincident Tracking .................................................................. 23
Input Power ................................................................................. 13
Ratiometric Tracking ................................................................. 23
Start-Up Logic ............................................................................. 13
Thermal Considerations............................................................ 24
Internal Linear Regulator .......................................................... 13
PCB Layout Guidelines .................................................................. 25
Oscillator and Synchronization ................................................ 13
LFCSP Package Considerations................................................ 25
Error Amplifier ........................................................................... 14
Application Circuits ....................................................................... 26
Soft Start ...................................................................................... 14
Outline Dimensions ....................................................................... 28
Power OK Indicator ................................................................... 14
Ordering Guide .......................................................................... 28
REVISION HISTORY
4/16—Rev. C to Rev. D
Changes to Figure 3 .......................................................................... 7
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
10/12—Rev. B to Rev. C
Changes to PCB Layout Guidelines Section ............................... 25
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
1/11—Rev. A to Rev. B
Changes to VREG Short-Circuit Current Parameter, Table 1 .... 3
Changes to Figure 3 and Table 3 ..................................................... 7
Added Exposed Paddle Notation to Outline Dimensions ........ 29
4/09—Rev. 0 to Rev. A
Changes to Features and General Description Sections ..............1
Changes to IN Input Voltage; EN1, IN2 Input High Voltage;
EN1, EN2 Input Low Voltage; and EN1, EN2 Input Impedance
to 5 V Zener Parameters, Table 1 ....................................................3
Changes to Table 2.............................................................................5
Changes to Table 3.............................................................................7
Changes to Theory of Operation Section, Input Power Section,
and Start-Up Logic Section ........................................................... 13
Changes to Ordering Guide .......................................................... 29
6/07—Revision 0: Initial Version
Rev. D | Page 2 of 28
Data Sheet
ADP1829
SPECIFICATIONS
IN = 12 V, ENx = FREQ = PV = VREG = 5 V, SYNC = GND, TJ = −40°C to +125°C, unless otherwise specified. All limits at temperature
extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C.
Table 1.
Parameter
POWER SUPPLY
IN Input Voltage
IN Quiescent Current
IN Shutdown Current
VREG Undervoltage Lockout Threshold
VREG Undervoltage Lockout Hysteresis
ERROR AMPLIFIER
FB1, FB2 Regulation Voltage
FB1, FB2 Input Bias Current
Open-Loop Voltage Gain
Gain-Bandwidth Product
COMP1, COMP2 Sink Current
COMP1, COMP2 Source Current
COMP1, COMP2 Clamp High Voltage
COMP1, COMP2 Clamp Low Voltage
LINEAR REGULATOR
VREG Output Voltage
VREG Load Regulation
VREG Line Regulation
VREG Current Limit
VREG Short-Circuit Current
IN to VREG Dropout Voltage 1
VREG Minimum Output Capacitance
PWM CONTROLLER
PWM Ramp Voltage Peak
DH1, DH2 Maximum Duty Cycle
DH1, DH2 Minimum Duty Cycle
SOFT START
SS1, SS2 Pull-Up Resistance
SS1, SS2 Pull-Down Resistance
SS1, SS2 to FB1, FB2 Offset Voltage
SS1, SS2 Pull-Up Voltage
TRACKING
TRK1, TRK2 Common-Mode Input
Voltage Range
TRK1, TRK2 to FB1, FB2 Offset Voltage
TRK1, TRK2 Input Bias Current
Conditions
Min
PV = VREG (using internal regulator)
IN = PV = VREG (not using internal regulator)
Not switching, IVREG = 0 mA
EN1 = EN2 = GND
VREG rising
5.5
3.0
TA = 25°C, TRK1, TRK2 > 700 mV
TJ = 0°C to 85°C, TRK1, TRK2 > 700 mV
TJ = −40°C to +125°C, TRK1, TRK2 > 700 mV
TJ = 0°C to 70°C, TRK1, TRK2 > 700 mV
597
591
588
595
2.4
Typ
1.5
10
2.7
0.125
600
Max
Unit
20
5.5
3
20
3.0
V
V
mA
μA
V
V
603
609
612
605
100
mV
mV
mV
mV
nA
dB
MHz
μA
μA
V
V
5.15
5.25
V
V
mV
mV
mA
mA
V
μF
70
20
600
120
2.4
0.75
TA = 25°C, IVREG = 20 mA
IN = 7 V to 18 V, IVREG = 0 mA to 100 mA
IVREG = 0 mA to 100 mA, IN = 12 V
IN = 7 V to 18 V, IVREG = 20 mA
VREG = 4 V
VREG < 0.5 V
IVREG = 100 mA, IN < 5 V
4.85
4.75
5.0
5.0
−40
1
220
140
0.7
200
1.4
1
SYNC = GND
FREQ = GND (300 kHz)
FREQ = GND (300 kHz)
91
SS1, SS2 = GND
SS1, SS2 = 0.6 V
SS1, SS2 = 0 mV to 500 mV
TRK1, TRK2 = 0 mV to 500 mV
Rev. D | Page 3 of 28
1.3
93
1
3
90
6
−45
0.8
V
%
%
kΩ
kΩ
mV
V
0
600
mV
−5
+5
100
mV
nA
ADP1829
Parameter
OSCILLATOR
Oscillator Frequency
SYNC Synchronization Range 2
SYNC Minimum Input Pulse Width
CURRENT SENSE
CSL1, CSL2 Threshold Voltage
CSL1, CSL2 Output Current
Current Sense Blanking Period
GATE DRIVERS
DH1, DH2 Rise Time
DH1, DH2 Fall Time
DL1, DL2 Rise Time
DL1, DL2 Fall Time
DH to DL, DL to DH Dead Time
LOGIC THRESHOLDS
SYNC, FREQ, LDOSD Input High Voltage
SYNC, FREQ, LDOSD Input Low Voltage
SYNC, FREQ Input Leakage Current
LDOSD Pull-Down Resistance
EN1, EN2 Input High Voltage
EN1, EN2 Input Low Voltage
EN1, EN2 Current Source
EN1, EN2 Input Impedance to 5 V Zener
THERMAL SHUTDOWN
Thermal Shutdown Threshold 3
Thermal Shutdown Hysteresis3
POWER GOOD
FB1, UV2 Overvoltage Threshold
FB1, UV2 Overvoltage Hysteresis
FB1, UV2 Undervoltage Threshold
FB1, UV2 Undervoltage Hysteresis
POK1, POK2 Propagation Delay
POK1, POK2 Off Leakage Current
POK1, POK2 Output Low Voltage
UV2 Input Bias Current
Data Sheet
Conditions
Min
Typ
Max
Unit
SYNC = FREQ = GND (fSW = fOSC)
SYNC = GND, FREQ = VREG (fSW = fOSC)
FREQ = GND, SYNC = 600 kHz to 1.2 MHz (fSW = fSYNC/2)
FREQ = VREG, SYNC = 1.2 MHz to 2 MHz (fSW = fSYNC/2)
240
480
300
600
300
600
370
720
600
1000
200
kHz
kHz
kHz
kHz
ns
Relative to PGND
CSL1, CSL2 = PGND
−30
44
0
50
100
+30
56
mV
μA
ns
CDH = 3 nF, VBST − VSW = 5 V
CDH = 3 nF, VBST − VSW = 5 V
CDL = 3 nF
CDL = 3 nF
15
10
15
10
40
ns
ns
ns
ns
ns
2.2
0.4
1
SYNC, FREQ = 0 V to 5.5 V
100
IN = 3.0 V to 20 V
IN = 3.0 V to 20 V
EN1, EN2 = 0 V to 3.0 V
EN1, EN2 = 5.5 V to 20 V
VFB1, VUV2 rising
VFB1, VUV2 rising
VPOK1, VPOK2 = 5.5 V
IPOK1, IPOK2 = 10 mA
2.0
−0.3
−0.6
100
0.8
−1.5
V
V
μA
kΩ
V
V
μA
kΩ
145
15
°C
°C
750
50
550
50
8
mV
mV
mV
mV
μs
μA
mV
nA
150
10
1
500
100
Not recommended to use the LDO in dropout when VIN < 5.5 V because of the dropout voltage. Connect IN to VREG when VIN < 5.5 V.
SYNC input frequency is 2× single-channel switching frequency. The SYNC frequency is divided by 2 and the separate phases were used to clock the controllers.
3
Guaranteed by design and not subject to production test.
1
2
Rev. D | Page 4 of 28
Data Sheet
ADP1829
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
IN, EN1, EN2
BST1, BST2
BST1, BST2 to SW1, SW2
CSL1, CSL2
SW1, SW2
DH1
DH2
DL1, DL2 to PGND
PGND to GND
LDOSD, SYNC, FREQ, COMP1,
COMP2, SS1, SS2, FB1, FB2, VREG,
PV, POK1, POK2, TRK1, TRK2
θJA 4-Layer
(JEDEC Standard Board) 1, 2
Operating Ambient Temperature
Operating Junction Temperature 3
Storage Temperature
Rating
−0.3 V to +20.5 V
−0.3 V to +30 V
−0.3 V to +6 V
−1 V to +30 V
−2 V to +30 V
SW1 − 0.3 V to BST1 + 0.3 V
SW2 − 0.3 V to BST2 + 0.3 V
−0.3 V to PV + 0.3 V
±2 V
−0.3 V to +6 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
45°C/W
−40°C < TA< +85°C
−40°C < TJ < +125°C
−65°C to +150°C
Measured with exposed pad attached to PCB.
Junction-to-ambient thermal resistance (θJA) of the package is based on
modeling and calculation using a 4-layer board. The junction-to-ambient
thermal resistance is application and board-layout dependent. In applications where high maximum power dissipation exists, attention to thermal
dissipation issues in board design is required. For more information, refer to
Application Note AN-772, A Design and Manufacturing Guide for the Lead
Frame Chip Scale Package (LFCSP).
3
In applications where high power dissipation and poor package thermal
resistance are present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA_MAX) is dependent on the
maximum operating junction temperature (TJ_MAX_OP = 125oC), the maximum
power dissipation of the device in the application (PD_MAX), and the junctionto-ambient thermal resistance of the part/package in the application (θJA)
and is given by the following equation: TA_MAX = TJ_MAX_OP – (θJA × PD_MAX).
1
2
Rev. D | Page 5 of 28
ADP1829
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
IN
ADP1829
VREG
LINEAR REG
0.75V
0.6V
0.8V
REF
0.55V
THERMAL
SHUTDOWN
UVLO
VREG
VREG
BST1
LDOSD
ILIM2
EN1
DH1
CK1
LOGIC
S
Q
SW1
PWM
EN2
FAULT1
R
FAULT2
PV
Q
CK1
FREQ
SYNC
DL1
RAMP1
OSCILLATOR
PHASE 1 = 0°
PHASE 2 = 180°
VREG
+
ILIM1
CK2
50µA
PGND1
–
CSL1
RAMP2
RAMP1
+
POK1
–
COMP1
FB1
TRK1
0.6V
–
+
+
+
0.75V
+
–
BST2
+
SS1
0.8V
0.55V
DH2
–
S
CK2
FAULT1
Q
PWM
RAMP2
+
R
Q
–
COMP2
FB2
TRK2
0.6V
–
+
+
+
0.75V
+
–
SW2
PV
DL2
VREG
50µA
ILIM2
+
PGND2
–
UV2
+
SS2
0.8V
CSL2
POK2
0.55V
–
FAULT2
GND
06784-002
BOTTOM PADDLE
OF LFCSP
Figure 2.
Rev. D | Page 6 of 28
Data Sheet
ADP1829
COMP1
TRK1
SS1
VREG
IN
LDOSD
EN2
EN1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADP1829
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
POK1
BST1
DH1
SW1
CSL1
PGND1
DL1
PV
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
06784-003
SS2
POK2
BST2
DH2
SW2
CSL2
PGND2
DL2
9
10
11
12
13
14
15
16
FB1
SYNC
FREQ
GND
UV2
FB2
COMP2
TRK2
32
31
30
29
28
27
26
25
PIN 1
INDICATOR
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
FB1
2
SYNC
3
4
FREQ
GND
5
UV2
6
FB2
7
8
COMP2
TRK2
9
10
SS2
POK2
11
BST2
12
13
14
DH2
SW2
CSL2
15
16
17
PGND2
DL2
PV
18
19
20
DL1
PGND1
CSL1
21
22
SW1
DH1
Description
Feedback Voltage Input for Channel 1. Connect a resistor divider from the buck regulator output to GND and tie
the tap to FB1 to set the output voltage.
Frequency Synchronization Input. Accepts external signal between 600 kHz and 1.2 MHz or between 1.2 MHz
and 2 MHz depending on whether FREQ is low or high, respectively. Connect SYNC to ground if not used.
Frequency Select Input. Low for 300 kHz or high for 600 kHz.
Ground. Connect to a ground plane directly beneath the ADP1829. Tie the bottom of the feedback dividers to
this GND.
Input to the POK2 Undervoltage and Overvoltage Comparators. For the default thresholds, connect UV2
directly to FB2. For some tracking applications, connect UV2 to an extra tap on the FB2 voltage divider string.
Voltage Feedback Input for Channel 2. Connect a resistor divider from the buck regulator output to GND and
tie the tap to FB2 to set the output voltage.
Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to FB2 to compensate Channel 2.
Tracking Input for Channel 2. To track a master voltage, drive TRK2 from a voltage divider from the master
voltage. If the tracking function is not used, connect TRK2 to VREG.
Soft Start Control Input. Connect a capacitor from SS2 to GND to set the soft start period.
Open-Drain Power OK Output for Channel 2. Sinks current when UV2 is out of regulation. Connect a pull-up
resistor from POK2 to VREG.
Boost Capacitor Input for Channel 2. Powers the high-side gate driver DH2. Connect a 0.22 μF to 0.47 μF
ceramic capacitor from BST2 to SW2 and a Schottky diode from PV to BST2.
High-Side (Switch) Gate Driver Output for Channel 2.
Switch Node Connection for Channel 2.
Current Sense Comparator Inverting Input for Channel 2. Connect a resistor between CSL2 and SW2 to set the
current-limit offset.
Ground for Channel 2 Gate Driver. Connect to a ground plane directly beneath the ADP1829.
Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 2.
Positive Input Voltage for Gate Driver DL1 and Gate Driver DL2. Connect PV to VREG and bypass to ground with
a 1 μF capacitor.
Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 1.
Ground for Channel 1 Gate Driver. Connect to a ground plane directly beneath the ADP1829.
Current Sense Comparator Inverting Input for Channel 1. Connect a resistor between CSL1 and SW1 to set the
current-limit offset.
Switch Node Connection for Channel 1.
High-Side (Switch) Gate Driver Output for Channel 1.
Rev. D | Page 7 of 28
ADP1829
Pin No.
23
Mnemonic
BST1
24
POK1
25
EN1
26
EN2
27
LDOSD
28
IN
29
VREG
30
31
SS1
TRK1
32
COMP1
EPAD
Data Sheet
Description
Boost Capacitor Input for Channel 1. Powers the high-side gate driver DH1. Connect a 0.22 μF to 0.47 μF
ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1.
Open-Drain Power OK Output for Channel 1. Sinks current when FB1 is out of regulation. Connect a pull-up
resistor from POK1 to VREG.
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn off.
Enabling starts the internal LDO. Tie to IN for automatic startup.
Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off.
Enabling starts the internal LDO. Tie to IN for automatic startup.
LDO Shut-Down Input. Only used to shut down the LDO in those applications where IN is tied directly to VREG.
Otherwise, connect LDOSD to GND or leave it open, as it has an internal 100 kΩ pull-down resistor.
Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 20 V to power the ADP1829 from the LDO.
For input voltages between 3.0 V and 5.5 V, tie IN to VREG and PV.
Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from VREG.
Bypass VREG to ground plane with 1 μF ceramic capacitor.
Soft Start Control Input. Connect a capacitor from SS1 to GND to set the soft start period.
Tracking Input for Channel 1. To track a master voltage, drive TRK1 from a voltage divider to the master voltage.
If the tracking function is not used, connect TRK1 to VREG.
Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to FB1 to compensate Channel 1.
The exposed pad must be connected to AGND.
Rev. D | Page 8 of 28
Data Sheet
ADP1829
TYPICAL PERFORMANCE CHARACTERISTICS
95
92
VIN = 5V
SWITCHING FREQUENCY = 300kHz
VIN = 12V
90
90
85
EFFICIENCY (%)
EFFICIENCY (%)
88
VIN = 20V
VIN = 15V
80
86
84
SWITCHING FREQUENCY = 600kHz
82
75
0
5
10
15
20
LOAD CURRENT (A)
78
06784-004
70
0
5
10
20
15
LOAD CURRENT (A)
Figure 4. Efficiency vs. Load Current, VOUT = 1.8 V, 300 kHz Switching
06784-007
80
Figure 7. Efficiency vs. Load Current, VIN = 12 V, VOUT = 1.8 V
95
4.980
VOUT = 3.3V
90
4.975
VREG VOLTAGE (V)
EFFICIENCY (%)
VOUT = 1.8V
85
VOUT = 1.2V
80
4.970
4.965
5
10
15
20
LOAD CURRENT (A)
4.960
–40
–15
10
35
60
85
06784-008
0
06784-005
70
20
06784-009
75
TEMPERATURE (°C)
Figure 5. Efficiency vs. Load Current, VIN = 12 V, 300 kHz Switching
Figure 8. VREG Voltage vs. Temperature
94
4.970
SWITCHING FREQUENCY = 300kHz
92
4.968
4.966
90
VREG (V)
86
SWITCHING FREQUENCY = 600kHz
84
4.962
4.960
4.958
4.956
82
4.954
80
78
4.952
0
5
10
15
LOAD CURRENT (A)
20
06784-006
EFFICIENCY (%)
4.964
88
Figure 6. Efficiency vs. Load Current, VIN = 5 V, VOUT = 1.8 V
4.950
5
8
11
14
17
INPUT VOLTAGE (V)
Figure 9. VREG vs. Input Voltage, 10 mA Load
Rev. D | Page 9 of 28
ADP1829
Data Sheet
4.960
0.6010
0.6005
FEEDBACK VOLTAGE (V)
4.952
4.948
4.944
0.6000
0.5995
0.5990
0.5985
0
20
40
60
80
100
LOAD CURRENT (mA)
0.5980
–40
06784-010
4.940
–15
10
35
60
85
TEMPERATURE (°C)
Figure 10. VREG vs. Load Current, VIN = 12 V
06784-013
VREG (V)
4.956
Figure 13. Feedback Voltage vs. Temperature, VIN = 12 V
330
5
320
FREQUENCY (Hz)
310
3
2
300
290
280
1
50
100
150
200
250
LOAD CURRENT (mA)
260
–40
–15
10
35
60
85
06784-014
0
06784-011
0
20
06784-015
270
TEMPERATURE (°C)
Figure 11. VREG Current-Limit Foldback
Figure 14. Switching Frequency vs. Temperature, VIN = 12 V
5
T
SUPPLY CURRENT (mA)
4
VREG, AC-COUPLED, 1V/DIV
SW1 PIN, VOUT = 1.8V, 10V/DIV
3
2
1
SW2 PIN, VOUT = 1.2V, 10V/DIV
200ns/DIV
06784-012
VREG OUTPUT (V)
4
0
2
5
8
11
14
17
SUPPLY VOLTAGE (V)
Figure 15. Supply Current vs. Input Voltage
Figure 12. VREG Output During Normal Operation
Rev. D | Page 10 of 28
Data Sheet
ADP1829
T EXTERNAL CLOCK, FREQUENCY = 1MHz
T
VOUT1, AC-COUPLED,
100mV/DIV
SW PIN, CHANNEL 1
LOAD ON
100µs/DIV
400ns/DIV
Figure 16. 1.5 A to 15 A Load Transient Response, VIN = 12 V
T
06784-019
SW PIN, CHANNEL 2
LOAD OFF
06784-016
LOAD OFF
Figure 19. Out-of-Phase Switching, External 1 MHz Clock
T
SS1, 0.5V/DIV
VOUT1, 0.5V/DIV
EXTERNAL CLOCK, FREQUENCY = 2MHz
SW PIN, CHANNEL 1
INPUT CURRENT, 0.2A/DIV
SHORT CIRCUIT REMOVED
06784-020
SW PIN, CHANNEL 2
4ms/DIV
06784-017
SHORT CIRCUIT APPLIED
200ns/DIV
Figure 17. Output Short-Circuit Response
Figure 20. Out-of-Phase Switching, External 2 MHz Clock
T
VIN = 12V
T
VOUT1, 2V/DIV
SWITCH NODE
CHANNEL 1
EN1, 5V/DIV
10ms/DIV
Figure 18. Out-of-Phase Switching, Internal Oscillator
Figure 21. Enable Pin Response, VIN = 12 V
Rev. D | Page 11 of 28
06784-021
400ns/DIV
06784-018
SWITCH NODE CHANNEL 2
ADP1829
Data Sheet
T
VIN, 5V/DIV
EN2 PIN, 5V/DIV
VOUT2, 2V/DIV
VOUT, 2V/DIV
EN1 = 5V
Figure 22. Power-On Response, EN Tied to IN
TRACK PIN VOLTAGE,
200mV/DIV
Figure 24. Coincident Voltage Tracking Response
T
06784-023
FEEDBACK PIN
VOLTAGE, 200mV/DIV
20ms/DIV
40ms/DIV
Figure 23. Output Voltage Tracking Response
Rev. D | Page 12 of 28
06784-024
06784-022
SOFT START, 1V/DIV
4ms/DIV
VOUT1, 2V/DIV
Data Sheet
ADP1829
THEORY OF OPERATION
The ADP1829 is a dual, synchronous, PWM buck controller
capable of generating output voltages down to 0.6 V and output
currents in the tens of amps. The switching of the regulators is
interleaved for reduced current ripple. It is ideal for a wide
range of applications, such as DSP and processor core I/O
supplies, general-purpose power in telecommunications,
medical imaging, gaming, PCs, set-top boxes, and industrial
controls. The ADP1829 controller operates directly from 3.0 V
to 20 V, and the power stage input voltage range is 1 V to 24 V,
which applies directly to the drain of the high-side external
power MOSFET. It includes fully integrated MOSFET gate
drivers and a linear regulator for internal and gate drive bias.
The ADP1829 operates at a fixed 300 kHz or 600 kHz switching
frequency. The ADP1829 can also be synchronized to an
external clock to switch at up to 1 MHz per channel. The
ADP1829 includes soft start to prevent inrush current during
startup, as well as a unique adjustable lossless current limit.
The ADP1829 offers flexible tracking for startup and shutdown
sequencing. It is specified over the −40°C to +85°C temperature
range and is available in a space-saving, 5 mm × 5 mm,
32-lead LFCSP.
INPUT POWER
The ADP1829 is powered from the IN pin up to 20 V. The
internal low dropout linear regulator, VREG, regulates the IN
voltage down to 5 V. The control circuits, gate drivers, and
external boost capacitors operate from the LDO output. Tie the
PV pin to VREG and bypass VREG with a 1 µF or greater
capacitor.
The ADP1829 phase shifts the switching of the two step-down
converters by 180°, thereby reducing the input ripple current.
This reduces the size and cost of the input capacitors. The input
voltage should be bypassed with a capacitor close to the highside switch MOSFETs (see the Selecting the Input Capacitor
section). In addition, a minimum 0.1 μF ceramic capacitor
should be placed as close as possible to the IN pin.
The VREG output is sensed by the undervoltage lockout
(UVLO) circuit to be certain that enough voltage headroom
is available to run the controllers and gate drivers. As VREG
rises above about 2.7 V, the controllers are enabled. The IN
voltage is not directly monitored by UVLO. If the IN voltage is
insufficient to allow VREG to be above the UVLO threshold,
the controllers are disabled but the LDO continues to operate.
The LDO is enabled whenever either EN1 or EN2 is high, even
if VREG is below the UVLO threshold.
If the desired input voltage is between 3.0 V and 5.5 V, connect
the IN directly to the VREG and PV pins, and drive LDOSD
high to disable the internal regulator. The ADP1829 requires
that the voltage at VREG and PV be limited to no more than
5.5 V. This is the only application where the LDOSD pin is used,
and it should otherwise be grounded or left open. LDOSD has
an internal 100 kΩ pull-down resistor.
While IN is limited to 20 V, the switching stage can run from up
to 24 V and the BST pins can go to 30 V to support the gate drive.
This can provide an advantage, for example, in the case of high
frequency operation from a high input voltage. Dissipation on the
ADP1829 can be limited by running IN from a low voltage rail
while operating the switches from the high voltage rail.
START-UP LOGIC
The ADP1829 features independent enable inputs for each
channel. Drive EN1 or EN2 high to enable their respective
controllers. The LDO starts when either channel is enabled.
When both controllers are disabled, the LDO is disabled and
the IN quiescent current drops to about 10 μA. For automatic
startup, connect EN1 and/or EN2 to IN. The enable pins are
20 V compliant, but they sink current through an internal
100 kΩ resistor once the EN pin voltage exceeds about 5 V.
INTERNAL LINEAR REGULATOR
The internal linear regulator, VREG, is low dropout, meaning it
can regulate its output voltage close to the input voltage. It
powers up the internal control and provides bias for the gate
drivers. It is guaranteed to have more than 100 mA of output
current capability, which is sufficient to handle the gate drive
requirements of typical logic threshold MOSFETs driven at up
to 1 MHz. Bypass VREG with a 1 µF or greater capacitor.
Because the LDO supplies the gate drive current, the output of
VREG is subjected to sharp transient currents as the drivers
switch and the boost capacitors recharge during each switching
cycle. The LDO has been optimized to handle these transients
without overload faults. Due to the gate drive loading, using the
VREG output for other auxiliary system loads is not
recommended.
The LDO includes a current limit well above the expected
maximum gate drive load. This current limit also includes a
short-circuit foldback to further limit the VREG current in the
event of a fault.
OSCILLATOR AND SYNCHRONIZATION
The ADP1829 internal oscillator can be set to either 300 kHz or
600 kHz. Drive the FREQ pin low for 300 kHz; drive it high for
600 kHz. The oscillator generates a start clock for each
switching phase and also generates the internal ramp voltages
for the PWM modulation.
The SYNC input is used to synchronize the converter switching
frequency to an external signal. The SYNC input should be
driven with twice the desired switching frequency because the
SYNC input is divided by 2 and the resulting phases are used to
clock the two channels alternately.
Rev. D | Page 13 of 28
ADP1829
Data Sheet
If FREQ is driven low, the recommended SYNC input
frequency is between 600 kHz and 1.2 MHz. If FREQ is driven
high, the recommended SYNC frequency is between 1.2 MHz
and 2 MHz. The FREQ setting should be carefully observed for
these SYNC frequency ranges, as the PWM voltage ramp scales
down from about 1.3 V based on the percentage of frequency
overdrive. Driving SYNC faster than recommended for the
FREQ setting results in a small ramp signal, which could affect
the signal-to-noise ratio and the modulator gain and stability.
When an external clock is detected at the first SYNC edge, the
internal oscillator is reset and clock control shifts to SYNC. The
SYNC edges then trigger subsequent clocking of the PWM
outputs. The DH rising edges appear about 400 ns after the
corresponding SYNC edge, and the frequency is locked to the
external signal. Depending on the startup conditions of
Channel 1 and Channel 2, either Channel 1 or Channel 2 can be
the first channel synchronized to the rising edge of the SYNC
clock. If the external SYNC signal disappears during operation,
the ADP1829 reverts back to its internal oscillator and
experiences a delay of no more than a single cycle of the
internal oscillator.
ERROR AMPLIFIER
The ADP1829 error amplifiers are operational amplifiers. The
ADP1829 senses the output voltages through external resistor
dividers at the FB1 and FB2 pins. The FB pins are the inverting
inputs to the error amplifiers. The error amplifiers compare
these feedback voltages to the internal 0.6 V reference, and the
outputs of the error amplifiers appear at the COMP1 and
COMP2 pins. The COMP pin voltages then directly control the
duty cycle of each respective switching converter.
A series/parallel RC network is tied between the FB pins and
their respective COMP pins to provide the compensation for
the buck converter control loops. A detailed design procedure
for compensating the system is provided in the Compensating
the Voltage Mode Buck Regulator section.
The error amplifier outputs are clamped between a lower limit
of about 0.7 V and a higher limit of about 2.4 V. When the
COMP pins are low, the switching duty cycle goes to 0%, and
when the COMP pins are high, the switching duty cycle goes to
the maximum.
The SS and TRK pins are auxiliary positive inputs to the error
amplifiers. Whichever has the lowest voltage, SS, TRK, or the
internal 0.6 V reference, controls the FB pin voltage and thus
the output. Therefore, if two or more of these inputs are close to
each other, a small offset is imposed on the error amplifier. For
example, if TRK approaches the 0.6 V reference, the FB sees
about 18 mV of negative offset at room temperature. For this
reason, the soft start pins have a built-in negative offset and
they charge to 0.8 V. If the TRK pins are not used, they should
be tied high to VREG.
SOFT START
The ADP1829 employs a programmable soft start that reduces
input current transients and prevents output overshoot. The SS1
and SS2 pins drive auxiliary positive inputs to their respective
error amplifiers, thus the voltage at these pins regulate the
voltage at their respective feedback control pins.
Program soft start by connecting capacitors from SS1 and SS2
to GND. On startup, the capacitor charges from an internal
90 kΩ resistor to 0.8 V. The regulator output voltage rises with
the voltage at its respective soft start pin, allowing the output
voltage to rise slowly, reducing inrush current. See the information about Soft Start in the Applications Information section.
When a controller is disabled or experiences a current fault, the
soft start capacitor is discharged through an internal 6 kΩ
resistor, so that at restart or recovery from fault, the output
voltage soft starts again.
POWER OK INDICATOR
The ADP1829 features open-drain, Power OK outputs (POK1
and POK2) that sink current when their respective output
voltages drop, typically 8% below the nominal regulation
voltage. The POK pins also go low for overvoltage of typically
25%. Use this output as a logical power-good signal by
connecting pull-up resistors from POK1 and POK2 to VREG.
The POK1 comparator directly monitors FB1, and the threshold
is fixed at 550 mV for undervoltage and 750 mV for overvoltage. However, the POK2 undervoltage and overvoltage
comparator input is connected to UV2 rather than FB2. For the
default thresholds at FB2, connect UV2 directly to FB2.
In a ratiometric tracking configuration, however, Channel 2 can
be configured to be a fraction of a master voltage, and thus FB2
regulated to a voltage lower than the 0.6 V internal reference. In
this configuration, UV2 can be tied to a different tap on the
feedback divider, allowing a POK2 indication at an appropriate
output voltage threshold. See the Setting the Channel 2
Undervoltage Threshold for Ratiometric Tracking section.
TRACKING
The ADP1829 features tracking inputs (TRK1 and TRK2) that
make the output voltages track another, master voltage. This is
especially useful in core and I/O voltage sequencing applications
where one output of the ADP1829 can be set to track and not
exceed the other, or in other multiple output systems where
specific sequencing is required.
The internal error amplifiers include three positive inputs, the
internal 0.6 V reference voltage and their respective SS and TRK
pins. The error amplifiers regulate the FB pins to the lowest of
the three inputs. To track a supply voltage, tie the TRK pin to a
resistor divider from the voltage to be tracked. See the Voltage
Tracking section.
Rev. D | Page 14 of 28
Data Sheet
ADP1829
MOSFET DRIVERS
CURRENT LIMIT
The DH1 and DH2 pins drive the high-side switch MOSFETs.
These are boosted 5 V gate drivers that are powered by
bootstrap capacitor circuits. This configuration allows the highside, N-channel MOSFET gate to be driven above the input
voltage, allowing full enhancement and a low voltage drop
across the MOSFET. The bootstrap capacitors are connected
from the SW pins to their respective BST pins. The bootstrap
Schottky diodes from the PV pins to the BST pins recharge the
bootstrap capacitors every time the SW nodes go low. Use a
bootstrap capacitor value greater than 100× the high-side
MOSFET input capacitance.
The ADP1829 employs a unique, programmable, cycle-by-cycle
lossless current-limit circuit that uses a small, ordinary, inexpensive resistor to set the threshold. Every switching cycle, the
synchronous rectifier turns on for a minimum time and the
voltage drop across the MOSFET RDSON is measured during the
off cycle to determine if the current is too high.
In practice, the switch node can run up to 24 V of input voltage,
and the boost nodes can operate more than 5 V above this to
allow full gate drive. The IN pin can be run from 3.0 V to 18 V.
This can provide an advantage, for example, in the case of high
frequency operation from very high input voltage. Dissipation on
the ADP1829 can be limited by running IN from a lower voltage
rail while operating the switches from the high voltage rail.
The switching cycle is initiated by the internal clock signal. The
high-side MOSFET is turned on by the DH driver, and the SW
node goes high, pulling up on the inductor. When the internally
generated ramp signal crosses the COMP pin voltage, the switch
MOSFET is turned off and the low-side synchronous rectifier
MOSFET is turned on by the DL driver. Active break-beforemake circuitry, as well as a supplemental fixed dead time, are
used to prevent cross-conduction in the switches.
This measurement is done by an internal current-limit
comparator and an external current-limit set resistor. The
resistor is connected between the switch node (that is, the drain
of the rectifier MOSFET) and the CSL pin. The CSL pin, which
is the inverting input of the comparator, forces 50 μA through
the resistor to create an offset voltage drop across it.
When the inductor current is flowing in the MOSFET rectifier,
its drain is forced below PGND by the voltage drop across its
RDSON. If the RDSON voltage drop exceeds the preset drop on the
external resistor, the inverting comparator input is similarly
forced below PGND and an overcurrent fault is flagged.
The normal transient ringing on the switch node is ignored for
100 ns after the synchronous rectifier turns on, so the overcurrent condition must also persist for 100 ns in order for a fault to
be flagged.
The synchronous rectifiers are turned on for a minimum time
of about 200 ns on every switching cycle in order to sense the
current. This and the nonoverlap dead times put a limit on the
maximum high-side switch duty cycle based on the selected
switching frequency. Typically, this is about 90% at 300 kHz
switching; at 1 MHz switching, it reduces to about 70%
maximum duty cycle.
When an overcurrent event occurs, the overcurrent comparator
prevents switching cycles until the rectifier current has decayed
below the threshold. The overcurrent comparator is blanked for
the first 100 ns of the synchronous rectifier cycle to prevent
switch node ringing from falsely tripping the current limit. The
ADP1829 senses the current limit during the off cycle. When
the current-limit condition occurs, the ADP1829 resets the
internal clock until the overcurrent condition disappears. This
suppresses the start clock cycles until the overload condition is
removed. At the same time, the SS cap is discharged through a
6 kΩ resistor. The SS input is an auxiliary positive input of the
error amplifier, so it behaves like another voltage reference. The
lowest reference voltage wins. Discharging the SS voltage causes
the converter to use a lower voltage reference when switching is
allowed again. Therefore, as switching cycles continue around
the current limit, the output looks roughly like a constant
current source due to the rectifier limit, and the output voltage
droops as the load resistance decreases. In the event of a short
circuit, the short circuit output current is the current limit set
by the RCL resistor and is monitored cycle by cycle. When the
overcurrent condition is removed, operation resumes in soft
start mode.
Because the two channels are 180° out of phase, if one is operating around 50% duty cycle, it is common for it to jitter when the
other channel starts switching. The magnitude of the jitter depends
somewhat on layout, but it is difficult to avoid in practice.
In the event of a short circuit, the ADP1829 also offers a
technique for implementing a current-limit foldback with the
use of an additional resistor. See the Setting the Current Limit
section for more information.
The DL1 and DL2 pins provide gate drive for the low-side
MOSFET synchronous rectifiers. Internal circuitry monitors the
external MOSFETs to ensure break-before-make switching to
prevent cross-conduction. An active dead time reduction circuit
reduces the break-before-make time of the switching to limit
the losses due to current flowing through the synchronous
rectifier body diode.
The PV pin provides power to the low-side drivers. It is limited
to 5.5 V maximum input and should have a local decoupling
capacitor.
When the ADP1829 is disabled, the drivers shut off the external
MOSFETs, so that the SW node becomes three-stated or
changes to high impedance.
Rev. D | Page 15 of 28
ADP1829
Data Sheet
APPLICATIONS INFORMATION
SELECTING THE INPUT CAPACITOR
Choose the inductor value using the equation
The input current to a buck converter is a pulse waveform. It is
zero when the high-side switch is off and approximately equal
to the load current when it is on. The input capacitor carries the
input ripple current, allowing the input power source to supply
only the dc current. The input capacitor needs sufficient ripple
current rating to handle the input ripple and also ESR that is
low enough to mitigate input voltage ripple. For the usual current
ranges for these converters, good practice is to use two parallel
capacitors placed close to the drains of the high-side switch
MOSFETs, one bulk capacitor of sufficiently high current rating
as calculated in Equation 1, along with 10 μF of ceramic capacitor.
Select an input bulk capacitor based on its ripple current rating.
If both Channel 1 and Channel 2 maximum output load
currents are about the same, the input ripple current is less than
half of the higher of the output load currents. In this case, use
an input capacitor with a ripple current rating greater than half
of the highest load current.
I RIPPLE >
IL
(1)
2
If the Output 1 and Output 2 load currents are significantly
different (if the smaller is less than 50% of the larger), then the
procedure in Equation 1 yields a larger input capacitor than
required. In this case, the input capacitor can be chosen as in
the case of a single phase converter with only the higher load
current, so first determine the duty cycle of the output with the
larger load current.
D=
VOUT
VIN
(2)
In this case, the input capacitor ripple current is approximately
I RIPPLE ≈ I L D(1 − D)
(3)
where IL is the maximum inductor or load current for the
channel and D is the duty cycle. Use this method to determine
the input capacitor ripple current rating for duty cycles between
20% and 80%.
For duty cycles less than 20% or greater than 80%, use an input
capacitor with ripple current rating IRIPPLE > 0.4 IL.
Selecting the Output LC Filter
The output LC filter attenuates the switching voltage, making
the output an almost dc voltage. The output LC filter characteristics determine the residual output ripple voltage.
Choose an inductor value such that the inductor ripple current
is approximately 1/3 of the maximum dc output load current.
Using a larger value inductor results in a physical size larger
than is required, and using a smaller value results in increased
losses in the inductor and MOSFETs.
L=
VIN − VOUT VOUT
ΔI L f SW VIN
(4)
where:
L is the inductor value.
fSW is the switching frequency.
VOUT is the output voltage.
VIN is the input voltage.
∆IL is the inductor ripple current, typically 1/3 of the maximum
dc load current.
Choose the output bulk capacitor to set the desired output voltage
ripple. The impedance of the output capacitor at the switching
frequency multiplied by the ripple current gives the output
voltage ripple. The impedance is made up of the capacitive
impedance plus the nonideal parasitic characteristics, the
equivalent series resistance (ESR), and the equivalent series
inductance (ESL). The output voltage ripple can be approximated with
1
∆VOUT = ∆I L ESR +
+ 4 f SW ESL
8 f SW COUT
(5)
where:
∆VOUT is the output ripple voltage.
∆IL is the inductor ripple current.
ESR is the equivalent series resistance of the output capacitor
(or the parallel combination of ESR of all output capacitors).
ESL is the equivalent series inductance of the output capacitor
(or the parallel combination of ESL of all capacitors).
Note that the factors of 8 and 4 in Equation 5 would normally
be 2π for sinusoidal waveforms, but the ripple current waveform
in this application is triangular. Parallel combinations of different
types of capacitors, for example, a large aluminum electrolytic
in parallel with MLCCs, may give different results.
Usually, the impedance is dominated by ESR at the switching
frequency, as stated in the maximum ESR rating on the
capacitor data sheet, so this equation reduces to
∆VOUT ≈ ∆I L ESR
(6)
Electrolytic capacitors have significant ESL also, on the order of
5 nH to 20 nH, depending on type, size, and geometry. PCB
traces contribute some ESR and ESL as well. However, using the
maximum ESR rating from the capacitor data sheet usually
provides some margin such that measuring the ESL is not
usually required.
Rev. D | Page 16 of 28
Data Sheet
ADP1829
In the case of output capacitors where the impedance of the
ESR and ESL are small at the switching frequency, for instance,
where the output capacitor is a bank of parallel MLCC capacitors,
the capacitive impedance dominates and the ripple equation
reduces to
∆VOUT ≈
∆I L
8 C OUT f SW
(7)
Make sure that the ripple current rating of the output capacitors
is greater than the maximum inductor ripple current.
During a load step transient on the output, the output capacitor
supplies the load until the control loop has a chance to ramp the
inductor current. This initial output voltage deviation due to a
change in load is dependent on the output capacitor characteristics.
Again, usually the capacitor ESR dominates this response, and
the ΔVOUT in Equation 6 can be used with the load step current
value for ΔIL.
SELECTING THE MOSFETS
The choice of MOSFET directly affects the dc-to-dc converter
performance. The MOSFET must have low on resistance
(RDSON) to reduce I2R losses and low gate-charge to reduce
switching losses. In addition, the MOSFET must have low
thermal resistance to ensure that the power dissipated in the
MOSFET does not result in overheating.
The power switch, or high-side MOSFET, carries the load
current during the PWM on-time, carries the transition loss of
the switching behavior, and requires gate charge drive to switch.
Typically, the smaller the MOSFET RDSON, the higher the gate
charge and vice versa. Therefore, it is important to choose a
high-side MOSFET that balances those two losses. The conduction
loss of the high-side MOSFET is determined by the equation
PC ≈ I L 2 R DSON
VOUT
VIN
(8)
where:
PC is the conduction power loss.
RDSON is the MOSFET on resistance.
The gate charge losses are dissipated by the ADP1829 regulator
and gate drivers and affect the efficiency of the system. The gate
charge loss is approximated by the equation
PG ≈ VIN QG f SW
where:
PG is the gate charge power.
QG is the MOSFET total gate charge.
fSW is the converter switching frequency.
Making the conduction losses balance the gate charge losses
usually yields the most efficient choice.
(9)
Furthermore, the high-side MOSFET transition loss is
approximated by the equation
PT ≈
V IN I L (t R + t F ) f SW
(10)
2
where tR and tF are the rise and fall times of the selected
MOSFET as stated in the MOSFET data sheet.
The total power dissipation of the high-side MOSFET is the
sum of the previous losses.
PD = PC + PG + PT
(11)
where PD is the total high-side MOSFET power loss. This
dissipation heats the high-side MOSFET.
The conduction losses may need an adjustment to account for
the MOSFET RDSON variation with temperature. Note that
MOSFET RDSON increases with increasing temperature. The
MOSFET data sheet should list the thermal resistance of the
package, θJA, along with a normalized curve of the temperature
coefficient of the RDSON. For the power dissipation estimated in
Equation 11, calculate the MOSFET junction temperature rise
over the ambient temperature of interest.
TJ = TA + θ JA PD
(12)
Then calculate the new RDSON from the temperature coefficient
curve and the RDSON specification at 25°C. A typical value of the
temperature coefficient (TC) of the RDSON is 0.004/°C, so an
alternate method to calculate the MOSFET RDSON at a second
temperature, TJ, is
R DSON @ TJ = R DSON @ 25° C [1 + TC(TJ − 25° C )]
(13)
Then the conduction losses can be recalculated and the
procedure iterated once or twice until the junction temperature
calculations are relatively consistent.
The synchronous rectifier, or low-side MOSFET, carries the
inductor current when the high-side MOSFET is off. For high
input voltage and low output voltage, the low-side MOSFET
carries the current most of the time, and therefore, to achieve
high efficiency, it is critical to optimize the low-side MOSFET
for small on resistance. In cases where the power loss exceeds
the MOSFET rating, or lower resistance is required than is
available in a single MOSFET, connect multiple low-side
MOSFETs in parallel. The equation for low-side MOSFET
power loss is
V
PLS ≈ I L 2 R DSON 1 − OUT
VIN
(14)
where:
PLS is the low-side MOSFET on resistance.
RDSON is the parallel combination of the resistances of the lowside MOSFETs.
Check the gate charge losses of the synchronous rectifier(s)
using the PG equation (Equation 9) to be sure they are
reasonable.
Rev. D | Page 17 of 28
ADP1829
Data Sheet
SETTING THE CURRENT LIMIT
VIN
ADP1829
The current-limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
Because the CSL current and the MOSFET RDSON vary over
process and temperature, the minimum current limit should be
set to ensure that the system can handle the maximum desired
load current. To do this, use the peak current in the inductor,
which is the desired current-limit level plus the ripple current,
the maximum RDSON of the MOSFET at its highest expected
temperature, and the minimum CSL current.
RCL =
I LPK R DSON (MAX )
(15)
44 μA
where ILPK is the peak inductor current.
In addition, the ADP1829 offers a technique for implementing
a current-limit foldback in the event of a short circuit with the
use of an additional resistor, as shown in Figure 25. Resistor RLO
is largely responsible for setting the foldback current limit during
a short circuit, and RHI is mainly responsible for setting up the
normal current limit. RLO is lower than RHI. These current-limit
sense resistors can be calculated by
RLO =
R HI =
I PKFOLDBACK RDSON (MAX )
44 μA
VOUT
I LPK
R DSON ( MAX )
R LO
(16)
(17)
− 44 μA
where:
IPKFOLDBACK is the desired short circuit peak inductor current limit.
ILPK is the peak inductor current limit during normal operation
and is also used in Equation 15.
L
VOUT
COUT
M2
DL
RLO
RHI
06784-035
The current limit is set through the current-limit resistor, RCL.
The current sense pins, CSL1 and CSL2, source 50 μA through
their respective RCL. This creates an offset voltage of RCL multiplied
by the 50 μA CSL current. When the drop across the low-side
MOSFET RDSON is equal to or greater than this offset voltage, the
ADP1829 flags a current-limit event.
M1
DH
CSL
Figure 25. Short Circuit Current Foldback Scheme
Because the buck converters are usually running fairly high
current, PCB layout and component placement may affect the
current-limit setting. An iteration of the RCL or RLO and RHI
values may be required for a particular board layout and
MOSFET selection. If alternate MOSFETs are substituted at
some point in production, these resistor values may also need
an iteration.
FEEDBACK VOLTAGE DIVIDER
The output regulation voltage is set through the feedback
voltage divider. The output voltage is reduced through the
voltage divider and drives the FB feedback input. The regulation
threshold at FB is 0.6 V. The maximum input bias current into
FB is 100 nA. For a 0.15% degradation in regulation voltage and
with 100 nA bias current, the low-side resistor, RBOT, needs to be
less than 9 kΩ, which results in 67 µA of divider current. For
RBOT, use 1 kΩ to 10 kΩ. A larger value resistor can be used, but
would result in a reduction in output voltage accuracy due to
the input bias current at the FB pin, while lower values cause
increased quiescent current consumption. Choose RTOP to set
the output voltage by using the following equation:
V
− VFB
RTOP = R BOT OUT
VFB
where:
RTOP is the high-side voltage divider resistance.
RBOT is the low-side voltage divider resistance.
VOUT is the regulated output voltage.
VFB is the feedback regulation threshold, 0.6 V.
Rev. D | Page 18 of 28
(18)
Data Sheet
ADP1829
LC FILTER BODE PLOT
COMPENSATING THE VOLTAGE MODE BUCK
REGULATOR
GAIN
Assuming the LC filter design is complete, the feedback control
system can then be compensated. Good compensation is critical
to proper operation of the regulator. Calculate the quantities in
Equation 19 through Equation 47 to derive the compensation
values. The goal is to guarantee that the voltage gain of the buck
converter crosses unity at a slope that provides adequate phase
margin for stable operation. Additionally, at frequencies above
the crossover frequency, fCO, guaranteeing sufficient gain
margin and attenuation of switching noise are important
secondary goals. For initial practical designs, a good choice for
the crossover frequency is 1/10 of the switching frequency, so
first calculate
f SW
10
fSW
AFILTER
–20dB/dec
PHASE
0°
(19)
1
–90°
ΦFILTER
–180°
Figure 26. LC Filter Bode Plot
(20)
2π LC
Generally speaking, the LC corner frequency is about two
orders of magnitude below the switching frequency, and
therefore, about one order of magnitude below crossover. To
achieve sufficient phase margin at crossover to guarantee
stability, the design must compensate for the two poles at the
LC corner frequency with two zeros to boost the system phase
prior to crossover. The two zeros require an additional pole or
two above the crossover frequency to guarantee adequate gain
margin and attenuation of switching noise at high frequencies.
Depending on component selection, one zero might already be
generated by the equivalent series resistance (ESR) of the output
capacitor. Calculate this zero corner frequency, fESR, as
1
2π R ESRCOUT
To compensate the control loop, the gain of the system must be
brought back up so that it is 0 dB at the desired crossover
frequency. Some gain is provided by the PWM modulation itself.
V
A MOD 20 log IN
V
RAMP
V
AMOD 20 log IN
1.3 V
A FILTER A LC A ESR
20 dB log f CO
f
ESR
(22)
(23)
(24)
Note that if the converter is being synchronized, the ramp
voltage, VRAMP, is lower than 1.3 V by the percentage of
frequency increase over the nominal setting of the FREQ pin.
(21)
The gain of the LC filter at crossover can be linearly approximated from Figure 26 as
For systems using the internal oscillator, this becomes
2 f FREQ
VRAMP 1.3 V
f
SYNC
Figure 26 shows a typical Bode plot of the LC filter by itself.
f
A FILTER 40 dB log ESR
f
LC
fCO
–40dB/dec
The output LC filter is a resonant network that inflicts two poles
upon the response at a frequency fLC, so next calculate
f ESR
fESR
FREQUENCY
This gives sufficient frequency range to design a compensation
that attenuates switching artifacts, while also giving sufficient
control loop bandwidth to provide good transient response.
f LC
fLC
06784-025
f CO
0dB
(25)
The factor of 2 in the numerator takes into account that the
SYNC frequency is divided by 2 to generate the switching
frequency. For example, if the FREQ pin is set high for the
600 kHz range and a 2 MHz SYNC signal is applied, the ramp
voltage is 0.78 V. This increases the gain of the modulator by
4.4 dB in this example.
If fESR ≈ fCO, then add another 3 dB to account for the local
difference between the exact solution and the linear approximation in Equation 22.
Rev. D | Page 19 of 28
ADP1829
Data Sheet
The rest of the system gain is needed to reach 0 dB at crossover.
The total gain of the system, therefore, is given by
GAIN
(26)
where:
AMOD is the gain of the PWM modulator.
AFILTER is the gain of the LC filter including the effects of
the ESR zero.
ACOMP is the gain of the compensated error amplifier.
PHASE
0°
Φ1
–90°
Φ2
Figure 27. LC Filter Bode Plot
The following equations were used for the calculation of the
compensation components as shown in Figure 28 and Figure 29:
f Z2
In Figure 27, the location of the ESR zero corner frequency
gives significantly different net phase at the crossover frequency.
f P1
f Z1
Use the following guidelines for selecting between Type II and
Type III compensators:
f CO
2
, use Type III compensation.
Φ3
–180°
If the zero produced by the ESR of the output capacitor provides
sufficient phase boost at crossover, Type II compensation is
adequate. If the phase boost produced by the ESR of the output
capacitor is not sufficient, another zero is added to the
compensation network, and thus, Type III is used.
If f ESRZ
FREQUENCY
–20dB/dec
The two common compensation schemes used are sometimes
referred to as Type II or Type III compensation, depending on
whether the compensation design includes two or three poles.
(Dominant-pole compensations, or single-pole compensation,
is referred to as Type I compensation, but unfortunately, it is not
very useful for dealing successfully with switching regulators.)
f CO
, use Type II compensation.
2
fSW
–40dB/dec
Additionally, the phase of the system must be brought back up
to guarantee stability. Note from the bode plot of the filter that
the LC contributes −180° of phase shift. Additionally, because
the error amplifier is an integrator at low frequency, it contributes an initial −90°. Therefore, before adding compensation or
accounting for the ESR zero, the system is already down −270°.
To avoid loop inversion at crossover, or −180° phase shift, a
good initial practical design is to require a phase margin of 60°,
which is therefore an overall phase loss of −120° from the initial
low frequency dc phase. The goal of the compensation is to
boost the phase back up from −270° to −120° at crossover.
If f ESRZ
fLC fESR1 fESR2 fESR3 fCO
0dB
06784-026
AT = AMOD + AFILTER + ACOMP
LC FILTER BODE PLOT
PHASE CONTRIBUTION AT CROSSOVER
OF VARIOUS ESR ZERO CORNERS
f P2
1
(27)
2R Z C I
1
2C FF (RTOP R FF )
2R Z
1
C I C HF
(29)
C I C HF
1
2R FF C FF
where:
fZ1 is the zero produced in the Type II compensation.
fZ2 is the zero produced in the Type III compensation.
fP1 is the pole produced in the Type II compensation.
fP2 in the pole produced in the Type III compensation.
Rev. D | Page 20 of 28
(28)
(30)
Data Sheet
ADP1829
Type II Compensator
Next choose the high frequency pole, fP1, to be 1/2 of fSW.
LO
PE
–1
S
fZ
PHASE
LO
PE
2
–270°
CHF
(37)
2R Z C HF
Solving for CHF in Equation 36 and Equation 37 yields
CI
C HF
RTOP
EA
VRAMP
VREF
0V
1
(38)
f SW R Z
Type III Compensator
TO PWM
COMP
06784-027
RBOT
(36)
1
f P1
RZ
f SW
Because CHF
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