ADP1850ACPZ-R7

Wide Range Input, Dual/Two-Phase, DC-to-DC Synchronous Buck Controller ADP1850 Data Sheet FEATURES TYPICAL OPERATION CIRCUIT APPLICATIONS High current single and dual output intermediate bus and point of load converters requiring sequencing and tracking capability, including converters for: Point-of-load power supplies Telecom base station and networking Consumer Industrial and instrumentation Healthcare and medical GENERAL DESCRIPTION The ADP1850 is a configurable dual output or two-phase, single output dc-to-dc synchronous buck controller capable of running from commonly used 3.3 V to 12 V (up to 20 V) voltage inputs. The device operates in current mode for improved transient response and uses valley current sensing for enhanced noise immunity. The architecture enables accurate current sharing between interleaved phases for high current outputs. The ADP1850 is ideal in system applications requiring multiple output voltages: the ADP1850 includes a synchronization feature to eliminate beat frequencies between switching devices; provides accurate tracking capability between supplies and includes precision enable for simple, robust sequencing. Rev. C VIN RRAMP1 RAMP1 VIN ADP1850 EN1 EN2 VDL VCCO TRK1 TRK2 HI LO M1 DH1 BST1 L1 SW1 ILIM1 FB1 R11 VOUT1 M2 DL1 R12 RCSG1 PGOOD1 PGOOD2 SYNC PGND1 FREQ RAMP2 RRAMP2 VIN M3 COMP1 DH2 BST2 L2 SW2 ILIM2 FB2 R21 VOUT2 COMP2 SS1 SS2 AGND M4 DL2 R22 RCSG2 PGND2 09440-001 Wide range input: 2.75 V to 20 V Power stage input voltage: 1 V to 20 V Output voltage range: 0.6 V up to 90% VIN Output current to more than 25 A per channel Accurate current sharing between channels (interleaved) Programmable frequency: 200 kHz to 1.5 MHz 180° phase shift between channels for reduced input capacitance ±0.85% reference voltage accuracy from −40°C to +85°C Integrated boost diodes Power saving mode (PSM) at light loads Accurate power good with internal pull-up resistor Accurate voltage tracking capability Independent channel precision enable Overvoltage and overcurrent limit protection Externally programmable soft start, slope compensation and current sense gain Synchronization input Thermal overload protection Input undervoltage lockout (UVLO) Available in 32-lead 5 mm × 5 mm LFCSP Figure 1. Single Phase Circuit The ADP1850 provides high speed, high peak current drive capability with dead-time optimization to enable energy efficient power conversion. For low load operation, the device can be configured to operate in power saving mode (PSM) by skipping pulses and reducing switching losses to improve the energy efficiency at light load and standby conditions. The accurate current limit (±6%) allows the power architect to design within a narrower range of tolerances and can reduce overall converter size and cost. The ADP1850 provides a configurable architecture capable of wide range input operation to provide the designer with maximum re-use opportunities and improved time to market. Additional flexibility is provided by external programmability of loop compensation, soft start, frequency setting, power saving mode, current limit and current sense gain can all be programmed using external components. The ADP1850 includes a high level of integration in a small size package. The start-up linear regulator and the boot-strap diode for the high side drive are included. Protection features include: undervoltage lock-out, overvoltage, overcurrent/short-circuit and over temperature. The ADP1850 is available in a compact 32-lead LFCSP 5 mm × 5 mm thermally enhanced package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP1850 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Accurate Current-Limit Sensing .............................................. 17 Applications ....................................................................................... 1 Setting the Slope Compensation .............................................. 17 General Description ......................................................................... 1 Setting the Current Sense Gain ................................................ 17 Typical Operation Circuit................................................................ 1 Input Capacitor Selection .......................................................... 18 Revision History ............................................................................... 2 Input Filter................................................................................... 18 Specifications..................................................................................... 3 Boost Capacitor Selection ......................................................... 18 Absolute Maximum Ratings ............................................................ 5 Inductor Selection ...................................................................... 18 ESD Caution .................................................................................. 5 Output Capacitor Selection....................................................... 19 Simplified Block Diagram ............................................................... 6 MOSFET Selection ..................................................................... 19 Pin Configuration and Function Descriptions ............................. 7 Loop Compensation (Single Phase Operation) ..................... 21 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 12 Configuration and Loop Compensation (Dual-Phase Operation) ................................................................................... 22 Control Architecture .................................................................. 12 Switching Noise and Overshoot Reduction ............................ 22 Oscillator Frequency .................................................................. 12 Voltage Tracking ......................................................................... 23 Modes of Operation ................................................................... 13 Indepdendent Power Stage Input Voltage ............................... 24 Synchronization .......................................................................... 13 PCB Layout Guidelines .................................................................. 25 Synchronous Rectifier and Dead Time ................................... 14 MOSFETs, Input Bulk Capacitor, and Bypass Capacitor ...... 25 Input Undervoltage Lockout ..................................................... 14 High Current and Current Sense Paths ................................... 25 Internal Linear Regulator .......................................................... 14 Signal Paths ................................................................................. 25 Overvoltage Protection .............................................................. 14 PGND Plane ................................................................................ 25 Power Good ................................................................................. 14 Feedback and Current-Limit Sense Paths ............................... 25 Short-Circuit and Current-Limit Protection .......................... 15 Switch Node ................................................................................ 26 Shutdown Control ...................................................................... 15 Gate Driver Paths ....................................................................... 26 Thermal Overload Protection................................................... 15 Output Capacitors ...................................................................... 26 Applications Information .............................................................. 16 Typical Operating Circuits ............................................................ 27 Setting the Output Voltage ........................................................ 16 Outline Dimensions ....................................................................... 31 Soft Start ...................................................................................... 16 Ordering Guide .......................................................................... 31 Setting the Current Limit .......................................................... 16 REVISION HISTORY 5/2017—Rev. B to Rev. C Changes to Oscillator Frequency Section.................................... 12 2/2017—Rev. A to Rev. B Changed CP-32-11 to CP-32-12 .................................. Throughout Changes to Oscillator Frequency Section.................................... 12 Updated Outline Dimensions ....................................................... 31 Changes to Ordering Guide .......................................................... 31 4/2012—Rev. 0 to Rev. A Changes to Setting the Current Sense Gain Section .................. 17 Updated Outline Dimensions ....................................................... 31 11/2010—Revision 0: Initial Version Rev. C | Page 2 of 32 Data Sheet ADP1850 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C. Table 1. Parameter POWER SUPPLY Input Voltage Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Quiescent Current Shutdown Current ERROR AMPLIFIER FBx Input Bias Current Transconductance TRK1, TRK2 Input Bias Current CURRENT SENSE AMPLIFIER GAIN OUTPUT CHARACTERICTISTICS Feedback Accuracy Voltage Symbol VIN INUVLO IIN IIN_SD IFB Gm ITRK ACS VFB Line Regulation of PWM Load Regulation of PWM OSCILLATOR Frequency VFB/VIN VFB/VCOMP SYNC Input Frequency Range SYNC Input Pulse Width SYNC Pin Capacitance to GND LINEAR REGULATOR VCCO Output Voltage VCCO Load Regulation VCCO Line Regulation VCCO Current Limit 1 VCCO Short-Circuit Current1 VIN to VCCO Dropout Voltage2 LOGIC INPUTS EN1, EN2 EN1, EN2 Hysteresis EN1, EN2 Input Leakage Current SYNC Logic Input Low SYNC Logic Input High SYNC Input Pull-Down Resistance fSYNC tSYNCMIN CSYNC fSW VDROPOUT IEN Conditions Min VIN rising VIN falling 2.75 2.45 2.4 TJ = −40°C to +85°C, VFB = 0.6 V TJ = −40°C to +125°C, VFB = 0.6 V Unit 20 2.75 2.6 V V V mA 2.8 100 200 mA µA −100 385 −100 2.4 +1 550 +1 3 +100 715 +100 3.6 nA µS nA V/V 5.2 6 6.9 V/V 10.5 20.5 12 24 13.5 26.5 V/V V/V −0.85% −1.5% +0.6 +0.6 ±0.015 ±0.3 +0.85% +1.5% V V %/V % 170 720 1275 235 475 400 100 200 800 1500 300 600 235 880 1725 345 690 3000 kHz kHz kHz kHz kHz kHz ns pF 5.0 35 10 350 370 0.33 5.3 V mV mV mA mA V 0.63 0.03 1 0.68 VCOMP range = 0.9 V to 2.2 V RFREQ = 340 kΩ to AGND RFREQ = 78.7 kΩ to AGND RFREQ = 39.2 kΩ to AGND FREQ to AGND FREQ to VCCO fSYNC = 2 × fSW 2.6 2.5 0.1 4.5 Max 5.8 EN1 = EN2 = VIN = 12 V, VFB = VCCO in PWM mode (no switching) EN1 = EN2 = VIN = 12 V, VFB = VCCO in PSM mode EN1 = EN2 = GND, VIN = 5.5 V or 20 V Sink or source 1 µA 0 V ≤ VTRK1/VTRK2 ≤ 5 V Gain resistor connected to DLx, RCSG = 47 kΩ ± 5% Gain resistor connected to DLx, RCSG = 22 kΩ ± 5% Default setting, RCSG = open Gain resistor connected to DLx, RCSG = 100 kΩ ± 5% Typ 5 IVCCO = 100 mA IVCCO = 0 mA to 100 mA, VIN = 5.5 V to 20 V, IVCCO = 20 mA VCCO drops to 4 V from 5 V VCCO < 0.5 V IVCCO = 100 mA, VIN ≤ 5 V 4.7 EN1/EN2 rising 0.57 VIN = 2.75 V to 20 V 1.9 RSYNC 1 Rev. C | Page 3 of 32 400 200 1.3 V V nA V V MΩ ADP1850 Parameter GATE DRIVERS DHx Rise Time DHx Fall Time DLx Rise Time DLx Fall Time DHx to DLx Dead Time DHx or DLx Driver RON, Sourcing Current1 DHx or DLx Driver RON, Tempco DHx or DLx Driver RON, Sinking Current1 DHx Maximum Duty Cycle DHx Maximum Duty Cycle Minimum DHx On Time Minimum DHx Off Time Minimum DLx On Time COMPx VOLTAGE RANGE COMPx Pulse Skip Threshold COMPx Clamp High Voltage THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis OVERVOLTAGE AND POWER GOOD THRESHOLDS FBx Overvoltage Threshold FBx Overvoltage Hysteresis FBx Undervoltage Threshold FBx Undervoltage Hysteresis TRKx INPUT VOLTAGE RANGE FBx TO TRKx OFFSET VOLTAGE SOFT START SSx Output Current SSx Pull-Down Resistor FBx to SSx Offset PGOODx PGOODx Pull-up Resistor PGOODx Delay Over Voltage or Under Voltage Data Sheet Symbol Conditions RON_SOURCE CDH = 3 nF, VBST − VSW = 5 V CDH = 3 nF, VBST − VSW = 5 V CDL = 3 nF CDL = 3 nF External 3 nF is connected to DHx and DLx Sourcing 2 A with a 100 ns pulse 16 14 16 14 25 2 ns ns ns ns ns Ω TCRON RON_SINK Sourcing 1 A with a 100 ns pulse, VIN = 3 V VIN = 3 V or 12 V Sinking 2 A with a 100 ns pulse 2.3 0.3 1.5 Ω %/oC Ω 2 Ω % % ns ns ns Sinking 1 A with a 100 ns pulse, VIN = 3 V fSW = 300 kHz fSW = 1500 kHz fSW = 200 kHz to 1500 kHz fSW = 200 kHz to 1500 kHz fSW = 200 kHz to 1500 kHz VCOMP,THRES VCOMP,HIGH VUV VFB falling 0.525 TRKx = 0.1 V to 0.57 V, offset = VFB − VTRK 0 −10 During start-up During a fault condition VSS = 0.1 V to 0.6 V, offset = VFB − VSS 4.6 V V 155 20 °C °C Relative to PGNDx ILIMx = PGNDx After DLx goes high, current limit is not sensed during this period At 20 mA forward current −5 47 In pulse skip mode only, fSW = 600 kHz 0 Rev. C | Page 4 of 32 0 6.5 3 0.665 0.578 5 +10 8.4 +10 12.5 12 10 This is the minimum duration required to trip the PGOOD signal Guaranteed by design. Connect VIN to VCCO when 2.75 V < VIN < 5.5 V. 0.65 30 0.55 30 −10 Internal pull-up resistor to VCCO Unit 0.9 2.25 0.635 INTEGRATED RECTIFIER (BOOST DIODE) RESISTANCE ZERO CURRENT CROSS OFFSET (SWx TO PGNDx)1 2 In pulse skip mode VFB rising RPGOOD Max 135 335 285 VOV ISS Typ 90 50 TTMSD Minimum Duration ILIM1, ILIM2 Threshold Voltage1 ILIM1, ILIM2 Output Current Current Sense Blanking Period 1 Min 0 50 100 µA kΩ mV kΩ µs µs +5 53 16 2 V mV V mV V mV mV µA ns Ω 4 mV Data Sheet ADP1850 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VIN, EN1/EN2, RAMP1/RAMP2 FB1/FB2, COMP1/COMP2, SS1/SS2, TRK1/TRK2, FREQ, SYNC, VCCO, VDL, PGOOD1/PGOOD2 ILIM1/ILIM2, SW1/SW2 to PGND1/PGND2 BST1/BST2, DH1/DH2 to PGND1/PGND2 DL1/DL2 to PGND1/PGND2 BST1/BST2 to SW1/SW2 BST1/BST2 to PGND1/PGND2 20 ns Transients SW1/SW2 to PGND1/PGND2 20 ns Transients DL1/DL2, SW1/SW2, ILIM1/ILIM2 to PGND1/PGND2 20 ns Negative Transients PGND1/PGND2 to AGND PGND1/PGND2 to AGND 20 ns Transients θJA on Multilayer PCB (Natural Convection)1, 2 Operating Junction Temperature Range3 Storage Temperature Range Maximum Soldering Lead Temperature Rating 21 V −0.3 V to +6 V −0.3 V to +21 V −0.3 V to +28 V −0.3V to VCCO + 0.3 V −0.3 V to +6 V 32 V 25 V −8 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND. ESD CAUTION −0.3 V to +0.3 V −8 V to +4 V 32.6°C/W −40°C to +125°C −65°C to +150°C 260°C 1 Measured with exposed pad attached to PCB. Junction-to-ambient thermal resistance (θJA) of the package was calculated or simulated on multilayer PCB. 3 The junction temperature, TJ, of the device is dependent on the ambient temperature, TA, the power dissipation of the device, PD, and the junction-toambient thermal resistance of the package, θJA. Maximum junction temperature is calculated from the ambient temperature and power dissipation using the formula: TJ = TA + PD × θJA. 2 Rev. C | Page 5 of 32 ADP1850 Data Sheet SIMPLIFIED BLOCK DIAGRAM VCCO VIN THERMAL SHUTDOWN OV 0.6V UV REF LDO AGND UVLO 0.6V EN1_SW EN2_SW LOGIC + – EN1 + EN2 VCCO – OV1 LOGIC SYNC UV1 PH1 1MΩ PGOOD1 FREQ + – OV FB1 0.6V COMP1 FB1 TRK1 SS1 ERROR AMPLIFIER – + + Gm + + – UV VDL BST1 SYNC EN1_SW VREF = 0.6V 6.5µA 5V 0.9V FAULT 1kΩ LOGIC DH1 DRIVER LOGIC CONTROL AND STATE MACHINE OVER_LIM1 – OV1 SW1 PULSE SKIP + OV1 – EN1 OVER_LIM1 DCM + PWM COMPARATOR ZERO CROSS DETECT VDL + – DL1 CS GAIN SLOPE COMP AND RAMP GENERATOR PGND1 VCCO – AV = 3, 6, 12, 24 + CURRENT SENSE AMPLIFIER 50µA + CURRENT LIMIT OVER_LIM1 CONTROL – ILIM1 09440-003 RAMP1 12kΩ DUPLICATE FOR CHANNEL 2 PH2 OSCILLATOR Figure 2. Rev. C | Page 6 of 32 Data Sheet ADP1850 32 31 30 29 28 27 26 25 TRK1 FB1 COMP1 RAMP1 SS1 PGOOD1 ILIM1 BST1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADP1850 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 SW1 DH1 PGND1 DL1 DL2 PGND2 DH2 SW2 NOTES 1. CONNECT THE BOTTOM EXPOSED PAD OF THE LFCSP PACKAGE TO SYSTEM AGND PLANE. 09440-004 TRK2 FB2 COMP2 RAMP2 SS2 PGOOD2 ILIM2 BST2 9 10 11 12 13 14 15 16 EN1 SYNC VIN VCCO VDL AGND FREQ EN2 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic EN1 2 SYNC 3 VIN 4 VCCO 5 VDL 6 7 AGND FREQ 8 EN2 9 10 11 TRK2 FB2 COMP2 12 RAMP2 13 SS2 14 PGOOD2 Description Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive EN1 low to turn off the Channel 1 controller. Tie EN1 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND and tie the midpoint to this pin. Frequency Synchronization Input. Accepts an external signal between 1× and 2.3× of the internal oscillator frequency, fSW, set by the FREQ pin. The controller operates in forced PWM when a signal is detected at SYNC or when SYNC is high. The resulting switching frequency is ½ of the SYNC frequency. When SYNC is low or left floating, the controller operates in pulse skip mode. For dual-phase operation, connect SYNC to a logic high or an external clock. Connect to Main Power Supply. Bypass with a 1 µF or larger ceramic capacitor connected as close to this pin as possible and PGNDx. Output of the Internal Low Dropout Regulator (LDO). Bypass VCCO to AGND with a 1 μF or larger ceramic capacitor. The VCCO output remains active even when EN1 and EN2 are low. For operation with VIN below 5 V, VIN may be shorted to VCCO. Do not use the LDO to power other auxiliary system loads. Power Supply for the Low-Side Driver. Bypass VDL to PGNDx with a 1 µF or greater ceramic capacitor. Connect VCCO to VDL. Analog Ground. Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND. Connect FREQ to AGND for a preprogrammed 300 kHz or FREQ to VCCO for 600 kHz operating frequency. Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive EN2 low to turn off the Channel 2 controller. Tie EN2 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND, and tie the midpoint to this pin. Tracking Input for Channel 2. Connect TRK2 to VCCO if tracking is not used. Output Voltage Feedback for Channel 2. Connect to Output 2 via a resistor divider. Compensation Node for Channel 2. Output of Channel 2 error amplifier. Connect a series resistor-capacitor network from COMP2 to AGND to compensate the regulation control loop. Connect a resistor from RAMP2 to VIN to set up a ramp current for slope compensation in Channel 2. The voltage at RAMP2 is 0.2 V. This pin is high impedance when the channel is disabled. Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. The node is internally pulled up to 5 V with a 6.5 µA current source. Power Good. Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between PGOOD2 and VCCO. PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window. An external pull-up resistor is not required. Rev. C | Page 7 of 32 ADP1850 Pin No. 15 Mnemonic ILIM2 16 BST2 17 SW2 18 DH2 19 PGND2 20 DL2 21 DL1 22 PGND1 23 DH1 24 SW1 25 BST1 26 ILIM1 27 PGOOD1 28 SS1 29 RAMP1 30 COMP1 31 32 33 (EPAD) FB1 TRK1 Exposed Pad (EPAD) Data Sheet Description Current Limit Sense Comparator Inverting Input for Channel 2. Connect a resistor between ILIM2 and SW2 to set the current limit offset. For accurate current limit sensing, connect ILIM2 to a current sense resistor at the source of the low-side MOSFET. Boot-Strapped Upper Rail of High Side Internal Driver for Channel 2. Connect a multilayer ceramic capacitor (0.1 µF to 0.22 µF) between BST2 and SW2. There is an internal boost rectifier connected between VDL and BST2. Switch Node for Channel 2. Connect to source of the high-side N-channel MOSFET and the drain of the low-side N-channel MOSFET of Channel 2. High-Side Switch Gate Driver Output for Channel 2. Capable of driving MOSFETs with total input capacitance up to 20 nF. Power Ground for Channel 2. Ground for internal Channel 2 driver. Differential current is sensed between SW2 and PGND2. Use the Kelvin sensing connection technique between PGND2 and source of the low-side MOSFET. Low-Side Synchronous Rectifier Gate Driver Output for Channel 2. To set the gain of the current sense amplifier, connect a resistor between DL2 and PGND2. Capable of driving MOSFETs with a total input capacitance up to 20 nF. Low-Side Synchronous Rectifier Gate Driver Output for Channel 1. To set the gain of the current sense amplifier, connect a resistor between DL1 and PGND1. Capable of driving MOSFETs with a total input capacitance up to 20 nF. Power Ground for Channel 1. Ground for internal Channel 1 driver. Differential current is sensed between SW1 and PGND1. Use the Kelvin sensing connection technique between PGND1 and source of the low-side MOSFET. High-Side Switch Gate Driver Output for Channel 1. Capable of driving MOSFETs with a total input capacitance up to 20 nF. Power Switch Node for Channel 1. Connect to source of the high-side N-channel MOSFET and the drain of the low-side N-channel MOSFET of Channel 1. Boot-Strapped Upper Rail of High Side Internal Driver for Channel 1. Connect a multilayer ceramic capacitor (0.1 µF to 0.22 µF) between BST1 and SW1. There is an internal boost diode or rectifier connected between VDL and BST1. Current Limit Sense Comparator Inverting Input for Channel 1. Connect a resistor between ILIM1 and SW1 to set the current limit offset. For accurate current limit sensing, connect ILIM1 to a current sense resistor at the source of the low-side MOSFET. Power Good. Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between PGOOD1 and VCCO. PGOOD1 is pulled to ground when the Channel 1 output is outside the regulation window. An external pull-up resistor is not required. Soft Start Input for Channel 1. Connect a capacitor from SS1 to AGND to set the soft start period. This node is internally pulled up to 5 V with a 6.5 µA current source. Connect a resistor from RAMP1 to VIN to set up a ramp current for slope compensation in Channel 1. The voltage at RAMP2 is 0.2 V. This pin is high impedance when the channel is disabled. Compensation Node for Channel 1. Output of Channel 1 error amplifier. Connect a series resistor-capacitor network from COMP1 to AGND to compensate the regulation control loop. Output Voltage Feedback for Channel 1. Connect to Output 1 via a resistor divider. Tracking Input for Channel 1. Connect TRK1 to VCCO if tracking is not used. Connect the bottom exposed pad of the LFCSP package to the system AGND plane. Rev. C | Page 8 of 32 Data Sheet ADP1850 TYPICAL PERFORMANCE CHARACTERISTICS 100 5.10 90 5.05 VO = 3.3V, PSM 80 100mA LOAD ON LDO 70 4.95 60 VCCO (V) VO = 3.3V, PWM 50 VO = 1.8V, PSM 40 4.90 4.85 4.80 30 VO = 1.8V, PWM 4.75 20 4.70 10 VIN = 12V, 600kHz 0.1 1 10 100 LOAD (A) 4.65 09440-005 0 0.01 5 7 9 11 13 15 17 5 6 VIN (V) Figure 4. Efficiency Plot of Figure 44 09440-008 EFFICIENCY (%) NO LOAD ON LDO 5.00 Figure 7. LDO Line Regulation 100 6 90 5 80 VO = 5V, PSM 4 60 VO = 1.8V, PSM 50 40 VCCO (V) EFFICIENCY (%) 70 3 VO = 5V, PWM 2 30 20 1 VO = 1.8V, PWM VIN = 12V, 750kHz 0.1 1 10 LOAD (A) 0 09440-006 0 0.01 0 1 2 3 4 VIN (V) Figure 8. VCCO vs. VIN Figure 5. Efficiency Plot of Figure 45 0 SW1 1 –0.10 SW2 2 50mA LOAD 3 100mA LOAD SYNC 600kHz –0.20 –0.25 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 CH1 10V CH3 5V CH2 10V M1µs A CH1 5.60V Figure 9. An Example of Synchronization, fSYNC = 600 kHz Figure 6. LDO Load Regulation Rev. C | Page 9 of 32 09440-010 –0.15 09440-007 ΔVCCO (V) –0.05 09440-009 10 ADP1850 Data Sheet SW1 OUTPUT RESPONSE 1 1 PGOOD1 VCCO (CH3) 8A TO 13A STEP LOAD 2 VOUT, PRELOADED (CH4) 3 VIN = 12V VOUT = 3.3V B M200µs W A CH4 11.5A CH4 5A Ω 4 CH1 10V CH2 2V CH4 2V Ω CH3 2V M10ms A CH2 09440-014 CH1 20mV 09440-011 4 3.76V Figure 13. Thermal Shutdown Waveform Figure 10. Step Load Transient of Figure 44 0.5 REFERENCED AT VIN = 2.75V 0 DH1 CHANGE IN fSW (%) 1 DL1 2 VOUT1 3 IL1 –0.5 600kHz –1.0 300kHz –1.5 4 VIN = 12V VOUT = 1.8V OUTPUT PRECHARGED TO 1V M1ms A CH1 2.4V 3 5 7 9 11 13 15 17 21 09440-015 CH2 5V CH4 1A Ω –2.5 135 09440-016 CH3 1V 850kHz 09440-012 CH1 5V –2.0 19 VIN (V) Figure 14. Change in fSW vs. VIN Figure 11. Soft Start into Precharged Output 2.0 VIN = 12V; REFERENCED AT 25°C 1.5 1.0 1 CHANGE IN fSW (%) SW VOUT (CH3) EN M10ms A CH2 1.52V –1.0 –2.5 –40 09440-013 CH3 1V CH2 2V CH4 1V –0.5 –2.0 CSS = 100nF CH1 10V 0 –1.5 SS (CH4) 3 2 4 0.5 –15 10 35 60 85 TEMPERATURE (°C) Figure 15. fSW vs. Temperature Figure 12. Enable Start-Up Function Rev. C | Page 10 of 32 110 Data Sheet ADP1850 45 350 TA = 25°C OUTPUT IS LOADED HS FET = BSC080N03LS LS FET = BSC030N03LS 43 300 41 DH MINIMUM OFF TIME 39 DEAD TIME (ns) 200 150 37 35 33 31 DH MINIMUM ON TIME 29 100 27 DEAD TIME BETWEEN SW FALLING EDGE AND DL RISING EDGE, INCLUDING DIODE RECOVERY TIME 5.0 7.5 10.0 12.5 15.0 17.5 20.0 VIN (V) 09440-017 25 50 2.5 0 5 10 15 20 VIN (V) Figure 16. Typical DH Minimum On Time and Off Time 09440-020 TIME (ns) 250 Figure 19. Dead Time vs. VIN 4 600 DH MINIMUM OFF TIME 560 2 540 1 520 Gm (µS) DH MINIMUM ON TIME 0 500 480 –1 460 –2 440 –3 –15 10 35 60 85 110 135 TEMPERATURE (°C) 400 –40 35 60 85 110 135 Figure 20. Gm of Error Amplifier vs. Temperature 35 4.5 VIN = 12V 34 OUTPUT IS LOADED HS FET = BSC080N03LS 33 LS FET = BSC030N03LS 4.0 DRIVER RESISTANCE (Ω) 3.5 32 31 30 29 28 VIN = 2.75V, SOURCING 3.0 VIN = 12V, SOURCING 2.5 VIN = 2.75V, SINKING 2.0 1.5 VIN = 12V, SINKING 1.0 27 25 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 140 Figure 18. Dead Time vs. Temperature 0 –40 –15 10 35 60 85 110 TEMPERATURE (°C) Figure 21. Driver Resistance vs. Temperature Rev. C | Page 11 of 32 135 09440-022 0.5 DEAD TIME BETWEEN SW FALLING EDGE AND DL RISING EDGE, INCLUDING DIODE RECOVERY TIME 09440-019 DEAD TIME (ns) 10 TEMPERATURE (°C) Figure 17. DH Minimum On Time and Off Time Over Temperature 26 –15 09440-021 420 –4 –40 09440-018 CHANGE IN MINIMUM ON/OFF TIME (%) VIN = 2.75V TO 20V 580 3 ADP1850 Data Sheet THEORY OF OPERATION The ADP1850 is a current mode, dual-channel, step-down switching controller with integrated MOSFET drivers for external N-channel synchronous power MOSFETs. The two outputs are phase shifted 180°. This reduces the input RMS ripple current, thus minimizing required input capacitance. In addition, the two outputs can be combined for dual-phase PWM operation that can deliver more than 50 A output current and the two channels are optimized for current sharing. The ADP1850 can be set to operate in pulse skip high efficiency mode (power saving mode) under light load or in forced PWM. The integrated boost diodes in the ADP1850 reduce the overall system cost and component count. The ADP1850 includes programmable soft start, output overvoltage protection, programmable current limit, power good, and tracking function. The ADP1850 can be set to operate in any switching frequency between 200 kHz and 1.5 MHz with one external resistor. CONTROL ARCHITECTURE The ADP1850 is based on a fixed frequency, current mode, PWM control architecture. The inductor current is sensed by the voltage drop measured across the external low-side MOSFET, RDSON, during the off period of the switching cycle (valley inductor current). The current sense signal is further processed by the current sense amplifier. The output of the current sense amplifier is held, and the emulated current ramp is multiplexed and fed into the PWM comparator as shown in Figure 22. The valley current information is captured at the end of the off period, and the emulated current ramp is applied at that point when the next on cycle begins. An error amplifier integrates the error between the feedback voltage and the generated error voltage from the COMPx pin (from error amplifier in Figure 22). current signal is sampled at the end of the turn-off period, which gives time for the switch node ringing to settle. Other benefits of using current mode control scheme still apply, such as simplicity of loop compensation. Control logic enforces antishoot-through operation to limit cross conduction of the internal drivers and external MOSFETs. OSCILLATOR FREQUENCY The internal oscillator frequency, which ranges from 200 kHz to 1.5 MHz, is set by an external resistor, RFREQ, at the FREQ pin. Some popular fSW values are shown in Table 4, and a graphical relationship is shown in Figure 23. For instance, a 78.7 kΩ resistor sets the oscillator frequency to 800 kHz. Furthermore, connecting FREQ to AGND or FREQ to VCCO sets the oscillator frequency to 300 kHz or 600 kHz, respectively. For other frequencies that are not listed in Table 4, the values of RFREQ and fSW can be obtained from Figure 23, or use the following empirical formula to calculate these values: RFREQ (kΩ) = 96,568 × fSW (kHz)−1.065 Table 4. Setting the Oscillator Frequency RFREQ 332 kΩ 78.7 kΩ 60.4 kΩ 51 kΩ 40.2 kΩ FREQ to AGND FREQ to VCCO fSW (Typical) 200 kHz 800 kHz 1000 kHz 1200 kHz 1500 kHz 300 kHz 600 kHz 410 RFREQ (kΩ) = 96,568 fSW (kHz)–1.065 360 OSC VIN S Q TO DRIVERS 310 FF RRAMP R Q RFREQ (kΩ) IRAMP AR CR 260 210 160 110 FROM ERROR AMP ACS FROM LOW-SIDE MOSFET 60 09440-023 VCS Figure 22. Simplified Control Architecture 10 100 400 700 1000 1300 fSW (kHz) As shown in Figure 22, the emulated current ramp is generated inside the IC but offers programmability through the RAMPx pin. Selecting an appropriate value resistor from VIN to the RAMPx pin programs a desired slope compensation value and, at the same time, provides a feed forward feature. The benefits realized by deploying this type of control scheme are that there is no need to worry about the turn-on current spike corrupting the current ramp. Also, the current signal is stable because the Rev. C | Page 12 of 32 Figure 23. RFREQ vs. fSW 1600 1900 09440-024 VIN Data Sheet ADP1850 MODES OF OPERATION The SYNC pin is a multifunctional pin. PWM mode is enabled when SYNC is connected to VCCO or a high logic. With SYNC connected to ground or left floating, the pulse skip mode is enabled. Switching SYNC from low to high or high to low on the fly causes the controller to transition from forced PWM to pulse skip mode or pulse skip mode to forced PWM, respectively, in two clock cycles. DH1 1 DL1 2 Table 5. Mode of Operation Truth Table Mode of Operation Pulse skip mode Forced PWM or two-phase operation Pulse skip mode Forced PWM or two-phase operation The ADP1850 has a pulse skip sensing circuitry that allows the controller to skip PWM pulses, thus, reducing the switching frequency at light loads and, therefore, maintaining high efficiency during a light load operation. The switching frequency is a fraction of the natural oscillator frequency and is automatically adjusted to regulate the output voltage. The resulting output ripple is larger than that of the fixed frequency forced PWM. Figure 24 shows that the ADP1850 operates in PSM under a very light load. Pulse skip frequency under light load is dependent on the inductor, output capacitance, output load, and input and output voltages. COMP1 (CH2) VOUT RIPPLE INDUCTOR CURRENT CH1 10V CH3 20mV CH2 200mV CH4 2A Ω M200µs A CH1 7.8V 09440-025 4 2 INDUCTOR CURRENT CH1 10V CH3 20mV CH2 5V CH4 2A Ω M1µs A CH1 13.4V Figure 25. Example of Discontinuous Conduction Mode (DCM) Waveform In forced PWM, the ADP1850 always operates in CCM at any load. The inductor current is always continuous, thus, efficiency is poor at light loads. SYNCHRONIZATION The switching frequency of the ADP1850 can be synchronized to an external clock by connecting SYNC to a clock signal. The external clock should be between 1× and 2.3× of the internal oscillator frequency, fSW. The resulting switching frequency is ½ of the external SYNC frequency because the SYNC input is divided by 2, and the resulting phases are used to clock the two channels alternately. In synchronization, the ADP1850 operates in PWM. When an external clock is detected at the first SYNC edge, the internal oscillator is reset, and the clock control shifts to SYNC. The SYNC edges then trigger subsequent clocking of the PWM outputs. The DH1/DH2 rising edges appear approximately 100 ns after the corresponding SYNC edge, and the frequency is locked to the external signal. Depending on the start-up conditions of Channel 1 and Channel 2, either Channel 1 or Channel 2 can be the first channel synchronized to the rising edge of the SYNC clock. If the external SYNC signal disappears during operation, the ADP1850 reverts to its internal oscillator. When the SYNC function is used, it is recommended to connect a pull-up resistor from SYNC to VCCO so that when the SYNC signal is lost, the ADP1850 continues to operate in PWM. SW1 1 3 4 09440-026 SYNC Pin Low High No Connect Clock Signal OUTPUT RIPPLE 3 Figure 24. Example of Pulse Skip Mode Under Light Load When the output load is greater than the pulse skip threshold current, that is, VCOMP reaches the threshold of 0.9 V, the ADP1850 exits the pulse skip mode of operation and enters the fixed frequency discontinuous conduction mode (DCM), as shown in Figure 25. When the load increases further, the ADP1850 enters CCM. Rev. C | Page 13 of 32 ADP1850 Data Sheet SYNCHRONOUS RECTIFIER AND DEAD TIME VIN = 2.75V TO 5.5V When the bias input voltage, VIN, is less than the undervoltage lockout (UVLO) threshold, the switch drivers stay inactive. When VIN exceeds the UVLO threshold, the switchers start switching. INTERNAL LINEAR REGULATOR The internal linear regulator is low dropout (LDO) meaning it can regulate its output voltage, VCCO. VCCO powers up the internal control circuitry and provides power for the gate drivers. It is guaranteed to have more than 200 mA of output current capability, which is sufficient to handle the gate drive requirements of typical logic threshold MOSFETs driven at up to 1.5 MHz. VCCO is always active and cannot be shut down by the EN1 and EN2 pins. Bypass VCCO to AGND with a 1 µF or greater capacitor. Because the LDO supplies the gate drive current, the output of VCCO is subject to sharp transient currents as the drivers switch and the boost capacitors recharge during each switching cycle. The LDO has been optimized to handle these transients without overload faults. Due to the gate drive loading, using the VCCO output for other external auxiliary system loads is not recommended. The LDO includes a current limit well above the expected maximum gate drive load. This current limit also includes a short-circuit fold back to further limit the VCCO current in the event of a short-circuit fault. The VDL pin provides power to the low-side driver. Connect VDL to VCCO. Bypass VDL to PGNDx with a 1 µF (minimum) ceramic capacitor, which must be placed close to the VDL pin. For an input voltage less than 5.5 V, it is recommended to bypass the LDO by connecting VIN to VCCO, as shown in Figure 26, thus eliminating the dropout voltage. However, if the input range is 4 V to 7 V, the LDO cannot be bypassed by shorting VIN to VCCO because the 7 V input has exceeded the maximum voltage rating of the VCCO pin. In this case, use the LDO to drive the internal drivers, but keep in mind that there is a dropout when VIN is less than 5 V. VCCO ADP1850 Figure 26. Configuration for VIN < 5.5 V OVERVOLTAGE PROTECTION The ADP1850 has a built-in circuit for detecting output overvoltage at the FB node. When the FB voltage, VFB, rises above the overvoltage threshold, the low-side N-channel MOSFET (NMOSFET) is immediately turned on, and the high-side NMOSFET is turned off until the VFB drops below the undervoltage threshold. This action is known as the crowbar overvoltage protection. If the overvoltage condition is not removed, the controller maintains the feedback voltage between the overvoltage and undervoltage thresholds, and the output is regulated to within typically +8% and −8% of the regulation voltage. During an overvoltage event, the SS node discharges toward zero through an internal 3 kΩ pull-down resistor. When the voltage at FBx drops below the undervoltage threshold, the soft start sequence restarts. Figure 27 shows the overvoltage protection scheme in action in PSM. DH1 1 PGOOD1 2 VO1 = 1.8V SHORTED TO 2V SOURCE 3 VIN 4 CH1 20.0V CH3 1.00V CH2 5.00V CH4 10.0V M100µs A CH1 10.0V 09440-028 INPUT UNDERVOLTAGE LOCKOUT VIN 09440-027 The synchronous rectifier (low-side MOSFET) improves efficiency by replacing the Schottky diode that is normally used in an asynchronous buck regulator. In the ADP1850, the antishootthrough circuit monitors the SW and DL nodes and adjusts the low-side and high-side drivers to ensure break-before-make switching which prevents cross-conduction or shoot-through between the high-side and low-side MOSFETs. This breakbefore-make switching is known as dead time, which is not fixed and depends on how fast the MOSFETs are turned on and off. In a typical application circuit that uses medium sized MOSFETs with input capacitance of approximately 3 nF, the typical dead time is approximately 30 ns. When small and fast MOSFETs with fast diode recovery time are used, the dead time can be as low as 13 ns. Figure 27. Overvoltage Protection in PSM POWER GOOD The PGOODx pin is an open-drain NMOSFET with an internal 12 kΩ pull-up resistor connected between PGOODx and VCCO. PGOODx is internally pulled up to VCCO during normal operation and is active low when tripped. When the feedback voltage, VFB, rises above the overvoltage threshold or drops below the undervoltage threshold, the PGOODx output is pulled to ground after a delay of 12 µs. The overvoltage or undervoltage condition must exist for more than 10 µs for PGOODx to become active. The PGOODx output also becomes active if a thermal overload condition is detected. Rev. C | Page 14 of 32 Data Sheet ADP1850 SHUTDOWN CONTROL When the output is shorted or the output current exceeds the current limit set by the current limit setting resistor (between ILIMx and SWx) for eight consecutive cycles, the ADP1850 shuts off both the high-side and low-side drivers and restarts the soft start sequence every 10 ms, which is known as hiccup mode. The SS node discharges to zero through an internal 1 kΩ resistor during an overcurrent or short-circuit event. Figure 28 shows that the ADP1850 on a high current application circuit is entering current limit hiccup mode when the output is shorted. SW1 1 The EN1 and EN2 pins are used to enable or disable Channel 1 and Channel 2 of the ADP1850. The precision enable (minimum) threshold for EN1/EN2 is 0.57 V. When the voltage at EN1/EN2 rises above the threshold voltage, the ADP1850 is enabled and starts normal operation after the soft start period. And when the voltage at EN1/EN2 drops typically 30 mV (hysteresis) below the threshold voltage, the switchers and the internal circuits in the ADP1850 are turned off. Note that EN1/EN2 cannot shut down the LDO at VCCO, which is always active. For the purpose of start-up power sequencing, the startup of the ADP1850 can be programmed by connecting an appropriate resistor divider from the master power supply to the EN1/EN2 pin, as shown in Figure 29. For instance, if the desired start-up voltage from the master power supply is 10 V, R1 and R2 can be set to 156 kΩ and 10 kΩ, respectively. MASTER SUPPLY VOLTAGE SS1 3 R1 R2 INDUCTOR CURRENT VOUT1 ADP1850 EN1 OR EN2 FB1 OR FB2 RTOP RBOT CH1 10V CH3 500mV M2ms A CH1 11.2V CH4 10A Ω Figure 28. Current Limit Hiccup Mode, 20 A Current Limit 09440-029 4 09440-030 SHORT-CIRCUIT AND CURRENT-LIMIT PROTECTION Figure 29. Optional Power-Up Sequencing Circuit THERMAL OVERLOAD PROTECTION The ADP1850 has an internal temperature sensor that senses the junction temperature of the chip. When the junction temperature of the ADP1850 reaches approximately 155°C, the ADP1850 goes into thermal shutdown, the converter is turned off, and SS discharges toward zero through an internal 1 kΩ resistor. At the same time, VCCO discharges to zero. When the junction temperature drops below 135°C, the ADP1850 resumes normal operation after the soft start sequence. Rev. C | Page 15 of 32 ADP1850 Data Sheet APPLICATIONS INFORMATION SETTING THE OUTPUT VOLTAGE The output voltage is set using a resistive voltage divider from the output to FB. The voltage divider divides down the output voltage to the 0.6 V FB regulation voltage to set the regulation output voltage. The output voltage can be set to as low as 0.6 V and as high as 90% of the power input voltage. The maximum input bias current into FB is 100 nA. For a 0.15% degradation in regulation voltage and with 100 nA bias current, the low-side resistor, RBOT, must be less than 9 kΩ, which results in 67 µA of divider current. For RBOT, use a 1 kΩ to 20 kΩ resistor. A larger value resistor can be used but results in a reduction in output voltage accuracy due to the input bias current at the FBx pin, while lower values cause increased quiescent current consumption. Choose RTOP to set the output voltage by using the following equation: RTOP  V − VFB = R BOT  OUT VFB      The SSx pin reaches a final voltage equal to VCCO. If the output voltage is precharged prior to turn-on, the ADP1850 prevents reverse inductor current, which discharges the output capacitor. Once the voltage at SSx exceeds the regulation voltage (typically 0.6 V), the reverse current is reenabled to allow the output voltage regulation to be independent of load current. Furthermore, in dual-phase operation, where SS1 is shorted to SS2, the current source is doubled to 13 µA during the soft start sequence. When a controller is disabled, for instance, EN1/EN2 is pulled low or experiences an overcurrent limit condition, the soft start capacitor is discharged through an internal 3 kΩ pull-down resistor. SETTING THE CURRENT LIMIT The current limit comparator measures the voltage across the low-side MOSFET to determine the load current. The current limit is set by an external current limit resistor, RILIM, between ILIMx and SWx. The current sense pin, ILIMx, sources nominally 50 μA to this external resistor. This creates an offset voltage of RILIM multiplied by 50 μA. When the drop across the low-side MOSFET, RDSON, is equal to or greater than this offset voltage, the ADP1850 flags a current limit event. where: RTOP is the high-side voltage divider resistance. RBOT is the low-side voltage divider resistance. VOUT is the regulated output voltage. VFB is the feedback regulation threshold, 0.6 V. The minimum output voltage is dependent on fSW and minimum DH on time. The maximum output voltage is dependent on fSW, the minimum DH off time, and the IR drop across the high-side NMOSFET and the DCR of the inductor. For example, with fSW of 600 kHz (or 1.67 µs) and a minimum on time of 130 ns, the minimum duty cycle is approximately 7.8% (130 ns/1.67 µs). If VIN is 12 V and the duty cycle is 7.8%, then the lowest output is 0.94 V. As an example for the maximum output voltage, if VIN is 5 V, fSW is 600 kHz, and the minimum DH off time is 395 ns (335 ns DH off time plus approximately 60 ns total dead time), then the maximum duty cycle is 76%. Therefore, the maximum output is approximately 3.8 V. If the IR drop across the highside NMOSFET and the DCR of the inductor is 0.5 V, then the absolute maximum output is 4.5 V (5 V − 0.5 V), independent of fSW and duty cycle. Because the ILIMx current and the MOSFET, RDSON, vary over process and temperature, the minimum current limit should be set to ensure that the system can handle the maximum desired load current. To do this, use the peak current in the inductor, which is the desired output current limit level plus ½ of the ripple current, the maximum RDSON of the MOSFET at its highest expected temperature, and the minimum ILIM current. Keep in mind that the temperature coefficient of the MOSFET, RDSON, is typically 0.4%/oC. R ILIM = The soft start period is set by an external capacitor between SS1/SS2 and AGND. The soft start function limits the input inrush current and prevents output overshoot. When EN1/EN2 is enabled, a current source of 6.5 µA starts charging the capacitor, and the regulation voltage is reached when the voltage at SS1/SS2 reaches 0.6 V. The soft start period is approximated by 0. 6 V 6.5 μA 47 µA where: ILPK is the peak inductor current. SOFT START t SS = I LPK × R DSON _ MAX C SS Rev. C | Page 16 of 32 Data Sheet ADP1850 ACCURATE CURRENT-LIMIT SENSING VIN RRAMP RDSON of the MOSFET can vary by more than 50% over the temperature range. Accurate current limit sensing is achieved by adding a current sense resistor from the source of the lowside MOSFET to PGNDx. Make sure that the power rating of the current sense resistor is adequate for the application. Apply the previous equation and calculate RILIM by replacing RDSON_MAX with RSENSE. Figure 30 illustrates the implementation of accurate current limit sensing. RAMP ADP1850 DHx SWx RILIM ILIMx RCSG VIN Figure 31. Slope Compensation and CS Gain Connection ADP1850 SETTING THE CURRENT SENSE GAIN DHx SWx RILIM ILIMx RSENSE 09440-031 DLx Figure 30. Accurate Current Limit Sensing SETTING THE SLOPE COMPENSATION In a current-mode control topology, slope compensation is needed to prevent subharmonic oscillations in the inductor current and to maintain a stable output. The external slope compensation is implemented by summing the amplified sense signal and a scaled voltage at the RAMPx pin. To implement the slope compensation, connect a resistor between RAMPx and the input voltage. The resistor, RRAMP, is calculated by R RAMP = 7 × 10 9 L ACS × R DSON _ MAX where: 7 × 109 is an internal parameter. L is the inductance (with units in H) of the inductor. RDSON_MAX is the low-side MOSFET maximum on resistance. ACS is the gain, either 3 V/V, 6 V/V, 12 V/V, or 24 V/V, of the current sense amplifier (see the Setting the Current Sense Gain section for more details). RDSON is temperature dependent and can vary as much as 0.4%/oC. Choose RDSON at the maximum operating temperature. The voltage at RAMPx is fixed at 0.2 V, and the current going into RAMPx should be between 10 µA and 160 µA. Make sure that the following condition is satisfied: 10 µA ≤ V IN − 0.2 V R RAMP 09440-032 DLx ≤ 160 µA For instance, with an input voltage of 12 V, RRAMP should not exceed 1.1 MΩ. If the calculated RRAMP produces less than 10 µA, then select an RRAMP value that produces between 10 µA and 15 µA. Figure 31 illustrates the connection of the slope compensation resistor, RRAMP, and the current sense gain resistor, RCSG. The voltage drop across the external low-side MOSFET is sensed by a current sense amplifier by multiplying the peak inductor current and the RDSON of the MOSFET. The result is then amplified by a gain factor of either 3 V/V, 6 V/V, 12 V/V, or 24 V/V, which is programmable by an external resistor, RCSG, connected to the DLx pin. This gain is sensed only during power-up and not during normal operation. The amplified voltage is summed with the slope compensation ramp voltage and fed into the PWM controller for a stable regulation voltage. The voltage range of the internal node, VCS, is between 0.4 V and 2.2 V. Select the current sense gain such that the internal minimum amplified voltage (VCSMIN) is above 0.4 V and the maximum amplified voltage (VCSMAX) is 2.1 V. Note that VCSMIN or VCSMAX is not the same as VCOMP, which has a range of 0.85 V to 2.25 V. Make sure that the maximum VCOMP (VCOMPMAX) does not exceed 2.2 V to account for temperature and part-to-part variations. See the following equations for VCSMIN, VCSMAX, and VCOMPMAX: VCSMIN = 0.75 V − 1 I LPP × R DSON _ MIN × ACS 2 VCSMAX = 0.75 V + ( I LOADMAX − VCOMPMAX = (VIN − 0.2 V)t ON 100 pF × R RAMP 1 I LPP ) × R DSON _ MAX × ACS 2 + VCSMAX where: VCSMIN is the minimum amplified voltage of the internal current sense amplifier at zero output current. VCSMAX is the maximum amplified voltage of the internal current sense amplifier at maximum output current. RDSON_MIN is the low-side MOSFET minimum on resistance. The zero-current level voltage of the current sense amplifier is 0.75 V. ILPP is the peak-to-peak ripple current in the inductor. ILOADMAX is the maximum output dc load current. VCOMPMAX is the maximum voltage at the COMP pin. 100 pF is an internal parameter. tON is the high-side driver (DH) on time. Rev. C | Page 17 of 32 ADP1850 Data Sheet INPUT CAPACITOR SELECTION INPUT FILTER The input current to a buck converter is a pulse waveform. It is zero when the high-side switch is off and approximately equal to the load current when it is on. The input capacitor carries the input ripple current, allowing the input power source to supply only the direct current. The input capacitor needs sufficient ripple current rating to handle the input ripple, as well as an ESR that is low enough to mitigate input voltage ripple. For the usual current ranges for these converters, it is good practice to use two parallel capacitors placed close to the drains of the high-side switch MOSFETs (one bulk capacitor of sufficiently high current rating and a 10 μF ceramic decoupling capacitor, typically). Normally a 0.1 µF or greater value bypass capacitor from the input pin (VIN) to AGND is sufficient for filtering out any unwanted switching noise. However, depending on the PCB layout, some switching noise can enter the ADP1850 internal circuitry; therefore, it is recommended to have a low pass filter at the VIN pin. Connecting a resistor, between 2 Ω and 5 Ω, in series with VIN and a 1 µF ceramic capacitor between VIN and AGND creates a low pass filter that effectively filters out any unwanted glitches caused by the switching regulator. Keep in mind that the input current could be larger than 100 mA when driving large MOSFETs. A 100 mA across a 5 Ω resistor creates a 0.5 V drop, which is the same voltage drop in VCCO. In this case, a lower resistor value is desirable. Select an input bulk capacitor based on its ripple current rating. First, determine the duty cycle of the output. VOUT VIN ADP1850 VIN 1µF AGND The input capacitor RMS ripple current is given by Figure 32. Input Filter Configuration I RMS = I O D(1 − D) BOOST CAPACITOR SELECTION where: IO is the output current. D is the duty cycle The minimum input capacitance required for a particular load is C IN , MIN = 2Ω TO 5Ω I O × D(1 − D) To lower system component count and cost, the ADP1850 has an integrated rectifier (equivalent to the boost diode) between VCCO and BSTx. Choose a boost ceramic capacitor with a value between 0.1 µF and 0.22 µF; this capacitor provides the current for the high-side driver during switching. INDUCTOR SELECTION (VPP − I O × DR ESR ) f SW The output LC filter smoothes the switched voltage at SWx. For most applications, choose an inductor value such that the inductor ripple current is between 20% and 40% of the maximum dc output load current. Generally, a larger inductor current ripple generates more power loss in the inductor and larger voltage ripples at the output. Check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak inductor current of a particular design. where: VPP is the desired input ripple voltage. RESR is the equivalent series resistance of the capacitor. If an MLCC capacitor is used, the ESR is near 0, then the equation is simplified to C IN , MIN = I O × 09440-033 D= VIN D(1 − D) VPP × f SW The capacitance of MLCC is voltage dependent. The actual capacitance of the selected capacitor must be derated according to the manufacturer’s specification. In addition, add more bulk capacitance, such as by using electrolytic or polymer capacitors, as necessary for large step load transients. Make sure the current ripple rating of the bulk capacitor exceeds the maximum input current ripple of a particular design. Choose the inductor value by the following equation: L= V IN − VOUT VOUT × f SW × ∆I L V IN where: L is the inductor value. fSW is the switching frequency. VOUT is the output voltage. VIN is the input voltage. ∆IL is the peak-to-peak inductor ripple current. Rev. C | Page 18 of 32 Data Sheet ADP1850 OUTPUT CAPACITOR SELECTION Choose the output bulk capacitor to set the desired output voltage ripple. The impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple. The impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics, the equivalent series resistance (ESR), and the equivalent series inductance (ESL). The output voltage ripple can be approximated by   1 ∆VOUT ≅ ∆I L  R ESR + + 4 f SW × L ESL    8 f SW × COUT   SR, required to satisfy the voltage droop requirement is approximated by COUT ≅ ∆I STEP ∆VDROOP × f SW where: ∆ISTEP is the step load. ∆VDROOP is the voltage droop at the output. When a load is suddenly removed from the output, the energy stored in the inductor rushes into the capacitor, causing the output to overshoot. The output capacitance required to satisfy the output overshoot requirement can be approximated by where: ∆VOUT is the output ripple voltage. ∆IL is the inductor ripple current. RESR is the equivalent series resistance of the output capacitor (or the parallel combination of ESR of all output capacitors). LESL is the equivalent series inductance of the output capacitor (or the parallel combination of ESL of all capacitors). where: ∆VOVERSHOOT is the overshoot voltage during the step load. Solving COUT in the previous equation yields MOSFET SELECTION C OUT ≅ ∆I L 1 × 8 f SW ∆VOUT − ∆I L R ESR − 4 ∆I L f SW × L ESL Usually the capacitor impedance is dominated by ESR. The maximum ESR rating of the capacitor, such as in electrolytic or polymer capacitors, is provided in the manufacturer’s data sheet; therefore, output ripple reduces to ∆VOUT ≅ ∆I L × RESR Electrolytic capacitors also have significant ESL, on the order of 5 nH to 20 nH, depending on type, size, and geometry. PCB traces contribute some ESR and ESL, as well. However, using the maximum ESR rating from the capacitor data sheet usually provides some margin such that measuring the ESL is not usually required. In the case of output capacitors where the impedance of the ESR and ESL are small at the switching frequency, for instance, where the output capacitor is a bank of parallel MLCC capacitors, the capacitive impedance dominates and the output capacitance equation reduces to COUT ≅ ∆I L 8 ∆VOUT × f SW C OUT ≅ (VOUT ∆I STEP 2 L + ∆VOVERSHOOT )2 − VOUT 2 Select the largest output capacitance given by any of the previous three equations. The choice of MOSFET directly affects the dc-to-dc converter performance. A MOSFET with low on resistance reduces I2R losses, and low gate charge reduces transition losses. The MOSFET should have low thermal resistance to ensure that the power dissipated in the MOSFET does not result in excessive MOSFET die temperature. The high-side MOSFET carries the load current during on time and usually carries most of the transition losses of the converter. Typically, the lower the on resistance of the MOSFET, the higher the gate charge and vice versa. Therefore, it is important to choose a high-side MOSFET that balances the two losses. The conduction loss of the high-side MOSFET is determined by the equation V PC ≅ (I LOAD )2 × R DSON  OUT  VIN     where: RDSON is the MOSFET on resistance. The gate charging loss is approximated by the equation PG ≅ VPV × QG × f SW Make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current. During a load step transient on the output, for instance, when the load is suddenly increased, the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. This initial output voltage deviation results in a voltage droop or undershoot. The output capacitance, assuming 0 Ω where: VPV is the gate driver supply voltage. QG is the MOSFET total gate charge. Note that the gate charging power loss is not dissipated in the MOSFET but rather in the ADP1850 internal drivers. This power loss should be taken into consideration when calculating the overall power efficiency. Rev. C | Page 19 of 32 ADP1850 Data Sheet The high-side MOSFET transition loss is approximated by the equation PT ≅ The total power dissipation of the high-side MOSFET is the sum of conduction and transition losses: VIN × I LOAD × (t R + t F ) × f SW PHS ≅ PC + PT 2 The synchronous rectifier, or low-side MOSFET, carries the inductor current when the high-side MOSFET is off. The lowside MOSFET transition loss is small and can be neglected in the calculation. For high input voltage and low output voltage, the low-side MOSFET carries the current most of the time. Therefore, to achieve high efficiency, it is critical to optimize the low-side MOSFET for low on resistance. In cases where the power loss exceeds the MOSFET rating or lower resistance is required than is available in a single MOSFET, connect multiple low-side MOSFETs in parallel. The equation for low-side MOSFET conduction power loss is where: PT is the high-side MOSFET switching loss power. tR is the rise time in charging the high-side MOSFET. tF is the fall time in discharging the high-side MOSFET. tR and tF can be estimated by tR ≅ Q GSW I DRIVER _ RISE tF ≅ Q GSW I DRIVER _ FALL where: QGSW is the gate charge of the MOSFET during switching and is given in the MOSFET data sheet. IDRIVER_RISE and IDRIVER_FALL are the driver current put out by the ADP1850 internal gate drivers. If QGSW is not given in the data sheet, it can be approximated by Q GSW ≅ Q GD + Q GS 2 where: QGD and QGS are the gate-to-drain and gate-to-source charges given in the MOSFET data sheet. IDRIVER_RISE and IDRIVER_FALL can be estimated by I DRIVER _ RISE ≅ VDD − VSP RON _ SOURCE + RGATE I DRIVER _ FALL ≅ VSP RON _ SINK + RGATE  V  PCLS ≅ (I LOAD )2 × R DSON 1 − OUT  VIN   There is also additional power loss during the time, known as dead time, between the turn-off of the high-side switch and the turn-on of the low-side switch, when the body diode of the lowside MOSFET conducts the output current. The power loss in the body diode is given by PBODYDIODE = VF × t D × f SW × I O where: VF is the forward voltage drop of the body diode, typically 0.7 V. tD is the dead time in the ADP1850, typically 30 ns when driving some medium-size MOSFETs with input capacitance, Ciss, of approximately 3 nF. The dead time is not fixed. Its effective value varies with gate drive resistance and Ciss, so PBODYDIODE increases in high load current designs and low voltage designs. Then the power loss in the low-side MOSFET is where: VDD is the input supply voltage to the driver and is between 2.75 V and 5 V, depending on the input voltage. VSP is the switching point where the MOSFET fully conducts; this voltage can be estimated by inspecting the gate charge graph given in the MOSFET data sheet. RON_SOURCE is the on resistance of the ADP1850 internal driver, given in Table 1 when charging the MOSFET. RON_SINK is the on resistance of the ADP1850 internal driver, given in Table 1 when discharging the MOSFET. RGATE is the on gate resistance of MOSFET given in the MOSFET data sheet. If an external gate resistor is added, add this external resistance to RGATE. PLS = PCLS + PBODYDIODE Note that MOSFET, RDSON, increases with increasing temperature with a typical temperature coefficient of 0.4%/oC. The MOSFET junction temperature (TJ) rise over the ambient temperature is TJ = TA + θJA × PD where: θJA is the thermal resistance of the MOSFET package. TA is the ambient temperature. PD is the total power dissipated in the MOSFET. Rev. C | Page 20 of 32 Data Sheet ADP1850 LOOP COMPENSATION (SINGLE PHASE OPERATION) As with most current mode step-down controller, a transconductance error amplifier is used to stabilize the external voltage loop. Compensating the ADP1850 is fairly easy; an RC compensator is needed between COMPx and AGND. Figure 33 shows the configuration of the compensation components: RCOMP, CCOMP, and CC2. Because CC2 is very small compared to CCOMP, to simplify calculation, CC2 is ignored for the stability compensation analysis. ADP1850 COMPx Gm At the crossover frequency, the open-loop transfer function is unity or 0 dB, H (fCROSS) = 1. Combining Equation 1 and Equation 3, ZCOMP at the crossover frequency can be written as  2π × f CROSS Z COMP ( f CROSS ) =   Gm × G CS  CCOMP f ZERO = 09440-034 The open loop gain transfer function at angular frequency, s, is given by VREF × Z COMP (s) × Z FILTER (s) VOUT (2) where: ACS is the current sense gain of either 3 V/V, 6 V/V, 12 V/V, or 24 V/V set by the gain resistor between DLx and PGNDx. RDSON_MIN is the low-side MOSFET minimum on resistance. If a sense resistor, RS, is added in series with the low-side FET, then GCS becomes 1 ACS × (R DSON _ MIN + RS ) Because the zero produced by the ESR of the output capacitor is not needed to stabilize the control loop, assuming ESR is small the ESR is ignored for analysis. Then ZFILTER is given by 1 (3) sC OUT 1 sC COMP = 1 + sRCOMP × CCOMP sC COMP f CROSS f CROSS + f ZERO 2 2  2π × f CROSS ×  Gm × G CS    C OUT × VOUT ×   VREF     (8)   Choose the crossover and zero frequencies as follows: f CROSS = f SW 12 f ZERO = f CROSS f SW = 4 48 (9) (10)   C OUT × VOUT ×   VREF     (11)   where: Gm is the transconductance of the error amplifier, 500 µS. ACS is the current sense gain of 3 V/V, 6 V/V, 12 V/V, or 24 V/V. RDSON is on resistance of the low-side MOSFET. VREF = 0.6 V. And combining Equation 6 and Equation 10 yields C COMP = 2 πRCOMP × f CROSS (12) Note that the previous simplified compensation equations for RCOMP and CCOMP yield reasonable results in fCROSS and phase margin assuming that the compensation ramp current is ideal. Varying the ramp current or deviating the ramp current from ideal can affect fCROSS and phase margin. And lastly, set CC2 to Because CC2 is small relative to CCOMP, ZCOMP can be simplified to Z COMP = RCOMP + (7) f CROSS  2π × f CROSS RCOMP = 0.97 × ACS × R DSON  Gm  1 ACS × R DSON _ MIN Z FILTER = f CROSS 2 + f ZERO 2 Substituting Equation 2, Equation 9, and Equation 10 into Equation 8 yields GCS with units of A/V is given by GCS = RCOMP = (1) where: Gm is the transconductance of the error amplifier, 500 µS. GCS is the tranconductance of the power stage. ZCOMP is the impedance of the compensation network. ZFILTER is the impedance of the output filter. VREF = 0.6 V. GCS = (6) Combining Equation 5 and Equation 7 and solving for RCOMP gives Figure 33. Compensation Components H (s) = Gm × GCS × 1 2πRCOMP × C COMP Z COMP ( f CROSS ) = RCOMP × 0.6V (5) At the crossover frequency, Equation 4 can be shown as FBx AGND     The zero produced by RCOMP and CCOMP is RCOMP CC2  C OUT × VOUT   VREF  (4) Rev. C | Page 21 of 32 1 1 × C COMP ≤ C C 2 ≤ × C COMP 20 10 (13) ADP1850 Data Sheet CONFIGURATION AND LOOP COMPENSATION (DUAL-PHASE OPERATION) SWITCHING NOISE AND OVERSHOOT REDUCTION In dual-phase operation, the two outputs of the switching regulators are shorted together and can source more than 50 A of output current depending on the selection of the power components. Internal parameters in the ADP1850 are optimized and trimmed in the factory to minimize the mismatch in output currents between the two channels. See Figure 34 and Figure 47 for a configuration of a typical dualphase application circuit. Note that FB1 shorts to FB2, SS1 to SS2, and COMP1 to COMP2, where the outputs of the two error amplifiers are shared. Furthermore, the controller needs to be placed in forced PWM operation by connecting SYNC to VCCO or logic high. The equations for calculating the loop compensation components are identical to the single-phase operation, but the combined value of Gm of the error amplifiers, the modulator gain and the effective fSW are all doubled. In any high speed step-down regulator, high frequency noise (generally in the range of 50 MHz to 100 MHz) and voltage overshoot are always present at the gate, the switch node (SW), and the drains of the external MOSFETs. The high frequency noise and overshoot are caused by the parasitic capacitance, CGD, of the external MOSFET and the parasitic inductance of the gate trace and the packages of the MOSFETs. When the high current is switched, electromagnetic interference (EMI) is generated, which can affect the operation of the surrounding circuits. To reduce voltage ringing and noise, it is recommended to add an RC snubber between SWx and PGNDx for high current applications, as illustrated in Figure 35. In most applications, RSNUB is typically 2 Ω to 4 Ω, and CSNUB typically 1.2 nF to 3 nF. RSNUB can be estimated by RRAMP1 L MOSFET C OSS RSNUB ≅ 2 VIN And CSNUB can be estimated by VIN C SNUB ≅ COSS ADP1850 EN1 EN2 VDL HI SW1 ILIM1 FB1 M2 DL1 VOUTx RCSG1 RRAMP2 VIN RAMP2 COMP1 COMP2 M3 PSNUB = V IN 2 × C SNUB × f SW L2 DH2 BST2 SW2 ILIM2 FB2 R1 M4 DL2 R2 RCSG2 PGND2 Figure 34. Dual-Phase Circuit 09440-002 AGND The size of the RC snubber components needs to be chosen correctly to handle the power dissipation. The power dissipated in RSNUB is PGND1 FREQ SS1 SS2 where: LMOSFET is the total parasitic inductance of the high-side and low-side MOSFETs, typically 3 nH, and is package dependent. COSS is the total output capacitance of the high-side and lowside MOSFETs given in the MOSFET data sheet. L1 DH1 BST1 VCCO TRK1 TRK2 PGOOD1 PGOOD2 SYNC LO M1 In most applications, a component size 0805 for RSNUB is sufficient. However, the use of an RC snubber reduces the overall efficiency, generally by an amount in the range of 0.1% to 0.5%. The RC snubber does not reduce the voltage overshoot. A resistor, shown as RRISE in Figure 35, at the BSTx pin helps to reduce overshoot and is generally between 2 Ω and 4 Ω. Adding a resistor in series, typically between 2 Ω and 4 Ω, with the gate driver also helps to reduce overshoot. If a gate resistor is added, then RRISE is not needed. VDL ADP1850 (CHANNEL 1) RRISE VIN BST1 M1 DH1 L VOUTx SW1 ILIM1 DL1 RSNUB RILIM1 M2 COUT CSNUB PGND1 Figure 35. Application Circuit with a Snubber Rev. C | Page 22 of 32 09440-035 RAMP1 Data Sheet ADP1850 VOLTAGE TRACKING Two tracking configurations are possible with the ADP1850: coincident and ratiometric trackings. Coincident Tracking The most common application is coincident tracking, used in core vs. I/O voltage sequencing and similar applications. Coincident tracking forces the slave output voltage’s ramp rate to be the same as the master’s until the slave output reaches its regulation. Connect the slave TRKx input to a resistor divider from the master voltage that is the same as the divider used on the slave FBx pin. This forces the slave voltage to be the same as the master voltage. For coincident tracking, use RTRKT = RTOP and RTRKB = RBOT, as shown in Figure 37. VOUT _ MASTER As the master voltage rises, the slave voltage rises identically. Eventually, the slave voltage reaches its regulation voltage, where the internal reference takes over the regulation while the TRKx input continues to increase and thus removes itself from influencing the output voltage. To ensure that the output voltage accuracy is not compromised by the TRKx pin being too close in voltage to the reference voltage (VFB, typically 0.6 V), make sure that the final value of the TRKx voltage of the slave channel is at least 30 mV above VFB. Ratiometric Tracking Ratiometric tracking limits the output voltage to a fraction of the master voltage, as illustrated in Figure 38 and Figure 39. The final TRKx voltage of the slave channel should be set to at least 30 mV below the FB voltage of the master channel. When the TRKx voltage of the slave channel drops to a level that’s below the minimum on-time condition, the slave channel operates in pulse skip mode while keeping the output regulated and tracked to the master channel. Also, when TRKx or FBx drops below the PGOOD undervoltage threshold, the PGOOD signal gets tripped and becomes active low. SLAVE VOLTAGE 09440-036 TIME Figure 38. Ratiometric Tracking Figure 36. Coincident Tracking EN1 EN2 ADP1850 TRK1 45.3kΩ FB1 10kΩ CSS1 100nF SS1 FB2 EN2 ADP1850 RTRKT 20kΩ 1.1V VCCO FB1 TRK1 RTRKB 10kΩ CSS1 37nF SS1 CSS2 20nF SS2 RBOT 10kΩ VOUT2_SLAVE 0.6V 0.55V RTRKB 10kΩ CSS2 20nF RTOP 22.6kΩ 0.55V 1.8V RTRKT 49.9kΩ TRK2 FB2 RTOP 20kΩ 45.3kΩ 10kΩ TRK2 SS2 RBOT 10kΩ EN1 09440-037 VCCO 3.3V VOUT1_MASTER EN 3.3V VOUT1_MASTER EN SLAVE VOLTAGE 1.8V VOUT2_SLAVE 09440-039 VOLTAGE (V) MASTER VOLTAGE TIME MASTER VOLTAGE 09440-038 In all tracking configurations, the output can be set as low as 0.6 V for a given operating condition. The soft start time setting of the master voltage should be longer than the soft start of the slave voltage. This forces the rise time of the master voltage to be imposed on the slave voltage. If the soft start setting of the slave voltage is longer, the slave comes up more slowly, and the tracking relationship is not seen at the output. VOUT _ SLAVE VOLTAGE (V) The ADP1850 includes a tracking feature that tracks a master voltage. This feature is especially important when the ADP1850 is providing separate power supply voltages to a single integrated circuit, such as the core and I/O voltages of a DSP, FPGA, or microcontroller. In these cases, improper sequencing can cause damage to the load IC.   R 1 + TOP   R  BOT  =   RTRKT  1 +   RTRKB   Figure 39. Example of a Ratiometric Tracking Circuit Figure 37. Example of a Coincident Tracking Circuit The ratio of the slave output voltage to the master voltage is a function of the two dividers. Rev. C | Page 23 of 32 ADP1850 Data Sheet Another ratiometric tracking configuration is having the slave channel rise more quickly than the master channel, as shown in Figure 40 and Figure 41. The tracking circuits in Figure 39 and Figure 41 are virtually identical with the exception that RTRKB > RTRKT as shown in Figure 41. 09440-040 SLAVE VOLTAGE In addition to the single power supply configuration, the power stage input voltage of the dc-to-dc converter can come from a different voltage supply, as illustrated in Figure 42. The range of the power stage input voltage (VPIN) is 1 V to 20 V. For instance, the bias input voltage (VIN) is 5 V, VPIN can be as low as 1 V or as high as 20 V. The user needs to make sure that the minimum or the maximum duty cycle is not violated in this operating condition. Furthermore, note that RRAMP is connected to VPIN. TIME Figure 40. Ratiometric Tracking (Slave Channel Has a Faster Ramp Rate) SS1 SW1 10kΩ RTRKB 10kΩ DL1 PGND1 FB1 FB1 TRK2 SS2 FB2 RBOT 10kΩ RTRKT 5kΩ 2.2V RRAMP2 RAMP2 CSS2 20nF DH2 RTOP 20kΩ 1.8V VOUT2_SLAVE VPIN = 1V TO 20V VOUT2 SW2 09440-041 CSS1 100nF TRK1 VOUT1 DH1 45.3kΩ EN2 ADP1850 RAMP1 ADP1850 VOUT1_MASTER EN1 VCCO VIN 3.3V EN VPIN = 1V TO 20V RRAMP1 VIN = 2.7V TO 20V FB2 Figure 41. Example of a Ratiometric Tracking Circuit (Slave Channel Has a Faster Ramp Rate) DL2 PGND2 09440-042 VOLTAGE (V) MASTER VOLTAGE INDEPDENDENT POWER STAGE INPUT VOLTAGE Figure 42. Independent Power Stage Input Voltage (Simplified Schematic) Rev. C | Page 24 of 32 Data Sheet ADP1850 PCB LAYOUT GUIDELINES In any switching converter, there are some circuit paths that carry high dI/dt, which can create spikes and noise. Some circuit paths are sensitive to noise, while other circuits carry high dc current and can produce significant IR voltage drops. The key to proper PCB layout of a switching converter is to identify these critical paths and arrange the components and the copper area accordingly. When designing PCB layouts, be sure to keep high current loops small. In addition, keep compensation and feedback components away from the switch nodes and their associated components. VIN ADP1850 Part of the ADP1850 architecture is sensing the current across the low-side FET between the SWx and PGNDx pins. The switching GND currents of one channel creates noise and can be picked up by the other channel. It is essential to have Kelvin sensing connection between SWx and the drain of the respective low-side MOSFET, and between PGNDx and the source of the respective low-side MOSFET, as illustrated in Figure 43. Place these Kelvin connections very close to the FETs to achieve accurate current sensing. Figure 43 illustrates the proper connection technique for the SW1/SW2, PGND1/ PGND2, and PGND plane. CDECOUPLE1 DL1 21 M2 VOUT1 CIN1 KELVIN CONNECTIONS DL2 20 CDECOUPLE2 PGND2 19 M4 SW2 17 DH2 18 COUT1 AGND PLANE PGND1 22 MOSFETS, INPUT BULK CAPACITOR, AND BYPASS CAPACITOR HIGH CURRENT AND CURRENT SENSE PATHS L1 SW1 24 The following is a list of recommended layout practices for the synchronous buck controller, arranged by decreasing order of importance. The current waveform in the top and bottom FETs is a pulse with very high dI/dt; therefore, the path to, through, and from each individual FET should be as short as possible, and the two paths should be commoned as much as possible. In designs that use a pair of D-Pak, or a pair of SO-8 FETs, on one side of the PCB, it is best to counter-rotate the two so that the switch node is on one side of the pair. This allows the high-side FET’s drain to be bypassed to the low-side FET’s source with a suitable ceramic bypass capacitor placed as close as possible to the FETs. Close proximity of the bypass capacitor minimizes the inductance around the loop through the FETs and capacitor. The recommended bypass ceramic capacitor values range from 1 µF to 22 µF, depending on the output current. The ceramic bypass capacitor is usually connected to a larger value bulk filter capacitor and should be grounded to the PGNDx plane. M1 PGND PLANE CIN2 COUT2 L2 VOUT2 M3 VIN 09440-043 DH1 23 Figure 43. Grounding Technique for Two Channels SIGNAL PATHS The negative terminals of VIN bypass, compensation components, soft start capacitor, and the bottom end of the output feedback divider resistors should be tied to a small AGND plane. These connections should attach from their respective pins to the AGND plane and should be as short as possible. No high current or high dI/dt signals should be connected to this AGND plane. The AGND area should be connected through one wide trace to the negative terminal of the output filter capacitors. PGND PLANE The PGNDx pin handles a high dI/dt gate drive current returning from the source of the low side MOSFET. The voltage at this pin also establishes the 0 V reference for the overcurrent limit protection function and the ILIMx pin. A PGND plane should connect the PGNDx pin and the VDL bypass capacitor, 1 µF, through a wide and direct path to the source of the low side MOSFET. The placement of CIN is critical for controlling ground bounce. The negative terminal of CIN must be placed very close to the source of the low-side MOSFET. FEEDBACK AND CURRENT-LIMIT SENSE PATHS Avoid long traces or large copper areas at the FBx and ILIMx pins, which are low-level signal inputs that are sensitive to capacitive and inductive noise pickup. It is best to position any series resistors and capacitors as close as possible to these pins. Avoid running these traces close and/or parallel to high dI/dt traces. Rev. C | Page 25 of 32 ADP1850 Data Sheet SWITCH NODE The switch node is the noisiest place in the switcher circuit with large ac and dc voltages and currents. This node should be wide to minimize resistive voltage drop. To minimize capacitively coupled noise, the total area should be small. Place the FETs and inductor close together on a small copper plane to minimize series resistance and keep the copper area small. GATE DRIVER PATHS Gate drive traces (DH and DL) handle high dI/dt and tend to produce noise and ringing. They should be as short and direct as possible. If vias are needed, it is best to use two relatively large ones in parallel to reduce the peak current density and the current in each via. If the overall PCB layout is less than optimal, slowing down the gate drive slightly can be helpful to reduce noise and ringing. It is occasionally helpful to place small value resistors, such as between 2 Ω and 4 Ω, on the DHx and DLx pins. These can be populated with 0 Ω resistors if resistance is not needed. Note that the added gate resistance increases the switching rise and fall times, as well as increasing switching power loss in the MOSFET. OUTPUT CAPACITORS The negative terminal of the output filter capacitors should be tied close to the source of the low side FET. Doing this helps to minimize voltage differences between AGND and PGNDx. Rev. C | Page 26 of 32 Data Sheet ADP1850 TYPICAL OPERATING CIRCUITS 330pF 42.2kΩ 47pF VIN = 10V TO 18V M1 CIN 45.3kΩ 187kΩ 22pF CIN1 100nF VCCO L1 2.1kΩ 2Ω 3 VIN 4 VCCO RAMP1 27 26 25 BST1 SYNC 28 ILIM1 2 29 SS1 EN1 30 PGOOD1 1 31 FB1 TRK1 32 COMP1 10kΩ 0.1µF COUT11 COUT12 VOUT1 3.3V 14A M2 SW1 24 DH1 23 1µF 22kΩ PGND1 22 1µF DL1 21 1µF 2Ω ADP1850 5 VDL 6 AGND PGND2 19 7 FREQ DH2 18 8 EN2 SW2 17 FB2 COMP2 RAMP2 SS2 PGOOD2 ILIM2 BST2 10 11 12 13 14 15 16 187kΩ TRK2 9 VCCO M3 CIN2 2.1kΩ L2 M4 COUT21 0.1µF COUT22 VOUT2 1.8V 14A 100nF 22pF 23.2kΩ 22kΩ TO VIN 47pF 10kΩ 20kΩ fSW = 600kHz CIN: 150µF/20V, OS-CON, 20SEP150M, SANYO L1, L2: 1.2µH, WURTH ELEKTRONIK, 744325120 M1, M3: BSC080N03LS M2, M4: BSC030N03LS CIN1, CIN2: 10µF/X7R/25V/1210 × 2, GRM32DR71E106KA12, MURATA COUT11, COUT21: 330µF/6.3V/POSCAP × 2, 6TPF330M9L, SANYO COUT12, COUT22: 22µF/X5R/0805/6.3V × 3, GRM21BR60J226ME39, MURATA Figure 44. Typical 14 A Operating Circuit Rev. C | Page 27 of 32 09440-044 560pF VIN DL2 20 ADP1850 Data Sheet 560pF 28kΩ 33pF VIN = 10V TO 20V M1A 73.2kΩ 150kΩ CIN1 100nF VCCO L1 2.8kΩ 2Ω VCCO 25 ILIM1 4 26 BST1 VIN 27 PGOOD1 3 28 SS1 SYNC 29 RAMP1 2 30 COMP1 EN1 31 FB1 1 32 TRK1 10kΩ 0.1µF COUT1 VOUT1 5V 5A M1B SW1 24 DH1 23 1µF 22kΩ PGND1 22 1µF DL1 21 1µF 2Ω ADP1850 5 VDL 6 AGND PGND2 19 7 FREQ DH2 18 8 EN2 SW2 17 VIN DL2 20 M2A CIN2 FB2 COMP2 RAMP2 SS2 PGOOD2 ILIM2 BST2 9 10 11 12 13 14 15 16 150kΩ TRK2 84.5kΩ VCCO 10kΩ 10kΩ COUT2 100nF 22kΩ TO VIN 100pF M2B 0.1µF VOUT2 1.8V 5A 20kΩ fSW = 750kHz, PULSE SKIP MODE L1: 2µH, WURTH ELEKTRONIK, 744310200 L2: 1.15µH, WURTH ELEKTRONIK, 744310115 CIN1, CIN2: 10µF/X5R/16V/1206 × 2, GRM31CR61C106KA88, MURATA M1, M2: SI944DY OR BSON03MD COUT1, COUT2: 22µF/XR5/1210/6.3V × 3, GRM32DR60J226KA01, MURATA Figure 45. Typical Low Current Operating Circuit Rev. C | Page 28 of 32 09440-045 1.5nF L2 2.8kΩ Data Sheet ADP1850 1.8nF 5.34kΩ 33pF VIN = 3V TO 5.5V M1 7.5kΩ 20kΩ CIN1 100nF VCCO L1 4.99kΩ 5Ω 3 VIN 4 VCCO RAMP1 27 26 25 BST1 SYNC 28 ILIM1 2 29 SS1 EN1 30 PGOOD1 1 31 FB1 TRK1 32 COMP1 10kΩ 0.1µF COUT1 VOUT1 1.05V 1.8A M2 SW1 24 DH1 23 1µF 47kΩ PGND1 22 1µF DL1 21 1µF ADP1850 5 VDL 6 AGND PGND2 19 7 FREQ DH2 18 8 EN2 SW2 17 VIN DL2 20 M3 CIN2 FB2 COMP2 RAMP2 SS2 PGOOD2 ILIM2 BST2 9 10 11 12 13 14 15 16 8.66kΩ 10kΩ fSW = 800kHz, PULSE SKIP MODE L1, L2: 1µH, TOKO D62LCB1R0M M1, M2, M3, M4: SI2302ADS, SOT23 M4 0.1µF COUT2 VOUT2 1.8V 1.8A 100nF 47kΩ TO VIN 33pF L2 4.99kΩ 20kΩ CIN1, CIN2: 4.7µF/X5R/16V/0805 × 2, GRM219R60J475KE19, MURATA COUT1, COUT2: 22µF/XR5/0805/6.3V, GRM21BR60J226ME39, MURATA Figure 46. Typical Low Current Application with VIN < 5.5 V Rev. C | Page 29 of 32 09440-046 VCCO 1nF 20kΩ TRK2 78.7kΩ ADP1850 Data Sheet 3.3nF 8.87kΩ VIN = 10V TO 14V 180pF CIN 8.3kΩ M1 CIN11 22pF 137kΩ M2 CIN12 100nF TO VCCO 10kΩ L1 2Ω VCCO BST1 4 25 ILIM1 VIN 26 PGOOD1 3 27 SS1 SYNC 28 RAMP1 2 29 COMP1 EN1 30 FB1 1 31 TRK1 1.74kΩ 32 0.1µF COUT11 M3 COUT12 M4 SW1 24 DH1 23 1µF 22kΩ PGND1 22 1µF DL1 21 ADP1850 SW2 17 9 10 11 12 13 14 15 16 CIN21 TO VCCO TO FB1 TO TO VIN SS1 M5 M6 M7 M8 22pF CIN22 L2 1.74kΩ 0.1µF 137kΩ BST2 EN2 ILIM2 8 PGOOD2 DH2 18 SS2 FREQ RAMP2 PGND2 19 COMP2 AGND 7 FB2 6 TRK2 VDL VOUT1 1.09V 50A VIN DL2 20 5 COUT21 COUT22 22kΩ TO COMP1 fSW = 300kHz CIN = 180µF/16V × 4, 16SEP180M, OS-CON, SANYO M1, M2, M5, M6: BSC080N03IS M3, M4, M7, M8: BSC030N03LS L1, L2: SER1408-301, 300nH, COILCRAFT; OR 744355147, 0.4µH, WURTH ELECTRONIK CIN11, CIN12, CIN21, CIN22: 10µF/X7R/25V/1210, MURATA COUT11, COUT21, 2SEPC560MZ × 3, 560µF, OSCON, SANYO COUT12, COUT22: GRM31CR60J476ME19 × 2, 47µV/1206/6.3V, MURATA Figure 47. Dual-Phase Circuit, 50 A Output Rev. C | Page 30 of 32 09440-047 2Ω 1µF Data Sheet ADP1850 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 5.10 5.00 SQ 4.90 1 0.50 BSC 3.75 3.60 SQ 3.55 EXPOSED PAD 17 TOP VIEW 0.80 0.75 0.70 TOP VIEW PKG-004570 SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 32 25 24 0.50 0.40 0.30 8 16 9 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5. 02-22-2017-B PIN 1 INDICATOR 0.30 0.25 0.18 Figure 48. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP1850ACPZ-R7 ADP1850SP-EVALZ ADP1850DP-EVALZ 1 Temperature Range −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board in Single-Phase Mode with 14 A Output Evaluation Board in Dual-Phase Mode with 50 A Output Z = RoHS Compliant Part. Rev. C | Page 31 of 32 Package Option CP-32-12 ADP1850 Data Sheet NOTES ©2010–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09440-0-5/17(C) Rev. C | Page 32 of 32