ADP1850SP-EVALZ

Evaluation Board User Guide UG-204 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluation Board for the ADP1850SP Step-Down DC-to-DC Controller power MOSFETs. The two PWM outputs are phase shifted 180°, which reduces the input RMS ripple current, thus minimizing required input capacitance. The two outputs can be combined for dual-phase PWM operation that can deliver more than 50 A output current. The internal parameters of the two channels are optimized for current sharing. FEATURES Input range: 10 V to 20 V Two output voltages: 3.3 V and 1.8 V Output current: 14 A per channel Switching frequency: 600 kHz Operates in PWM or PSM Compact, low cost, and efficient design In addition, boost diodes are integrated into the ADP1850, thus lowering the overall system cost and component count. The ADP1850 can be set to operate in pulse skip, high efficiency mode under light load or in PWM continuous conduction mode. EVALUATION BOARD DESCRIPTION This document describes the design, operation, and test results of the ADP1850SP-EVALZ. The input range for this evaluation board is 10 V to 20 V, and the two regulated output voltages are set to 3.3 V (VOUT1) and 1.8 V (VOUT2) with a maximum 14 A output current. A switching frequency (fSW) of 600 kHz is chosen to achieve a good balance between efficiency and the sizes of the power components. The ADP1850 includes externally adjustable soft start, output overvoltage protection, externally adjustable current limit, power good, tracking function, and a programmable oscillator frequency that ranges from 200 kHz to 1.5 MHz. The ADP1850 provides an output voltage accuracy of ±0.85% from −40°C to +85°C and ±1.5% from −40°C to +125°C junction temperature. This controller can be powered from a 2.75 V to 20 V supply and is available in a 32-lead 5 mm × 5 mm LFCSP package. ADP1850 DEVICE DESCRIPTION The ADP1850 is a dual-channel, step-down switching controller with integrated drivers for external N-channel synchronous ADP1850SP EVALUATION BOARD GND TERMINAL ADP1850 VOUT1 TERMINAL VOUT2 TERMINAL GND TERMINAL 09455-001 GND TERMINAL VIN TERMINAL Figure 1. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 12 UG-204 Evaluation Board User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Output Capacitors .........................................................................3 Evaluation Board Description......................................................... 1 MOSFET Selection........................................................................3 ADP1850 Device Description......................................................... 1 Test Results .........................................................................................4 ADP1850SP Evaluation Board........................................................ 1 Evaluation Board Operating Instruction .......................................5 Revision History ............................................................................... 2 Other Information About the Evaluation Board PCB Layout......6 Component Design .......................................................................... 3 Evaluation Board Schematics and Artwork...................................7 Inductor Selection ........................................................................ 3 Ordering Information.................................................................... 11 Input Capacitors ........................................................................... 3 Bill of Materials........................................................................... 11 REVISION HISTORY 8/11—Rev. 0 to Rev. A Changes to Figure 2 and Figure 4................................................... 4 Changes to Table 3.......................................................................... 11 11/10—Revision 0: Initial Version Rev. A | Page 2 of 12 Evaluation Board User Guide UG-204 COMPONENT DESIGN For information about selecting power components and calculating component values, see the ADP1850 data sheet. OUTPUT CAPACITORS A 1.2 μH inductor with a 20 A average current rating (744325120 from Würth Elektronik) is selected. This is a compact inductor with a ferrite core, which offers high performance in terms of low RDC and low core loss. A combination of POSCAP™ polymer capacitors and MLCCs are selected for the output rails. Polymer capacitors have low ESR and high current ripple rating. Connecting polymer capacitors and MLCCs in parallel is very effective in reducing voltage ripple. Two 330 μF POSCAP capacitors and two 22 μF MLCCs are selected for each output. INPUT CAPACITORS MOSFET SELECTION Because of the very low ESR and high input current rating of multilayer ceramic capacitors (MLCCs), two 10 μF MLCCs in Size 1210 are selected as the input capacitors at the input of each channel. In addition, a 150 μF bulk OS-CON™ (aluminum solid capacitor with conductive polymer) capacitor from Sanyo is chosen for filtering out any unwanted low-frequency noise from the input power supply. For low output or low duty cycle, select a high-side MOSFET with fast rise and fall times and with low input capacitance to minimize charging and switching power loss. As for the synchronous rectifier (low-side MOSFET), select a MOSFET with low RDSON because the switching speed is not critical and there is no switching power loss in the low-side MOSFET. INDUCTOR SELECTION For the high-side MOSFET, the BSC080N03LS from Infineon Technologies in the PG-TDSON-8 or Super-SO8 package is selected. This part has low input capacitance (1.2 nF) and fast transition times (3 ns). For the low-side MOSFET, the BSC030N03LS, with RDSON of 4.7 mΩ at a VGS of 4.5 V, is selected. Rev. A | Page 3 of 12 UG-204 Evaluation Board User Guide TEST RESULTS TA = 25°C. 100 SW1 90 80 1 VOUT1 RIPPLE 60 2 VIN = 12V, FREQUENCY = 600kHz 50 SW2 40 3 30 VOUT1 = 3.3V VOUT2 = 1.8V VOUT1_1.8V_PWM VOUT1_1.8V_PSM 10 0 0.01 0.1 1 10 4 VOUT2 RIPPLE 100 LOAD (A) 09455-002 20 CH1 10V CH3 10V CH2 20mV CH4 20mV M1µs A CH1 12.8V 09455-005 EFFICIENCY (%) 70 Figure 5. Output Ripple, 14 A Load Figure 2. Efficiency (Measurement Is Made with the Adjacent Channel Disabled) 0.10 VIN = 12V, fSW = 600kHz, AT 5A LOAD 0.08 7A TO 14A STEP LOAD LINE REGULATION (%) 0.06 0.04 0.02 0 3 –0.02 4 VOUT1 RESPONSE –0.04 –0.06 10 20 15 VIN (V) CH3 5A Ω Figure 3. Line Regulation CH4 20mV M100µs A CH3 10.2A 09455-006 5 10.2A 09455-007 –0.10 09455-003 VOUT1 = 3.3V VOUT2 = 1.8V –0.08 Figure 6. Step Load Transient, VOUT1 0.4 VIN = 12V, fSW = 600kHz 0.3 0.1 0 3 VOUT1 = 3.3V VOUT2 RESPONSE –0.1 4 –0.2 VOUT2 = 1.8V –0.3 –0.4 0 2 4 6 8 LOAD (A) 10 12 14 09455-004 LOAD REGULATION (%) 7A TO 14A STEP LOAD 0.2 Figure 4. Load Regulation CH3 5A Ω CH4 20mV M100µs A CH3 Figure 7. Step Load Transient, VOUT2 Rev. A | Page 4 of 12 Evaluation Board User Guide UG-204 EVALUATION BOARD OPERATING INSTRUCTION 1. 2. 3. Connect Jumper J3 (EN1) to the high position to enable Channel 1 of the ADP1850. Connect Jumper J2 (EN2) to the high position to enable Channel 2 of the ADP1850. Connect Jumper J4 (FREQ) to the high position for 600 kHz operation. 4. 5. Connect Jumper J1 (SYNC) to the high position for PWM operation or to low for PSM operation. Connect the positive terminal of the input power supply to the input terminal, T1. The input range is 10 V to 20 V. Table 1. Jumper Description Jumper J1 Description SYNC Default Factory Setting High J2 J3 J4 EN2 EN1 FREQ High High High Function Connect high for PWM or low for PSM operation. For synchronization, run an external clock source to this pin. Connect high to enable Channel 2 of the ADP1850 or low to disable the channel. Connect high to enable Channel 1 of the ADP1850 or low to disable the channel. Connect low for 300 kHz or high for 600 kHz operation. This 14 A evaluation board is configured for operation at 600 kHz. Connect J4 high. Table 2. Performance Summary (TA = 25°C) Parameter VIN fSW VOUT1 IOUT1 VOUT1 Ripple, DC Load VOUT1 Deviation upon Step Load Release VOUT2 IOUT2 VOUT2 Ripple, DC Load VOUT2 Deviation upon Step Load Release Condition 10 V to 20 V Switching frequency, 600 kHz 3.3 V 0 A to 14 A 18 mV at 14 A load 1.5% with a 7 A step load 1.8 V 0 A to 14 A 18 mV at 14 A load 1.8% with a 7 A step load Rev. A | Page 5 of 12 UG-204 Evaluation Board User Guide OTHER INFORMATION ABOUT THE EVALUATION BOARD PCB LAYOUT As seen in Figure 1, the layout of this evaluation board is not optimized for the smallest PCB area. It is laid out in such a way that any of the components can be desoldered and replaced easily with different components with a hand soldering iron so that the user can modify the existing design without acquiring a new PCB layout. The physical size of the compensation components is 0603, which is selected for its ease of hand soldering when reworking the board is needed. The size of these components can be 0402 or even smaller in the final design. Note that there are extra place holders for input bulk capacitors, output filter capacitors, and MOSFETs. The user can remove, add, or change any of these power components to achieve a particular design objective. The track functions, where TRK1 and TRK2 are pulled up to VCCO through 0 Ω dummy resistors, are not used on this evaluation board. If a tracking function is needed, the user can remove the 0 Ω dummy resistors and add external resistive components to obtain the desired tracking function. Dummy 0 Ω resistors are placed at the driver gates, DHx and DLx, for evaluation purpose only and can be removed in the final design. Also, the configuration of this evaluation board can be modified to obtain a single output dual-phase operation. Furthermore, many test points are placed on the evaluation board so that the user can easily evaluate the performances of the ADP1850 with an oscilloscope. See Figure 8, the evaluation board schematic, for more information. Rev. A | Page 6 of 12 1 1 2 3 4 1 VDL 1 2 3 4 1 VDL TP16 TURRET T11 T2 TURRET T10 T1 VIN VIN 2 RB0 open RFREQ 100nf CVIN 1 J1 VCC 2 Vin = 10V to 20V 1 1 TP3 J4 SYNC 3 2 Way Link VCC FB1 J2 J3 VCC 2 Way Link 3 RT22 open RT24 RT21 0 TP5 REN21 REN22 RT23 TRK2 open VOUT1 187k RR2 23.2k 10k RF22 560pF RC2 CC21 EN2 FREQ AGND VDL VCCO VIN SYNC EN1 47pF 8 7 6 5 4 3 2 1 42.2k U1 330pF 47pF RC1 CC11 CC12 187k COMP1 RR1 10K CC22 1.0uF 1.0uF VDL CDR R103 EN2 EN1 VCC CV5 2 1 REN11 RVCC0 REN12 VIN 3 2 Way Link FREQ open RV5 SYNC 2 Way Link 3 1 2 RF12 FB1 45.3k RF11 SS1 FB2 20k RF21 32 TRK1 open RT12 31 FB1 FB2 10 DL2 DL1 SW2 DH2 open open open R101 open R102 R100 SW2 0 RDL2 22pF FB1 COMP1 SS1 2.1K RILIM21 CLIM2 VCC TP14 100nf DH2 DL2 DL1 DH1 TP11 VCC TP12 open RPG1 TP18 CBST2 0 RDH2 0 RDL1 0 RDH1 100nf CBST1 TP8 SW1 TP10 2.1K ADP1850-LFCSP 17 18 RPG2 TP4 100nF 20 21 PGND2 19 TP15 CSS2 23 24 PGND1 22 DH1 SW1 22pF CLIM 100nf RILIM11 TP2 R1 0 CSS1 TP6 TP17 27 RT14 30 COMP1 COMP2 11 TRK2 1 VOUT2 29 RAMP1 RAMP2 12 PGOOD1 ILIM2 RT13 28 SS1 SS2 13 1 26 ILIM1 1 25 BST1 BST2 15 1 2 2 PGOOD2 14 9 1 0 1 FB2 1 1 16 1 TP7 TP13 0 R2 RGCS2 22.6k 1 1 1 1 RT11 1 TRK1 RGCS1 22.6k TP9 1 S3 S2 S1 S3 S2 S1 QH3 BSC080N03 D4 D3 D2 D1 D4 D3 D2 D1 D4 D3 D2 D1 D4 D3 D2 D1 D4 D3 D2 D1 QH4 QL4 QL2 BSC030N03 D4 S3 D3 S2 D2 S1 D1 S3 S2 S1 QL1 S3 S2 S1 10uF 25V CIN21 10uF/25V 10uF 25V QH2 Cin11 VIN Cin12 QL3 BSC030N03 D4 D3 D2 D1 S3 S2 S1 S3 S2 S1 QH1 BSC080N03 D4 S3 D3 S2 D2 S1 D1 G G G G G G G TP1 1 Rev. A | Page 7 of 12 G Figure 8. Evaluation Board Schematic 10uF/25V CIN22 VIN L2 1.2uH RSNB2 open open CSNB2 CSNB1 open RSNB1 open 1.2uH L1 CON12 J8 1 2 3 4 5 6 7 8 9 10 11 12 open + COV8 open open 330uF open VOUT1 330uF CON12 J9 330uF + COV6 + COV4 + COV2 330uF 1 2 3 4 5 6 7 8 9 10 11 12 J7 22uF + VOUT2 22uF 1 2 3 4 1 2 3 4 T5 T4 T12 T8 T9 TURRET 1 T6 TURRET 1 1 2 3 4 T3 TURRET 1 VOUT2 = 1.8V J5 + COV23 J6 22uF COV22 22uF 1 2 3 4 VOUT1 = 3.3V open + CIN23 + COV12 + COV13 open + CIN13 VOUT2 VOUT1 150uF + CIN20 + COV7 + COV5 + COV3 + COV1 open + CIN10 VIN 09455-008 VCC Evaluation Board User Guide UG-204 EVALUATION BOARD SCHEMATICS AND ARTWORK Evaluation Board User Guide 09455-009 UG-204 09455-010 Figure 9. Top Silkscreen Figure 10. Top Layer Rev. A | Page 8 of 12 UG-204 09455-011 Evaluation Board User Guide 09455-012 Figure 11. Second Layer (AGND Plane) Figure 12. Third Layer (PGND Layer) Rev. A | Page 9 of 12 Evaluation Board User Guide 09455-013 UG-204 09455-014 Figure 13. Bottom Layer (PGND Layer) Figure 14. Bottom Silk Screen Rev. A | Page 10 of 12 Evaluation Board User Guide UG-204 ORDERING INFORMATION BILL OF MATERIALS Table 3. Qty 1 1 4 Reference Designator U1 CIN20 CIN11, CIN12, CIN21, CIN22 Manufacturer Analog Devices Sanyo Murata Part No. ADP1850 20SEP150M GRM32DR71E106KA12 Murata GRM188R71E104KA01 Murata GRM185R60J105KE21 Vishay Vishay Vishay Sanyo Murata Würth Elektronik CRCW06032R00F CRCW06032262F CRCW06031873F 6TPE330MFL GRM31CR60J226ME19L 744325120 Vishay Vishay Vishay Vishay CRCW06031002F CRCW06032002F CRCW06034532F CRCW06030R00F 2 2 1 1 2 1 1 2 2 4 5 RF22, RF12 RF21 RF11 RDH1, RDH2, RDL1, RDL2, Rt11, Rt21, R1, R2 QH1, QH3 QL2, QL3 CC11 CC21 CC12, CC22 RC1 RC2 RLIM11, RLIM21 CLIM, CLIM2 J1, J2, J3, J4 T8, T9, T10, T11, T12 Description Device under test, LFCSP OS-CON, 150 μF, 20 V Input capacitor MLCC, 10 μF, X7R, 25 V, 1210 Input capacitor MLCC, 100 nF, X7R, 25 V, 0603 Input capacitor MLCC, 1.0 μF, X5R, 6.3 V, 0603 Resistor, 2 Ω, 0603 Resistor, 22.6 kΩ, 0603 Resistor, 187 kΩ, 0603 POSCAP, 330 μF, 6.3 V, 18 mΩ MLCC, 22 μF, X5R, 1206 Inductor, 1.2 μH, 1.8 mΩ, IN = 20 A, ISAT = 25 A Resistor, 10 kΩ, 0603 Resistor, 20 kΩ, 0603 Resistor, 45.3 kΩ, 0603 Resistor, 0 Ω, 0603 5 CSS1, CSS2, CBST1, CBST2, CVIN 2 CV5, CDR 2 2 2 4 4 2 RB0, RVCCO RGCS1, RGCS2 RR1, RR2 COV1 COV11, COV2, COV21 COV12, COV13, COV22, COV23 L1, L2 2 1 1 8 N MOSFET, 30 V, 9 mΩ, super-SO8 N MOSFET, 30 V, 4.5 mΩ, super-SO8 MLCC, 330 pF, 0603 MLCC, 560 pF, 0603 MLCC, 47 pF, 0603 Resistor, 42.2 kΩ, 0603 Resistor, 23.2 kΩ, 0603 Resistor, 2.1 kΩ, 0603 MLCC, 22 pF, 0603 3-terminal jumpers, 0.1 inch Spacing Test points, 110 mil through hole Infineon Infineon Vishay Vishay Vishay Vishay Vishay Vishay BSC080N03LS BSC030N03LS VJ0603Y331KXAA VJ0603Y561KXAA VJ0603A470KXAA CRCW06034222F 6 T1, T2, T3, T4, T5, T6 Terminals Rev. A | Page 11 of 12 Any Keystone Electronics Corp. Keystone Electronics Corp. CRCW06032322F CRCW06032101F VJ0603A220KXAA 1502-1 8191 UG-204 Evaluation Board User Guide NOTES ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG09455-0-8/11(A) Rev. A | Page 12 of 12