Synchronous Buck Controller with Constant On-Time and Valley Current Mode ADP1870/ADP1871
FEATURES
Power input voltage range: 2.95 V to 20 V On-board bias regulator Minimum output voltage: 0.6 V 0.6 V reference voltage with ±1.0% accuracy Supports all N-channel MOSFET power stages Available in 300 kHz, 600 kHz, and 1.0 MHz options No current-sense resistor required Power saving mode (PSM) for light loads (ADP1871 only) Resistor-programmable current-sense gain Thermal overload protection Short-circuit protection Precision enable input Integrated bootstrap diode for high-side drive Starts into a precharged load Small, 10-lead MSOP package
TYPICAL APPLICATIONS CIRCUIT
VIN = 2.95V TO 20V
CC RTOP RC CC2
VIN
ADP1870/ ADP1871
COMP/EN BST CBST FB DRVH SW
CIN
VOUT
Q1
L
VOUT
RBOT GND CVREG2 COUT Q2 RRES LOAD
VREG DRVL PGND
CVREG
Figure 1.
100 95 90 85 80
EFFICIENCY (%)
VIN = 5V (PSM)
APPLICATIONS
Telecom and networking systems Mid to high end servers Set-top boxes DSP core power supplies
75 70 65 60 55 50 45 40 VIN = 16.5V (PSM) 35 30 25 10 100 VIN = 13V (PSM) TA = 25°C VOUT = 1.8V fSW = 300kHz WÜRTH INDUCTOR: 744325120, L = 1.2µH, DCR = 1.8mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 1k LOAD CURRENT (mA) 10k 100k
08730-102
VIN = 16.5V VIN = 13V
GENERAL DESCRIPTION
The ADP1870/ADP1871 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current-limit protection by using a constant on-time, pseudo-fixed frequency with a programmable currentlimit, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by utilizing valley current-mode control architecture. This allows the ADP1870/ ADP1871 to drive all N-channel power stages to regulate output voltages as low as 0.6 V. The ADP1871 is the power saving mode (PSM) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the Power Saving Mode (PSM) Version (ADP1871) section for more information). Available in three frequency options (300 kHz, 600 kHz, and 1.0 MHz, plus the PSM option), the ADP1870/ADP1871 are well suited for a wide range of applications that require a single-input power supply range from 2.95 V to 20 V. Low voltage biasing is supplied via a 5 V internal LDO.
Figure 2. Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz)
In addition, an internally fixed soft start period is included to limit input in-rush current from the input supply during startup and to provide reverse current protection during soft start for a precharged output. The low-side current-sense, current-gain scheme and integration of a boost diode, along with the PSM/forced pulsewidth modulation (PWM) option, reduce the external part count and improve efficiency. The ADP1870/ADP1871 operate over the −40°C to +125°C junction temperature range and are available in a 10-lead MSOP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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08730-001
ADP1870/ADP1871 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Applications Circuit............................................................ 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Boundary Condition .................................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 ADP1870/ADP1871 Block Diagram............................................ 18 Theory of Operation ...................................................................... 19 Startup .......................................................................................... 19 Soft Start ...................................................................................... 19 Precision Enable Circuitry ........................................................ 19 Undervoltage Lockout ............................................................... 19 On-Board Low Dropout Regulator .......................................... 19 Thermal Shutdown..................................................................... 20 Programming Resistor (RES) Detect Circuit .......................... 20 Valley Current-Limit Setting .................................................... 20 Hiccup Mode During Short Circuit ......................................... 21 Synchronous Rectifier ................................................................ 22 Power Saving Mode (PSM) Version (ADP1871) ................... 22 Timer Operation ........................................................................ 22 Pseudo-Fixed Frequency ........................................................... 23 Applications Information .............................................................. 24 Feedback Resistor Divider ........................................................ 24 Inductor Selection ...................................................................... 24 Output Ripple Voltage (ΔVRR) .................................................. 24 Output Capacitor Selection....................................................... 24 Compensation Network ............................................................ 25 Efficiency Considerations ......................................................... 26 Input Capacitor Selection .......................................................... 27 Thermal Considerations............................................................ 28 Design Example .......................................................................... 29 External Component Recommendations .................................... 31 Layout Considerations ................................................................... 33 IC Section (Left Side of Evaluation Board) ............................. 37 Power Section ............................................................................. 37 Differential Sensing .................................................................... 38 Typical Applications Circuits ........................................................ 39 15 A, 300 kHz High Current Application Circuit .................. 39 5.5 V Input, 600 kHz Application Circuit ............................... 39 300 kHz High Current Application Circuit ............................ 40 Outline Dimensions ....................................................................... 41 Ordering Guide .......................................................................... 41
REVISION HISTORY
3/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
ADP1870/ADP1871 SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V, VBST − VSW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Table 1.
Parameter POWER SUPPLY CHARACTERISTICS High Input Voltage Range Symbol VIN Conditions CIN = 22 μF to PGND (at Pin 1) ADP1870ARMZ-0.3/ADP1871ARMZ-0.3 (300 kHz) ADP1870ARMZ-0.6/ADP1871ARMZ-0.6 (600 kHz) ADP1870ARMZ-1.0/ADP1871ARMZ-1.0 (1.0 MHz) VFB = 1.5 V, no switching COMP/EN < 285 mV Rising VIN (see Figure 35 for temperature variation) Falling VIN from operational state Min Typ Max Unit
2.95 2.95 3.25
Quiescent Current Shutdown Current Undervoltage Lockout UVLO Hysteresis INTERNAL REGULATOR CHARACTERISTICS VREG Operational Output Voltage
IQ_REG + IQ_BST IREG,SD + IBST,SD UVLO
12 12 12 1.1 190 2.65 190
20 20 20 280
V V V mA μA V mV
VREG
VREG Output in Regulation Load Regulation Line Regulation VIN to VREG Dropout Voltage Short VREG to PGND SOFT START Soft Start Period ERROR AMPLIFER FB Regulation Voltage
CVREG = 1 μF to PGND, 0.22 μF to GND, VIN = 2.95 V to 20 V ADP1870ARMZ-0.3/ADP1871ARMZ-0.3 (300 kHz) ADP1870ARMZ-0.6/ADP1871ARMZ-0.6 (600 kHz) ADP1870ARMZ-1.0/ADP1871ARMZ-1.0 (1.0 MHz) VIN = 7 V, 100 mA VIN = 12 V, 100 mA 0 mA to 100 mA, VIN = 7 V 0 mA to 100 mA, VIN = 20 V VIN = 7 V to 20 V, 20 mA VIN = 7 V to 20 V, 100 mA 100 mA out of VREG, VIN ≤ 5 V VIN = 20 V See Figure 58
2.75 2.75 3.05 4.8 4.8
5 5 5 4.981 4.982 32 33 2.5 2.0 300 229 3.0 600 600 600 496 1 3 6 12 24
5.5 5.5 5.5 5.16 5.16
415 320
V V V V V mV mV mV mV mV mA ms mV mV mV μS nA V/V V/V V/V V/V
VFB
TJ = +25°C TJ = −40°C to +85°C TJ = −40°C to +125°C VFB = 0.6 V, COMP/EN = released RES = 47 kΩ ± 1% RES = 22 kΩ ± 1% RES = none RES = 100 kΩ ± 1% Typical values measured at 50% time points with 0 nF at DRVH and DRVL; maximum values are guaranteed by bench evaluation 1
Transconductance FB Input Leakage Current CURRENT-SENSE AMPLIFIER GAIN Programming Resistor (RES) Value from DRVL to PGND
Gm IFB, Leak
596 594.2 320
604 605.8 670 50 3.3 6.5 13 26
2.7 5.5 11 22
SWITCHING FREQUENCY
ADP1870ARMZ-0.3/ ADP1871ARMZ-0.3 (300 kHz) On-Time Minimum On-Time Minimum Off-Time
300 VIN = 5 V, VOUT = 2 V, TJ = 25°C VIN = 20 V 84% duty cycle (maximum) 1120 1200 146 340 1280 190 400
kHz ns ns ns
Rev. 0 | Page 3 of 44
ADP1870/ADP1871
Parameter ADP1870ARMZ-0.6/ ADP1871ARMZ-0.6 (600 kHz) On-Time Minimum On-Time Minimum Off-Time ADP1870ARMZ-1.0/ ADP1871ARMZ-1.0 (1.0 MHz) On-Time Minimum On-Time Minimum Off-Time OUTPUT DRIVER CHARACTERISTICS High-Side Driver Output Source Resistance Output Sink Resistance Rise Time 2 Fall Time2 Low-Side Driver Output Source Resistance Output Sink Resistance Rise Time2 Fall Time2 Propagation Delays DRVL Fall to DRVH Rise2 DRVH Fall to DRVL Rise2 SW Leakage Current Integrated Rectifier Channel Impedance PRECISION ENABLE THRESHOLD Logic High Level Enable Hysteresis COMP VOLTAGE COMP Clamp Low Voltage COMP Clamp High Voltage COMP Zero Current Threshold THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Hiccup Current Limit Timing
1
Symbol
Conditions
Min
Typ 600 540 82 340 1.0 312 60 340
Max
Unit kHz ns ns ns MHz ns ns ns
VIN = 5 V, VOUT = 2 V, TJ = 25°C VIN = 20 V, VOUT = 0.8 V 65% duty cycle (maximum)
500
580 110 400
VIN = 5 V, VOUT = 2 V, TJ = 25°C VIN = 20 V 45% duty cycle (maximum)
285
340 85 400
tr,DRVH tf,DRVH
ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) VBST − VSW = 4.4 V, CIN = 4.3 nF (see Figure 60) VBST − VSW = 4.4 V, CIN = 4.3 nF (see Figure 61) ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) VREG = 5.0 V, CIN = 4.3 nF (see Figure 61) VREG = 5.0 V, CIN = 4.3 nF (see Figure 60) VBST − VSW = 4.4 V (see Figure 60) VBST − VSW = 4.4 V (see Figure 61) VBST = 25 V, VSW = 20 V, VREG = 5 V ISINK = 10 mA VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V 245
2.25 0.7 25 11 1.6 0.7 18 16 15.4 18
3 1
Ω Ω ns ns Ω Ω ns ns ns ns μA Ω
2.2 1
tr,DRVL tf,DRVL ttpdhDRVH ttpdhDRVL ISWLEAK
110 22 285 37 330
mV mV V
VCOMP(low) VCOMP(high) VCOMP_ZCT TTMSD
From disabled state, release COMP/EN pin to enable device (2.75 V ≤ VREG ≤ 5.5 V) (2.75 V ≤ VREG ≤ 5.5 V) (2.75 V ≤ VREG ≤ 5.5 V) Rising temperature
0.47 2.55 1.07 155 15 6
V V °C °C ms
The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 60 and Figure 61), CGATE = 4.3 nF, and the upper- and lower-side MOSFETs being Infineon BSC042N03MSG. 2 Not automatic test equipment (ATE) tested.
Rev. 0 | Page 4 of 44
ADP1870/ADP1871 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VREG to PGND, GND VIN to PGND FB, COMP/EN to GND DRVL to PGND SW to PGND BST to SW BST to PGND DRVH to SW PGND to GND θJA (10-Lead MSOP) 2-Layer Board 4-Layer Board Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Maximum Soldering Lead Temperature (10 sec) Rating −0.3 V to +6 V −0.3 V to +28 V −0.3 V to (VREG + 0.3 V) −0.3 V to (VREG + 0.3 V) −2.0 V to +28 V −0.6 V to (VREG + 0.3 V) −0.3 V to 28 V −0.3 V to VREG ±0.3 V 213.1°C/W 171.7°C/W −40°C to +125°C −65°C to +150°C JEDEC J-STD-020 300°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type θJA (10-Lead MSOP) 2-Layer Board 4- Layer Board
1
θJA1 213.1 171.7
Unit °C/W °C/W
θJA is specified for the worst-case conditions; that is, θJA is specified for the device soldered in a circuit board for surface-mount packages.
BOUNDARY CONDITION
In determining the values given in Table 2 and Table 3, natural convection was used to transfer heat to a 4-layer evaluation board.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to PGND.
Rev. 0 | Page 5 of 44
ADP1870/ADP1871 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN 1 COMP/EN 2 FB 3 GND 4 VREG 5
10
BST SW DRVH
08730-003
ADP1870/ ADP1871
TOP VIEW (Not to Scale)
9 8 7 6
PGND DRVL
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic VIN COMP/EN FB GND VREG DRVL PGND DRVH SW BST Description High Input Voltage. Connect VIN to the drain of the upper-side MOSFET. Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC. Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane (see the Layout Considerations section). Internal Regulator Supply Bias Voltage for the ADP1870/ADP1871 Controller (Includes the Output Gate Drivers). A bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF across VREG and GND are recommended. Drive Output for the External Lower-Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting pin (see Figure 69). Power GND. Ground for the lower-side gate driver and lower-side, N-channel MOSFET. Drive Output for the External Upper-Side, N-Channel MOSFET. Switch Node Connection. Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VREG and BST for increased gate drive capability.
Rev. 0 | Page 6 of 44
ADP1870/ADP1871 TYPICAL PERFORMANCE CHARACTERISTICS
100 95 90 85 VIN = 13V (PSM) 80 75 70 65 60 55 50 45 40 35 V = 16.5V (PSM) IN 30 25 20 15 10 5 0 10 100 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 VIN = 13V
VIN = 13V (PSM)
EFFICIENCY (%)
VIN = 16.5V VIN = 13V TA = 25°C VOUT = 0.8V fSW = 300kHz WÜRTH INDUCTOR: 744325072, L = 0.72µH, DCR = 1.3mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
08730-104
EFFICIENCY (%)
VIN = 16.5V TA = 25°C VOUT = 0.8V fSW = 600kHz WÜRTH INDUCTOR: 744355147, L = 0.47µH, DCR = 0.67mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 100 1k LOAD CURRENT (mA) 10k 100k
08730-107 08730-109 08730-108
VIN = 16.5V (PSM)
1k LOAD CURRENT (mA)
10k
100k
Figure 4. Efficiency—300 kHz, VOUT = 0.8 V
Figure 7. Efficiency—600 kHz, VOUT = 0.8 V
08730-105
100 95 VIN = 5V (PSM) 90 85 80 75 70 VIN = 16.5V 65 VIN = 13V (PSM) 60 55 VIN = 13V 50 45 40 VIN = 16.5V (PSM) 35 TA = 25°C 30 VOUT = 1.8V 25 fSW = 300kHz 20 WÜRTH INDUCTOR: 15 744325120, L = 1.2µH, DCR = 1.8mΩ 10 INFINEON FETs: 5 BSC042N03MS G (UPPER/LOWER) 0 10 100 1k 10k 100k LOAD CURRENT (mA)
100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10
VIN = 13V VIN = 13V (PSM)
EFFICIENCY (%)
EFFICIENCY (%)
VIN = 16.5V (PSM)
VIN = 16.5V TA = 25°C VOUT = 1.8V fSW = 600kHz WÜRTH INDUCTOR: 744325072, L = 0.72µH, DCR = 1.3mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
100
1k LOAD CURRENT (mA)
10k
100k
Figure 5. Efficiency—300 kHz, VOUT = 1.8 V
Figure 8. Efficiency—600 kHz, VOUT = 1.8 V
1k LOAD CURRENT (mA)
10k
100k
08730-106
100 95 VIN = 16.5V (PSM) 90 85 80 75 V = 13V (PSM) IN 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100
EFFICIENCY (%)
VIN = 16.5V
TA = 25°C VOUT = 7V fSW = 300kHz WÜRTH INDUCTOR: 7443551200, L = 2.0µH, DCR = 2.6mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
EFFICIENCY (%)
VIN = 13V
100 VIN = 13V (PSM) 95 90 V = 16.5V (PSM) IN 85 80 75 70 65 VIN = 16.5V 60 55 50 VIN = 20V (PSM) VIN = 20V 45 40 35 TA = 25°C 30 VOUT = 5V 25 fSW = 600kHz 20 WÜRTH INDUCTOR: 15 744318180, L = 1.4µH, DCR = 3.2mΩ 10 INFINEON FETs: 5 BSC042N03MS G (UPPER/LOWER) 0 10 100 1k 10k 100k LOAD CURRENT (mA)
Figure 6. Efficiency—300 kHz, VOUT = 7 V
Figure 9. Efficiency—600 kHz, VOUT = 5 V
Rev. 0 | Page 7 of 44
ADP1870/ADP1871
100 95 90 85 80 75 70 65 VIN = 13V (PSM) 60 55 50 45 40 35 30 VIN = 16.5V (PSM) 25 20 15 10 5 0 10 100
0.807
VIN = 13V
0.806 0.805 0.804
OUTPUT VOLTAGE (V)
0.803 0.802 0.801 0.800 0.799 0.798 0.797 0.796 0.795 0.794 0.793 0.792 0 VIN = 13V +125°C +25°C –40°C 2000 VIN = 16.5V +125°C +25°C –40°C 4000 6000 8000 10,000
08730-013
EFFICIENCY (%)
VIN = 16.5V
TA = 25°C VOUT = 0.8V fSW = 1.0MHz WÜRTH INDUCTOR: 744303012, L = 0.12µH, DCR = 0.33mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 1k LOAD CURRENT (mA) 10k 100k
08730-110
LOAD CURRENT (mA)
Figure 10. Efficiency—1.0 MHz, VOUT = 0.8 V
Figure 13. Output Voltage Accuracy—300 kHz, VOUT = 0.8 V
1k
10k
100k
0
1500
3000
4500
6000
7500
9000 10,500 12,000 13,500 15,000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 11. Efficiency—1.0 MHz, VOUT = 1.8 V
Figure 14. Output Voltage Accuracy—300 kHz, VOUT = 1.8 V
100
1k LOAD CURRENT (mA)
10k
100k
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
LOAD CURRENT (mA)
Figure 12. Efficiency—1.0 MHz, VOUT = 5 V
Figure 15. Output Voltage Accuracy—300 kHz, VOUT = 7 V
Rev. 0 | Page 8 of 44
08730-015
08730-112
100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10
VIN = 13V (PSM)
VIN = 16.5V (PSM)
VIN = 13V VIN = 16.5V TA = 25°C VOUT = 5V fSW = 1.0MHz WÜRTH INDUCTOR: 744355090, L = 0.9µH, DCR = 1.6mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
7.100 7.095 7.090 7.085 7.080 7.075 7.070 7.065 7.060 7.055 7.050 7.045 7.040 7.035 7.030 7.025 7.020 7.015 7.010 7.005 7.000
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
+125°C +25°C –40°C
VIN = 13V VIN = 16.5V
08730-014
08730-111
100 95 90 85 80 VIN = 13V (PSM) 75 70 65 60 55 50 45 40 V = 16.5V (PSM) IN 35 30 25 20 15 10 5 0 10 100
1.821
VIN = 13V
1.816
OUTPUT VOLTAGE (V)
1.811 1.806 1.801 1.796 1.791 1.786 VIN = 5.5V +125°C +25°C –40°C VIN = 13V +125°C +25°C –40°C VIN = 16.5V +125°C +25°C –40°C
EFFICIENCY (%)
VIN = 16.5V TA = 25°C VOUT = 1.8V fSW = 1.0MHz WÜRTH INDUCTOR: 744303022, L = 0.22µH, DCR = 0.33mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
ADP1870/ADP1871
0.808 0.806 0.804
FREQUENCY (kHz)
0.807 0.805 0.803
OUTPUT VOLTAGE (V)
0.801 0.799 0.797 0.795 0.793 0.791 VIN = 13V +125°C +25°C –40°C 0 2000 4000 VIN = 16.5V +125°C +25°C –40°C 6000 8000 10,000
08730-118 08730-020 08730-019
0.802 0.800 0.798 0.796 0.794 0.792 0 +125°C +25°C –40°C
VIN = 13V VIN = 16.5V
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0.789 0.787
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 16. Output Voltage Accuracy—600 kHz, VOUT = 0.8 V
Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 0.8 V
08730-016
1.818 1.816 1.814 1.812 1.810 1.808 1.806 1.804 1.802 1.800 1.798 1.796 1.794 1.792 1.790 1.788 1.786 1.784 1.782 1.780 1.778 1.776 1.774 1.772 1.770 0 1500 3000
1.820
1.815
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.810
1.805
1.800
VIN = 13V +125°C +25°C –40°C 4500 6000
VIN = 16.5V +125°C +25°C –40°C 7500 9000 10,500 12,000
1.795
VIN = 13V +125°C +25°C –40°C 0
VIN = 16.5V +125°C +25°C –40°C
1.790 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 17. Output Voltage Accuracy—600 kHz, VOUT = 1.8 V
Figure 20. Output Voltage Accuracy—1.0 MHz, VOUT = 1.8 V
5.030 5.025 5.020
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
5.04 5.03 5.02 5.01 5.00 4.99 4.98 4.97 4.96 4.95 4.94 4.93 +125°C +25°C –40°C 0 VIN = 13V VIN = 16.5V VIN = 20V
08730-017
5.015 5.010 5.005 5.000 4.995 4.990 4.985 4.980 4.975 4.970
4.92 4.91 4.90 0
VIN = 13V +125°C +25°C –40°C
VIN = 16.5V +125°C +25°C –40°C
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA)
800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600 LOAD CURRENT (mA)
Figure 18. Output Voltage Accuracy—600 kHz, VOUT = 5 V
Figure 21. Output Voltage Accuracy—1.0 MHz, VOUT =5 V
Rev. 0 | Page 9 of 44
ADP1870/ADP1871
601.0 600.5
FEEDBACK VOLTAGE (V)
900 880
+125°C +25°C –40°C
600.0 599.5 VREG = 5V, VIN = 13V 599.0 598.5 598.0 597.5 597.0 –40.0
SWITCHING FREQUENCY (kHz)
08730-121
VREG = 5V, VIN = 30V
860 840 820 800 780 760 740 720
–7.5
25.0
57.5
90.0
122.5
13.5
14.0
14.5
15.0
15.5
16.0
16.5
TEMPERATURE (°C)
VIN (V)
Figure 22. Feedback Voltage vs. Temperature
Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz, VIN Range = 13 V to 16.5 V
325 315
SWITCHING FREQUENCY (kHz)
+125°C +25°C –40°C
NO LOAD
280
265
VIN = 13V VIN = 20V VIN = 16.5V
+125°C +25°C –40°C
305
FREQUENCY (kHz)
250
295 285 275 265 255 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 VIN (V)
235
220
205
08730-022
0
2000
4000
6000
8000
10,000
LOAD CURRENT (mA)
Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, ±10% of 12 V
Figure 26. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V
650
+125°C +25°C –40°C
NO LOAD
330 320 310
VIN = 20V VIN = 13V VIN = 16.5V
+125°C +25°C –40°C
SWITCHING FREQUENCY (kHz)
600
FREQUENCY (kHz)
300 290 280 270 260 250
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550
500
450
13.4
13.8
14.2
14.6
15.0
15.4
15.8
16.2
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400 13.0
240
0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,00
VIN (V)
LOAD CURRENT (mA)
Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, VOUT = 1.8 V, VIN Range = 13 V to 16.5 V
Figure 27. Frequency vs. Load Current, 300 kHz, VOUT = 1.8 V
Rev. 0 | Page 10 of 44
08730-025
190
08730-124
700 13.0
ADP1870/ADP1871
338 334 330
FREQUENCY (kHz) FREQUENCY (kHz)
VIN = 13V VIN = 16.5V
+125°C +25°C –40°C
326 322 318 314 310 306 302
08730-027
0
800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 LOAD CURRENT (mA)
0
800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600
LOAD CURRENT (mA)
Figure 28. Frequency vs. Load Current, 300 kHz, VOUT = 7 V
Figure 31. Frequency vs. Load Current, 600 kHz, VOUT = 5 V
540 510 480
FREQUENCY (kHz)
VIN = 13V VIN = 16.5V
+125°C +25°C –40°C
850
VIN = 13V VIN = 16.5V
+125°C +25°C –40°C
775
FREQUENCY (kHz)
700
450 420 390 360 330 300
0 1200 2400 3600 4800 6000 7200 8400 9600 10,800 12,000
625
550
475
08730-028
0
2000
4000
6000
8000
10,000
12,000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 29. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V
Figure 32. Frequency vs. Load Current, VOUT = 1.0 MHz, 0.8 V
675 655 635
FREQUENCY (kHz)
1225 VIN = 13V VIN = 16.5V 1150 1075
FREQUENCY (kHz)
VIN = 13V VIN = 16.5V
+125°C +25°C –40°C
615 595 575 555 535 515 495 0 LOAD CURRENT (mA) +125°C +25°C –40°C
08730-029
1000 925 850 775 700 625
08730-032
550
0 1200 2400 3600 4800 6000 7200 8400 9600 10,800 12,000
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
LOAD CURRENT (mA)
Figure 30. Frequency vs. Load Current, 600 kHz, VOUT = 1.8 V
Figure 33. Frequency vs. Load Current, 1.0 MHz, VOUT = 1.8 V
Rev. 0 | Page 11 of 44
08730-031
400
08730-030
298
740 733 726 719 712 705 698 691 684 677 670 663 656 649 642 635 628 621
VIN = 13V VIN = 16.5V
+125°C +25°C –40°C
ADP1870/ADP1871
1450 1400 1350
FREQUENCY (kHz)
82 VIN = 13V VIN = 16.5V +125°C +25°C –40°C
MAXIMUM DUTY CYCLE (%)
80 78 76 74 72 70 68 66 64
08730-033
+125°C +25°C –40°C
1300 1250 1200 1150 1100 1050 1000 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 LOAD CURRENT (mA)
6.7
7.9
9.1
10.3
11.5
12.7
13.9
15.1
16.3
VIN (V)
Figure 34. Frequency vs. Load Current, 1.0 MHz, VOUT = 5 V
Figure 37. Maximum Duty Cycle vs. High Voltage Input (VIN)
2.658 2.657 2.656
MINUMUM OFF-TIME (ns)
680 630 580 530 480 430 380 330 280 230
08730-034
VREG = 2.7V VREG = 3.6V VREG = 5.5V
2.655
UVLO (V)
2.654 2.653 2.652 2.651 2.650 2.649 –40
–20
0
20
40
60
80
100
120
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 35. UVLO vs. Temperature
Figure 38. Minimum Off-Time vs. Temperature
95 90
MAXIMUM DUTY CYCLE (%)
680
+125°C +25°C –40°C
MINUMUM OFF-TIME (ns)
630 580
+125°C +25°C –40°C
85 80 75 70 65 60 55 300
530 480 430 380 330 280 230
08730-035
400
500
600
700
800
900
1000
3.1
3.5
3.9
4.3
4.7
5.1
5.5
FREQUENCY (kHz)
VREG (V)
Figure 36. Maximum Duty Cycle vs. Frequency
Figure 39. Minimum Off-Time vs. VREG (Low Input Voltage)
Rev. 0 | Page 12 of 44
08730-038
180 2.7
08730-037
180 –40
08730-036
62 5.5
ADP1870/ADP1871
800 720 640
RECTIFIER DROP (mV) BODY DIODE CONDUCTION TIME (ns)
VREG = 2.7V VREG = 3.6V VREG = 5.5V
+125°C +25°C –40°C
80 72 64 56 48 40 32 24 16 8 2.7
300kHz 1MHz
+125°C +25°C –40°C
560 480 400 320 240 160
08730-039
400
500
600
700
800
900
1000
3.1
3.5
3.9
4.3
4.7
5.1
5.5
FREQUENCY (kHz)
VREG (V)
Figure 40. Internal Rectifier Drop vs. Frequency
Figure 43. Lower-Side MOSFET Body Diode Conduction Time vs. VREG
1280 1200 1120 1040
RECTIFIER DROP (mV)
VIN = 5.5V VIN = 13V VIN = 16.5V
1MHz 300kHz
TA = 25°C
OUTPUT VOLTAGE
1
960 880 800 720 640 560 480 400 320 240 160 3.1 3.5 3.9 4.3 4.7 5.1 5.5
08730-040
INDUCTOR CURRENT
2
SW NODE
3
LOW SIDE
4
VREG (V)
CH1 50mV BW CH3 10V BW
CH2 5A Ω CH4 5V
M400ns T 35.8%
A CH2
3.90A
Figure 41. Internal Boost Rectifier Drop vs. VREG (Low Input Voltage) Over VIN Variation
Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA
720 640 560 480 400 320 240 160
300kHz 1MHz
+125°C +25°C –40°C
1
OUTPUT VOLTAGE
RECTIFIER DROP (mV)
INDUCTOR CURRENT
2
SW NODE
3
LOW SIDE
4
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VREG (V)
Figure 42. Internal Boost Rectifier Drop vs. VREG
08730-041
CH1 50mV BW CH3 10V BW
CH2 5A Ω CH4 5V
M4.0µs T 35.8%
A CH2
3.90A
Figure 45. PSM Waveform at Light Load, 500 mA
Rev. 0 | Page 13 of 44
08730-044
80 2.7
08730-043
80 2.7
08730-042
80 300
ADP1870/ADP1871
OUTPUT VOLTAGE
4 2
OUTPUT VOLTAGE
INDUCTOR CURRENT
12A NEGATIVE STEP
1
SW NODE
1 3
SW NODE
3 4
LOW SIDE
CH1 5A Ω CH3 10V
08730-045
CH4 100mV
B W
M400ns T 30.6%
A CH3
2.20V
CH1 10A Ω CH3 20V
CH2 200mV CH4 5V
B W M20µs
A CH1
3.40A
T 48.2%
Figure 46. CCM Operation at Heavy Load, 12 A (See Figure 93 for Application Circuit)
Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled, 12 A (See Figure 93 Application Circuit)
OUTPUT VOLTAGE
2
4
OUTPUT VOLTAGE
12A STEP
1
12A STEP
1
LOW SIDE
SW NODE
3
2
SW NODE
LOW SIDE
4
08730-046
3
CH1 10A Ω CH3 20V
CH2 200mV CH4 5V
B W
M2ms T 75.6%
A CH1
3.40A
CH1 10A Ω CH3 20V
CH2 5V CH4 200mV
B W
M2ms T 15.6%
A CH1
6.20A
Figure 47. Load Transient Step—PSM Enabled, 12 A (See Figure 93 Application Circuit)
Figure 50. Load Transient Step—Forced PWM at Light Load, 12 A (See Figure 93 Application Circuit)
OUTPUT VOLTAGE
2 4
OUTPUT VOLTAGE
12A POSITIVE STEP 12A POSITIVE STEP
1
SW NODE
1
LOW SIDE
3
2
SW NODE LOW SIDE
4
08730-047
3
CH1 10A Ω CH3 20V
CH2 200mV CH4 5V
B W M20µs
A CH1
3.40A
T 30.6%
CH1 10A Ω CH3 20V
CH2 5V CH4 200mV
M20µs
B W T 43.8%
A CH1
6.20A
Figure 48. Positive Step During Heavy Load Transient Behavior—PSM Enabled, 12 A, VOUT = 1.8 V (See Figure 93 Application Circuit)
Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM at Light Load, 12 A, VOUT = 1.8 V (See Figure 93 Application Circuit)
Rev. 0 | Page 14 of 44
08730-050
08730-049
08730-048
ADP1870/ADP1871
2
OUTPUT VOLTAGE
1
OUTPUT VOLTAGE
INDUCTOR CURRENT
12A NEGATIVE STEP
1 2
SW NODE LOW SIDE
4 3
08730-051
CH1 10A Ω CH3 20V
CH2 200mV CH4 5V
B W M10µs
A CH1
5.60A
T 23.8%
CH1 2V BW CH2 5A Ω CH3 10V CH4 5V
M2ms T 32.8%
A CH1
720mV
Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM at Light Load, 12 A (See Figure 93 Application Circuit)
Figure 55. Start-Up Behavior at Heavy Load, 12 A, 300 kHz (See Figure 93 Application Circuit)
OUTPUT VOLTAGE
1 1
OUTPUT VOLTAGE
INDUCTOR CURRENT
2
LOW SIDE
4
INDUCTOR CURRENT
2
LOW SIDE
4
SW NODE
3
08730-052
SW NODE
3
CH1 2V BW CH2 5A Ω CH3 10V CH4 5V
M4ms T 49.4%
A CH1
920mV
CH1 2V BW CH2 5A Ω CH3 10V CH4 5V
M4ms T 41.6%
A CH1
720mV
Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode
Figure 56. Power-Down Waveform During Heavy Load
1
OUTPUT VOLTAGE
1
OUTPUT VOLTAGE
INDUCTOR CURRENT INDUCTOR CURRENT
2
2
SW NODE SW NODE
3 3
LOW SIDE LOW SIDE
4
08730-053
4
CH1 5V BW CH3 10V
CH2 10A Ω CH4 5V
M10µs T 36.2%
A CH2
8.20A
CH1 50mV BW CH3 10V BW
CH2 5A Ω CH4 5V
M2µs T 35.8%
A CH2
3.90A
Figure 54. Magnified Waveform During Hiccup Mode
Figure 57. Output Voltage Ripple Waveform During PSM Operation at Light Load, 2 A
Rev. 0 | Page 15 of 44
08730-056
08730-055
08730-054
4
LOW SIDE
SW NODE
3
ADP1870/ADP1871
18ns (tr,DRVL ) LOW SIDE
OUTPUT VOLTAGE
1 4
HIGH SIDE
24ns (tpdh,DRVL )
LOW SIDE
4
HS MINUS SW
SW NODE
3 3 2
11ns (tf,DRVH )
SW NODE
INDUCTOR CURRENT
2
08730-057
M
TA = 25°C
08730-060 08730-062 08730-061
CH1 1V BW CH3 10V BW
CH2 5A Ω CH4 2V
M1ms T 63.2%
A CH1
1.56V
CH2 5V CH3 5V CH4 2V MATH 2V 20ns
M20ns T 39.2%
A CH2
4.20V
Figure 58. Soft Start and RES Detect Waveform
Figure 61. Upper-Side Driver Falling and Lower-Side Rising Edge Waveforms (CIN = 4.3 nF (Upper-/Lower-Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
LOW SIDE
TA = 25°C
570 550 530 510 490 470 450
VREG = 5.5V VREG = 3.6V VREG = 2.7V
4
HIGH SIDE SW NODE
3 2 M
HS MINUS SW CH3 5V MATH 2V 40ns
08730-058
TRANSCONDUCTANCE (µS)
CH2 5V CH4 2V
M40ns T 29.0%
A CH2
4.20V
430 –40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 59. Output Drivers and SW Node Waveforms
Figure 62. Transconductance (Gm) vs. Temperature
LOW SIDE
16ns (tf,DRVL )
TA = 25°C
680 630
TRANSCONDUCTANCE (µS)
+125°C +25°C –40°C
4
22ns (tpdhDRVH ) HIGH SIDE
580 530 480 430 380 330 2.7
25ns (tr,DRVH) SW NODE
3 2 M
HS MINUS SW
08730-059
CH2 5V CH3 5V CH4 2V MATH 2V 40ns
M40ns T 29.0%
A CH2
4.20V
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
VREG (V)
Figure 60. Upper-Side Driver Rising and Lower-Side Falling Edge Waveforms (CIN = 4.3 nF (Upper-/Lower-Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
Rev. 0 | Page 16 of 44
Figure 63. Transconductance (Gm) vs. VREG
ADP1870/ADP1871
1.30 1.25 1.20
QUIESCENT CURRENT (mA)
1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 3.1 3.5 3.9 4.3 4.7 5.1 5.5
08730-163
+125°C
+25°C
–40°C
0.70 2.7
VREG (V)
Figure 64. Quiescent Current vs. VREG
Rev. 0 | Page 17 of 44
ADP1870/ADP1871 ADP1870/ADP1871 BLOCK DIAGRAM
ADP1870/ADP1871
tON TIMER
C PRECISION ENABLE BLOCK TO ENABLE ALL BLOCKS LDO SW INFORMATION R (TRIMMED) I VREG VIN
VREG
tON = 2RC(VOUT/VIN)
REF SW FILTER VREG BIAS BLOCK AND REFERENCE REF_ZERO ISS SS COMP CSS COMP/ EN FB SS_REF ERROR AMP INL_HICC PSM STATE MACHINE TON BG_REF BG_REF BG_REF 300kΩ HI SW 8kΩ BG_REF BG_REF 0.6V PWM IREV COMP LOWER COMP CLAMP REF_ZERO CS GAIN SET 0.4V CS AMP LO LS VREG DRVL PGND LEVEL SHIFT HS SW DRVH BST
ADC
RES DETECT AND GAIN SET
GND
Figure 65. ADP1870/ADP1871 Block Diagram
Rev. 0 | Page 18 of 44
08730-063
ADP1870/ADP1871 THEORY OF OPERATION
The ADP1870/ADP1871 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current limit protection by using a constant on-time, pseudo-fixed frequency with a programmable currentsense gain, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by utilizing valley current-mode control architecture. This allows the ADP1870/ ADP1871 to drive all N-channel power stages to regulate output voltages as low as 0.6 V. ADP1870/ADP1871, reducing the supply current of the devices to approximately 140 μA. For more information, see Figure 67.
ADP1870/ADP1871
FB VREG
SS ERROR AMPLIFIER PRECISION ENABLE TO ENABLE ALL BLOCKS 285mV
0.6V
COMP/EN CC RC CC2
STARTUP
The ADP1870/ADP1871 have an internal regulator (VREG) for biasing and supplying power for the integrated MOSFET drivers. A bypass capacitor should be located directly across the VREG (Pin 5) and PGND (Pin 7) pins. Included in the power-up sequence is the biasing of the current-sense amplifier, the current-sense gain circuit (see the Programming Resistor (RES) Detect Circuit section), the soft start circuit, and the error amplifier. The current-sense blocks provide valley current information (see the Programming Resistor (RES) Detect Circuit section) and are a variable of the compensation equation for loop stability (see the Compensation Network section). The valley current information is extracted by forcing 0.4 V across the DRVL output and PGND pin, which generates a current depending on the resistor across DRVL and PGND in a process performed by the RES detect circuit. The current through the resistor is used to set the current-sense amplifier gain. This process takes approximately 800 μs, after which the drive signal pulses appear at the DRVL and DRVH pins synchronously and the output voltage begins to rise in a controlled manner through the soft start sequence. The rise time of the output voltage is determined by the soft start and error amplifier blocks (see the Soft Start section). At the beginning of a soft start, the error amplifier charges the external compensation capacitor, causing the COMP/EN pin to rise above the enable threshold of 285 mV, thus enabling the ADP1870/ADP1871.
Figure 66. Release COMP/EN Pin to Enable the ADP1870/ADP1871
COMP/EN
>2.4V 2.4V
HICCUP MODE INITIALIZED MAXIMUM CURRENT (UPPER CLAMP)
1.0V
ZERO CURRENT
USABLE RANGE ONLY AFTER SOFT START PERIOD IF CONTUNUOUS CONDUCTION MODE OF OPERATION IS SELECTED.
500mV
LOWER CLAMP
0V
35mV HYSTERESIS
Figure 67. COMP/EN Voltage Range
UNDERVOLTAGE LOCKOUT
The undervoltage lockout (UVLO) feature prevents the part from operating both the upper- and lower-side MOSFETs at extremely low or undefined input voltage (VIN) ranges. Operation at an undefined bias voltage may result in the incorrect propagation of signals to the high-side power switches. This, in turn, results in invalid output behavior that can cause damage to the output devices, ultimately destroying the device tied at the output. The UVLO level has been set at 2.65 V (nominal).
SOFT START
The ADP1870/ADP1871 have digital soft start circuitry, which involves a counter that initiates an incremental increase in current, by 1 μA, via a current source on every cycle through a fixed internal capacitor. The output tracks the ramping voltage by producing PWM output pulses to the upper-side MOSFET. The purpose is to limit the in-rush current from the high voltage input supply (VIN) to the output (VOUT).
ON-BOARD LOW DROPOUT REGULATOR
The ADP1870 uses an on-board LDO to bias the internal digital and analog circuitry. With proper bypass capacitors connected to the VREG pin (output of internal LDO), this pin also provides power for the internal MOSFET drivers. It is recommended to float VREG if VIN is utilized for greater than 5.5 V operation. The minimum voltage where bias is guaranteed to operate is 2.75 V at VREG. For applications where VIN is decoupled from VREG, the minimum voltage at VIN must be 2.9 V. It is recommended that
PRECISION ENABLE CIRCUITRY
The ADP1870/ADP1871 employ precision enable circuitry. The enable threshold is 285 mV typical with 35 mV of hysteresis. The devices are enabled when the COMP/EN pin is released, allowing the error amplifier output to rise above the enable threshold (see Figure 66). Grounding this pin disables the
Rev. 0 | Page 19 of 44
08730-065
285mV
PRECISION ENABLE THRESHOLD
08730-064
ADP1870/ADP1871
VIN and VREG be tied together if the VIN pin is subjected to a 2.75 V rail. Table 5. Power Input and LDO Output Configurations
VIN >5.5 V
