ADP1872-EVALZ/ADP1873-EVALZ User Guide
UG-057
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADP1872/ADP1873 PWM Buck Controllers
FEATURES
TYPICAL APPLICATIONS CIRCUIT
VIN = 2.75V TO 20V
VIN
CC
ADP1872/
ADP1873
CC2
RC
BST
COMP/EN
VOUT
CIN
CBST
RTOP
FB
DRVH
RBOT
GND
CVDD2
VDD = 2.75V
TO 5.5V
APPLICATIONS
L
VOUT
COUT
Q2
SW
VDD
Q1
DRVL
PGND
RRES
LOAD
5A
CVDD
Perform basic evaluation board operations
Evaluate IC and application board performance
+
08548-001
Wide power input voltage (VIN): 2.75 V to 20 V
Bias supply voltage (VDD) range: 2.75 V to 5.5 V
Available in 1.8 V fixed-output voltage
Available in 300 kHz, 600 kHz, and 1.0 MHz switching
frequency options
Available in power saving mode (PSM) for light loads
(ADP1873 only)
Starts into a precharged or preloaded output
Figure 1.
GENERAL DESCRIPTION
This document describes the evaluation board hardware for the
ADP1872/ADP1873 PWM buck controllers. The evaluation boards
can be used to evaluate the ADP1872 or ADP1873 and application
circuits using these ICs without requiring any additional software.
The ADP1872/ADP1873 evaluation boards employ a power input
voltage (VIN) that ranges between 2.75 V and 20 V and a bias supply
voltage (VDD) that ranges between 2.75 V and 5.5 V. Both inputs
can be tied together for application input voltage conditions equal
to or less than 5.5 V. The evaluation board is available in a fixedoutput voltage option (VOUT = 1.8 V), as well as in a 300 kHz,
600 kHz, or 1 MHz switching frequency (test trimmed in
production). The ADP1872/ADP1873 evaluation boards offer
an output accuracy of 2% over the full temperature range and
provide a high input voltage (VIN ± 10%) and a full-scale load
current up to 15 A.
See the last page for an important warning and disclaimers.
08548-100
The ADP1872/ADP1873 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable currentsense gain, current-control scheme. The ADP1873 is the power
saving mode (PSM) version of the device and is capable of pulse
skipping to maintain output regulation while achieving improved
system efficiency at light loads (see the ADP1872/ADP1873 data
sheet for more information). Both devices are available in a small,
10-lead MSOP package and can operate over the −40°C to +125°C
temperature range.
Figure 2. ADP1872 Evaluation Board Configured
for 300 kHz Switching Frequency Operation
The ADP1872/ADP1873 data sheet provides more information,
including details about how to modify the evaluation board while
maintaining system stability throughout the entire load current
range and, therefore, should be consulted in conjunction with
this user guide when using the evaluation boards.
Rev. A | Page 1 of 20
UG-057
ADP1872-EVALZ/ADP1873-EVALZ User Guide
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................6
Applications ....................................................................................... 1
Typical Application Circuits ......................................................... 10
General Description ......................................................................... 1
Dual-Input, 300 kHz High Current Application Circuit ...... 10
Typical Applications Circuit............................................................ 1
Evaluation Board Schematics and Layout ................................... 11
Revision History ............................................................................... 2
1.8 V Output, 300 kHz, 14 A Application Circuit.................. 11
Evaluation Board Hardware ............................................................ 3
Layer 1.......................................................................................... 12
Setting Up the Evaluation Board ................................................ 3
Layer 2.......................................................................................... 13
Powering Up and Powering Down the Evaluation Board ....... 4
Layer 3.......................................................................................... 14
Enabling and Disabling the ADP1872/ADP1873 .................... 4
Layer 4.......................................................................................... 15
Evaluating the Performance of the ADP1872/ADP1873 ........ 4
Bill of Materials ............................................................................... 16
Modifying the Evaluation Board ................................................ 5
1.8 V Output, 300 kHz, 14 A Application Circuit.................. 16
REVISION HISTORY
12/13—Rev. 0 to Rev. A
Deleted 3.3 V Fixed-Output Voltage Model ................... Universal
Deleted Single-Input, 600 kHz Application Circuit Section
and Figure 29............................................................................... 10
Updated ESD Caution and Legal Terms and Conditions ......... 18
3/10—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADP1872-EVALZ/ADP1873-EVALZ User Guide
UG-057
EVALUATION BOARD HARDWARE
Upon receipt of the ADP1872/ADP1873 evaluation board, the
following criteria have already been determined:
•
•
The IC is either the ADP1872 (forced pulse-width modulation
[PWM]) or the ADP1873 (power saving mode [PSM]).
The switching frequency is 300 kHz, 600 kHz, or 1 MHz.
SETTING UP THE EVALUATION BOARD
Before powering up the system, set up the evaluation board as
follows to ensure that all passive and active components are
properly soldered to the evaluation board:
1.
2.
3.
4.
5.
6.
7.
Ensure that the Headers JP2 and J1 connections are correct
for a given application (see Table 1 and the Headers JP2
and J1 section).
Ensure that the main power supply (VIN) is off but set to 0 V,
and then connect the main power supply to the evaluation
board, connecting the positive terminal to TP_VIN1 and
the negative terminal to TP_PGND.
Optionally, place a current meter in series with the main
power supply to monitor the input current.
Ensure that the low input voltage supply (VDD) is off but set
to 0 V, and then connect the low input voltage supply to the
evaluation board, connecting the positive terminal to J1
and the negative terminal to TP_PGND.
Ensure that the electronic load is turned off, and then connect
the load to the evaluation board, connecting the positive
terminal to TP_VOUT1 and the negative terminal to
TP_PGND.
Optionally, connect a power resistor of the appropriate
value for your application across the TP_VOUT1 and
TP_PGND terminals of the evaluation board.
Optionally, to continually monitor VIN, VDD, and VOUT, solder
SMB jacks to each of the following measuring points: VIN1,
VOUT1, and VREG1 (see Figure 33).
Table 1. Header Connections
Header
J1
Input Voltage (V)
≤5.5
>5.5
JP2
≤5.5
>5.5
JP3
N/A
Description of Connection
Floating (no jumper), single
input configuration.
Connect to VDD (dual input
configuration), and, optionally,
add a voltmeter across J1 and
TP_PGND to monitor the low
input voltage.
Jumper between VIN and VDD
(single input configuration).
Open (no jumper), dual input
configuration.
Jumper at all times.
Headers JP2 and J1
When the power input voltage is greater than 5.5 V, the device
is in dual input configuration. If this configuration is chosen,
ensure that Header JP2 is open (no jumper), and connect J1 to
VDD. Optionally, you can also add a voltmeter across J1 and
TP_PGND to monitor the low input voltage.
If the power input voltage is less than or equal to 5.5 V, the device is
in single input configuration. In this case, a jumper can be placed
on Header JP2 that connects VIN to VDD. If a jumper is used in
this way, leave Header J1 floating (no jumper), and ensure that
VIN does not exceed 5.5 V.
Header JP3
Always put a jumper on Header JP3 to connect the high voltage
input to Pin 1 (VIN) of the IC.
High Input Voltage Power Source (VIN)
Ensure that the main power supply equipment is turned off but set
to 0 V before connecting the main power supply to the evaluation
board. Place a current meter in series with this power supply to
monitor the input current. Connect the positive terminal (+) of
the power supply to the TP_VIN1 terminal of the evaluation board.
Connect the negative terminal of the power supply (−) to the
TP_PGND terminal of the evaluation board.
Low Input Voltage Supply for Bias (VDD)
Set the low input voltage supply to 0 V and make sure that it is
turned off before connecting the positive terminal (+) to Jumper J1
of the evaluation board. Connect the negative terminal (−) to
the TP_PGND terminal of the evaluation board.
Output Terminal
The output terminal (TP_VOUT1) of the ADP1872/ADP1873
evaluation board is equipped with a banana terminal plug similar
to TP_VIN1 and TP_PGND. The evaluation board is designed to
withstand load immediately upon power-up, but may be damaged
if the load is not properly connected to TP_VOUT1. Ensure that
the electronic load is turned off prior to connecting the positive
terminal (+) and negative terminal (−) to the VOUT and TP_PGND
terminals of the evaluation board, respectively. If a power resistor is
used, connect this device across the TP_VOUT1 and TP_PGND
terminals of the evaluation board.
Ensure that proper current values for your application are
programmed on the electronic load prior to activation and, if
applicable, that the correct power resistor value for your application
is in place before powering up the evaluation board.
DC Voltmeter on VIN, VDD, and VOUT
For more accurate dc measurements of VIN, VDD, and VOUT, add
a dedicated voltmeter for each of these voltage nodes (resources
permitting) to continually monitor VIN, VOUT, and VDD. This can
be done by placing an SMB jack on VIN1, VOUT2, VREG1 (see
Figure 33).
Rev. A | Page 3 of 20
UG-057
ADP1872-EVALZ/ADP1873-EVALZ User Guide
Placeholders for SMB jacks are integrated into each evaluation
board to facilitate such connections. Therefore, to accurately
measure VIN, connect the voltmeter’s positive terminal (+) to
the node where the positive terminal of the high voltage input
capacitors (C3 to C8) and the drain of Q1/Q2 meet, and connect
the voltmeter’s negative terminal (−) to the node where the negative
terminal of the input capacitors and the source terminal of Q3
meet. These SMB terminals are optimally placed to minimize
unnecessary voltage drops that may otherwise produce inaccurate
VIN dc measurements.
Similarly, for output voltage (VOUT) dc measurements, a placeholder for an SMB terminal is positioned directly across the
positive and negative terminals of the output capacitor that
is farthest from the inductor terminal and source of Q3. For
accurate low input voltage (VDD) dc measurements, an SMB
terminal footprint is positioned as close as possible across C1,
which is laid out near the VDD pin (Pin 5) and the PGND pin
(Pin 7) of the ADP1872/ADP1873.
POWERING UP AND POWERING DOWN
THE EVALUATION BOARD
After completing the procedure described in the Setting Up the
Evaluation Board section, power up the evaluation board as
follows:
1.
2.
3.
4.
5.
Apply power to the VDD pin.
Apply power to the VIN pin.
Slowly increase the VDD supply while monitoring the current
meter until VDD is equal to 5 V.
Because VIN is 0 V, IDD should jump between 120 µA (when
approaching the UVLO threshold of 2.65 V) to less than 1 mA
until VDD is equal to 5 V. Do not exceed 5.5 V on VDD. No
output (VOUT) regulation is expected yet because VIN is 0 V.
Slowly increase VIN up to 12 V.
When VIN is increased, VOUT begins regulating to the desired
voltage setpoint (via the VOUT dedicated voltmeter). Continue
to increase VIN up to 12 V. Do not exceed 20 V on VIN. Output
voltage regulation should occur regardless of whether there is
a load connected at the output.
After the output voltage is in regulation with the desired input
voltage, increase the electronic load to the desired value.
To power down the evaluation board,
1.
2.
voltage on this pin above the enable threshold of 285 mV, thus
enabling the IC, which causes the output voltage to regulate.
EVALUATING THE PERFORMANCE
OF THE ADP1872/ADP1873
Verifying the Switching Waveform
To verify the switching waveform,
1.
2.
3.
4.
5.
6.
7.
The resultant switching waveform should be between 0 V and
the value of VIN (that is, 12 V), and the jitter should be less than
or equal to 100 ns.
Observing the Output Voltage Ripple
To observe the output voltage ripple,
1.
2.
3.
4.
Power down VIN.
Power down VDD.
Ensure that the oscilloscope, probe tips, and ground loop clip
are in good working condition; that the probe tips have been
calibrated per the manufacturer’s instructions and are clear
of debris and dirt; and that the ground loops do not have any
breaks or peels.
Set the operating mode of the respective oscilloscope to
DC Coupling in the oscilloscope’s Channel menu.
Set the bandwidth to its maximum value (≥150 MHz).
Set the vertical scale to 5 V per division and the timescale
(x-axis) to 1/(2 × fSW) per division, where fSW is the switching
frequency of the evaluation board.
Securely attach the ground loop clip onto the TP_PGND
terminal of the evaluation board. Ideally, the loop should
be as close as possible to the negative terminal of the high
input voltage capacitors (C3 to C8) and to the source of
MOSFET Q1.
Land or securely attach the probe tip to the drain of Q1.
Observe the subsequent switching waveform and jitter.
Set the operating mode of the respective oscilloscope to
AC Coupling in the oscilloscope’s Channel menu.
Set the vertical scale to 100 mV per division and the timescale
to 1/(2 × fSW).
Securely attach the ground loop clip onto the TP_PGND
terminal of the evaluation board. Ideally, the loop should
be as close as possible to the negative terminal (−) of the
farthest output capacitor from the inductor terminal, and
the probe tip should touch the positive terminal (+) of the
same output capacitor.
Observe the output voltage ripple.
Evaluating the Inductor Current Waveform
To evaluate the inductor current waveform,
ENABLING AND DISABLING
THE ADP1872/ADP1873
1.
The ADP1872/ADP1873 evaluation board has a placeholder for
a switch (normally open) for the COMP/EN pin to allow you to
enable (open) and disable (closed) the ADP1872/ADP1873 on
the evaluation board. When closed, the switch shorts this pin to
ground, disabling the ADP1872/ADP1873. When the switch is
subsequently opened (released), the error amplifier brings the
2.
3.
Rev. A | Page 4 of 20
Calibrate the current probe per the manufacturer’s
instructions.
Power up the system (see the Powering Up and Powering
Down the Evaluation Board section).
Solder a 3 inch wire loop (from 10 gauge to 14 gauge) between
the source of Q1 and the inductor terminal. The current probe
has a clamping mechanism and can clamp onto this wire to
measure the current traveling through the wire.
ADP1872-EVALZ/ADP1873-EVALZ User Guide
4.
5.
6.
7.
Ensure that the current direction is toward the output voltage
(TP_VOUT1) and that the clamp of the current probe is in the
closed, or locked, position.
Set the vertical scale to one-third of the total load current that
the converter is designed to deliver.
Set the timescale similar to how the switching and output
ripple waveforms were set.
Observe the inductor current waveform.
UG-057
Observing Transient Response
To observe the transient response,
1.
2.
3.
Obtaining Efficiency Measurements
To obtain more accurate efficiency measurements,
1.
2.
3.
4.
Power down the device.
Remove the 3 inch wire loop between the source of Q1 and
the inductor terminal.
Power up the device.
Record the current and voltage readings.
Efficiency is calculated based on the measurements made between
the output and the input of the converter:
η=
VOUT × I OUT
V IN × I IN
where:
VOUT is the dc voltage readout by the voltmeter that is connected to
the SMB terminal of the evaluation board or by the voltmeter
that is connected across the output capacitor that is located
farthest from the inductor terminal.
IOUT is the digital readout produced by the electronic load
equipment.
VIN is the dc voltage readout by the voltmeter.
IIN is the current readout from the current meter in series
between the high input voltage supply equipment and the
TP_VIN1 terminal of the evaluation board.
Assessing Line Regulation
To assess the line regulation,
1.
2.
Vary the high input voltage.
Record the resultant changes on the dc level of the output
voltage (VOUT).
Evaluating Short-Circuit Protection
To evaluate the self-protection scheme of the ADP1873 during
output short-circuit events,
1.
2.
Achieve steady state regulation.
Short the voltage output (TP_VOUT1) to TP_PGND.
The system then enters hiccup mode and remains in this mode
until the violation disappears (see the ADP1872/ADP1873 data
sheet for more details).
MODIFYING THE EVALUATION BOARD
For any given ADP1872/ADP1873 evaluation board, an ADP1872
or ADP1873 IC can be used interchangeably as long as the pretrimmed frequency setpoint is the same for both ICs.
To maintain system stability throughout the entire load current
range, one component (passive or active) cannot be modified
without modifying the rest. Refer to the ADP1872/ADP1873
data sheet for information about how each of the following
elements can be adjusted, keeping in mind that any change
affects the entire system:
•
•
•
•
Examining Load Regulation
To examine the load regulation,
1.
2.
Power up the system (see the Powering Up and Powering
Down the Evaluation Board section).
Solder a 3 inch wire loop (from 10 gauge to 14 gauge)
between the source of Q1 and the inductor terminal.
Record instances where the output transient is out of phase
with the load. Such occurrences are caused by sudden changes
in the output load current and can be recorded by capturing
the inductor ripple current waveform and the output voltage
ac transient using the single acquisition feature of the
oscilloscope.
Vary the load current through electronic load adjustments.
Record the resultant changes on the dc level of the output
voltage (VOUT).
Rev. A | Page 5 of 20
Feedback resistor divider
Inductor
Output capacitor
Compensation network
• Output filter impedance (ZFILT)
• Error amplifier output impedance (ZCOMP)
• Error amplifier gain (GM)
• Current-sense loop gain (GCS)
• Programmable current-sense gain (ACS)
• Valley current limit setting
• Crossover frequency
UG-057
ADP1872-EVALZ/ADP1873-EVALZ User Guide
TYPICAL PERFORMANCE CHARACTERISTICS
For the most up-to-date typical performance characteristics, see the ADP1872/ADP1873 data sheet.
100
95
VDD = 5.5V, VIN = 5.5V (PSM)
VDD = 5.5V, VIN = 5.5V
1.815
90
1.813
VDD = 5.5V, VIN = 16.5V (PSM)
VDD = 5.5V, VIN = 16.5V
65
VDD = 5.5V, VIN = 13V (PSM)
60
55
VDD = 3.6V, VIN = 3.6V
50
VDD = 5.5V, VIN = 13V
45
40
VDD = 3.6V, VIN = 5.5V
35
25
100
1k
10k
100k
LOAD CURRENT (mA)
VIN = 13V
1.807
1.805
1.803
WURTH IND: 744325120, L = 1.2µH, DCR: 2.0mΩ
INFINEON FETS: BSC042N03MS G (UPPER/LOWER)
TA = 25°C
30
1.809
1.801
0
4500
6000
7500
9000 10,500 12,000 13,500 15,000
Figure 6. Load Regulation Plot for fSW = 300 kHz, VOUT = 1.8 V
1.821
OUTPUT VOLTAGE (V)
1.816
1.811
1.806
1.801
1.796
VIN = 5.5V
+125°C
+25°C
–40°C
1.791
VIN = 13V
+125°C
+25°C
–40°C
VIN = 16.5V
+125°C
+25°C
–40°C
1.786
08548-010
EFFICIENCY (%)
LOAD CURRENT (mA)
3000
LOAD CURRENT (mA)
Figure 3. Efficiency—300 kHz, VOUT = 1.8 V
100
VDD = 5.5V, VIN = 5V (PSM)
V = 5.5V,
95 VDD= 16.5V (PSM)
IN
90
85
VDD = 5.5V,
80
VIN = 5V
VDD = 5.5V,
V
=
5.5V,
V
=
16.5V
75 VIN = 13V
DD
IN
V
=
3.6V,
V
=
13V
(PSM)
DD
IN
70
VDD = 3.6V, VIN = 16.5V
65
VDD = 5.5V, VIN = 13V
60
55
50
45
40
35
30
WURTH IND: 744303022, L = 0.22µH, DCR: 0.33mΩ
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
25
TA = 25°C
20
1k
10k
100k
100
1500
08548-102
70
VIN = 16.5V
1.811
0
1500
3000
4500
6000
7500
9000 10,500 12,000 13,500 15,000
LOAD CURRENT (mA)
Figure 4. Efficiency—1 MHz, VOUT = 1.8 V
Figure 7. Output Voltage Accuracy—300 kHz, VOUT = 1.8 V
1.821
2.658
VDD = 5V
TA = 25°C
2.657
1.816
1.811
UVLO (V)
2.655
1.806
NO LOAD
1.801
2.654
2.653
2.652
2.651
1.796
1.791
5.50
6.95
8.40
9.85 11.30 12.75 14.20 15.65 17.10 18.55 20.00
VIN (V)
Figure 5. Line Regulation Plot for fSW = 300 kHz, VOUT = 1.8 V
2.649
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 8. UVLO vs. Temperature
Rev. A | Page 6 of 20
100
120
08548-034
2.650
08548-101
OUTPUT VOLTAGE (V)
2.656
LOAD = 15A
08548-014
75
08548-005
EFFICIENCY (%)
80
OUTPUT VOLTAGE (V)
85
ADP1872-EVALZ/ADP1873-EVALZ User Guide
UG-057
OUTPUT VOLTAGE
OUTPUT VOLTAGE
2
1
INDUCTOR CURRENT
20A STEP
2
1
SW NODE
SW NODE
3
3
LOW SIDE
LOW SIDE
CH2 5A Ω
CH4 5V
M400ns
T 35.8%
A CH2
3.90A
08548-043
CH1 50mV BW
CH3 10V BW
CH1 10A Ω
CH3 20V
CH2 200mV
CH4 5V
B
W
M2ms
T 75.6%
A CH1
3.40A
08548-046
4
4
Figure 12. Load Transient Step—PSM Enabled, 20 A
(See Figure 28 for Application Circuit)
Figure 9. Power Saving Mode (PSM) Operational Waveform, 100 mA
OUTPUT VOLTAGE
OUTPUT VOLTAGE
2
1
INDUCTOR CURRENT
20A POSITIVE STEP
2
SW NODE
1
SW NODE
3
3
LOW SIDE
LOW SIDE
CH2 5A Ω
CH4 5V
M4.0µs
T 35.8%
A CH2
3.90A
08548-044
CH1 50mV BW
CH3 10V BW
CH1 10A Ω
CH3 20V
CH2 200mV
CH4 5V
B
W
M20µs
T 30.6%
A CH1
3.40A
08548-047
4
4
Figure 13. Positive Step During Heavy Load Transient Behavior—PSM Enabled,
20 A, VOUT = 1.8 V (See Figure 28 for Application Circuit)
Figure 10. PSM Waveform at Light Load, 500 mA
OUTPUT VOLTAGE
2
4
OUTPUT VOLTAGE
INDUCTOR CURRENT
20A NEGATIVE STEP
1
SW NODE
3
1
SW NODE
LOW SIDE
3
CH4 100mV
B
W
M400ns
T 30.6%
A CH3
Figure 11. CCM Operation at Heavy Load, 18 A
(See Figure 28 for Application Circuit)
2.20V
CH1 10A Ω
CH3 20V
CH2 200mV
CH4 5V
B
W M20µs
T 48.2%
A CH1
3.40A
08548-048
CH1 5A Ω
CH3 10V
08548-045
4
Figure 14. Negative Step During Heavy Load Transient Behavior—PSM Enabled,
20 A (See Figure 28 for Application Circuit)
Rev. A | Page 7 of 20
UG-057
ADP1872-EVALZ/ADP1873-EVALZ User Guide
OUTPUT VOLTAGE
4
1
OUTPUT VOLTAGE
INDUCTOR CURRENT
2
20A STEP
LOW SIDE
LOW SIDE
1
4
2
SW NODE
SW NODE
CH2 5V
CH4 200mV
B
W
M2ms
T 15.6%
A CH1
6.20A
08548-049
CH1 10A Ω
CH3 20V
CH1 2V BW CH2 5A Ω
CH3 10V
CH4 5V
M4ms
T 49.4%
A CH1
920mV
08548-052
3
3
Figure 18. Output Short-Circuit Behavior Leading to Hiccup Mode
Figure 15. Load Transient Step—Forced PWM at Light Load, 20 A
(See Figure 28 for Application Circuit)
OUTPUT VOLTAGE
1
4
OUTPUT VOLTAGE
INDUCTOR CURRENT
20A POSITIVE STEP
2
LOW SIDE
1
SW NODE
3
2
SW NODE
LOW SIDE
CH2 5V
CH4 200mV
B
W
M20µs
T 43.8%
A CH1
6.20A
08548-050
CH1 10A Ω
CH3 20V
CH1 5V BW CH2 10A Ω
CH4 5V
CH3 10V
A CH2
8.20A
Figure 19. Magnified Waveform During Hiccup Mode
Figure 16. Positive Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 20 A, VOUT = 1.8 V (See Figure 28 for Application Circuit)
OUTPUT VOLTAGE
2
M10µs
T 36.2%
08548-053
4
3
OUTPUT VOLTAGE
1
INDUCTOR CURRENT
20A NEGATIVE STEP
2
1
SW NODE
LOW SIDE
4
3
SW NODE
LOW
SIDE
CH2 200mV
CH4 5V
B
W
M10µs
T 23.8%
A CH1
5.60A
CH1 2V BW CH2 5A Ω
CH3 10V
CH4 5V
Figure 17. Negative Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 20 A (See Figure 28 for Application Circuit)
Rev. A | Page 8 of 20
M2ms
T 32.8%
A CH1
720mV
Figure 20. Start-Up Behavior at Heavy Load, 18 A, 300 kHz
(See Figure 28 for Application Circuit)
08548-054
CH1 10A Ω
CH3 20V
3
08548-051
4
ADP1872-EVALZ/ADP1873-EVALZ User Guide
UG-057
LOW SIDE
TA = 25°C
OUTPUT VOLTAGE
1
4
HIGH SIDE
SW NODE
INDUCTOR CURRENT
2
LOW SIDE
4
3
2
M
SW NODE
M4ms
T 41.6%
A CH1
720mV
08548-055
CH1 2V BW CH2 5A Ω
CH3 10V
CH4 5V
CH2 5V
CH4 2V
CH3 5V
MATH 2V 40ns
Figure 21. Power-Down Waveform During Heavy Load
M40ns
T 29.0%
A CH2
4.20V
08548-058
HS MINUS
SW
3
Figure 24. Output Drivers and SW Node Waveforms
LOW SIDE
OUTPUT VOLTAGE
TA = 25°C
16ns (tf, DRVL)
1
INDUCTOR CURRENT
4
22ns (tpdh, DRVH)
HIGH SIDE
2
SW NODE
25ns (tr, DRVH)
SW NODE
3
LOW SIDE
3
2
CH2 5A Ω
CH4 5V
M2µs
T 35.8%
A CH2
3.90A
08548-056
CH1 50mV BW
CH3 10V BW
Figure 22. Output Voltage Ripple Waveform During PSM Operation
at Light Load, 2 A
HS MINUS
SW
CH2 5V
CH4 2V
CH3 5V
MATH 2V 40ns
M40ns
T 29.0%
A CH2
4.20V
08548-059
M
4
Figure 25. Upper-Side Driver Rising and Lower-Side Falling Edge Waveforms,
CIN = 4.3 nF (Upper-/Lower-Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)
18ns (tr, DRVL)
LOW SIDE
OUTPUT VOLTAGE
1
4
HIGH SIDE
24ns (tpdh, DRVL)
LOW SIDE
4
HS MINUS
SW
SW NODE
11ns (tf, DRVH)
SW NODE
3
2
3
M
INDUCTOR CURRENT
CH2 5A Ω
CH4 2V
M1ms
T 63.2%
A CH1
Figure 23. Soft Start and RES Detect Waveform
1.56V
08548-057
CH1 1V BW
CH3 10V BW
CH2 5V
CH4 2V
CH3 5V
MATH 2V 20ns
M20ns
T 39.2%
A CH2
4.20V
08548-060
TA = 25°C
2
Figure 26. Upper-Side Driver Falling and Lower-Side Rising Edge Waveforms,
CIN = 4.3 nF (Upper-/Lower-Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)
Rev. A | Page 9 of 20
UG-057
ADP1872-EVALZ/ADP1873-EVALZ User Guide
TYPICAL APPLICATION CIRCUITS
DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT
HIGH VOLTAGE INPUT
VIN = 12V
LOW VOLTAGE INPUT
VDD = 5.0V
JP2
5
C2
0.1µF
VDD
10
C12
100nF
C3
22µF
Q1
C5
22µF
1.0µH
8
Q3
7
C6
22µF
C7
22µF
Q2
9
Q4
DRVL 6
C1
1µF
C4
22µF
R6
2Ω
C13
1.5nF
C20
270µF
VOUT = 1.8V, 15A
+
+
C21
270µF
C22
270µF
+
C23
270µF
+
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
PANASONIC: (OUTPUT CAPACITORS)
270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (BOTTOM)
BSC080N03MS G (TOP)
WURTH INDUCTORS:
1µH, 3.3mΩ, 20A 7443552100
R5
100kΩ
08548-088
C11 JP3
ADP1872/
571pF
ADP1873
C10
R3
1 VIN
BST
57pF
47kΩ
2 COMP/EN
SW
R1 30kΩ
VOUT
3 FB
DRVH
R2
15kΩ
4 GND
PGND
Figure 27. Application Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect)
LOW VOLTAGE INPUT
VDD = 5V
HIGH VOLTAGE INPUT
VIN = 13V
JP2
5
C2
0.1µF
VDD
10
C12
100nF
C3
22µF
Q1
C5
22µF
0.8µH
8
Q3
C6
22µF
C7
22µF
Q2
9
7
C4
22µF
Q4
DRVL 6
C1
1µF
C20
R6
270µF
2Ω
C13
1.5nF
VOUT = 1.8V, 20A
+
C21
270µF
+
C22
270µF
+
C23
270µF
+
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
PANASONIC: (OUTPUT CAPACITORS)
270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (BOTTOM)
BSC080N03MS G (TOP)
WURTH INDUCTORS:
0.72µH, 1.65mΩ, 35A 744325072
Figure 28. Application Circuit for 13 V Input, 1.8 V Output, 20 A, 300 kHz (Q2/Q4 No Connect)
Rev. A | Page 10 of 20
08548-090
C11 JP3
ADP1872/
800pF
ADP1873
C10
R3
1 VIN
BST
80pF
33.5kΩ
2 COMP/EN
SW
R1 30kΩ
VOUT
3 FB
DRVH
R2
15kΩ
4 GND
PGND
ADP1872-EVALZ/ADP1873-EVALZ User Guide
UG-057
EVALUATION BOARD SCHEMATICS AND LAYOUT
This section provides the schematics for the 1.8 V output, 300 kHz, 14 A application circuit. For other application circuits, see the
ADP1872/ADP1873 data sheet for the recommended values for the external components.
1.8 V OUTPUT, 300 kHz, 14 A APPLICATION CIRCUIT
HIGH VOLTAGE INPUT
VIN = 13V
LOW VOLTAGE INPUT
VDD = 5.0V
(J1 HEADER)
TP_VIN1 (BANANA PLUG)
JP2
(HEADER)
VIN1 (SMB)
C11 JP3
U1
571pF
ADP1872
C10
R3
1 VIN
BST
47kΩ
FB1 (SMB) 57pF
2 COMP/EN
SW
R1 30kΩ
VOUT
3 FB
DRVH
R2
15kΩ
4 GND
PGND
C1
1µF
VREG1 (SMB)
VDD
C3
22µF
Q1
7
C5
22µF
C6
22µF
C7
22µF
L1
1.0µH
R4
0kΩ
DRVL 6
Q3
C8
N/A
TP_VOUT1
(BANANA PLUG)
VOUT2 (SMB)
Q2
9
8
C4
22µF
Q4
VOUT = 1.8V, 14A
C20
270µF
R6
2Ω
C13
1.5nF
C14
N/A
R5
100kΩ
+
C21
270µF
+
C15
N/A
C16
N/A
C22
270µF
+
C17
N/A
C23
270µF
C18
N/A
+ C24
N/A
+
C19
N/A
TP_PGND
(BANANA PLUG)
08548-103
5
C2
0.1µF
10
C12
100nF
Figure 29. 1.8 V Output, 300 kHz, 14 A Application Circuit
Rev. A | Page 11 of 20
UG-057
ADP1872-EVALZ/ADP1873-EVALZ User Guide
08548-082
LAYER 1
Figure 30. Layer 1
Rev. A | Page 12 of 20
ADP1872-EVALZ/ADP1873-EVALZ User Guide
UG-057
08548-083
LAYER 2
Figure 31. Layer 2
Rev. A | Page 13 of 20
UG-057
ADP1872-EVALZ/ADP1873-EVALZ User Guide
08548-084
LAYER 3
Figure 32. Layer 3
Rev. A | Page 14 of 20
ADP1872-EVALZ/ADP1873-EVALZ User Guide
UG-057
08548-085
LAYER 4
Figure 33. Layer 4
Rev. A | Page 15 of 20
UG-057
ADP1872-EVALZ/ADP1873-EVALZ User Guide
BILL OF MATERIALS
1.8 V OUTPUT, 300 kHz, 14 A APPLICATION CIRCUIT
Table 2.
Name
CVDD
CVDD
CIN
CIN
CIN
CIN
CIN
CIN
CPAR
CC
CBST
CSNUBBER
COUT
COUT
COUT
COUT
COUT
COUT
COUT
COUT
COUT
COUT
COUT
RTOP
RBOT
RC
RGATE
RRES
RSNUBBER
Top MOSFET
Top MOSFET
Bottom MOSFET
Bottom MOSFET
Inductor
Header
Header
Header
Banana Plugs
Banana Plugs
Banana Plugs
Controller/Driver
Diode
1
2
Reference
Designator
C1
C2
C3
C4
C5
C6
C7
C8
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
R1
R2
R3
R4
R5
R6
Q1
Q2
Q3
Q4
L1
J1
JP2
JP3
TP_VIN1
TP_PGND
TP_VOUT1
U1
D3
Value
1.0
0.1
22
22
22
22
22
N/A
57
571
100
1.5
N/A
N/A
N/A
N/A
N/A
N/A
270
270
270
270
N/A
30
15
47
0
100
2
N/A
N/A
N/A
N/A
1.0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Unit
µF
µF
µF
µF
µF
µF
µF
N/A
pF
pF
nF
nF
N/A
N/A
N/A
N/A
N/A
N/A
µF
µF
µF
µF
N/A
kΩ
kΩ
kΩ
kΩ
kΩ
Ω
N/A
N/A
N/A
N/A
µH
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Manufacturer
Taiyo Yuden
TDK
Murata
Murata
Murata
Murata
Murata
Description/Model
1.0 µF, 6.3 V, X5R ceramic capacitor (0402), JMK105BJ105KV-F
0.1 µF, 25 V, X5R ceramic capacitor (0402), C1005X5R1E104K
25 V, X7R, 1210 (3.2 mm × 2.5 mm × 2.5 mm) GRM32ER71E226KE15L
25 V, X7R, 1210 (3.2 mm × 2.5 mm × 2.5 mm) GRM32ER71E226KE15L
25 V, X7R, 1210 (3.2 mm × 2.5 mm × 2.5 mm) GRM32ER71E226KE15L
25 V, X7R, 1210 (3.2 mm × 2.5 mm × 2.5 mm) GRM32ER71E226KE15L
25 V, X7R, 1210 (3.2 mm × 2.5 mm × 2.5 mm) GRM32ER71E226KE15L
Taiyo Yuden 1
Taiyo Yuden1
Taiyo Yuden1
Taiyo Yuden1
±10%, 50 V, X7R ceramic capacitor (0402)
±5%, 50 V, C0H ceramic capacitor (0402)
±10%, 50 V, X7R ceramic capacitors (0603)
±10%, 50 V, X7R ceramic capacitors (0603)
Panasonic
Panasonic
Panasonic
Panasonic
SP-series, 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm)
SP-series, 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm)
SP-series, 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm)
SP-series, 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm)
Vishay1
Vishay1
Vishay1
Vishay1
Vishay1
Vishay1
Infineon
Infineon
Infineon
Infineon
Würth Elek
±1% resistors (0603)
±1% resistors (0603)
±1% resistors (0603)
±1% resistors (0603)
±1% resistors (0603)
±1% resistors (0603)
BSC080N03MS G
BSC080N03MS G
BSC080N03MS G
BSC080N03MS G
7443251200
Analog Devices
ADP1872ARMZ-0.3-R7 2 (LDT) or ADP1873ARMZ-0.3-R72 (LDF)
Components from other manufacturers can also be used, as long as the characteristics listed in the corresponding description are met.
Z = RoHS Compliant Part.
Rev. A | Page 16 of 20
ADP1872-EVALZ/ADP1873-EVALZ User Guide
NOTES
Rev. A | Page 17 of 20
UG-057
UG-057
ADP1872-EVALZ/ADP1873-EVALZ User Guide
NOTES
Rev. A | Page 18 of 20
ADP1872-EVALZ/ADP1873-EVALZ User Guide
NOTES
Rev. A | Page 19 of 20
UG-057
UG-057
ADP1872-EVALZ/ADP1873-EVALZ User Guide
NOTES
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
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temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
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UG08548-0-12/13(A)
Rev. A | Page 20 of 20
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